drivers/gpu/drm/i915/display/intel_display_device.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2023 Intel Corporation
   4  */
   5
   6 #include <drm/i915_pciids.h>
   7 #include <drm/drm_color_mgmt.h>
   8 #include <linux/pci.h>
   9
  10 #include "i915_drv.h"
  11 #include "i915_reg.h"
  12 #include "intel_de.h"
  13 #include "intel_display.h"
  14 #include "intel_display_device.h"
  15 #include "intel_display_power.h"
  16 #include "intel_display_reg_defs.h"
  17 #include "intel_fbc.h"
  18
  19 static const struct intel_display_device_info no_display = {};
  20
  21 #define PIPE_A_OFFSET           0x70000
  22 #define PIPE_B_OFFSET           0x71000
  23 #define PIPE_C_OFFSET           0x72000
  24 #define PIPE_D_OFFSET           0x73000
  25 #define CHV_PIPE_C_OFFSET       0x74000
  26 /*
  27  * There's actually no pipe EDP. Some pipe registers have
  28  * simply shifted from the pipe to the transcoder, while
  29  * keeping their original offset. Thus we need PIPE_EDP_OFFSET
  30  * to access such registers in transcoder EDP.
  31  */
  32 #define PIPE_EDP_OFFSET 0x7f000
  33
  34 /* ICL DSI 0 and 1 */
  35 #define PIPE_DSI0_OFFSET        0x7b000
  36 #define PIPE_DSI1_OFFSET        0x7b800
  37
  38 #define TRANSCODER_A_OFFSET 0x60000
  39 #define TRANSCODER_B_OFFSET 0x61000
  40 #define TRANSCODER_C_OFFSET 0x62000
  41 #define CHV_TRANSCODER_C_OFFSET 0x63000
  42 #define TRANSCODER_D_OFFSET 0x63000
  43 #define TRANSCODER_EDP_OFFSET 0x6f000
  44 #define TRANSCODER_DSI0_OFFSET  0x6b000
  45 #define TRANSCODER_DSI1_OFFSET  0x6b800
  46
  47 #define CURSOR_A_OFFSET 0x70080
  48 #define CURSOR_B_OFFSET 0x700c0
  49 #define CHV_CURSOR_C_OFFSET 0x700e0
  50 #define IVB_CURSOR_B_OFFSET 0x71080
  51 #define IVB_CURSOR_C_OFFSET 0x72080
  52 #define TGL_CURSOR_D_OFFSET 0x73080
  53
  54 #define I845_PIPE_OFFSETS \
  55         .pipe_offsets = { \
  56                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  57         }, \
  58         .trans_offsets = { \
  59                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  60         }
  61
  62 #define I9XX_PIPE_OFFSETS \
  63         .pipe_offsets = { \
  64                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  65                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  66         }, \
  67         .trans_offsets = { \
  68                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  69                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  70         }
  71
  72 #define IVB_PIPE_OFFSETS \
  73         .pipe_offsets = { \
  74                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  75                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  76                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  77         }, \
  78         .trans_offsets = { \
  79                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  80                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  81                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  82         }
  83
  84 #define HSW_PIPE_OFFSETS \
  85         .pipe_offsets = { \
  86                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  87                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  88                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  89                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  90         }, \
  91         .trans_offsets = { \
  92                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  93                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  94                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  95                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  96         }
  97
  98 #define CHV_PIPE_OFFSETS \
  99         .pipe_offsets = { \
 100                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 101                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 102                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
 103         }, \
 104         .trans_offsets = { \
 105                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 106                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 107                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
 108         }
 109
 110 #define I845_CURSOR_OFFSETS \
 111         .cursor_offsets = { \
 112                 [PIPE_A] = CURSOR_A_OFFSET, \
 113         }
 114
 115 #define I9XX_CURSOR_OFFSETS \
 116         .cursor_offsets = { \
 117                 [PIPE_A] = CURSOR_A_OFFSET, \
 118                 [PIPE_B] = CURSOR_B_OFFSET, \
 119         }
 120
 121 #define CHV_CURSOR_OFFSETS \
 122         .cursor_offsets = { \
 123                 [PIPE_A] = CURSOR_A_OFFSET, \
 124                 [PIPE_B] = CURSOR_B_OFFSET, \
 125                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 126         }
 127
 128 #define IVB_CURSOR_OFFSETS \
 129         .cursor_offsets = { \
 130                 [PIPE_A] = CURSOR_A_OFFSET, \
 131                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 132                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 133         }
 134
 135 #define TGL_CURSOR_OFFSETS \
 136         .cursor_offsets = { \
 137                 [PIPE_A] = CURSOR_A_OFFSET, \
 138                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 139                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 140                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 141         }
 142
 143 #define I845_COLORS \
 144         .color = { .gamma_lut_size = 256 }
 145 #define I9XX_COLORS \
 146         .color = { .gamma_lut_size = 129, \
 147                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 148         }
 149 #define ILK_COLORS \
 150         .color = { .gamma_lut_size = 1024 }
 151 #define IVB_COLORS \
 152         .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 153 #define CHV_COLORS \
 154         .color = { \
 155                 .degamma_lut_size = 65, .gamma_lut_size = 257, \
 156                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 157                 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 158         }
 159 #define GLK_COLORS \
 160         .color = { \
 161                 .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 162                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 163                                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
 164         }
 165 #define ICL_COLORS \
 166         .color = { \
 167                 .degamma_lut_size = 33, .gamma_lut_size = 262145, \
 168                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 169                                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
 170                 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 171         }
 172
 173 #define I830_DISPLAY \
 174         .has_overlay = 1, \
 175         .cursor_needs_physical = 1, \
 176         .overlay_needs_physical = 1, \
 177         .has_gmch = 1, \
 178         I9XX_PIPE_OFFSETS, \
 179         I9XX_CURSOR_OFFSETS, \
 180         I9XX_COLORS, \
 181         \
 182         .__runtime_defaults.ip.ver = 2, \
 183         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 184         .__runtime_defaults.cpu_transcoder_mask = \
 185                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
 186
 187 #define I845_DISPLAY \
 188         .has_overlay = 1, \
 189         .overlay_needs_physical = 1, \
 190         .has_gmch = 1, \
 191         I845_PIPE_OFFSETS, \
 192         I845_CURSOR_OFFSETS, \
 193         I845_COLORS, \
 194         \
 195         .__runtime_defaults.ip.ver = 2, \
 196         .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
 197         .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
 198
 199 static const struct intel_display_device_info i830_display = {
 200         I830_DISPLAY,
 201
 202         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
 203 };
 204
 205 static const struct intel_display_device_info i845_display = {
 206         I845_DISPLAY,
 207
 208         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
 209 };
 210
 211 static const struct intel_display_device_info i85x_display = {
 212         I830_DISPLAY,
 213
 214         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
 215         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 216 };
 217
 218 static const struct intel_display_device_info i865g_display = {
 219         I845_DISPLAY,
 220
 221         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
 222         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 223 };
 224
 225 #define GEN3_DISPLAY \
 226         .has_gmch = 1, \
 227         .has_overlay = 1, \
 228         I9XX_PIPE_OFFSETS, \
 229         I9XX_CURSOR_OFFSETS, \
 230         \
 231         .__runtime_defaults.ip.ver = 3, \
 232         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 233         .__runtime_defaults.cpu_transcoder_mask = \
 234                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 235         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
 236
 237 static const struct intel_display_device_info i915g_display = {
 238         GEN3_DISPLAY,
 239         I845_COLORS,
 240         .cursor_needs_physical = 1,
 241         .overlay_needs_physical = 1,
 242 };
 243
 244 static const struct intel_display_device_info i915gm_display = {
 245         GEN3_DISPLAY,
 246         I9XX_COLORS,
 247         .cursor_needs_physical = 1,
 248         .overlay_needs_physical = 1,
 249         .supports_tv = 1,
 250
 251         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 252 };
 253
 254 static const struct intel_display_device_info i945g_display = {
 255         GEN3_DISPLAY,
 256         I845_COLORS,
 257         .has_hotplug = 1,
 258         .cursor_needs_physical = 1,
 259         .overlay_needs_physical = 1,
 260 };
 261
 262 static const struct intel_display_device_info i945gm_display = {
 263         GEN3_DISPLAY,
 264         I9XX_COLORS,
 265         .has_hotplug = 1,
 266         .cursor_needs_physical = 1,
 267         .overlay_needs_physical = 1,
 268         .supports_tv = 1,
 269
 270         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 271 };
 272
 273 static const struct intel_display_device_info g33_display = {
 274         GEN3_DISPLAY,
 275         I845_COLORS,
 276         .has_hotplug = 1,
 277 };
 278
 279 static const struct intel_display_device_info pnv_display = {
 280         GEN3_DISPLAY,
 281         I9XX_COLORS,
 282         .has_hotplug = 1,
 283 };
 284
 285 #define GEN4_DISPLAY \
 286         .has_hotplug = 1, \
 287         .has_gmch = 1, \
 288         I9XX_PIPE_OFFSETS, \
 289         I9XX_CURSOR_OFFSETS, \
 290         I9XX_COLORS, \
 291         \
 292         .__runtime_defaults.ip.ver = 4, \
 293         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 294         .__runtime_defaults.cpu_transcoder_mask = \
 295                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
 296
 297 static const struct intel_display_device_info i965g_display = {
 298         GEN4_DISPLAY,
 299         .has_overlay = 1,
 300
 301         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
 302 };
 303
 304 static const struct intel_display_device_info i965gm_display = {
 305         GEN4_DISPLAY,
 306         .has_overlay = 1,
 307         .supports_tv = 1,
 308
 309         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
 310         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 311 };
 312
 313 static const struct intel_display_device_info g45_display = {
 314         GEN4_DISPLAY,
 315
 316         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
 317 };
 318
 319 static const struct intel_display_device_info gm45_display = {
 320         GEN4_DISPLAY,
 321         .supports_tv = 1,
 322
 323         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
 324         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 325 };
 326
 327 #define ILK_DISPLAY \
 328         .has_hotplug = 1, \
 329         I9XX_PIPE_OFFSETS, \
 330         I9XX_CURSOR_OFFSETS, \
 331         ILK_COLORS, \
 332         \
 333         .__runtime_defaults.ip.ver = 5, \
 334         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 335         .__runtime_defaults.cpu_transcoder_mask = \
 336                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 337         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
 338
 339 static const struct intel_display_device_info ilk_d_display = {
 340         ILK_DISPLAY,
 341 };
 342
 343 static const struct intel_display_device_info ilk_m_display = {
 344         ILK_DISPLAY,
 345
 346         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 347 };
 348
 349 static const struct intel_display_device_info snb_display = {
 350         .has_hotplug = 1,
 351         I9XX_PIPE_OFFSETS,
 352         I9XX_CURSOR_OFFSETS,
 353         ILK_COLORS,
 354
 355         .__runtime_defaults.ip.ver = 6,
 356         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 357         .__runtime_defaults.cpu_transcoder_mask =
 358                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 359         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
 360         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 361 };
 362
 363 static const struct intel_display_device_info ivb_display = {
 364         .has_hotplug = 1,
 365         IVB_PIPE_OFFSETS,
 366         IVB_CURSOR_OFFSETS,
 367         IVB_COLORS,
 368
 369         .__runtime_defaults.ip.ver = 7,
 370         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 371         .__runtime_defaults.cpu_transcoder_mask =
 372                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 373         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
 374         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 375 };
 376
 377 static const struct intel_display_device_info vlv_display = {
 378         .has_gmch = 1,
 379         .has_hotplug = 1,
 380         .mmio_offset = VLV_DISPLAY_BASE,
 381         I9XX_PIPE_OFFSETS,
 382         I9XX_CURSOR_OFFSETS,
 383         I9XX_COLORS,
 384
 385         .__runtime_defaults.ip.ver = 7,
 386         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 387         .__runtime_defaults.cpu_transcoder_mask =
 388                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 389         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
 390 };
 391
 392 static const struct intel_display_device_info hsw_display = {
 393         .has_ddi = 1,
 394         .has_dp_mst = 1,
 395         .has_fpga_dbg = 1,
 396         .has_hotplug = 1,
 397         .has_psr = 1,
 398         .has_psr_hw_tracking = 1,
 399         HSW_PIPE_OFFSETS,
 400         IVB_CURSOR_OFFSETS,
 401         IVB_COLORS,
 402
 403         .__runtime_defaults.ip.ver = 7,
 404         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 405         .__runtime_defaults.cpu_transcoder_mask =
 406                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 407                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
 408         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
 409         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 410 };
 411
 412 static const struct intel_display_device_info bdw_display = {
 413         .has_ddi = 1,
 414         .has_dp_mst = 1,
 415         .has_fpga_dbg = 1,
 416         .has_hotplug = 1,
 417         .has_psr = 1,
 418         .has_psr_hw_tracking = 1,
 419         HSW_PIPE_OFFSETS,
 420         IVB_CURSOR_OFFSETS,
 421         IVB_COLORS,
 422
 423         .__runtime_defaults.ip.ver = 8,
 424         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 425         .__runtime_defaults.cpu_transcoder_mask =
 426                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 427                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
 428         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
 429         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 430 };
 431
 432 static const struct intel_display_device_info chv_display = {
 433         .has_hotplug = 1,
 434         .has_gmch = 1,
 435         .mmio_offset = VLV_DISPLAY_BASE,
 436         CHV_PIPE_OFFSETS,
 437         CHV_CURSOR_OFFSETS,
 438         CHV_COLORS,
 439
 440         .__runtime_defaults.ip.ver = 8,
 441         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 442         .__runtime_defaults.cpu_transcoder_mask =
 443                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 444         .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
 445 };
 446
 447 static const struct intel_display_device_info skl_display = {
 448         .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */
 449         .dbuf.slice_mask = BIT(DBUF_S1),
 450         .has_ddi = 1,
 451         .has_dp_mst = 1,
 452         .has_fpga_dbg = 1,
 453         .has_hotplug = 1,
 454         .has_ipc = 1,
 455         .has_psr = 1,
 456         .has_psr_hw_tracking = 1,
 457         HSW_PIPE_OFFSETS,
 458         IVB_CURSOR_OFFSETS,
 459         IVB_COLORS,
 460
 461         .__runtime_defaults.ip.ver = 9,
 462         .__runtime_defaults.has_dmc = 1,
 463         .__runtime_defaults.has_hdcp = 1,
 464         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 465         .__runtime_defaults.cpu_transcoder_mask =
 466                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 467                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
 468         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
 469         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
 470 };
 471
 472 #define GEN9_LP_DISPLAY \
 473         .dbuf.slice_mask = BIT(DBUF_S1), \
 474         .has_dp_mst = 1, \
 475         .has_ddi = 1, \
 476         .has_fpga_dbg = 1, \
 477         .has_hotplug = 1, \
 478         .has_ipc = 1, \
 479         .has_psr = 1, \
 480         .has_psr_hw_tracking = 1, \
 481         HSW_PIPE_OFFSETS, \
 482         IVB_CURSOR_OFFSETS, \
 483         IVB_COLORS, \
 484         \
 485         .__runtime_defaults.has_dmc = 1, \
 486         .__runtime_defaults.has_hdcp = 1, \
 487         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
 488         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 489         .__runtime_defaults.cpu_transcoder_mask = \
 490                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 491                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 492                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 493         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
 494
 495 static const struct intel_display_device_info bxt_display = {
 496         GEN9_LP_DISPLAY,
 497         .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 498
 499         .__runtime_defaults.ip.ver = 9,
 500 };
 501
 502 static const struct intel_display_device_info glk_display = {
 503         GEN9_LP_DISPLAY,
 504         .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 505         GLK_COLORS,
 506
 507         .__runtime_defaults.ip.ver = 10,
 508 };
 509
 510 #define ICL_DISPLAY \
 511         .abox_mask = BIT(0), \
 512         .dbuf.size = 2048, \
 513         .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 514         .has_ddi = 1, \
 515         .has_dp_mst = 1, \
 516         .has_fpga_dbg = 1, \
 517         .has_hotplug = 1, \
 518         .has_ipc = 1, \
 519         .has_psr = 1, \
 520         .has_psr_hw_tracking = 1, \
 521         .pipe_offsets = { \
 522                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 523                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 524                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 525                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 526                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 527                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 528         }, \
 529         .trans_offsets = { \
 530                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 531                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 532                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 533                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 534                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 535                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 536         }, \
 537         IVB_CURSOR_OFFSETS, \
 538         ICL_COLORS, \
 539         \
 540         .__runtime_defaults.ip.ver = 11, \
 541         .__runtime_defaults.has_dmc = 1, \
 542         .__runtime_defaults.has_dsc = 1, \
 543         .__runtime_defaults.has_hdcp = 1, \
 544         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 545         .__runtime_defaults.cpu_transcoder_mask = \
 546                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 547                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 548                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 549         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
 550
 551 static const struct intel_display_device_info icl_display = {
 552         ICL_DISPLAY,
 553
 554         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
 555 };
 556
 557 static const struct intel_display_device_info jsl_ehl_display = {
 558         ICL_DISPLAY,
 559
 560         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
 561 };
 562
 563 #define XE_D_DISPLAY \
 564         .abox_mask = GENMASK(2, 1), \
 565         .dbuf.size = 2048, \
 566         .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 567         .has_ddi = 1, \
 568         .has_dp_mst = 1, \
 569         .has_dsb = 1, \
 570         .has_fpga_dbg = 1, \
 571         .has_hotplug = 1, \
 572         .has_ipc = 1, \
 573         .has_psr = 1, \
 574         .has_psr_hw_tracking = 1, \
 575         .pipe_offsets = { \
 576                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 577                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 578                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 579                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 580                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 581                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 582         }, \
 583         .trans_offsets = { \
 584                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 585                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 586                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 587                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 588                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 589                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 590         }, \
 591         TGL_CURSOR_OFFSETS, \
 592         ICL_COLORS, \
 593         \
 594         .__runtime_defaults.ip.ver = 12, \
 595         .__runtime_defaults.has_dmc = 1, \
 596         .__runtime_defaults.has_dsc = 1, \
 597         .__runtime_defaults.has_hdcp = 1, \
 598         .__runtime_defaults.pipe_mask = \
 599                 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 600         .__runtime_defaults.cpu_transcoder_mask = \
 601                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 602                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 603                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 604         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
 605
 606 static const struct intel_display_device_info tgl_display = {
 607         XE_D_DISPLAY,
 608
 609         /*
 610          * FIXME DDI C/combo PHY C missing due to combo PHY
 611          * code making a mess on SKUs where the PHY is missing.
 612          */
 613         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
 614                 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
 615 };
 616
 617 static const struct intel_display_device_info dg1_display = {
 618         XE_D_DISPLAY,
 619
 620         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
 621                 BIT(PORT_TC1) | BIT(PORT_TC2),
 622 };
 623
 624 static const struct intel_display_device_info rkl_display = {
 625         XE_D_DISPLAY,
 626         .abox_mask = BIT(0),
 627         .has_hti = 1,
 628         .has_psr_hw_tracking = 0,
 629
 630         .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 631         .__runtime_defaults.cpu_transcoder_mask =
 632                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 633         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
 634                 BIT(PORT_TC1) | BIT(PORT_TC2),
 635 };
 636
 637 static const struct intel_display_device_info adl_s_display = {
 638         XE_D_DISPLAY,
 639         .has_hti = 1,
 640         .has_psr_hw_tracking = 0,
 641
 642         .__runtime_defaults.port_mask = BIT(PORT_A) |
 643                 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
 644 };
 645
 646 #define XE_LPD_FEATURES \
 647         .abox_mask = GENMASK(1, 0),                                             \
 648         .color = {                                                              \
 649                 .degamma_lut_size = 129, .gamma_lut_size = 1024,                \
 650                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |             \
 651                 DRM_COLOR_LUT_EQUAL_CHANNELS,                                   \
 652         },                                                                      \
 653         .dbuf.size = 4096,                                                      \
 654         .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |         \
 655                 BIT(DBUF_S4),                                                   \
 656         .has_ddi = 1,                                                           \
 657         .has_dp_mst = 1,                                                        \
 658         .has_dsb = 1,                                                           \
 659         .has_fpga_dbg = 1,                                                      \
 660         .has_hotplug = 1,                                                       \
 661         .has_ipc = 1,                                                           \
 662         .has_psr = 1,                                                           \
 663         .pipe_offsets = {                                                       \
 664                 [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
 665                 [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
 666                 [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
 667                 [TRANSCODER_D] = PIPE_D_OFFSET,                                 \
 668                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,                          \
 669                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,                          \
 670         },                                                                      \
 671         .trans_offsets = {                                                      \
 672                 [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
 673                 [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
 674                 [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
 675                 [TRANSCODER_D] = TRANSCODER_D_OFFSET,                           \
 676                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,                    \
 677                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,                    \
 678         },                                                                      \
 679         TGL_CURSOR_OFFSETS,                                                     \
 680                                                                                 \
 681         .__runtime_defaults.ip.ver = 13,                                        \
 682         .__runtime_defaults.has_dmc = 1,                                        \
 683         .__runtime_defaults.has_dsc = 1,                                        \
 684         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),                        \
 685         .__runtime_defaults.has_hdcp = 1,                                       \
 686         .__runtime_defaults.pipe_mask =                                         \
 687                 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
 688
 689 static const struct intel_display_device_info xe_lpd_display = {
 690         XE_LPD_FEATURES,
 691         .has_cdclk_crawl = 1,
 692         .has_psr_hw_tracking = 0,
 693
 694         .__runtime_defaults.cpu_transcoder_mask =
 695                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 696                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
 697                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
 698         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
 699                 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
 700 };
 701
 702 static const struct intel_display_device_info xe_hpd_display = {
 703         XE_LPD_FEATURES,
 704         .has_cdclk_squash = 1,
 705
 706         .__runtime_defaults.cpu_transcoder_mask =
 707                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 708                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 709         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
 710                 BIT(PORT_TC1),
 711 };
 712
 713 #define XE_LPDP_FEATURES                                                        \
 714         .abox_mask = GENMASK(1, 0),                                             \
 715         .color = {                                                              \
 716                 .degamma_lut_size = 129, .gamma_lut_size = 1024,                \
 717                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |             \
 718                 DRM_COLOR_LUT_EQUAL_CHANNELS,                                   \
 719         },                                                                      \
 720         .dbuf.size = 4096,                                                      \
 721         .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |         \
 722                 BIT(DBUF_S4),                                                   \
 723         .has_cdclk_crawl = 1,                                                   \
 724         .has_cdclk_squash = 1,                                                  \
 725         .has_ddi = 1,                                                           \
 726         .has_dp_mst = 1,                                                        \
 727         .has_dsb = 1,                                                           \
 728         .has_fpga_dbg = 1,                                                      \
 729         .has_hotplug = 1,                                                       \
 730         .has_ipc = 1,                                                           \
 731         .has_psr = 1,                                                           \
 732         .pipe_offsets = {                                                       \
 733                 [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
 734                 [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
 735                 [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
 736                 [TRANSCODER_D] = PIPE_D_OFFSET,                                 \
 737         },                                                                      \
 738         .trans_offsets = {                                                      \
 739                 [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
 740                 [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
 741                 [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
 742                 [TRANSCODER_D] = TRANSCODER_D_OFFSET,                           \
 743         },                                                                      \
 744         TGL_CURSOR_OFFSETS,                                                     \
 745                                                                                 \
 746         .__runtime_defaults.cpu_transcoder_mask =                               \
 747                 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |                         \
 748                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),                          \
 749         .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),     \
 750         .__runtime_defaults.has_dmc = 1,                                        \
 751         .__runtime_defaults.has_dsc = 1,                                        \
 752         .__runtime_defaults.has_hdcp = 1,                                       \
 753         .__runtime_defaults.pipe_mask =                                         \
 754                 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),          \
 755         .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |             \
 756                 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
 757
 758 static const struct intel_display_device_info xe_lpdp_display = {
 759         XE_LPDP_FEATURES,
 760 };
 761
 762 static const struct intel_display_device_info xe2_lpd_display = {
 763         XE_LPDP_FEATURES,
 764
 765         .__runtime_defaults.fbc_mask =
 766                 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
 767                 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
 768 };
 769
 770 /*
 771  * Separate detection for no display cases to keep the display id array simple.
 772  *
 773  * IVB Q requires subvendor and subdevice matching to differentiate from IVB D
 774  * GT2 server.
 775  */
 776 static bool has_no_display(struct pci_dev *pdev)
 777 {
 778         static const struct pci_device_id ids[] = {
 779                 INTEL_IVB_Q_IDS(0),
 780                 {}
 781         };
 782
 783         return pci_match_id(ids, pdev);
 784 }
 785
 786 #undef INTEL_VGA_DEVICE
 787 #define INTEL_VGA_DEVICE(id, info) { id, info }
 788
 789 static const struct {
 790         u32 devid;
 791         const struct intel_display_device_info *info;
 792 } intel_display_ids[] = {
 793         INTEL_I830_IDS(&i830_display),
 794         INTEL_I845G_IDS(&i845_display),
 795         INTEL_I85X_IDS(&i85x_display),
 796         INTEL_I865G_IDS(&i865g_display),
 797         INTEL_I915G_IDS(&i915g_display),
 798         INTEL_I915GM_IDS(&i915gm_display),
 799         INTEL_I945G_IDS(&i945g_display),
 800         INTEL_I945GM_IDS(&i945gm_display),
 801         INTEL_I965G_IDS(&i965g_display),
 802         INTEL_G33_IDS(&g33_display),
 803         INTEL_I965GM_IDS(&i965gm_display),
 804         INTEL_GM45_IDS(&gm45_display),
 805         INTEL_G45_IDS(&g45_display),
 806         INTEL_PINEVIEW_G_IDS(&pnv_display),
 807         INTEL_PINEVIEW_M_IDS(&pnv_display),
 808         INTEL_IRONLAKE_D_IDS(&ilk_d_display),
 809         INTEL_IRONLAKE_M_IDS(&ilk_m_display),
 810         INTEL_SNB_D_IDS(&snb_display),
 811         INTEL_SNB_M_IDS(&snb_display),
 812         INTEL_IVB_M_IDS(&ivb_display),
 813         INTEL_IVB_D_IDS(&ivb_display),
 814         INTEL_HSW_IDS(&hsw_display),
 815         INTEL_VLV_IDS(&vlv_display),
 816         INTEL_BDW_IDS(&bdw_display),
 817         INTEL_CHV_IDS(&chv_display),
 818         INTEL_SKL_IDS(&skl_display),
 819         INTEL_BXT_IDS(&bxt_display),
 820         INTEL_GLK_IDS(&glk_display),
 821         INTEL_KBL_IDS(&skl_display),
 822         INTEL_CFL_IDS(&skl_display),
 823         INTEL_ICL_11_IDS(&icl_display),
 824         INTEL_EHL_IDS(&jsl_ehl_display),
 825         INTEL_JSL_IDS(&jsl_ehl_display),
 826         INTEL_TGL_12_IDS(&tgl_display),
 827         INTEL_DG1_IDS(&dg1_display),
 828         INTEL_RKL_IDS(&rkl_display),
 829         INTEL_ADLS_IDS(&adl_s_display),
 830         INTEL_RPLS_IDS(&adl_s_display),
 831         INTEL_ADLP_IDS(&xe_lpd_display),
 832         INTEL_ADLN_IDS(&xe_lpd_display),
 833         INTEL_RPLP_IDS(&xe_lpd_display),
 834         INTEL_DG2_IDS(&xe_hpd_display),
 835
 836         /*
 837          * Do not add any GMD_ID-based platforms to this list.  They will
 838          * be probed automatically based on the IP version reported by
 839          * the hardware.
 840          */
 841 };
 842
 843 static const struct {
 844         u16 ver;
 845         u16 rel;
 846         const struct intel_display_device_info *display;
 847 } gmdid_display_map[] = {
 848         { 14,  0, &xe_lpdp_display },
 849         { 20,  0, &xe2_lpd_display },
 850 };
 851
 852 static const struct intel_display_device_info *
 853 probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step)
 854 {
 855         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 856         void __iomem *addr;
 857         u32 val;
 858         int i;
 859
 860         /* The caller expects to ver, rel and step to be initialized
 861          * here, and there's no good way to check when there was a
 862          * failure and no_display was returned.  So initialize all these
 863          * values here zero, to be sure.
 864          */
 865         *ver = 0;
 866         *rel = 0;
 867         *step = 0;
 868
 869         addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
 870         if (!addr) {
 871                 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
 872                 return &no_display;
 873         }
 874
 875         val = ioread32(addr);
 876         pci_iounmap(pdev, addr);
 877
 878         if (val == 0) {
 879                 drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
 880                 return &no_display;
 881         }
 882
 883         *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
 884         *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
 885         *step = REG_FIELD_GET(GMD_ID_STEP, val);
 886
 887         for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
 888                 if (*ver == gmdid_display_map[i].ver &&
 889                     *rel == gmdid_display_map[i].rel)
 890                         return gmdid_display_map[i].display;
 891
 892         drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
 893                 *ver, *rel);
 894         return &no_display;
 895 }
 896
 897 static const struct intel_display_device_info *
 898 probe_display(struct drm_i915_private *i915)
 899 {
 900         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 901         int i;
 902
 903         if (has_no_display(pdev)) {
 904                 drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
 905                 return &no_display;
 906         }
 907
 908         for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
 909                 if (intel_display_ids[i].devid == pdev->device)
 910                         return intel_display_ids[i].info;
 911         }
 912
 913         drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n",
 914                 pdev->device);
 915
 916         return &no_display;
 917 }
 918
 919 void intel_display_device_probe(struct drm_i915_private *i915)
 920 {
 921         const struct intel_display_device_info *info;
 922         u16 ver, rel, step;
 923
 924         if (HAS_GMD_ID(i915))
 925                 info = probe_gmdid_display(i915, &ver, &rel, &step);
 926         else
 927                 info = probe_display(i915);
 928
 929         DISPLAY_INFO(i915) = info;
 930
 931         memcpy(DISPLAY_RUNTIME_INFO(i915),
 932                &DISPLAY_INFO(i915)->__runtime_defaults,
 933                sizeof(*DISPLAY_RUNTIME_INFO(i915)));
 934
 935         if (HAS_GMD_ID(i915)) {
 936                 DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
 937                 DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
 938                 DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
 939         }
 940 }
 941
 942 static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915)
 943 {
 944         struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
 945         enum pipe pipe;
 946
 947         BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES);
 948         BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS);
 949         BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS);
 950
 951         /* This covers both ULT and ULX */
 952         if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915))
 953                 display_runtime->port_mask &= ~BIT(PORT_D);
 954
 955         if (IS_ICL_WITH_PORT_F(i915))
 956                 display_runtime->port_mask |= BIT(PORT_F);
 957
 958         /* Wa_14011765242: adl-s A0,A1 */
 959         if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
 960                 for_each_pipe(i915, pipe)
 961                         display_runtime->num_scalers[pipe] = 0;
 962         else if (DISPLAY_VER(i915) >= 11) {
 963                 for_each_pipe(i915, pipe)
 964                         display_runtime->num_scalers[pipe] = 2;
 965         } else if (DISPLAY_VER(i915) >= 9) {
 966                 display_runtime->num_scalers[PIPE_A] = 2;
 967                 display_runtime->num_scalers[PIPE_B] = 2;
 968                 display_runtime->num_scalers[PIPE_C] = 1;
 969         }
 970
 971         if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
 972                 for_each_pipe(i915, pipe)
 973                         display_runtime->num_sprites[pipe] = 4;
 974         else if (DISPLAY_VER(i915) >= 11)
 975                 for_each_pipe(i915, pipe)
 976                         display_runtime->num_sprites[pipe] = 6;
 977         else if (DISPLAY_VER(i915) == 10)
 978                 for_each_pipe(i915, pipe)
 979                         display_runtime->num_sprites[pipe] = 3;
 980         else if (IS_BROXTON(i915)) {
 981                 /*
 982                  * Skylake and Broxton currently don't expose the topmost plane as its
 983                  * use is exclusive with the legacy cursor and we only want to expose
 984                  * one of those, not both. Until we can safely expose the topmost plane
 985                  * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 986                  * we don't expose the topmost plane at all to prevent ABI breakage
 987                  * down the line.
 988                  */
 989
 990                 display_runtime->num_sprites[PIPE_A] = 2;
 991                 display_runtime->num_sprites[PIPE_B] = 2;
 992                 display_runtime->num_sprites[PIPE_C] = 1;
 993         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
 994                 for_each_pipe(i915, pipe)
 995                         display_runtime->num_sprites[pipe] = 2;
 996         } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) {
 997                 for_each_pipe(i915, pipe)
 998                         display_runtime->num_sprites[pipe] = 1;
 999         }
1000
1001         if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) &&
1002             !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) {
1003                 drm_info(&i915->drm, "Display not present, disabling\n");
1004                 goto display_fused_off;
1005         }
1006
1007         if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) {
1008                 u32 fuse_strap = intel_de_read(i915, FUSE_STRAP);
1009                 u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP);
1010
1011                 /*
1012                  * SFUSE_STRAP is supposed to have a bit signalling the display
1013                  * is fused off. Unfortunately it seems that, at least in
1014                  * certain cases, fused off display means that PCH display
1015                  * reads don't land anywhere. In that case, we read 0s.
1016                  *
1017                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1018                  * should be set when taking over after the firmware.
1019                  */
1020                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1021                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1022                     (HAS_PCH_CPT(i915) &&
1023                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1024                         drm_info(&i915->drm,
1025                                  "Display fused off, disabling\n");
1026                         goto display_fused_off;
1027                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
1028                         drm_info(&i915->drm, "PipeC fused off\n");
1029                         display_runtime->pipe_mask &= ~BIT(PIPE_C);
1030                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
1031                 }
1032         } else if (DISPLAY_VER(i915) >= 9) {
1033                 u32 dfsm = intel_de_read(i915, SKL_DFSM);
1034
1035                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
1036                         display_runtime->pipe_mask &= ~BIT(PIPE_A);
1037                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
1038                         display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
1039                 }
1040                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
1041                         display_runtime->pipe_mask &= ~BIT(PIPE_B);
1042                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
1043                         display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
1044                 }
1045                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
1046                         display_runtime->pipe_mask &= ~BIT(PIPE_C);
1047                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
1048                         display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
1049                 }
1050
1051                 if (DISPLAY_VER(i915) >= 12 &&
1052                     (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
1053                         display_runtime->pipe_mask &= ~BIT(PIPE_D);
1054                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
1055                         display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
1056                 }
1057
1058                 if (!display_runtime->pipe_mask)
1059                         goto display_fused_off;
1060
1061                 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
1062                         display_runtime->has_hdcp = 0;
1063
1064                 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
1065                         display_runtime->fbc_mask = 0;
1066
1067                 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
1068                         display_runtime->has_dmc = 0;
1069
1070                 if (IS_DISPLAY_VER(i915, 10, 12) &&
1071                     (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
1072                         display_runtime->has_dsc = 0;
1073         }
1074
1075         if (DISPLAY_VER(i915) >= 20) {
1076                 u32 cap = intel_de_read(i915, XE2LPD_DE_CAP);
1077
1078                 if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) ==
1079                     XE2LPD_DE_CAP_DSC_REMOVED)
1080                         display_runtime->has_dsc = 0;
1081
1082                 if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) ==
1083                     XE2LPD_DE_CAP_SCALER_SINGLE) {
1084                         for_each_pipe(i915, pipe)
1085                                 if (display_runtime->num_scalers[pipe])
1086                                         display_runtime->num_scalers[pipe] = 1;
1087                 }
1088         }
1089
1090         return;
1091
1092 display_fused_off:
1093         memset(display_runtime, 0, sizeof(*display_runtime));
1094 }
1095
1096 void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
1097 {
1098         if (HAS_DISPLAY(i915))
1099                 __intel_display_device_info_runtime_init(i915);
1100
1101         /* Display may have been disabled by runtime init */
1102         if (!HAS_DISPLAY(i915)) {
1103                 i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
1104                 i915->display.info.__device_info = &no_display;
1105         }
1106
1107         /* Disable nuclear pageflip by default on pre-g4x */
1108         if (!i915->params.nuclear_pageflip &&
1109             DISPLAY_VER(i915) < 5 && !IS_G4X(i915))
1110                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
1111 }
1112
1113 void intel_display_device_info_print(const struct intel_display_device_info *info,
1114                                      const struct intel_display_runtime_info *runtime,
1115                                      struct drm_printer *p)
1116 {
1117         if (runtime->ip.rel)
1118                 drm_printf(p, "display version: %u.%02u\n",
1119                            runtime->ip.ver,
1120                            runtime->ip.rel);
1121         else
1122                 drm_printf(p, "display version: %u\n",
1123                            runtime->ip.ver);
1124
1125 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
1126         DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
1127 #undef PRINT_FLAG
1128
1129         drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
1130         drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
1131         drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
1132 }
1133
1134 /*
1135  * Assuming the device has display hardware, should it be enabled?
1136  *
1137  * It's an error to call this function if the device does not have display
1138  * hardware.
1139  *
1140  * Disabling display means taking over the display hardware, putting it to
1141  * sleep, and preventing connectors from being connected via any means.
1142  */
1143 bool intel_display_device_enabled(struct drm_i915_private *i915)
1144 {
1145         /* Only valid when HAS_DISPLAY() is true */
1146         drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915));
1147
1148         return !i915->params.disable_display && !intel_opregion_headless_sku(i915);
1149 }