drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce/dce_8_0_d.h"
  27 #include "dce/dce_8_0_sh_mask.h"
  28
  29 #include "dm_services.h"
  30
  31 #include "link_encoder.h"
  32 #include "stream_encoder.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "irq/dce80/irq_service_dce80.h"
  37 #include "dce110/dce110_timing_generator.h"
  38 #include "dce110/dce110_resource.h"
  39 #include "dce80/dce80_timing_generator.h"
  40 #include "dce/dce_mem_input.h"
  41 #include "dce/dce_link_encoder.h"
  42 #include "dce/dce_stream_encoder.h"
  43 #include "dce/dce_ipp.h"
  44 #include "dce/dce_transform.h"
  45 #include "dce/dce_opp.h"
  46 #include "dce/dce_clock_source.h"
  47 #include "dce/dce_audio.h"
  48 #include "dce/dce_hwseq.h"
  49 #include "dce80/dce80_hwseq.h"
  50 #include "dce100/dce100_resource.h"
  51 #include "dce/dce_panel_cntl.h"
  52
  53 #include "reg_helper.h"
  54
  55 #include "dce/dce_dmcu.h"
  56 #include "dce/dce_aux.h"
  57 #include "dce/dce_abm.h"
  58 #include "dce/dce_i2c.h"
  59 /* TODO remove this include */
  60
  61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  62 #include "gmc/gmc_7_1_d.h"
  63 #include "gmc/gmc_7_1_sh_mask.h"
  64 #endif
  65
  66 #include "dce80/dce80_resource.h"
  67
  68 #ifndef mmDP_DPHY_INTERNAL_CTRL
  69 #define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
  70 #define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
  71 #define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
  72 #define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
  73 #define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
  74 #define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
  75 #define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
  76 #define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
  77 #endif
  78
  79
  80 #ifndef mmBIOS_SCRATCH_2
  81         #define mmBIOS_SCRATCH_2 0x05CB
  82         #define mmBIOS_SCRATCH_3 0x05CC
  83         #define mmBIOS_SCRATCH_6 0x05CF
  84 #endif
  85
  86 #ifndef mmDP_DPHY_FAST_TRAINING
  87         #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
  88         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
  89         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
  90         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
  91         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
  92         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
  93         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
  94         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
  95 #endif
  96
  97
  98 #ifndef mmHPD_DC_HPD_CONTROL
  99         #define mmHPD_DC_HPD_CONTROL                            0x189A
 100         #define mmHPD0_DC_HPD_CONTROL                           0x189A
 101         #define mmHPD1_DC_HPD_CONTROL                           0x18A2
 102         #define mmHPD2_DC_HPD_CONTROL                           0x18AA
 103         #define mmHPD3_DC_HPD_CONTROL                           0x18B2
 104         #define mmHPD4_DC_HPD_CONTROL                           0x18BA
 105         #define mmHPD5_DC_HPD_CONTROL                           0x18C2
 106 #endif
 107
 108 #define DCE11_DIG_FE_CNTL 0x4a00
 109 #define DCE11_DIG_BE_CNTL 0x4a47
 110 #define DCE11_DP_SEC 0x4ac3
 111
 112 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
 113                 {
 114                         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 115                         .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
 116                         .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
 117                                         - mmDPG_WATERMARK_MASK_CONTROL),
 118                 },
 119                 {
 120                         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 121                         .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 122                         .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
 123                                         - mmDPG_WATERMARK_MASK_CONTROL),
 124                 },
 125                 {
 126                         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 127                         .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 128                         .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
 129                                         - mmDPG_WATERMARK_MASK_CONTROL),
 130                 },
 131                 {
 132                         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 133                         .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 134                         .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
 135                                         - mmDPG_WATERMARK_MASK_CONTROL),
 136                 },
 137                 {
 138                         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 139                         .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 140                         .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
 141                                         - mmDPG_WATERMARK_MASK_CONTROL),
 142                 },
 143                 {
 144                         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 145                         .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 146                         .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
 147                                         - mmDPG_WATERMARK_MASK_CONTROL),
 148                 }
 149 };
 150
 151 /* set register offset */
 152 #define SR(reg_name)\
 153         .reg_name = mm ## reg_name
 154
 155 /* set register offset with instance */
 156 #define SRI(reg_name, block, id)\
 157         .reg_name = mm ## block ## id ## _ ## reg_name
 158
 159 #define ipp_regs(id)\
 160 [id] = {\
 161                 IPP_COMMON_REG_LIST_DCE_BASE(id)\
 162 }
 163
 164 static const struct dce_ipp_registers ipp_regs[] = {
 165                 ipp_regs(0),
 166                 ipp_regs(1),
 167                 ipp_regs(2),
 168                 ipp_regs(3),
 169                 ipp_regs(4),
 170                 ipp_regs(5)
 171 };
 172
 173 static const struct dce_ipp_shift ipp_shift = {
 174                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 175 };
 176
 177 static const struct dce_ipp_mask ipp_mask = {
 178                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 179 };
 180
 181 #define transform_regs(id)\
 182 [id] = {\
 183                 XFM_COMMON_REG_LIST_DCE80(id)\
 184 }
 185
 186 static const struct dce_transform_registers xfm_regs[] = {
 187                 transform_regs(0),
 188                 transform_regs(1),
 189                 transform_regs(2),
 190                 transform_regs(3),
 191                 transform_regs(4),
 192                 transform_regs(5)
 193 };
 194
 195 static const struct dce_transform_shift xfm_shift = {
 196                 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
 197 };
 198
 199 static const struct dce_transform_mask xfm_mask = {
 200                 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
 201 };
 202
 203 #define aux_regs(id)\
 204 [id] = {\
 205         AUX_REG_LIST(id)\
 206 }
 207
 208 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 209         aux_regs(0),
 210         aux_regs(1),
 211         aux_regs(2),
 212         aux_regs(3),
 213         aux_regs(4),
 214         aux_regs(5)
 215 };
 216
 217 #define hpd_regs(id)\
 218 [id] = {\
 219         HPD_REG_LIST(id)\
 220 }
 221
 222 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 223                 hpd_regs(0),
 224                 hpd_regs(1),
 225                 hpd_regs(2),
 226                 hpd_regs(3),
 227                 hpd_regs(4),
 228                 hpd_regs(5)
 229 };
 230
 231 #define link_regs(id)\
 232 [id] = {\
 233         LE_DCE80_REG_LIST(id)\
 234 }
 235
 236 static const struct dce110_link_enc_registers link_enc_regs[] = {
 237         link_regs(0),
 238         link_regs(1),
 239         link_regs(2),
 240         link_regs(3),
 241         link_regs(4),
 242         link_regs(5),
 243         link_regs(6),
 244 };
 245
 246 #define stream_enc_regs(id)\
 247 [id] = {\
 248         SE_COMMON_REG_LIST_DCE_BASE(id),\
 249         .AFMT_CNTL = 0,\
 250 }
 251
 252 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 253         stream_enc_regs(0),
 254         stream_enc_regs(1),
 255         stream_enc_regs(2),
 256         stream_enc_regs(3),
 257         stream_enc_regs(4),
 258         stream_enc_regs(5),
 259         stream_enc_regs(6)
 260 };
 261
 262 static const struct dce_stream_encoder_shift se_shift = {
 263                 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
 264 };
 265
 266 static const struct dce_stream_encoder_mask se_mask = {
 267                 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
 268 };
 269
 270 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 271         { DCE_PANEL_CNTL_REG_LIST() }
 272 };
 273
 274 static const struct dce_panel_cntl_shift panel_cntl_shift = {
 275         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 276 };
 277
 278 static const struct dce_panel_cntl_mask panel_cntl_mask = {
 279         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 280 };
 281
 282 #define opp_regs(id)\
 283 [id] = {\
 284         OPP_DCE_80_REG_LIST(id),\
 285 }
 286
 287 static const struct dce_opp_registers opp_regs[] = {
 288         opp_regs(0),
 289         opp_regs(1),
 290         opp_regs(2),
 291         opp_regs(3),
 292         opp_regs(4),
 293         opp_regs(5)
 294 };
 295
 296 static const struct dce_opp_shift opp_shift = {
 297         OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
 298 };
 299
 300 static const struct dce_opp_mask opp_mask = {
 301         OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
 302 };
 303
 304 static const struct dce110_aux_registers_shift aux_shift = {
 305         DCE10_AUX_MASK_SH_LIST(__SHIFT)
 306 };
 307
 308 static const struct dce110_aux_registers_mask aux_mask = {
 309         DCE10_AUX_MASK_SH_LIST(_MASK)
 310 };
 311
 312 #define aux_engine_regs(id)\
 313 [id] = {\
 314         AUX_COMMON_REG_LIST(id), \
 315         .AUX_RESET_MASK = 0 \
 316 }
 317
 318 static const struct dce110_aux_registers aux_engine_regs[] = {
 319                 aux_engine_regs(0),
 320                 aux_engine_regs(1),
 321                 aux_engine_regs(2),
 322                 aux_engine_regs(3),
 323                 aux_engine_regs(4),
 324                 aux_engine_regs(5)
 325 };
 326
 327 #define audio_regs(id)\
 328 [id] = {\
 329         AUD_COMMON_REG_LIST(id)\
 330 }
 331
 332 static const struct dce_audio_registers audio_regs[] = {
 333         audio_regs(0),
 334         audio_regs(1),
 335         audio_regs(2),
 336         audio_regs(3),
 337         audio_regs(4),
 338         audio_regs(5),
 339         audio_regs(6),
 340 };
 341
 342 static const struct dce_audio_shift audio_shift = {
 343                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 344 };
 345
 346 static const struct dce_audio_mask audio_mask = {
 347                 AUD_COMMON_MASK_SH_LIST(_MASK)
 348 };
 349
 350 #define clk_src_regs(id)\
 351 [id] = {\
 352         CS_COMMON_REG_LIST_DCE_80(id),\
 353 }
 354
 355
 356 static const struct dce110_clk_src_regs clk_src_regs[] = {
 357         clk_src_regs(0),
 358         clk_src_regs(1),
 359         clk_src_regs(2)
 360 };
 361
 362 static const struct dce110_clk_src_shift cs_shift = {
 363                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 364 };
 365
 366 static const struct dce110_clk_src_mask cs_mask = {
 367                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 368 };
 369
 370 static const struct bios_registers bios_regs = {
 371         .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 372         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 373 };
 374
 375 static const struct resource_caps res_cap = {
 376                 .num_timing_generator = 6,
 377                 .num_audio = 6,
 378                 .num_stream_encoder = 6,
 379                 .num_pll = 3,
 380                 .num_ddc = 6,
 381 };
 382
 383 static const struct resource_caps res_cap_81 = {
 384                 .num_timing_generator = 4,
 385                 .num_audio = 7,
 386                 .num_stream_encoder = 7,
 387                 .num_pll = 3,
 388                 .num_ddc = 6,
 389 };
 390
 391 static const struct resource_caps res_cap_83 = {
 392                 .num_timing_generator = 2,
 393                 .num_audio = 6,
 394                 .num_stream_encoder = 6,
 395                 .num_pll = 2,
 396                 .num_ddc = 2,
 397 };
 398
 399 static const struct dc_plane_cap plane_cap = {
 400         .type = DC_PLANE_TYPE_DCE_RGB,
 401
 402         .pixel_format_support = {
 403                         .argb8888 = true,
 404                         .nv12 = false,
 405                         .fp16 = true
 406         },
 407
 408         .max_upscale_factor = {
 409                         .argb8888 = 16000,
 410                         .nv12 = 1,
 411                         .fp16 = 1
 412         },
 413
 414         .max_downscale_factor = {
 415                         .argb8888 = 250,
 416                         .nv12 = 1,
 417                         .fp16 = 1
 418         }
 419 };
 420
 421 static const struct dc_debug_options debug_defaults = {
 422                 .enable_legacy_fast_update = true,
 423 };
 424
 425 static const struct dce_dmcu_registers dmcu_regs = {
 426                 DMCU_DCE80_REG_LIST()
 427 };
 428
 429 static const struct dce_dmcu_shift dmcu_shift = {
 430                 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
 431 };
 432
 433 static const struct dce_dmcu_mask dmcu_mask = {
 434                 DMCU_MASK_SH_LIST_DCE80(_MASK)
 435 };
 436 static const struct dce_abm_registers abm_regs = {
 437                 ABM_DCE110_COMMON_REG_LIST()
 438 };
 439
 440 static const struct dce_abm_shift abm_shift = {
 441                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 442 };
 443
 444 static const struct dce_abm_mask abm_mask = {
 445                 ABM_MASK_SH_LIST_DCE110(_MASK)
 446 };
 447
 448 #define CTX  ctx
 449 #define REG(reg) mm ## reg
 450
 451 #ifndef mmCC_DC_HDMI_STRAPS
 452 #define mmCC_DC_HDMI_STRAPS 0x1918
 453 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 454 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 455 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 456 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 457 #endif
 458
 459 static int map_transmitter_id_to_phy_instance(
 460         enum transmitter transmitter)
 461 {
 462         switch (transmitter) {
 463         case TRANSMITTER_UNIPHY_A:
 464                 return 0;
 465         case TRANSMITTER_UNIPHY_B:
 466                 return 1;
 467         case TRANSMITTER_UNIPHY_C:
 468                 return 2;
 469         case TRANSMITTER_UNIPHY_D:
 470                 return 3;
 471         case TRANSMITTER_UNIPHY_E:
 472                 return 4;
 473         case TRANSMITTER_UNIPHY_F:
 474                 return 5;
 475         case TRANSMITTER_UNIPHY_G:
 476                 return 6;
 477         default:
 478                 ASSERT(0);
 479                 return 0;
 480         }
 481 }
 482
 483 static void read_dce_straps(
 484         struct dc_context *ctx,
 485         struct resource_straps *straps)
 486 {
 487         REG_GET_2(CC_DC_HDMI_STRAPS,
 488                         HDMI_DISABLE, &straps->hdmi_disable,
 489                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 490
 491         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 492 }
 493
 494 static struct audio *create_audio(
 495                 struct dc_context *ctx, unsigned int inst)
 496 {
 497         return dce_audio_create(ctx, inst,
 498                         &audio_regs[inst], &audio_shift, &audio_mask);
 499 }
 500
 501 static struct timing_generator *dce80_timing_generator_create(
 502                 struct dc_context *ctx,
 503                 uint32_t instance,
 504                 const struct dce110_timing_generator_offsets *offsets)
 505 {
 506         struct dce110_timing_generator *tg110 =
 507                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 508
 509         if (!tg110)
 510                 return NULL;
 511
 512         dce80_timing_generator_construct(tg110, ctx, instance, offsets);
 513         return &tg110->base;
 514 }
 515
 516 static struct output_pixel_processor *dce80_opp_create(
 517         struct dc_context *ctx,
 518         uint32_t inst)
 519 {
 520         struct dce110_opp *opp =
 521                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 522
 523         if (!opp)
 524                 return NULL;
 525
 526         dce110_opp_construct(opp,
 527                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 528         return &opp->base;
 529 }
 530
 531 static struct dce_aux *dce80_aux_engine_create(
 532         struct dc_context *ctx,
 533         uint32_t inst)
 534 {
 535         struct aux_engine_dce110 *aux_engine =
 536                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 537
 538         if (!aux_engine)
 539                 return NULL;
 540
 541         dce110_aux_engine_construct(aux_engine, ctx, inst,
 542                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 543                                     &aux_engine_regs[inst],
 544                                         &aux_mask,
 545                                         &aux_shift,
 546                                         ctx->dc->caps.extended_aux_timeout_support);
 547
 548         return &aux_engine->base;
 549 }
 550 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 551
 552 static const struct dce_i2c_registers i2c_hw_regs[] = {
 553                 i2c_inst_regs(1),
 554                 i2c_inst_regs(2),
 555                 i2c_inst_regs(3),
 556                 i2c_inst_regs(4),
 557                 i2c_inst_regs(5),
 558                 i2c_inst_regs(6),
 559 };
 560
 561 static const struct dce_i2c_shift i2c_shifts = {
 562                 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 563 };
 564
 565 static const struct dce_i2c_mask i2c_masks = {
 566                 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 567 };
 568
 569 static struct dce_i2c_hw *dce80_i2c_hw_create(
 570         struct dc_context *ctx,
 571         uint32_t inst)
 572 {
 573         struct dce_i2c_hw *dce_i2c_hw =
 574                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 575
 576         if (!dce_i2c_hw)
 577                 return NULL;
 578
 579         dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 580                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 581
 582         return dce_i2c_hw;
 583 }
 584
 585 static struct dce_i2c_sw *dce80_i2c_sw_create(
 586         struct dc_context *ctx)
 587 {
 588         struct dce_i2c_sw *dce_i2c_sw =
 589                 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
 590
 591         if (!dce_i2c_sw)
 592                 return NULL;
 593
 594         dce_i2c_sw_construct(dce_i2c_sw, ctx);
 595
 596         return dce_i2c_sw;
 597 }
 598 static struct stream_encoder *dce80_stream_encoder_create(
 599         enum engine_id eng_id,
 600         struct dc_context *ctx)
 601 {
 602         struct dce110_stream_encoder *enc110 =
 603                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 604
 605         if (!enc110)
 606                 return NULL;
 607
 608         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 609                                         &stream_enc_regs[eng_id],
 610                                         &se_shift, &se_mask);
 611         return &enc110->base;
 612 }
 613
 614 #define SRII(reg_name, block, id)\
 615         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 616
 617 static const struct dce_hwseq_registers hwseq_reg = {
 618                 HWSEQ_DCE8_REG_LIST()
 619 };
 620
 621 static const struct dce_hwseq_shift hwseq_shift = {
 622                 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
 623 };
 624
 625 static const struct dce_hwseq_mask hwseq_mask = {
 626                 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
 627 };
 628
 629 static struct dce_hwseq *dce80_hwseq_create(
 630         struct dc_context *ctx)
 631 {
 632         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 633
 634         if (hws) {
 635                 hws->ctx = ctx;
 636                 hws->regs = &hwseq_reg;
 637                 hws->shifts = &hwseq_shift;
 638                 hws->masks = &hwseq_mask;
 639         }
 640         return hws;
 641 }
 642
 643 static const struct resource_create_funcs res_create_funcs = {
 644         .read_dce_straps = read_dce_straps,
 645         .create_audio = create_audio,
 646         .create_stream_encoder = dce80_stream_encoder_create,
 647         .create_hwseq = dce80_hwseq_create,
 648 };
 649
 650 #define mi_inst_regs(id) { \
 651         MI_DCE8_REG_LIST(id), \
 652         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 653 }
 654 static const struct dce_mem_input_registers mi_regs[] = {
 655                 mi_inst_regs(0),
 656                 mi_inst_regs(1),
 657                 mi_inst_regs(2),
 658                 mi_inst_regs(3),
 659                 mi_inst_regs(4),
 660                 mi_inst_regs(5),
 661 };
 662
 663 static const struct dce_mem_input_shift mi_shifts = {
 664                 MI_DCE8_MASK_SH_LIST(__SHIFT),
 665                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 666 };
 667
 668 static const struct dce_mem_input_mask mi_masks = {
 669                 MI_DCE8_MASK_SH_LIST(_MASK),
 670                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 671 };
 672
 673 static struct mem_input *dce80_mem_input_create(
 674         struct dc_context *ctx,
 675         uint32_t inst)
 676 {
 677         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 678                                                GFP_KERNEL);
 679
 680         if (!dce_mi) {
 681                 BREAK_TO_DEBUGGER();
 682                 return NULL;
 683         }
 684
 685         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 686         dce_mi->wa.single_head_rdreq_dmif_limit = 2;
 687         return &dce_mi->base;
 688 }
 689
 690 static void dce80_transform_destroy(struct transform **xfm)
 691 {
 692         kfree(TO_DCE_TRANSFORM(*xfm));
 693         *xfm = NULL;
 694 }
 695
 696 static struct transform *dce80_transform_create(
 697         struct dc_context *ctx,
 698         uint32_t inst)
 699 {
 700         struct dce_transform *transform =
 701                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 702
 703         if (!transform)
 704                 return NULL;
 705
 706         dce_transform_construct(transform, ctx, inst,
 707                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 708         transform->prescaler_on = false;
 709         return &transform->base;
 710 }
 711
 712 static const struct encoder_feature_support link_enc_feature = {
 713                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 714                 .max_hdmi_pixel_clock = 297000,
 715                 .flags.bits.IS_HBR2_CAPABLE = true,
 716                 .flags.bits.IS_TPS3_CAPABLE = true
 717 };
 718
 719 static struct link_encoder *dce80_link_encoder_create(
 720         struct dc_context *ctx,
 721         const struct encoder_init_data *enc_init_data)
 722 {
 723         struct dce110_link_encoder *enc110 =
 724                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 725         int link_regs_id;
 726
 727         if (!enc110)
 728                 return NULL;
 729
 730         link_regs_id =
 731                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
 732
 733         dce110_link_encoder_construct(enc110,
 734                                       enc_init_data,
 735                                       &link_enc_feature,
 736                                       &link_enc_regs[link_regs_id],
 737                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 738                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 739         return &enc110->base;
 740 }
 741
 742 static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 743 {
 744         struct dce_panel_cntl *panel_cntl =
 745                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 746
 747         if (!panel_cntl)
 748                 return NULL;
 749
 750         dce_panel_cntl_construct(panel_cntl,
 751                         init_data,
 752                         &panel_cntl_regs[init_data->inst],
 753                         &panel_cntl_shift,
 754                         &panel_cntl_mask);
 755
 756         return &panel_cntl->base;
 757 }
 758
 759 static struct clock_source *dce80_clock_source_create(
 760         struct dc_context *ctx,
 761         struct dc_bios *bios,
 762         enum clock_source_id id,
 763         const struct dce110_clk_src_regs *regs,
 764         bool dp_clk_src)
 765 {
 766         struct dce110_clk_src *clk_src =
 767                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 768
 769         if (!clk_src)
 770                 return NULL;
 771
 772         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 773                         regs, &cs_shift, &cs_mask)) {
 774                 clk_src->base.dp_clk_src = dp_clk_src;
 775                 return &clk_src->base;
 776         }
 777
 778         kfree(clk_src);
 779         BREAK_TO_DEBUGGER();
 780         return NULL;
 781 }
 782
 783 static void dce80_clock_source_destroy(struct clock_source **clk_src)
 784 {
 785         kfree(TO_DCE110_CLK_SRC(*clk_src));
 786         *clk_src = NULL;
 787 }
 788
 789 static struct input_pixel_processor *dce80_ipp_create(
 790         struct dc_context *ctx, uint32_t inst)
 791 {
 792         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 793
 794         if (!ipp) {
 795                 BREAK_TO_DEBUGGER();
 796                 return NULL;
 797         }
 798
 799         dce_ipp_construct(ipp, ctx, inst,
 800                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 801         return &ipp->base;
 802 }
 803
 804 static void dce80_resource_destruct(struct dce110_resource_pool *pool)
 805 {
 806         unsigned int i;
 807
 808         for (i = 0; i < pool->base.pipe_count; i++) {
 809                 if (pool->base.opps[i] != NULL)
 810                         dce110_opp_destroy(&pool->base.opps[i]);
 811
 812                 if (pool->base.transforms[i] != NULL)
 813                         dce80_transform_destroy(&pool->base.transforms[i]);
 814
 815                 if (pool->base.ipps[i] != NULL)
 816                         dce_ipp_destroy(&pool->base.ipps[i]);
 817
 818                 if (pool->base.mis[i] != NULL) {
 819                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 820                         pool->base.mis[i] = NULL;
 821                 }
 822
 823                 if (pool->base.timing_generators[i] != NULL)    {
 824                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 825                         pool->base.timing_generators[i] = NULL;
 826                 }
 827         }
 828
 829         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 830                 if (pool->base.engines[i] != NULL)
 831                         dce110_engine_destroy(&pool->base.engines[i]);
 832                 if (pool->base.hw_i2cs[i] != NULL) {
 833                         kfree(pool->base.hw_i2cs[i]);
 834                         pool->base.hw_i2cs[i] = NULL;
 835                 }
 836                 if (pool->base.sw_i2cs[i] != NULL) {
 837                         kfree(pool->base.sw_i2cs[i]);
 838                         pool->base.sw_i2cs[i] = NULL;
 839                 }
 840         }
 841
 842         for (i = 0; i < pool->base.stream_enc_count; i++) {
 843                 if (pool->base.stream_enc[i] != NULL)
 844                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 845         }
 846
 847         for (i = 0; i < pool->base.clk_src_count; i++) {
 848                 if (pool->base.clock_sources[i] != NULL) {
 849                         dce80_clock_source_destroy(&pool->base.clock_sources[i]);
 850                 }
 851         }
 852
 853         if (pool->base.abm != NULL)
 854                         dce_abm_destroy(&pool->base.abm);
 855
 856         if (pool->base.dmcu != NULL)
 857                         dce_dmcu_destroy(&pool->base.dmcu);
 858
 859         if (pool->base.dp_clock_source != NULL)
 860                 dce80_clock_source_destroy(&pool->base.dp_clock_source);
 861
 862         for (i = 0; i < pool->base.audio_count; i++)    {
 863                 if (pool->base.audios[i] != NULL) {
 864                         dce_aud_destroy(&pool->base.audios[i]);
 865                 }
 866         }
 867
 868         if (pool->base.irqs != NULL) {
 869                 dal_irq_service_destroy(&pool->base.irqs);
 870         }
 871 }
 872
 873 static bool dce80_validate_bandwidth(
 874         struct dc *dc,
 875         struct dc_state *context,
 876         bool fast_validate)
 877 {
 878         int i;
 879         bool at_least_one_pipe = false;
 880
 881         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 882                 if (context->res_ctx.pipe_ctx[i].stream)
 883                         at_least_one_pipe = true;
 884         }
 885
 886         if (at_least_one_pipe) {
 887                 /* TODO implement when needed but for now hardcode max value*/
 888                 context->bw_ctx.bw.dce.dispclk_khz = 681000;
 889                 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
 890         } else {
 891                 context->bw_ctx.bw.dce.dispclk_khz = 0;
 892                 context->bw_ctx.bw.dce.yclk_khz = 0;
 893         }
 894
 895         return true;
 896 }
 897
 898 static bool dce80_validate_surface_sets(
 899                 struct dc_state *context)
 900 {
 901         int i;
 902
 903         for (i = 0; i < context->stream_count; i++) {
 904                 if (context->stream_status[i].plane_count == 0)
 905                         continue;
 906
 907                 if (context->stream_status[i].plane_count > 1)
 908                         return false;
 909
 910                 if (context->stream_status[i].plane_states[0]->format
 911                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 912                         return false;
 913         }
 914
 915         return true;
 916 }
 917
 918 static enum dc_status dce80_validate_global(
 919                 struct dc *dc,
 920                 struct dc_state *context)
 921 {
 922         if (!dce80_validate_surface_sets(context))
 923                 return DC_FAIL_SURFACE_VALIDATE;
 924
 925         return DC_OK;
 926 }
 927
 928 static void dce80_destroy_resource_pool(struct resource_pool **pool)
 929 {
 930         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 931
 932         dce80_resource_destruct(dce110_pool);
 933         kfree(dce110_pool);
 934         *pool = NULL;
 935 }
 936
 937 static const struct resource_funcs dce80_res_pool_funcs = {
 938         .destroy = dce80_destroy_resource_pool,
 939         .link_enc_create = dce80_link_encoder_create,
 940         .panel_cntl_create = dce80_panel_cntl_create,
 941         .validate_bandwidth = dce80_validate_bandwidth,
 942         .validate_plane = dce100_validate_plane,
 943         .add_stream_to_ctx = dce100_add_stream_to_ctx,
 944         .validate_global = dce80_validate_global,
 945         .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
 946 };
 947
 948 static bool dce80_construct(
 949         uint8_t num_virtual_links,
 950         struct dc *dc,
 951         struct dce110_resource_pool *pool)
 952 {
 953         unsigned int i;
 954         struct dc_context *ctx = dc->ctx;
 955         struct dc_bios *bp;
 956
 957         ctx->dc_bios->regs = &bios_regs;
 958
 959         pool->base.res_cap = &res_cap;
 960         pool->base.funcs = &dce80_res_pool_funcs;
 961
 962
 963         /*************************************************
 964          *  Resource + asic cap harcoding                *
 965          *************************************************/
 966         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 967         pool->base.pipe_count = res_cap.num_timing_generator;
 968         pool->base.timing_generator_count = res_cap.num_timing_generator;
 969         dc->caps.max_downscale_ratio = 200;
 970         dc->caps.i2c_speed_in_khz = 40;
 971         dc->caps.i2c_speed_in_khz_hdcp = 40;
 972         dc->caps.max_cursor_size = 128;
 973         dc->caps.min_horizontal_blanking_period = 80;
 974         dc->caps.dual_link_dvi = true;
 975         dc->caps.extended_aux_timeout_support = false;
 976         dc->debug = debug_defaults;
 977
 978         /*************************************************
 979          *  Create resources                             *
 980          *************************************************/
 981
 982         bp = ctx->dc_bios;
 983
 984         if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
 985                 pool->base.dp_clock_source =
 986                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
 987
 988                 pool->base.clock_sources[0] =
 989                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
 990                 pool->base.clock_sources[1] =
 991                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 992                 pool->base.clock_sources[2] =
 993                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 994                 pool->base.clk_src_count = 3;
 995
 996         } else {
 997                 pool->base.dp_clock_source =
 998                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
 999
1000                 pool->base.clock_sources[0] =
1001                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1002                 pool->base.clock_sources[1] =
1003                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1004                 pool->base.clk_src_count = 2;
1005         }
1006
1007         if (pool->base.dp_clock_source == NULL) {
1008                 dm_error("DC: failed to create dp clock source!\n");
1009                 BREAK_TO_DEBUGGER();
1010                 goto res_create_fail;
1011         }
1012
1013         for (i = 0; i < pool->base.clk_src_count; i++) {
1014                 if (pool->base.clock_sources[i] == NULL) {
1015                         dm_error("DC: failed to create clock sources!\n");
1016                         BREAK_TO_DEBUGGER();
1017                         goto res_create_fail;
1018                 }
1019         }
1020
1021         pool->base.dmcu = dce_dmcu_create(ctx,
1022                         &dmcu_regs,
1023                         &dmcu_shift,
1024                         &dmcu_mask);
1025         if (pool->base.dmcu == NULL) {
1026                 dm_error("DC: failed to create dmcu!\n");
1027                 BREAK_TO_DEBUGGER();
1028                 goto res_create_fail;
1029         }
1030
1031         pool->base.abm = dce_abm_create(ctx,
1032                         &abm_regs,
1033                         &abm_shift,
1034                         &abm_mask);
1035         if (pool->base.abm == NULL) {
1036                 dm_error("DC: failed to create abm!\n");
1037                 BREAK_TO_DEBUGGER();
1038                 goto res_create_fail;
1039         }
1040
1041         {
1042                 struct irq_service_init_data init_data;
1043                 init_data.ctx = dc->ctx;
1044                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1045                 if (!pool->base.irqs)
1046                         goto res_create_fail;
1047         }
1048
1049         for (i = 0; i < pool->base.pipe_count; i++) {
1050                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1051                                 ctx, i, &dce80_tg_offsets[i]);
1052                 if (pool->base.timing_generators[i] == NULL) {
1053                         BREAK_TO_DEBUGGER();
1054                         dm_error("DC: failed to create tg!\n");
1055                         goto res_create_fail;
1056                 }
1057
1058                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1059                 if (pool->base.mis[i] == NULL) {
1060                         BREAK_TO_DEBUGGER();
1061                         dm_error("DC: failed to create memory input!\n");
1062                         goto res_create_fail;
1063                 }
1064
1065                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1066                 if (pool->base.ipps[i] == NULL) {
1067                         BREAK_TO_DEBUGGER();
1068                         dm_error("DC: failed to create input pixel processor!\n");
1069                         goto res_create_fail;
1070                 }
1071
1072                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1073                 if (pool->base.transforms[i] == NULL) {
1074                         BREAK_TO_DEBUGGER();
1075                         dm_error("DC: failed to create transform!\n");
1076                         goto res_create_fail;
1077                 }
1078
1079                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1080                 if (pool->base.opps[i] == NULL) {
1081                         BREAK_TO_DEBUGGER();
1082                         dm_error("DC: failed to create output pixel processor!\n");
1083                         goto res_create_fail;
1084                 }
1085         }
1086
1087         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1088                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1089                 if (pool->base.engines[i] == NULL) {
1090                         BREAK_TO_DEBUGGER();
1091                         dm_error(
1092                                 "DC:failed to create aux engine!!\n");
1093                         goto res_create_fail;
1094                 }
1095                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1096                 if (pool->base.hw_i2cs[i] == NULL) {
1097                         BREAK_TO_DEBUGGER();
1098                         dm_error(
1099                                 "DC:failed to create i2c engine!!\n");
1100                         goto res_create_fail;
1101                 }
1102                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1103                 if (pool->base.sw_i2cs[i] == NULL) {
1104                         BREAK_TO_DEBUGGER();
1105                         dm_error(
1106                                 "DC:failed to create sw i2c!!\n");
1107                         goto res_create_fail;
1108                 }
1109         }
1110
1111         dc->caps.max_planes =  pool->base.pipe_count;
1112
1113         for (i = 0; i < dc->caps.max_planes; ++i)
1114                 dc->caps.planes[i] = plane_cap;
1115
1116         dc->caps.disable_dp_clk_share = true;
1117
1118         if (!resource_construct(num_virtual_links, dc, &pool->base,
1119                         &res_create_funcs))
1120                 goto res_create_fail;
1121
1122         /* Create hardware sequencer */
1123         dce80_hw_sequencer_construct(dc);
1124
1125         return true;
1126
1127 res_create_fail:
1128         dce80_resource_destruct(pool);
1129         return false;
1130 }
1131
1132 struct resource_pool *dce80_create_resource_pool(
1133         uint8_t num_virtual_links,
1134         struct dc *dc)
1135 {
1136         struct dce110_resource_pool *pool =
1137                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1138
1139         if (!pool)
1140                 return NULL;
1141
1142         if (dce80_construct(num_virtual_links, dc, pool))
1143                 return &pool->base;
1144
1145         kfree(pool);
1146         BREAK_TO_DEBUGGER();
1147         return NULL;
1148 }
1149
1150 static bool dce81_construct(
1151         uint8_t num_virtual_links,
1152         struct dc *dc,
1153         struct dce110_resource_pool *pool)
1154 {
1155         unsigned int i;
1156         struct dc_context *ctx = dc->ctx;
1157         struct dc_bios *bp;
1158
1159         ctx->dc_bios->regs = &bios_regs;
1160
1161         pool->base.res_cap = &res_cap_81;
1162         pool->base.funcs = &dce80_res_pool_funcs;
1163
1164
1165         /*************************************************
1166          *  Resource + asic cap harcoding                *
1167          *************************************************/
1168         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1169         pool->base.pipe_count = res_cap_81.num_timing_generator;
1170         pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1171         dc->caps.max_downscale_ratio = 200;
1172         dc->caps.i2c_speed_in_khz = 40;
1173         dc->caps.i2c_speed_in_khz_hdcp = 40;
1174         dc->caps.max_cursor_size = 128;
1175         dc->caps.min_horizontal_blanking_period = 80;
1176         dc->caps.is_apu = true;
1177
1178         /*************************************************
1179          *  Create resources                             *
1180          *************************************************/
1181
1182         bp = ctx->dc_bios;
1183
1184         if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1185                 pool->base.dp_clock_source =
1186                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1187
1188                 pool->base.clock_sources[0] =
1189                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1190                 pool->base.clock_sources[1] =
1191                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1192                 pool->base.clock_sources[2] =
1193                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1194                 pool->base.clk_src_count = 3;
1195
1196         } else {
1197                 pool->base.dp_clock_source =
1198                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1199
1200                 pool->base.clock_sources[0] =
1201                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1202                 pool->base.clock_sources[1] =
1203                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1204                 pool->base.clk_src_count = 2;
1205         }
1206
1207         if (pool->base.dp_clock_source == NULL) {
1208                 dm_error("DC: failed to create dp clock source!\n");
1209                 BREAK_TO_DEBUGGER();
1210                 goto res_create_fail;
1211         }
1212
1213         for (i = 0; i < pool->base.clk_src_count; i++) {
1214                 if (pool->base.clock_sources[i] == NULL) {
1215                         dm_error("DC: failed to create clock sources!\n");
1216                         BREAK_TO_DEBUGGER();
1217                         goto res_create_fail;
1218                 }
1219         }
1220
1221         pool->base.dmcu = dce_dmcu_create(ctx,
1222                         &dmcu_regs,
1223                         &dmcu_shift,
1224                         &dmcu_mask);
1225         if (pool->base.dmcu == NULL) {
1226                 dm_error("DC: failed to create dmcu!\n");
1227                 BREAK_TO_DEBUGGER();
1228                 goto res_create_fail;
1229         }
1230
1231         pool->base.abm = dce_abm_create(ctx,
1232                         &abm_regs,
1233                         &abm_shift,
1234                         &abm_mask);
1235         if (pool->base.abm == NULL) {
1236                 dm_error("DC: failed to create abm!\n");
1237                 BREAK_TO_DEBUGGER();
1238                 goto res_create_fail;
1239         }
1240
1241         {
1242                 struct irq_service_init_data init_data;
1243                 init_data.ctx = dc->ctx;
1244                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1245                 if (!pool->base.irqs)
1246                         goto res_create_fail;
1247         }
1248
1249         for (i = 0; i < pool->base.pipe_count; i++) {
1250                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1251                                 ctx, i, &dce80_tg_offsets[i]);
1252                 if (pool->base.timing_generators[i] == NULL) {
1253                         BREAK_TO_DEBUGGER();
1254                         dm_error("DC: failed to create tg!\n");
1255                         goto res_create_fail;
1256                 }
1257
1258                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1259                 if (pool->base.mis[i] == NULL) {
1260                         BREAK_TO_DEBUGGER();
1261                         dm_error("DC: failed to create memory input!\n");
1262                         goto res_create_fail;
1263                 }
1264
1265                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1266                 if (pool->base.ipps[i] == NULL) {
1267                         BREAK_TO_DEBUGGER();
1268                         dm_error("DC: failed to create input pixel processor!\n");
1269                         goto res_create_fail;
1270                 }
1271
1272                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1273                 if (pool->base.transforms[i] == NULL) {
1274                         BREAK_TO_DEBUGGER();
1275                         dm_error("DC: failed to create transform!\n");
1276                         goto res_create_fail;
1277                 }
1278
1279                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1280                 if (pool->base.opps[i] == NULL) {
1281                         BREAK_TO_DEBUGGER();
1282                         dm_error("DC: failed to create output pixel processor!\n");
1283                         goto res_create_fail;
1284                 }
1285         }
1286
1287         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1288                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1289                 if (pool->base.engines[i] == NULL) {
1290                         BREAK_TO_DEBUGGER();
1291                         dm_error(
1292                                 "DC:failed to create aux engine!!\n");
1293                         goto res_create_fail;
1294                 }
1295                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1296                 if (pool->base.hw_i2cs[i] == NULL) {
1297                         BREAK_TO_DEBUGGER();
1298                         dm_error(
1299                                 "DC:failed to create i2c engine!!\n");
1300                         goto res_create_fail;
1301                 }
1302                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1303                 if (pool->base.sw_i2cs[i] == NULL) {
1304                         BREAK_TO_DEBUGGER();
1305                         dm_error(
1306                                 "DC:failed to create sw i2c!!\n");
1307                         goto res_create_fail;
1308                 }
1309         }
1310
1311         dc->caps.max_planes =  pool->base.pipe_count;
1312
1313         for (i = 0; i < dc->caps.max_planes; ++i)
1314                 dc->caps.planes[i] = plane_cap;
1315
1316         dc->caps.disable_dp_clk_share = true;
1317
1318         if (!resource_construct(num_virtual_links, dc, &pool->base,
1319                         &res_create_funcs))
1320                 goto res_create_fail;
1321
1322         /* Create hardware sequencer */
1323         dce80_hw_sequencer_construct(dc);
1324
1325         return true;
1326
1327 res_create_fail:
1328         dce80_resource_destruct(pool);
1329         return false;
1330 }
1331
1332 struct resource_pool *dce81_create_resource_pool(
1333         uint8_t num_virtual_links,
1334         struct dc *dc)
1335 {
1336         struct dce110_resource_pool *pool =
1337                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1338
1339         if (!pool)
1340                 return NULL;
1341
1342         if (dce81_construct(num_virtual_links, dc, pool))
1343                 return &pool->base;
1344
1345         kfree(pool);
1346         BREAK_TO_DEBUGGER();
1347         return NULL;
1348 }
1349
1350 static bool dce83_construct(
1351         uint8_t num_virtual_links,
1352         struct dc *dc,
1353         struct dce110_resource_pool *pool)
1354 {
1355         unsigned int i;
1356         struct dc_context *ctx = dc->ctx;
1357         struct dc_bios *bp;
1358
1359         ctx->dc_bios->regs = &bios_regs;
1360
1361         pool->base.res_cap = &res_cap_83;
1362         pool->base.funcs = &dce80_res_pool_funcs;
1363
1364
1365         /*************************************************
1366          *  Resource + asic cap harcoding                *
1367          *************************************************/
1368         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1369         pool->base.pipe_count = res_cap_83.num_timing_generator;
1370         pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1371         dc->caps.max_downscale_ratio = 200;
1372         dc->caps.i2c_speed_in_khz = 40;
1373         dc->caps.i2c_speed_in_khz_hdcp = 40;
1374         dc->caps.max_cursor_size = 128;
1375         dc->caps.min_horizontal_blanking_period = 80;
1376         dc->caps.is_apu = true;
1377         dc->debug = debug_defaults;
1378
1379         /*************************************************
1380          *  Create resources                             *
1381          *************************************************/
1382
1383         bp = ctx->dc_bios;
1384
1385         if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1386                 pool->base.dp_clock_source =
1387                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1388
1389                 pool->base.clock_sources[0] =
1390                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1391                 pool->base.clock_sources[1] =
1392                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1393                 pool->base.clk_src_count = 2;
1394
1395         } else {
1396                 pool->base.dp_clock_source =
1397                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1398
1399                 pool->base.clock_sources[0] =
1400                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1401                 pool->base.clk_src_count = 1;
1402         }
1403
1404         if (pool->base.dp_clock_source == NULL) {
1405                 dm_error("DC: failed to create dp clock source!\n");
1406                 BREAK_TO_DEBUGGER();
1407                 goto res_create_fail;
1408         }
1409
1410         for (i = 0; i < pool->base.clk_src_count; i++) {
1411                 if (pool->base.clock_sources[i] == NULL) {
1412                         dm_error("DC: failed to create clock sources!\n");
1413                         BREAK_TO_DEBUGGER();
1414                         goto res_create_fail;
1415                 }
1416         }
1417
1418         pool->base.dmcu = dce_dmcu_create(ctx,
1419                         &dmcu_regs,
1420                         &dmcu_shift,
1421                         &dmcu_mask);
1422         if (pool->base.dmcu == NULL) {
1423                 dm_error("DC: failed to create dmcu!\n");
1424                 BREAK_TO_DEBUGGER();
1425                 goto res_create_fail;
1426         }
1427
1428         pool->base.abm = dce_abm_create(ctx,
1429                         &abm_regs,
1430                         &abm_shift,
1431                         &abm_mask);
1432         if (pool->base.abm == NULL) {
1433                 dm_error("DC: failed to create abm!\n");
1434                 BREAK_TO_DEBUGGER();
1435                 goto res_create_fail;
1436         }
1437
1438         {
1439                 struct irq_service_init_data init_data;
1440                 init_data.ctx = dc->ctx;
1441                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1442                 if (!pool->base.irqs)
1443                         goto res_create_fail;
1444         }
1445
1446         for (i = 0; i < pool->base.pipe_count; i++) {
1447                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1448                                 ctx, i, &dce80_tg_offsets[i]);
1449                 if (pool->base.timing_generators[i] == NULL) {
1450                         BREAK_TO_DEBUGGER();
1451                         dm_error("DC: failed to create tg!\n");
1452                         goto res_create_fail;
1453                 }
1454
1455                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1456                 if (pool->base.mis[i] == NULL) {
1457                         BREAK_TO_DEBUGGER();
1458                         dm_error("DC: failed to create memory input!\n");
1459                         goto res_create_fail;
1460                 }
1461
1462                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1463                 if (pool->base.ipps[i] == NULL) {
1464                         BREAK_TO_DEBUGGER();
1465                         dm_error("DC: failed to create input pixel processor!\n");
1466                         goto res_create_fail;
1467                 }
1468
1469                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1470                 if (pool->base.transforms[i] == NULL) {
1471                         BREAK_TO_DEBUGGER();
1472                         dm_error("DC: failed to create transform!\n");
1473                         goto res_create_fail;
1474                 }
1475
1476                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1477                 if (pool->base.opps[i] == NULL) {
1478                         BREAK_TO_DEBUGGER();
1479                         dm_error("DC: failed to create output pixel processor!\n");
1480                         goto res_create_fail;
1481                 }
1482         }
1483
1484         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1485                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1486                 if (pool->base.engines[i] == NULL) {
1487                         BREAK_TO_DEBUGGER();
1488                         dm_error(
1489                                 "DC:failed to create aux engine!!\n");
1490                         goto res_create_fail;
1491                 }
1492                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1493                 if (pool->base.hw_i2cs[i] == NULL) {
1494                         BREAK_TO_DEBUGGER();
1495                         dm_error(
1496                                 "DC:failed to create i2c engine!!\n");
1497                         goto res_create_fail;
1498                 }
1499                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1500                 if (pool->base.sw_i2cs[i] == NULL) {
1501                         BREAK_TO_DEBUGGER();
1502                         dm_error(
1503                                 "DC:failed to create sw i2c!!\n");
1504                         goto res_create_fail;
1505                 }
1506         }
1507
1508         dc->caps.max_planes =  pool->base.pipe_count;
1509
1510         for (i = 0; i < dc->caps.max_planes; ++i)
1511                 dc->caps.planes[i] = plane_cap;
1512
1513         dc->caps.disable_dp_clk_share = true;
1514
1515         if (!resource_construct(num_virtual_links, dc, &pool->base,
1516                         &res_create_funcs))
1517                 goto res_create_fail;
1518
1519         /* Create hardware sequencer */
1520         dce80_hw_sequencer_construct(dc);
1521
1522         return true;
1523
1524 res_create_fail:
1525         dce80_resource_destruct(pool);
1526         return false;
1527 }
1528
1529 struct resource_pool *dce83_create_resource_pool(
1530         uint8_t num_virtual_links,
1531         struct dc *dc)
1532 {
1533         struct dce110_resource_pool *pool =
1534                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1535
1536         if (!pool)
1537                 return NULL;
1538
1539         if (dce83_construct(num_virtual_links, dc, pool))
1540                 return &pool->base;
1541
1542         BREAK_TO_DEBUGGER();
1543         return NULL;
1544 }