drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "amdgpu.h"
  28
  29 #include "dc.h"
  30
  31 #include "core_status.h"
  32 #include "core_types.h"
  33 #include "hw_sequencer.h"
  34 #include "dce/dce_hwseq.h"
  35
  36 #include "resource.h"
  37
  38 #include "gpio_service_interface.h"
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "bios/bios_parser_helper.h"
  45 #include "include/irq_service_interface.h"
  46 #include "transform.h"
  47 #include "dmcu.h"
  48 #include "dpp.h"
  49 #include "timing_generator.h"
  50 #include "abm.h"
  51 #include "virtual/virtual_link_encoder.h"
  52 #include "hubp.h"
  53
  54 #include "link_hwss.h"
  55 #include "link_encoder.h"
  56 #include "link_enc_cfg.h"
  57
  58 #include "link.h"
  59 #include "dm_helpers.h"
  60 #include "mem_input.h"
  61
  62 #include "dc_dmub_srv.h"
  63
  64 #include "dsc.h"
  65
  66 #include "vm_helper.h"
  67
  68 #include "dce/dce_i2c.h"
  69
  70 #include "dmub/dmub_srv.h"
  71
  72 #include "dce/dmub_psr.h"
  73
  74 #include "dce/dmub_hw_lock_mgr.h"
  75
  76 #include "dc_trace.h"
  77
  78 #include "hw_sequencer_private.h"
  79
  80 #include "dml2/dml2_internal_types.h"
  81
  82 #include "dce/dmub_outbox.h"
  83
  84 #define CTX \
  85         dc->ctx
  86
  87 #define DC_LOGGER \
  88         dc->ctx->logger
  89
  90 static const char DC_BUILD_ID[] = "production-build";
  91
  92 /**
  93  * DOC: Overview
  94  *
  95  * DC is the OS-agnostic component of the amdgpu DC driver.
  96  *
  97  * DC maintains and validates a set of structs representing the state of the
  98  * driver and writes that state to AMD hardware
  99  *
 100  * Main DC HW structs:
 101  *
 102  * struct dc - The central struct.  One per driver.  Created on driver load,
 103  * destroyed on driver unload.
 104  *
 105  * struct dc_context - One per driver.
 106  * Used as a backpointer by most other structs in dc.
 107  *
 108  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 109  * plugpoints).  Created on driver load, destroyed on driver unload.
 110  *
 111  * struct dc_sink - One per display.  Created on boot or hotplug.
 112  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 113  * (the display directly attached).  It may also have one or more remote
 114  * sinks (in the Multi-Stream Transport case)
 115  *
 116  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 117  * main pipeline.  Not directly accessible by dm.
 118  *
 119  * Main dc state structs:
 120  *
 121  * These structs can be created and destroyed as needed.  There is a full set of
 122  * these structs in dc->current_state representing the currently programmed state.
 123  *
 124  * struct dc_state - The global DC state to track global state information,
 125  * such as bandwidth values.
 126  *
 127  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 128  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 129  *
 130  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 131  * and may have more in the Multi-Plane Overlay case.
 132  *
 133  * struct resource_context - Represents the programmable state of everything in
 134  * the resource_pool.  Not directly accessible by dm.
 135  *
 136  * struct pipe_ctx - A member of struct resource_context.  Represents the
 137  * internal hardware pipeline components.  Each dc_plane_state has either
 138  * one or two (in the pipe-split case).
 139  */
 140
 141 /* Private functions */
 142
 143 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 144 {
 145         if (new > *original)
 146                 *original = new;
 147 }
 148
 149 static void destroy_links(struct dc *dc)
 150 {
 151         uint32_t i;
 152
 153         for (i = 0; i < dc->link_count; i++) {
 154                 if (NULL != dc->links[i])
 155                         dc->link_srv->destroy_link(&dc->links[i]);
 156         }
 157 }
 158
 159 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 160 {
 161         int i;
 162         uint32_t count = 0;
 163
 164         for (i = 0; i < num_links; i++) {
 165                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 166                                 links[i]->is_internal_display)
 167                         count++;
 168         }
 169
 170         return count;
 171 }
 172
 173 static int get_seamless_boot_stream_count(struct dc_state *ctx)
 174 {
 175         uint8_t i;
 176         uint8_t seamless_boot_stream_count = 0;
 177
 178         for (i = 0; i < ctx->stream_count; i++)
 179                 if (ctx->streams[i]->apply_seamless_boot_optimization)
 180                         seamless_boot_stream_count++;
 181
 182         return seamless_boot_stream_count;
 183 }
 184
 185 static bool create_links(
 186                 struct dc *dc,
 187                 uint32_t num_virtual_links)
 188 {
 189         int i;
 190         int connectors_num;
 191         struct dc_bios *bios = dc->ctx->dc_bios;
 192
 193         dc->link_count = 0;
 194
 195         connectors_num = bios->funcs->get_connectors_number(bios);
 196
 197         DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
 198
 199         if (connectors_num > ENUM_ID_COUNT) {
 200                 dm_error(
 201                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 202                         connectors_num,
 203                         ENUM_ID_COUNT);
 204                 return false;
 205         }
 206
 207         dm_output_to_console(
 208                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 209                 __func__,
 210                 connectors_num,
 211                 num_virtual_links);
 212
 213         for (i = 0; i < connectors_num; i++) {
 214                 struct link_init_data link_init_params = {0};
 215                 struct dc_link *link;
 216
 217                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 218
 219                 link_init_params.ctx = dc->ctx;
 220                 /* next BIOS object table connector */
 221                 link_init_params.connector_index = i;
 222                 link_init_params.link_index = dc->link_count;
 223                 link_init_params.dc = dc;
 224                 link = dc->link_srv->create_link(&link_init_params);
 225
 226                 if (link) {
 227                         dc->links[dc->link_count] = link;
 228                         link->dc = dc;
 229                         ++dc->link_count;
 230                 }
 231         }
 232
 233         DC_LOG_DC("BIOS object table - end");
 234
 235         /* Create a link for each usb4 dpia port */
 236         for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {
 237                 struct link_init_data link_init_params = {0};
 238                 struct dc_link *link;
 239
 240                 link_init_params.ctx = dc->ctx;
 241                 link_init_params.connector_index = i;
 242                 link_init_params.link_index = dc->link_count;
 243                 link_init_params.dc = dc;
 244                 link_init_params.is_dpia_link = true;
 245
 246                 link = dc->link_srv->create_link(&link_init_params);
 247                 if (link) {
 248                         dc->links[dc->link_count] = link;
 249                         link->dc = dc;
 250                         ++dc->link_count;
 251                 }
 252         }
 253
 254         for (i = 0; i < num_virtual_links; i++) {
 255                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 256                 struct encoder_init_data enc_init = {0};
 257
 258                 if (link == NULL) {
 259                         BREAK_TO_DEBUGGER();
 260                         goto failed_alloc;
 261                 }
 262
 263                 link->link_index = dc->link_count;
 264                 dc->links[dc->link_count] = link;
 265                 dc->link_count++;
 266
 267                 link->ctx = dc->ctx;
 268                 link->dc = dc;
 269                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 270                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 271                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 272                 link->link_id.enum_id = ENUM_ID_1;
 273                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 274
 275                 if (!link->link_enc) {
 276                         BREAK_TO_DEBUGGER();
 277                         goto failed_alloc;
 278                 }
 279
 280                 link->link_status.dpcd_caps = &link->dpcd_caps;
 281
 282                 enc_init.ctx = dc->ctx;
 283                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 284                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 285                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 286                 enc_init.connector = link->link_id;
 287                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 288                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 289                 enc_init.encoder.enum_id = ENUM_ID_1;
 290                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 291         }
 292
 293         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 294
 295         return true;
 296
 297 failed_alloc:
 298         return false;
 299 }
 300
 301 /* Create additional DIG link encoder objects if fewer than the platform
 302  * supports were created during link construction. This can happen if the
 303  * number of physical connectors is less than the number of DIGs.
 304  */
 305 static bool create_link_encoders(struct dc *dc)
 306 {
 307         bool res = true;
 308         unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 309         unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 310         int i;
 311
 312         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 313          * link encoders and physical display endpoints and does not require
 314          * additional link encoder objects.
 315          */
 316         if (num_usb4_dpia == 0)
 317                 return res;
 318
 319         /* Create as many link encoder objects as the platform supports. DPIA
 320          * endpoints can be programmably mapped to any DIG.
 321          */
 322         if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {
 323                 for (i = 0; i < num_dig_link_enc; i++) {
 324                         struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 325
 326                         if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {
 327                                 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,
 328                                                 (enum engine_id)(ENGINE_ID_DIGA + i));
 329                                 if (link_enc) {
 330                                         dc->res_pool->link_encoders[i] = link_enc;
 331                                         dc->res_pool->dig_link_enc_count++;
 332                                 } else {
 333                                         res = false;
 334                                 }
 335                         }
 336                 }
 337         }
 338
 339         return res;
 340 }
 341
 342 /* Destroy any additional DIG link encoder objects created by
 343  * create_link_encoders().
 344  * NB: Must only be called after destroy_links().
 345  */
 346 static void destroy_link_encoders(struct dc *dc)
 347 {
 348         unsigned int num_usb4_dpia;
 349         unsigned int num_dig_link_enc;
 350         int i;
 351
 352         if (!dc->res_pool)
 353                 return;
 354
 355         num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 356         num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 357
 358         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 359          * link encoders and physical display endpoints and does not require
 360          * additional link encoder objects.
 361          */
 362         if (num_usb4_dpia == 0)
 363                 return;
 364
 365         for (i = 0; i < num_dig_link_enc; i++) {
 366                 struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 367
 368                 if (link_enc) {
 369                         link_enc->funcs->destroy(&link_enc);
 370                         dc->res_pool->link_encoders[i] = NULL;
 371                         dc->res_pool->dig_link_enc_count--;
 372                 }
 373         }
 374 }
 375
 376 static struct dc_perf_trace *dc_perf_trace_create(void)
 377 {
 378         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 379 }
 380
 381 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 382 {
 383         kfree(*perf_trace);
 384         *perf_trace = NULL;
 385 }
 386
 387 /**
 388  *  dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
 389  *  @dc:     dc reference
 390  *  @stream: Initial dc stream state
 391  *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
 392  *
 393  *  Looks up the pipe context of dc_stream_state and updates the
 394  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 395  *  Rate, which is a power-saving feature that targets reducing panel
 396  *  refresh rate while the screen is static
 397  *
 398  *  Return: %true if the pipe context is found and adjusted;
 399  *          %false if the pipe context is not found.
 400  */
 401 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 402                 struct dc_stream_state *stream,
 403                 struct dc_crtc_timing_adjust *adjust)
 404 {
 405         int i;
 406
 407         /*
 408          * Don't adjust DRR while there's bandwidth optimizations pending to
 409          * avoid conflicting with firmware updates.
 410          */
 411         if (dc->ctx->dce_version > DCE_VERSION_MAX)
 412                 if (dc->optimized_required || dc->wm_optimized_required)
 413                         return false;
 414
 415         stream->adjust.v_total_max = adjust->v_total_max;
 416         stream->adjust.v_total_mid = adjust->v_total_mid;
 417         stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
 418         stream->adjust.v_total_min = adjust->v_total_min;
 419
 420         for (i = 0; i < MAX_PIPES; i++) {
 421                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 422
 423                 if (pipe->stream == stream && pipe->stream_res.tg) {
 424                         dc->hwss.set_drr(&pipe,
 425                                         1,
 426                                         *adjust);
 427
 428                         return true;
 429                 }
 430         }
 431         return false;
 432 }
 433
 434 /**
 435  * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of
 436  * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate)
 437  *
 438  * @dc: [in] dc reference
 439  * @stream: [in] Initial dc stream state
 440  * @refresh_rate: [in] new refresh_rate
 441  *
 442  * Return: %true if the pipe context is found and there is an associated
 443  *         timing_generator for the DC;
 444  *         %false if the pipe context is not found or there is no
 445  *         timing_generator for the DC.
 446  */
 447 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
 448                 struct dc_stream_state *stream,
 449                 uint32_t *refresh_rate)
 450 {
 451         bool status = false;
 452
 453         int i = 0;
 454
 455         for (i = 0; i < MAX_PIPES; i++) {
 456                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 457
 458                 if (pipe->stream == stream && pipe->stream_res.tg) {
 459                         /* Only execute if a function pointer has been defined for
 460                          * the DC version in question
 461                          */
 462                         if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
 463                                 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
 464
 465                                 status = true;
 466
 467                                 break;
 468                         }
 469                 }
 470         }
 471
 472         return status;
 473 }
 474
 475 bool dc_stream_get_crtc_position(struct dc *dc,
 476                 struct dc_stream_state **streams, int num_streams,
 477                 unsigned int *v_pos, unsigned int *nom_v_pos)
 478 {
 479         /* TODO: Support multiple streams */
 480         const struct dc_stream_state *stream = streams[0];
 481         int i;
 482         bool ret = false;
 483         struct crtc_position position;
 484
 485         for (i = 0; i < MAX_PIPES; i++) {
 486                 struct pipe_ctx *pipe =
 487                                 &dc->current_state->res_ctx.pipe_ctx[i];
 488
 489                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 490                         dc->hwss.get_position(&pipe, 1, &position);
 491
 492                         *v_pos = position.vertical_count;
 493                         *nom_v_pos = position.nominal_vcount;
 494                         ret = true;
 495                 }
 496         }
 497         return ret;
 498 }
 499
 500 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 501 static inline void
 502 dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,
 503                 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
 504 {
 505         union dmub_rb_cmd cmd = {0};
 506
 507         cmd.secure_display.roi_info.phy_id = mux_mapping->phy_output_num;
 508         cmd.secure_display.roi_info.otg_id = mux_mapping->otg_output_num;
 509
 510         if (is_stop) {
 511                 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
 512                 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE;
 513         } else {
 514                 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
 515                 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY;
 516                 cmd.secure_display.roi_info.x_start = rect->x;
 517                 cmd.secure_display.roi_info.y_start = rect->y;
 518                 cmd.secure_display.roi_info.x_end = rect->x + rect->width;
 519                 cmd.secure_display.roi_info.y_end = rect->y + rect->height;
 520         }
 521
 522         dm_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 523 }
 524
 525 static inline void
 526 dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,
 527                 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
 528 {
 529         if (is_stop)
 530                 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
 531         else
 532                 dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);
 533 }
 534
 535 bool
 536 dc_stream_forward_crc_window(struct dc_stream_state *stream,
 537                 struct rect *rect, bool is_stop)
 538 {
 539         struct dmcu *dmcu;
 540         struct dc_dmub_srv *dmub_srv;
 541         struct otg_phy_mux mux_mapping;
 542         struct pipe_ctx *pipe;
 543         int i;
 544         struct dc *dc = stream->ctx->dc;
 545
 546         for (i = 0; i < MAX_PIPES; i++) {
 547                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 548                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 549                         break;
 550         }
 551
 552         /* Stream not found */
 553         if (i == MAX_PIPES)
 554                 return false;
 555
 556         mux_mapping.phy_output_num = stream->link->link_enc_hw_inst;
 557         mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
 558
 559         dmcu = dc->res_pool->dmcu;
 560         dmub_srv = dc->ctx->dmub_srv;
 561
 562         /* forward to dmub */
 563         if (dmub_srv)
 564                 dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);
 565         /* forward to dmcu */
 566         else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
 567                 dc_stream_forward_dmcu_crc_window(dmcu, rect, &mux_mapping, is_stop);
 568         else
 569                 return false;
 570
 571         return true;
 572 }
 573 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 574
 575 /**
 576  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 577  * @dc: DC Object
 578  * @stream: The stream to configure CRC on.
 579  * @enable: Enable CRC if true, disable otherwise.
 580  * @crc_window: CRC window (x/y start/end) information
 581  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 582  *              once.
 583  *
 584  * By default, only CRC0 is configured, and the entire frame is used to
 585  * calculate the CRC.
 586  *
 587  * Return: %false if the stream is not found or CRC capture is not supported;
 588  *         %true if the stream has been configured.
 589  */
 590 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 591                              struct crc_params *crc_window, bool enable, bool continuous)
 592 {
 593         struct pipe_ctx *pipe;
 594         struct crc_params param;
 595         struct timing_generator *tg;
 596
 597         pipe = resource_get_otg_master_for_stream(
 598                         &dc->current_state->res_ctx, stream);
 599
 600         /* Stream not found */
 601         if (pipe == NULL)
 602                 return false;
 603
 604         /* By default, capture the full frame */
 605         param.windowa_x_start = 0;
 606         param.windowa_y_start = 0;
 607         param.windowa_x_end = pipe->stream->timing.h_addressable;
 608         param.windowa_y_end = pipe->stream->timing.v_addressable;
 609         param.windowb_x_start = 0;
 610         param.windowb_y_start = 0;
 611         param.windowb_x_end = pipe->stream->timing.h_addressable;
 612         param.windowb_y_end = pipe->stream->timing.v_addressable;
 613
 614         if (crc_window) {
 615                 param.windowa_x_start = crc_window->windowa_x_start;
 616                 param.windowa_y_start = crc_window->windowa_y_start;
 617                 param.windowa_x_end = crc_window->windowa_x_end;
 618                 param.windowa_y_end = crc_window->windowa_y_end;
 619                 param.windowb_x_start = crc_window->windowb_x_start;
 620                 param.windowb_y_start = crc_window->windowb_y_start;
 621                 param.windowb_x_end = crc_window->windowb_x_end;
 622                 param.windowb_y_end = crc_window->windowb_y_end;
 623         }
 624
 625         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 626         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 627
 628         /* Default to the union of both windows */
 629         param.selection = UNION_WINDOW_A_B;
 630         param.continuous_mode = continuous;
 631         param.enable = enable;
 632
 633         tg = pipe->stream_res.tg;
 634
 635         /* Only call if supported */
 636         if (tg->funcs->configure_crc)
 637                 return tg->funcs->configure_crc(tg, &param);
 638         DC_LOG_WARNING("CRC capture not supported.");
 639         return false;
 640 }
 641
 642 /**
 643  * dc_stream_get_crc() - Get CRC values for the given stream.
 644  *
 645  * @dc: DC object.
 646  * @stream: The DC stream state of the stream to get CRCs from.
 647  * @r_cr: CRC value for the red component.
 648  * @g_y:  CRC value for the green component.
 649  * @b_cb: CRC value for the blue component.
 650  *
 651  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 652  *
 653  * Return:
 654  * %false if stream is not found, or if CRCs are not enabled.
 655  */
 656 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 657                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 658 {
 659         int i;
 660         struct pipe_ctx *pipe;
 661         struct timing_generator *tg;
 662
 663         for (i = 0; i < MAX_PIPES; i++) {
 664                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 665                 if (pipe->stream == stream)
 666                         break;
 667         }
 668         /* Stream not found */
 669         if (i == MAX_PIPES)
 670                 return false;
 671
 672         tg = pipe->stream_res.tg;
 673
 674         if (tg->funcs->get_crc)
 675                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 676         DC_LOG_WARNING("CRC capture not supported.");
 677         return false;
 678 }
 679
 680 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 681                 enum dc_dynamic_expansion option)
 682 {
 683         /* OPP FMT dyn expansion updates*/
 684         int i;
 685         struct pipe_ctx *pipe_ctx;
 686
 687         for (i = 0; i < MAX_PIPES; i++) {
 688                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 689                                 == stream) {
 690                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 691                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 692                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 693                                         pipe_ctx->stream_res.opp,
 694                                         COLOR_SPACE_YCBCR601,
 695                                         stream->timing.display_color_depth,
 696                                         stream->signal);
 697                 }
 698         }
 699 }
 700
 701 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 702                 enum dc_dither_option option)
 703 {
 704         struct bit_depth_reduction_params params;
 705         struct dc_link *link = stream->link;
 706         struct pipe_ctx *pipes = NULL;
 707         int i;
 708
 709         for (i = 0; i < MAX_PIPES; i++) {
 710                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 711                                 stream) {
 712                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 713                         break;
 714                 }
 715         }
 716
 717         if (!pipes)
 718                 return;
 719         if (option > DITHER_OPTION_MAX)
 720                 return;
 721
 722         stream->dither_option = option;
 723
 724         memset(&params, 0, sizeof(params));
 725         resource_build_bit_depth_reduction_params(stream, &params);
 726         stream->bit_depth_params = params;
 727
 728         if (pipes->plane_res.xfm &&
 729             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 730                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 731                         pipes->plane_res.xfm,
 732                         pipes->plane_res.scl_data.lb_params.depth,
 733                         &stream->bit_depth_params);
 734         }
 735
 736         pipes->stream_res.opp->funcs->
 737                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 738 }
 739
 740 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 741 {
 742         int i;
 743         bool ret = false;
 744         struct pipe_ctx *pipes;
 745
 746         for (i = 0; i < MAX_PIPES; i++) {
 747                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 748                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 749                         dc->hwss.program_gamut_remap(pipes);
 750                         ret = true;
 751                 }
 752         }
 753
 754         return ret;
 755 }
 756
 757 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 758 {
 759         int i;
 760         bool ret = false;
 761         struct pipe_ctx *pipes;
 762
 763         for (i = 0; i < MAX_PIPES; i++) {
 764                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 765                                 == stream) {
 766
 767                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 768                         dc->hwss.program_output_csc(dc,
 769                                         pipes,
 770                                         stream->output_color_space,
 771                                         stream->csc_color_matrix.matrix,
 772                                         pipes->stream_res.opp->inst);
 773                         ret = true;
 774                 }
 775         }
 776
 777         return ret;
 778 }
 779
 780 void dc_stream_set_static_screen_params(struct dc *dc,
 781                 struct dc_stream_state **streams,
 782                 int num_streams,
 783                 const struct dc_static_screen_params *params)
 784 {
 785         int i, j;
 786         struct pipe_ctx *pipes_affected[MAX_PIPES];
 787         int num_pipes_affected = 0;
 788
 789         for (i = 0; i < num_streams; i++) {
 790                 struct dc_stream_state *stream = streams[i];
 791
 792                 for (j = 0; j < MAX_PIPES; j++) {
 793                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 794                                         == stream) {
 795                                 pipes_affected[num_pipes_affected++] =
 796                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 797                         }
 798                 }
 799         }
 800
 801         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 802 }
 803
 804 static void dc_destruct(struct dc *dc)
 805 {
 806         // reset link encoder assignment table on destruct
 807         if (dc->res_pool && dc->res_pool->funcs->link_encs_assign)
 808                 link_enc_cfg_init(dc, dc->current_state);
 809
 810         if (dc->current_state) {
 811                 dc_release_state(dc->current_state);
 812                 dc->current_state = NULL;
 813         }
 814
 815         destroy_links(dc);
 816
 817         destroy_link_encoders(dc);
 818
 819         if (dc->clk_mgr) {
 820                 dc_destroy_clk_mgr(dc->clk_mgr);
 821                 dc->clk_mgr = NULL;
 822         }
 823
 824         dc_destroy_resource_pool(dc);
 825
 826         if (dc->link_srv)
 827                 link_destroy_link_service(&dc->link_srv);
 828
 829         if (dc->ctx->gpio_service)
 830                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 831
 832         if (dc->ctx->created_bios)
 833                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 834
 835         kfree(dc->ctx->logger);
 836         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 837
 838         kfree(dc->ctx);
 839         dc->ctx = NULL;
 840
 841         kfree(dc->bw_vbios);
 842         dc->bw_vbios = NULL;
 843
 844         kfree(dc->bw_dceip);
 845         dc->bw_dceip = NULL;
 846
 847         kfree(dc->dcn_soc);
 848         dc->dcn_soc = NULL;
 849
 850         kfree(dc->dcn_ip);
 851         dc->dcn_ip = NULL;
 852
 853         kfree(dc->vm_helper);
 854         dc->vm_helper = NULL;
 855
 856 }
 857
 858 static bool dc_construct_ctx(struct dc *dc,
 859                 const struct dc_init_data *init_params)
 860 {
 861         struct dc_context *dc_ctx;
 862
 863         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 864         if (!dc_ctx)
 865                 return false;
 866
 867         dc_ctx->cgs_device = init_params->cgs_device;
 868         dc_ctx->driver_context = init_params->driver;
 869         dc_ctx->dc = dc;
 870         dc_ctx->asic_id = init_params->asic_id;
 871         dc_ctx->dc_sink_id_count = 0;
 872         dc_ctx->dc_stream_id_count = 0;
 873         dc_ctx->dce_environment = init_params->dce_environment;
 874         dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
 875         dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
 876         dc_ctx->clk_reg_offsets = init_params->clk_reg_offsets;
 877
 878         /* Create logger */
 879         dc_ctx->logger = kmalloc(sizeof(*dc_ctx->logger), GFP_KERNEL);
 880
 881         if (!dc_ctx->logger) {
 882                 kfree(dc_ctx);
 883                 return false;
 884         }
 885
 886         dc_ctx->logger->dev = adev_to_drm(init_params->driver);
 887         dc->dml.logger = dc_ctx->logger;
 888
 889         dc_ctx->dce_version = resource_parse_asic_id(init_params->asic_id);
 890
 891         dc_ctx->perf_trace = dc_perf_trace_create();
 892         if (!dc_ctx->perf_trace) {
 893                 kfree(dc_ctx);
 894                 ASSERT_CRITICAL(false);
 895                 return false;
 896         }
 897
 898         dc->ctx = dc_ctx;
 899
 900         dc->link_srv = link_create_link_service();
 901         if (!dc->link_srv)
 902                 return false;
 903
 904         return true;
 905 }
 906
 907 static bool dc_construct(struct dc *dc,
 908                 const struct dc_init_data *init_params)
 909 {
 910         struct dc_context *dc_ctx;
 911         struct bw_calcs_dceip *dc_dceip;
 912         struct bw_calcs_vbios *dc_vbios;
 913         struct dcn_soc_bounding_box *dcn_soc;
 914         struct dcn_ip_params *dcn_ip;
 915
 916         dc->config = init_params->flags;
 917
 918         // Allocate memory for the vm_helper
 919         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 920         if (!dc->vm_helper) {
 921                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 922                 goto fail;
 923         }
 924
 925         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 926
 927         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 928         if (!dc_dceip) {
 929                 dm_error("%s: failed to create dceip\n", __func__);
 930                 goto fail;
 931         }
 932
 933         dc->bw_dceip = dc_dceip;
 934
 935         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 936         if (!dc_vbios) {
 937                 dm_error("%s: failed to create vbios\n", __func__);
 938                 goto fail;
 939         }
 940
 941         dc->bw_vbios = dc_vbios;
 942         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 943         if (!dcn_soc) {
 944                 dm_error("%s: failed to create dcn_soc\n", __func__);
 945                 goto fail;
 946         }
 947
 948         dc->dcn_soc = dcn_soc;
 949
 950         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 951         if (!dcn_ip) {
 952                 dm_error("%s: failed to create dcn_ip\n", __func__);
 953                 goto fail;
 954         }
 955
 956         dc->dcn_ip = dcn_ip;
 957
 958         if (!dc_construct_ctx(dc, init_params)) {
 959                 dm_error("%s: failed to create ctx\n", __func__);
 960                 goto fail;
 961         }
 962
 963         dc_ctx = dc->ctx;
 964
 965         /* Resource should construct all asic specific resources.
 966          * This should be the only place where we need to parse the asic id
 967          */
 968         if (init_params->vbios_override)
 969                 dc_ctx->dc_bios = init_params->vbios_override;
 970         else {
 971                 /* Create BIOS parser */
 972                 struct bp_init_data bp_init_data;
 973
 974                 bp_init_data.ctx = dc_ctx;
 975                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 976
 977                 dc_ctx->dc_bios = dal_bios_parser_create(
 978                                 &bp_init_data, dc_ctx->dce_version);
 979
 980                 if (!dc_ctx->dc_bios) {
 981                         ASSERT_CRITICAL(false);
 982                         goto fail;
 983                 }
 984
 985                 dc_ctx->created_bios = true;
 986         }
 987
 988         dc->vendor_signature = init_params->vendor_signature;
 989
 990         /* Create GPIO service */
 991         dc_ctx->gpio_service = dal_gpio_service_create(
 992                         dc_ctx->dce_version,
 993                         dc_ctx->dce_environment,
 994                         dc_ctx);
 995
 996         if (!dc_ctx->gpio_service) {
 997                 ASSERT_CRITICAL(false);
 998                 goto fail;
 999         }
1000
1001         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
1002         if (!dc->res_pool)
1003                 goto fail;
1004
1005         /* set i2c speed if not done by the respective dcnxxx__resource.c */
1006         if (dc->caps.i2c_speed_in_khz_hdcp == 0)
1007                 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
1008         if (dc->caps.max_optimizable_video_width == 0)
1009                 dc->caps.max_optimizable_video_width = 5120;
1010         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
1011         if (!dc->clk_mgr)
1012                 goto fail;
1013 #ifdef CONFIG_DRM_AMD_DC_FP
1014         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
1015
1016         if (dc->res_pool->funcs->update_bw_bounding_box) {
1017                 DC_FP_START();
1018                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
1019                 DC_FP_END();
1020         }
1021 #endif
1022
1023         /* Creation of current_state must occur after dc->dml
1024          * is initialized in dc_create_resource_pool because
1025          * on creation it copies the contents of dc->dml
1026          */
1027
1028         dc->current_state = dc_create_state(dc);
1029
1030         if (!dc->current_state) {
1031                 dm_error("%s: failed to create validate ctx\n", __func__);
1032                 goto fail;
1033         }
1034
1035         if (!create_links(dc, init_params->num_virtual_links))
1036                 goto fail;
1037
1038         /* Create additional DIG link encoder objects if fewer than the platform
1039          * supports were created during link construction.
1040          */
1041         if (!create_link_encoders(dc))
1042                 goto fail;
1043
1044         dc_resource_state_construct(dc, dc->current_state);
1045
1046         return true;
1047
1048 fail:
1049         return false;
1050 }
1051
1052 static void disable_all_writeback_pipes_for_stream(
1053                 const struct dc *dc,
1054                 struct dc_stream_state *stream,
1055                 struct dc_state *context)
1056 {
1057         int i;
1058
1059         for (i = 0; i < stream->num_wb_info; i++)
1060                 stream->writeback_info[i].wb_enabled = false;
1061 }
1062
1063 static void apply_ctx_interdependent_lock(struct dc *dc,
1064                                           struct dc_state *context,
1065                                           struct dc_stream_state *stream,
1066                                           bool lock)
1067 {
1068         int i;
1069
1070         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
1071         if (dc->hwss.interdependent_update_lock)
1072                 dc->hwss.interdependent_update_lock(dc, context, lock);
1073         else {
1074                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1075                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1076                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1077
1078                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
1079                         if (stream == pipe_ctx->stream) {
1080                                 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) &&
1081                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
1082                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
1083                         }
1084                 }
1085         }
1086 }
1087
1088 static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1089 {
1090         if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1091                 memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));
1092
1093                 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
1094                         get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1095                 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1096                         get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1097                 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
1098                         get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1099                 else {
1100                         if (dc->ctx->dce_version < DCN_VERSION_2_0)
1101                                 color_space_to_black_color(
1102                                         dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));
1103                 }
1104                 if (dc->ctx->dce_version >= DCN_VERSION_2_0) {
1105                         if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
1106                                 get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1107                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
1108                                 get_subvp_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1109                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)
1110                                 get_mclk_switch_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1111                 }
1112         }
1113 }
1114
1115 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
1116 {
1117         int i, j;
1118         struct dc_state *dangling_context = dc_create_state(dc);
1119         struct dc_state *current_ctx;
1120         struct pipe_ctx *pipe;
1121         struct timing_generator *tg;
1122
1123         if (dangling_context == NULL)
1124                 return;
1125
1126         dc_resource_state_copy_construct(dc->current_state, dangling_context);
1127
1128         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1129                 struct dc_stream_state *old_stream =
1130                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
1131                 bool should_disable = true;
1132                 bool pipe_split_change = false;
1133
1134                 if ((context->res_ctx.pipe_ctx[i].top_pipe) &&
1135                         (dc->current_state->res_ctx.pipe_ctx[i].top_pipe))
1136                         pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=
1137                                 dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;
1138                 else
1139                         pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=
1140                                 dc->current_state->res_ctx.pipe_ctx[i].top_pipe;
1141
1142                 for (j = 0; j < context->stream_count; j++) {
1143                         if (old_stream == context->streams[j]) {
1144                                 should_disable = false;
1145                                 break;
1146                         }
1147                 }
1148                 if (!should_disable && pipe_split_change &&
1149                                 dc->current_state->stream_count != context->stream_count)
1150                         should_disable = true;
1151
1152                 if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&
1153                                 !dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {
1154                         struct pipe_ctx *old_pipe, *new_pipe;
1155
1156                         old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1157                         new_pipe = &context->res_ctx.pipe_ctx[i];
1158
1159                         if (old_pipe->plane_state && !new_pipe->plane_state)
1160                                 should_disable = true;
1161                 }
1162
1163                 if (should_disable && old_stream) {
1164                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1165                         tg = pipe->stream_res.tg;
1166                         /* When disabling plane for a phantom pipe, we must turn on the
1167                          * phantom OTG so the disable programming gets the double buffer
1168                          * update. Otherwise the pipe will be left in a partially disabled
1169                          * state that can result in underflow or hang when enabling it
1170                          * again for different use.
1171                          */
1172                         if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
1173                                 if (tg->funcs->enable_crtc) {
1174                                         int main_pipe_width, main_pipe_height;
1175
1176                                         main_pipe_width = old_stream->mall_stream_config.paired_stream->dst.width;
1177                                         main_pipe_height = old_stream->mall_stream_config.paired_stream->dst.height;
1178                                         if (dc->hwss.blank_phantom)
1179                                                 dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);
1180                                         tg->funcs->enable_crtc(tg);
1181                                 }
1182                         }
1183                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
1184                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
1185
1186                         if (pipe->stream && pipe->plane_state)
1187                                 dc_update_viusal_confirm_color(dc, context, pipe);
1188
1189                         if (dc->hwss.apply_ctx_for_surface) {
1190                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
1191                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
1192                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
1193                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1194                         }
1195                         if (dc->hwss.program_front_end_for_ctx) {
1196                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
1197                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
1198                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
1199                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1200                         }
1201                         /* We need to put the phantom OTG back into it's default (disabled) state or we
1202                          * can get corruption when transition from one SubVP config to a different one.
1203                          * The OTG is set to disable on falling edge of VUPDATE so the plane disable
1204                          * will still get it's double buffer update.
1205                          */
1206                         if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
1207                                 if (tg->funcs->disable_phantom_crtc)
1208                                         tg->funcs->disable_phantom_crtc(tg);
1209                         }
1210                 }
1211         }
1212
1213         current_ctx = dc->current_state;
1214         dc->current_state = dangling_context;
1215         dc_release_state(current_ctx);
1216 }
1217
1218 static void disable_vbios_mode_if_required(
1219                 struct dc *dc,
1220                 struct dc_state *context)
1221 {
1222         unsigned int i, j;
1223
1224         /* check if timing_changed, disable stream*/
1225         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1226                 struct dc_stream_state *stream = NULL;
1227                 struct dc_link *link = NULL;
1228                 struct pipe_ctx *pipe = NULL;
1229
1230                 pipe = &context->res_ctx.pipe_ctx[i];
1231                 stream = pipe->stream;
1232                 if (stream == NULL)
1233                         continue;
1234
1235                 if (stream->apply_seamless_boot_optimization)
1236                         continue;
1237
1238                 // only looking for first odm pipe
1239                 if (pipe->prev_odm_pipe)
1240                         continue;
1241
1242                 if (stream->link->local_sink &&
1243                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1244                         link = stream->link;
1245                 }
1246
1247                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
1248                         unsigned int enc_inst, tg_inst = 0;
1249                         unsigned int pix_clk_100hz;
1250
1251                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1252                         if (enc_inst != ENGINE_ID_UNKNOWN) {
1253                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
1254                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
1255                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1256                                                         dc->res_pool->stream_enc[j]);
1257                                                 break;
1258                                         }
1259                                 }
1260
1261                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1262                                         dc->res_pool->dp_clock_source,
1263                                         tg_inst, &pix_clk_100hz);
1264
1265                                 if (link->link_status.link_active) {
1266                                         uint32_t requested_pix_clk_100hz =
1267                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1268
1269                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
1270                                                 dc->link_srv->set_dpms_off(pipe);
1271                                                 pipe->stream->dpms_off = false;
1272                                         }
1273                                 }
1274                         }
1275                 }
1276         }
1277 }
1278
1279 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1280 {
1281         int i;
1282         PERF_TRACE();
1283         for (i = 0; i < MAX_PIPES; i++) {
1284                 int count = 0;
1285                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1286
1287                 if (!pipe->plane_state || pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1288                         continue;
1289
1290                 /* Timeout 100 ms */
1291                 while (count < 100000) {
1292                         /* Must set to false to start with, due to OR in update function */
1293                         pipe->plane_state->status.is_flip_pending = false;
1294                         dc->hwss.update_pending_status(pipe);
1295                         if (!pipe->plane_state->status.is_flip_pending)
1296                                 break;
1297                         udelay(1);
1298                         count++;
1299                 }
1300                 ASSERT(!pipe->plane_state->status.is_flip_pending);
1301         }
1302         PERF_TRACE();
1303 }
1304
1305 /* Public functions */
1306
1307 struct dc *dc_create(const struct dc_init_data *init_params)
1308 {
1309         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1310         unsigned int full_pipe_count;
1311
1312         if (!dc)
1313                 return NULL;
1314
1315         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1316                 if (!dc_construct_ctx(dc, init_params))
1317                         goto destruct_dc;
1318         } else {
1319                 if (!dc_construct(dc, init_params))
1320                         goto destruct_dc;
1321
1322                 full_pipe_count = dc->res_pool->pipe_count;
1323                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1324                         full_pipe_count--;
1325                 dc->caps.max_streams = min(
1326                                 full_pipe_count,
1327                                 dc->res_pool->stream_enc_count);
1328
1329                 dc->caps.max_links = dc->link_count;
1330                 dc->caps.max_audios = dc->res_pool->audio_count;
1331                 dc->caps.linear_pitch_alignment = 64;
1332
1333                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1334
1335                 dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;
1336
1337                 if (dc->res_pool->dmcu != NULL)
1338                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1339         }
1340
1341         dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
1342         dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
1343         dc->clk_reg_offsets = init_params->clk_reg_offsets;
1344
1345         /* Populate versioning information */
1346         dc->versions.dc_ver = DC_VER;
1347
1348         dc->build_id = DC_BUILD_ID;
1349
1350         DC_LOG_DC("Display Core initialized\n");
1351
1352
1353
1354         return dc;
1355
1356 destruct_dc:
1357         dc_destruct(dc);
1358         kfree(dc);
1359         return NULL;
1360 }
1361
1362 static void detect_edp_presence(struct dc *dc)
1363 {
1364         struct dc_link *edp_links[MAX_NUM_EDP];
1365         struct dc_link *edp_link = NULL;
1366         enum dc_connection_type type;
1367         int i;
1368         int edp_num;
1369
1370         dc_get_edp_links(dc, edp_links, &edp_num);
1371         if (!edp_num)
1372                 return;
1373
1374         for (i = 0; i < edp_num; i++) {
1375                 edp_link = edp_links[i];
1376                 if (dc->config.edp_not_connected) {
1377                         edp_link->edp_sink_present = false;
1378                 } else {
1379                         dc_link_detect_connection_type(edp_link, &type);
1380                         edp_link->edp_sink_present = (type != dc_connection_none);
1381                 }
1382         }
1383 }
1384
1385 void dc_hardware_init(struct dc *dc)
1386 {
1387
1388         detect_edp_presence(dc);
1389         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1390                 dc->hwss.init_hw(dc);
1391 }
1392
1393 void dc_init_callbacks(struct dc *dc,
1394                 const struct dc_callback_init *init_params)
1395 {
1396         dc->ctx->cp_psp = init_params->cp_psp;
1397 }
1398
1399 void dc_deinit_callbacks(struct dc *dc)
1400 {
1401         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1402 }
1403
1404 void dc_destroy(struct dc **dc)
1405 {
1406         dc_destruct(*dc);
1407         kfree(*dc);
1408         *dc = NULL;
1409 }
1410
1411 static void enable_timing_multisync(
1412                 struct dc *dc,
1413                 struct dc_state *ctx)
1414 {
1415         int i, multisync_count = 0;
1416         int pipe_count = dc->res_pool->pipe_count;
1417         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1418
1419         for (i = 0; i < pipe_count; i++) {
1420                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1421                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1422                         continue;
1423                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1424                         continue;
1425                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1426                 multisync_count++;
1427         }
1428
1429         if (multisync_count > 0) {
1430                 dc->hwss.enable_per_frame_crtc_position_reset(
1431                         dc, multisync_count, multisync_pipes);
1432         }
1433 }
1434
1435 static void program_timing_sync(
1436                 struct dc *dc,
1437                 struct dc_state *ctx)
1438 {
1439         int i, j, k;
1440         int group_index = 0;
1441         int num_group = 0;
1442         int pipe_count = dc->res_pool->pipe_count;
1443         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1444
1445         for (i = 0; i < pipe_count; i++) {
1446                 if (!ctx->res_ctx.pipe_ctx[i].stream
1447                                 || ctx->res_ctx.pipe_ctx[i].top_pipe
1448                                 || ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)
1449                         continue;
1450
1451                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1452         }
1453
1454         for (i = 0; i < pipe_count; i++) {
1455                 int group_size = 1;
1456                 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1457                 struct pipe_ctx *pipe_set[MAX_PIPES];
1458
1459                 if (!unsynced_pipes[i])
1460                         continue;
1461
1462                 pipe_set[0] = unsynced_pipes[i];
1463                 unsynced_pipes[i] = NULL;
1464
1465                 /* Add tg to the set, search rest of the tg's for ones with
1466                  * same timing, add all tgs with same timing to the group
1467                  */
1468                 for (j = i + 1; j < pipe_count; j++) {
1469                         if (!unsynced_pipes[j])
1470                                 continue;
1471                         if (sync_type != TIMING_SYNCHRONIZABLE &&
1472                                 dc->hwss.enable_vblanks_synchronization &&
1473                                 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1474                                 resource_are_vblanks_synchronizable(
1475                                         unsynced_pipes[j]->stream,
1476                                         pipe_set[0]->stream)) {
1477                                 sync_type = VBLANK_SYNCHRONIZABLE;
1478                                 pipe_set[group_size] = unsynced_pipes[j];
1479                                 unsynced_pipes[j] = NULL;
1480                                 group_size++;
1481                         } else
1482                         if (sync_type != VBLANK_SYNCHRONIZABLE &&
1483                                 resource_are_streams_timing_synchronizable(
1484                                         unsynced_pipes[j]->stream,
1485                                         pipe_set[0]->stream)) {
1486                                 sync_type = TIMING_SYNCHRONIZABLE;
1487                                 pipe_set[group_size] = unsynced_pipes[j];
1488                                 unsynced_pipes[j] = NULL;
1489                                 group_size++;
1490                         }
1491                 }
1492
1493                 /* set first unblanked pipe as master */
1494                 for (j = 0; j < group_size; j++) {
1495                         bool is_blanked;
1496
1497                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1498                                 is_blanked =
1499                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1500                         else
1501                                 is_blanked =
1502                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1503                         if (!is_blanked) {
1504                                 if (j == 0)
1505                                         break;
1506
1507                                 swap(pipe_set[0], pipe_set[j]);
1508                                 break;
1509                         }
1510                 }
1511
1512                 for (k = 0; k < group_size; k++) {
1513                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1514
1515                         status->timing_sync_info.group_id = num_group;
1516                         status->timing_sync_info.group_size = group_size;
1517                         if (k == 0)
1518                                 status->timing_sync_info.master = true;
1519                         else
1520                                 status->timing_sync_info.master = false;
1521
1522                 }
1523
1524                 /* remove any other pipes that are already been synced */
1525                 if (dc->config.use_pipe_ctx_sync_logic) {
1526                         /* check pipe's syncd to decide which pipe to be removed */
1527                         for (j = 1; j < group_size; j++) {
1528                                 if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {
1529                                         group_size--;
1530                                         pipe_set[j] = pipe_set[group_size];
1531                                         j--;
1532                                 } else
1533                                         /* link slave pipe's syncd with master pipe */
1534                                         pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;
1535                         }
1536                 } else {
1537                         for (j = j + 1; j < group_size; j++) {
1538                                 bool is_blanked;
1539
1540                                 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1541                                         is_blanked =
1542                                                 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1543                                 else
1544                                         is_blanked =
1545                                                 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1546                                 if (!is_blanked) {
1547                                         group_size--;
1548                                         pipe_set[j] = pipe_set[group_size];
1549                                         j--;
1550                                 }
1551                         }
1552                 }
1553
1554                 if (group_size > 1) {
1555                         if (sync_type == TIMING_SYNCHRONIZABLE) {
1556                                 dc->hwss.enable_timing_synchronization(
1557                                         dc, group_index, group_size, pipe_set);
1558                         } else
1559                                 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1560                                 dc->hwss.enable_vblanks_synchronization(
1561                                         dc, group_index, group_size, pipe_set);
1562                                 }
1563                         group_index++;
1564                 }
1565                 num_group++;
1566         }
1567 }
1568
1569 static bool streams_changed(struct dc *dc,
1570                             struct dc_stream_state *streams[],
1571                             uint8_t stream_count)
1572 {
1573         uint8_t i;
1574
1575         if (stream_count != dc->current_state->stream_count)
1576                 return true;
1577
1578         for (i = 0; i < dc->current_state->stream_count; i++) {
1579                 if (dc->current_state->streams[i] != streams[i])
1580                         return true;
1581                 if (!streams[i]->link->link_state_valid)
1582                         return true;
1583         }
1584
1585         return false;
1586 }
1587
1588 bool dc_validate_boot_timing(const struct dc *dc,
1589                                 const struct dc_sink *sink,
1590                                 struct dc_crtc_timing *crtc_timing)
1591 {
1592         struct timing_generator *tg;
1593         struct stream_encoder *se = NULL;
1594
1595         struct dc_crtc_timing hw_crtc_timing = {0};
1596
1597         struct dc_link *link = sink->link;
1598         unsigned int i, enc_inst, tg_inst = 0;
1599
1600         /* Support seamless boot on EDP displays only */
1601         if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1602                 return false;
1603         }
1604
1605         if (dc->debug.force_odm_combine)
1606                 return false;
1607
1608         /* Check for enabled DIG to identify enabled display */
1609         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1610                 return false;
1611
1612         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1613
1614         if (enc_inst == ENGINE_ID_UNKNOWN)
1615                 return false;
1616
1617         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1618                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1619
1620                         se = dc->res_pool->stream_enc[i];
1621
1622                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1623                                 dc->res_pool->stream_enc[i]);
1624                         break;
1625                 }
1626         }
1627
1628         // tg_inst not found
1629         if (i == dc->res_pool->stream_enc_count)
1630                 return false;
1631
1632         if (tg_inst >= dc->res_pool->timing_generator_count)
1633                 return false;
1634
1635         if (tg_inst != link->link_enc->preferred_engine)
1636                 return false;
1637
1638         tg = dc->res_pool->timing_generators[tg_inst];
1639
1640         if (!tg->funcs->get_hw_timing)
1641                 return false;
1642
1643         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1644                 return false;
1645
1646         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1647                 return false;
1648
1649         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1650                 return false;
1651
1652         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1653                 return false;
1654
1655         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1656                 return false;
1657
1658         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1659                 return false;
1660
1661         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1662                 return false;
1663
1664         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1665                 return false;
1666
1667         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1668                 return false;
1669
1670         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1671                 return false;
1672
1673         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1674                 return false;
1675
1676         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1677                 return false;
1678
1679         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1680                 return false;
1681
1682         /* block DSC for now, as VBIOS does not currently support DSC timings */
1683         if (crtc_timing->flags.DSC)
1684                 return false;
1685
1686         if (dc_is_dp_signal(link->connector_signal)) {
1687                 unsigned int pix_clk_100hz;
1688                 uint32_t numOdmPipes = 1;
1689                 uint32_t id_src[4] = {0};
1690
1691                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1692                         dc->res_pool->dp_clock_source,
1693                         tg_inst, &pix_clk_100hz);
1694
1695                 if (tg->funcs->get_optc_source)
1696                         tg->funcs->get_optc_source(tg,
1697                                                 &numOdmPipes, &id_src[0], &id_src[1]);
1698
1699                 if (numOdmPipes == 2)
1700                         pix_clk_100hz *= 2;
1701                 if (numOdmPipes == 4)
1702                         pix_clk_100hz *= 4;
1703
1704                 // Note: In rare cases, HW pixclk may differ from crtc's pixclk
1705                 // slightly due to rounding issues in 10 kHz units.
1706                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1707                         return false;
1708
1709                 if (!se->funcs->dp_get_pixel_format)
1710                         return false;
1711
1712                 if (!se->funcs->dp_get_pixel_format(
1713                         se,
1714                         &hw_crtc_timing.pixel_encoding,
1715                         &hw_crtc_timing.display_color_depth))
1716                         return false;
1717
1718                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1719                         return false;
1720
1721                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1722                         return false;
1723         }
1724
1725         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1726                 return false;
1727         }
1728
1729         if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {
1730                 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1731                 return false;
1732         }
1733
1734         return true;
1735 }
1736
1737 static inline bool should_update_pipe_for_stream(
1738                 struct dc_state *context,
1739                 struct pipe_ctx *pipe_ctx,
1740                 struct dc_stream_state *stream)
1741 {
1742         return (pipe_ctx->stream && pipe_ctx->stream == stream);
1743 }
1744
1745 static inline bool should_update_pipe_for_plane(
1746                 struct dc_state *context,
1747                 struct pipe_ctx *pipe_ctx,
1748                 struct dc_plane_state *plane_state)
1749 {
1750         return (pipe_ctx->plane_state == plane_state);
1751 }
1752
1753 void dc_enable_stereo(
1754         struct dc *dc,
1755         struct dc_state *context,
1756         struct dc_stream_state *streams[],
1757         uint8_t stream_count)
1758 {
1759         int i, j;
1760         struct pipe_ctx *pipe;
1761
1762         for (i = 0; i < MAX_PIPES; i++) {
1763                 if (context != NULL) {
1764                         pipe = &context->res_ctx.pipe_ctx[i];
1765                 } else {
1766                         context = dc->current_state;
1767                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1768                 }
1769
1770                 for (j = 0; pipe && j < stream_count; j++)  {
1771                         if (should_update_pipe_for_stream(context, pipe, streams[j]) &&
1772                                 dc->hwss.setup_stereo)
1773                                 dc->hwss.setup_stereo(pipe, dc);
1774                 }
1775         }
1776 }
1777
1778 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1779 {
1780         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1781                 enable_timing_multisync(dc, context);
1782                 program_timing_sync(dc, context);
1783         }
1784 }
1785
1786 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1787 {
1788         int i;
1789         unsigned int stream_mask = 0;
1790
1791         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1792                 if (context->res_ctx.pipe_ctx[i].stream)
1793                         stream_mask |= 1 << i;
1794         }
1795
1796         return stream_mask;
1797 }
1798
1799 void dc_z10_restore(const struct dc *dc)
1800 {
1801         if (dc->hwss.z10_restore)
1802                 dc->hwss.z10_restore(dc);
1803 }
1804
1805 void dc_z10_save_init(struct dc *dc)
1806 {
1807         if (dc->hwss.z10_save_init)
1808                 dc->hwss.z10_save_init(dc);
1809 }
1810
1811 /**
1812  * dc_commit_state_no_check - Apply context to the hardware
1813  *
1814  * @dc: DC object with the current status to be updated
1815  * @context: New state that will become the current status at the end of this function
1816  *
1817  * Applies given context to the hardware and copy it into current context.
1818  * It's up to the user to release the src context afterwards.
1819  *
1820  * Return: an enum dc_status result code for the operation
1821  */
1822 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1823 {
1824         struct dc_bios *dcb = dc->ctx->dc_bios;
1825         enum dc_status result = DC_ERROR_UNEXPECTED;
1826         struct pipe_ctx *pipe;
1827         int i, k, l;
1828         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1829         struct dc_state *old_state;
1830         bool subvp_prev_use = false;
1831
1832         dc_z10_restore(dc);
1833         dc_allow_idle_optimizations(dc, false);
1834
1835         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1836                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1837
1838                 /* Check old context for SubVP */
1839                 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);
1840                 if (subvp_prev_use)
1841                         break;
1842         }
1843
1844         for (i = 0; i < context->stream_count; i++)
1845                 dc_streams[i] =  context->streams[i];
1846
1847         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1848                 disable_vbios_mode_if_required(dc, context);
1849                 dc->hwss.enable_accelerated_mode(dc, context);
1850         }
1851
1852         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1853                 context->stream_count == 0)
1854                 dc->hwss.prepare_bandwidth(dc, context);
1855
1856         /* When SubVP is active, all HW programming must be done while
1857          * SubVP lock is acquired
1858          */
1859         if (dc->hwss.subvp_pipe_control_lock)
1860                 dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
1861
1862         if (dc->hwss.update_dsc_pg)
1863                 dc->hwss.update_dsc_pg(dc, context, false);
1864
1865         disable_dangling_plane(dc, context);
1866         /* re-program planes for existing stream, in case we need to
1867          * free up plane resource for later use
1868          */
1869         if (dc->hwss.apply_ctx_for_surface) {
1870                 for (i = 0; i < context->stream_count; i++) {
1871                         if (context->streams[i]->mode_changed)
1872                                 continue;
1873                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1874                         dc->hwss.apply_ctx_for_surface(
1875                                 dc, context->streams[i],
1876                                 context->stream_status[i].plane_count,
1877                                 context); /* use new pipe config in new context */
1878                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1879                         dc->hwss.post_unlock_program_front_end(dc, context);
1880                 }
1881         }
1882
1883         /* Program hardware */
1884         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1885                 pipe = &context->res_ctx.pipe_ctx[i];
1886                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1887         }
1888
1889         result = dc->hwss.apply_ctx_to_hw(dc, context);
1890
1891         if (result != DC_OK) {
1892                 /* Application of dc_state to hardware stopped. */
1893                 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
1894                 return result;
1895         }
1896
1897         dc_trigger_sync(dc, context);
1898
1899         /* Full update should unconditionally be triggered when dc_commit_state_no_check is called */
1900         for (i = 0; i < context->stream_count; i++) {
1901                 uint32_t prev_dsc_changed = context->streams[i]->update_flags.bits.dsc_changed;
1902
1903                 context->streams[i]->update_flags.raw = 0xFFFFFFFF;
1904                 context->streams[i]->update_flags.bits.dsc_changed = prev_dsc_changed;
1905         }
1906
1907         /* Program all planes within new context*/
1908         if (dc->hwss.program_front_end_for_ctx) {
1909                 dc->hwss.interdependent_update_lock(dc, context, true);
1910                 dc->hwss.program_front_end_for_ctx(dc, context);
1911                 dc->hwss.interdependent_update_lock(dc, context, false);
1912                 dc->hwss.post_unlock_program_front_end(dc, context);
1913         }
1914
1915         if (dc->hwss.commit_subvp_config)
1916                 dc->hwss.commit_subvp_config(dc, context);
1917         if (dc->hwss.subvp_pipe_control_lock)
1918                 dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);
1919
1920         for (i = 0; i < context->stream_count; i++) {
1921                 const struct dc_link *link = context->streams[i]->link;
1922
1923                 if (!context->streams[i]->mode_changed)
1924                         continue;
1925
1926                 if (dc->hwss.apply_ctx_for_surface) {
1927                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1928                         dc->hwss.apply_ctx_for_surface(
1929                                         dc, context->streams[i],
1930                                         context->stream_status[i].plane_count,
1931                                         context);
1932                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1933                         dc->hwss.post_unlock_program_front_end(dc, context);
1934                 }
1935
1936                 /*
1937                  * enable stereo
1938                  * TODO rework dc_enable_stereo call to work with validation sets?
1939                  */
1940                 for (k = 0; k < MAX_PIPES; k++) {
1941                         pipe = &context->res_ctx.pipe_ctx[k];
1942
1943                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1944                                 if (context->streams[l] &&
1945                                         context->streams[l] == pipe->stream &&
1946                                         dc->hwss.setup_stereo)
1947                                         dc->hwss.setup_stereo(pipe, dc);
1948                         }
1949                 }
1950
1951                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1952                                 context->streams[i]->timing.h_addressable,
1953                                 context->streams[i]->timing.v_addressable,
1954                                 context->streams[i]->timing.h_total,
1955                                 context->streams[i]->timing.v_total,
1956                                 context->streams[i]->timing.pix_clk_100hz / 10);
1957         }
1958
1959         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1960
1961         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1962                 context->stream_count == 0) {
1963                 /* Must wait for no flips to be pending before doing optimize bw */
1964                 wait_for_no_pipes_pending(dc, context);
1965                 /* pplib is notified if disp_num changed */
1966                 dc->hwss.optimize_bandwidth(dc, context);
1967         }
1968
1969         if (dc->hwss.update_dsc_pg)
1970                 dc->hwss.update_dsc_pg(dc, context, true);
1971
1972         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1973                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1974         else
1975                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1976
1977         context->stream_mask = get_stream_mask(dc, context);
1978
1979         if (context->stream_mask != dc->current_state->stream_mask)
1980                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1981
1982         for (i = 0; i < context->stream_count; i++)
1983                 context->streams[i]->mode_changed = false;
1984
1985         /* Clear update flags that were set earlier to avoid redundant programming */
1986         for (i = 0; i < context->stream_count; i++) {
1987                 context->streams[i]->update_flags.raw = 0x0;
1988         }
1989
1990         old_state = dc->current_state;
1991         dc->current_state = context;
1992
1993         dc_release_state(old_state);
1994
1995         dc_retain_state(dc->current_state);
1996
1997         return result;
1998 }
1999
2000 static bool commit_minimal_transition_state(struct dc *dc,
2001                 struct dc_state *transition_base_context);
2002
2003 /**
2004  * dc_commit_streams - Commit current stream state
2005  *
2006  * @dc: DC object with the commit state to be configured in the hardware
2007  * @streams: Array with a list of stream state
2008  * @stream_count: Total of streams
2009  *
2010  * Function responsible for commit streams change to the hardware.
2011  *
2012  * Return:
2013  * Return DC_OK if everything work as expected, otherwise, return a dc_status
2014  * code.
2015  */
2016 enum dc_status dc_commit_streams(struct dc *dc,
2017                                  struct dc_stream_state *streams[],
2018                                  uint8_t stream_count)
2019 {
2020         int i, j;
2021         struct dc_state *context;
2022         enum dc_status res = DC_OK;
2023         struct dc_validation_set set[MAX_STREAMS] = {0};
2024         struct pipe_ctx *pipe;
2025         bool handle_exit_odm2to1 = false;
2026
2027         if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
2028                 return res;
2029
2030         if (!streams_changed(dc, streams, stream_count))
2031                 return res;
2032
2033         DC_LOG_DC("%s: %d streams\n", __func__, stream_count);
2034
2035         for (i = 0; i < stream_count; i++) {
2036                 struct dc_stream_state *stream = streams[i];
2037                 struct dc_stream_status *status = dc_stream_get_status(stream);
2038
2039                 dc_stream_log(dc, stream);
2040
2041                 set[i].stream = stream;
2042
2043                 if (status) {
2044                         set[i].plane_count = status->plane_count;
2045                         for (j = 0; j < status->plane_count; j++)
2046                                 set[i].plane_states[j] = status->plane_states[j];
2047                 }
2048         }
2049
2050         /* ODM Combine 2:1 power optimization is only applied for single stream
2051          * scenario, it uses extra pipes than needed to reduce power consumption
2052          * We need to switch off this feature to make room for new streams.
2053          */
2054         if (stream_count > dc->current_state->stream_count &&
2055                         dc->current_state->stream_count == 1) {
2056                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2057                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2058                         if (pipe->next_odm_pipe)
2059                                 handle_exit_odm2to1 = true;
2060                 }
2061         }
2062
2063         if (handle_exit_odm2to1)
2064                 res = commit_minimal_transition_state(dc, dc->current_state);
2065
2066         context = dc_create_state(dc);
2067         if (!context)
2068                 goto context_alloc_fail;
2069
2070         dc_resource_state_copy_construct_current(dc, context);
2071
2072         res = dc_validate_with_context(dc, set, stream_count, context, false);
2073         if (res != DC_OK) {
2074                 BREAK_TO_DEBUGGER();
2075                 goto fail;
2076         }
2077
2078         res = dc_commit_state_no_check(dc, context);
2079
2080         for (i = 0; i < stream_count; i++) {
2081                 for (j = 0; j < context->stream_count; j++) {
2082                         if (streams[i]->stream_id == context->streams[j]->stream_id)
2083                                 streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;
2084
2085                         if (dc_is_embedded_signal(streams[i]->signal)) {
2086                                 struct dc_stream_status *status = dc_stream_get_status_from_state(context, streams[i]);
2087
2088                                 if (dc->hwss.is_abm_supported)
2089                                         status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, streams[i]);
2090                                 else
2091                                         status->is_abm_supported = true;
2092                         }
2093                 }
2094         }
2095
2096 fail:
2097         dc_release_state(context);
2098
2099 context_alloc_fail:
2100
2101         DC_LOG_DC("%s Finished.\n", __func__);
2102
2103         return res;
2104 }
2105
2106 bool dc_acquire_release_mpc_3dlut(
2107                 struct dc *dc, bool acquire,
2108                 struct dc_stream_state *stream,
2109                 struct dc_3dlut **lut,
2110                 struct dc_transfer_func **shaper)
2111 {
2112         int pipe_idx;
2113         bool ret = false;
2114         bool found_pipe_idx = false;
2115         const struct resource_pool *pool = dc->res_pool;
2116         struct resource_context *res_ctx = &dc->current_state->res_ctx;
2117         int mpcc_id = 0;
2118
2119         if (pool && res_ctx) {
2120                 if (acquire) {
2121                         /*find pipe idx for the given stream*/
2122                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
2123                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
2124                                         found_pipe_idx = true;
2125                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
2126                                         break;
2127                                 }
2128                         }
2129                 } else
2130                         found_pipe_idx = true;/*for release pipe_idx is not required*/
2131
2132                 if (found_pipe_idx) {
2133                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
2134                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
2135                         else if (!acquire && pool->funcs->release_post_bldn_3dlut)
2136                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
2137                 }
2138         }
2139         return ret;
2140 }
2141
2142 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
2143 {
2144         int i;
2145         struct pipe_ctx *pipe;
2146
2147         for (i = 0; i < MAX_PIPES; i++) {
2148                 pipe = &context->res_ctx.pipe_ctx[i];
2149
2150                 // Don't check flip pending on phantom pipes
2151                 if (!pipe->plane_state || (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM))
2152                         continue;
2153
2154                 /* Must set to false to start with, due to OR in update function */
2155                 pipe->plane_state->status.is_flip_pending = false;
2156                 dc->hwss.update_pending_status(pipe);
2157                 if (pipe->plane_state->status.is_flip_pending)
2158                         return true;
2159         }
2160         return false;
2161 }
2162
2163 /* Perform updates here which need to be deferred until next vupdate
2164  *
2165  * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
2166  * but forcing lut memory to shutdown state is immediate. This causes
2167  * single frame corruption as lut gets disabled mid-frame unless shutdown
2168  * is deferred until after entering bypass.
2169  */
2170 static void process_deferred_updates(struct dc *dc)
2171 {
2172         int i = 0;
2173
2174         if (dc->debug.enable_mem_low_power.bits.cm) {
2175                 ASSERT(dc->dcn_ip->max_num_dpp);
2176                 for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)
2177                         if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)
2178                                 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
2179         }
2180 }
2181
2182 void dc_post_update_surfaces_to_stream(struct dc *dc)
2183 {
2184         int i;
2185         struct dc_state *context = dc->current_state;
2186
2187         if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
2188                 return;
2189
2190         post_surface_trace(dc);
2191
2192         /*
2193          * Only relevant for DCN behavior where we can guarantee the optimization
2194          * is safe to apply - retain the legacy behavior for DCE.
2195          */
2196
2197         if (dc->ctx->dce_version < DCE_VERSION_MAX)
2198                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2199         else {
2200                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2201
2202                 if (is_flip_pending_in_pipes(dc, context))
2203                         return;
2204
2205                 for (i = 0; i < dc->res_pool->pipe_count; i++)
2206                         if (context->res_ctx.pipe_ctx[i].stream == NULL ||
2207                                         context->res_ctx.pipe_ctx[i].plane_state == NULL) {
2208                                 context->res_ctx.pipe_ctx[i].pipe_idx = i;
2209                                 dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
2210                         }
2211
2212                 process_deferred_updates(dc);
2213
2214                 dc->hwss.optimize_bandwidth(dc, context);
2215
2216                 if (dc->hwss.update_dsc_pg)
2217                         dc->hwss.update_dsc_pg(dc, context, true);
2218         }
2219
2220         dc->optimized_required = false;
2221         dc->wm_optimized_required = false;
2222 }
2223
2224 static void init_state(struct dc *dc, struct dc_state *context)
2225 {
2226         /* Each context must have their own instance of VBA and in order to
2227          * initialize and obtain IP and SOC the base DML instance from DC is
2228          * initially copied into every context
2229          */
2230         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
2231 }
2232
2233 struct dc_state *dc_create_state(struct dc *dc)
2234 {
2235         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
2236                                             GFP_KERNEL);
2237
2238         if (!context)
2239                 return NULL;
2240
2241         init_state(dc, context);
2242
2243 #ifdef CONFIG_DRM_AMD_DC_FP
2244         if (dc->debug.using_dml2) {
2245                 dml2_create(dc, &dc->dml2_options, &context->bw_ctx.dml2);
2246         }
2247 #endif
2248         kref_init(&context->refcount);
2249
2250         return context;
2251 }
2252
2253 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
2254 {
2255         int i, j;
2256         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
2257 #ifdef CONFIG_DRM_AMD_DC_FP
2258         struct dml2_context *dml2 =  NULL;
2259 #endif
2260
2261         if (!new_ctx)
2262                 return NULL;
2263         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
2264
2265 #ifdef CONFIG_DRM_AMD_DC_FP
2266         if (new_ctx->bw_ctx.dml2) {
2267                 dml2 = kzalloc(sizeof(struct dml2_context), GFP_KERNEL);
2268                 if (!dml2)
2269                         return NULL;
2270
2271                 memcpy(dml2, src_ctx->bw_ctx.dml2, sizeof(struct dml2_context));
2272                 new_ctx->bw_ctx.dml2 = dml2;
2273         }
2274 #endif
2275
2276         for (i = 0; i < MAX_PIPES; i++) {
2277                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
2278
2279                         if (cur_pipe->top_pipe)
2280                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2281
2282                         if (cur_pipe->bottom_pipe)
2283                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2284
2285                         if (cur_pipe->prev_odm_pipe)
2286                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2287
2288                         if (cur_pipe->next_odm_pipe)
2289                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2290
2291         }
2292
2293         for (i = 0; i < new_ctx->stream_count; i++) {
2294                         dc_stream_retain(new_ctx->streams[i]);
2295                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
2296                                 dc_plane_state_retain(
2297                                         new_ctx->stream_status[i].plane_states[j]);
2298         }
2299
2300         kref_init(&new_ctx->refcount);
2301
2302         return new_ctx;
2303 }
2304
2305 void dc_retain_state(struct dc_state *context)
2306 {
2307         kref_get(&context->refcount);
2308 }
2309
2310 static void dc_state_free(struct kref *kref)
2311 {
2312         struct dc_state *context = container_of(kref, struct dc_state, refcount);
2313         dc_resource_state_destruct(context);
2314
2315 #ifdef CONFIG_DRM_AMD_DC_FP
2316         dml2_destroy(context->bw_ctx.dml2);
2317         context->bw_ctx.dml2 = 0;
2318 #endif
2319
2320         kvfree(context);
2321 }
2322
2323 void dc_release_state(struct dc_state *context)
2324 {
2325         kref_put(&context->refcount, dc_state_free);
2326 }
2327
2328 bool dc_set_generic_gpio_for_stereo(bool enable,
2329                 struct gpio_service *gpio_service)
2330 {
2331         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
2332         struct gpio_pin_info pin_info;
2333         struct gpio *generic;
2334         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
2335                            GFP_KERNEL);
2336
2337         if (!config)
2338                 return false;
2339         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
2340
2341         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
2342                 kfree(config);
2343                 return false;
2344         } else {
2345                 generic = dal_gpio_service_create_generic_mux(
2346                         gpio_service,
2347                         pin_info.offset,
2348                         pin_info.mask);
2349         }
2350
2351         if (!generic) {
2352                 kfree(config);
2353                 return false;
2354         }
2355
2356         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
2357
2358         config->enable_output_from_mux = enable;
2359         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
2360
2361         if (gpio_result == GPIO_RESULT_OK)
2362                 gpio_result = dal_mux_setup_config(generic, config);
2363
2364         if (gpio_result == GPIO_RESULT_OK) {
2365                 dal_gpio_close(generic);
2366                 dal_gpio_destroy_generic_mux(&generic);
2367                 kfree(config);
2368                 return true;
2369         } else {
2370                 dal_gpio_close(generic);
2371                 dal_gpio_destroy_generic_mux(&generic);
2372                 kfree(config);
2373                 return false;
2374         }
2375 }
2376
2377 static bool is_surface_in_context(
2378                 const struct dc_state *context,
2379                 const struct dc_plane_state *plane_state)
2380 {
2381         int j;
2382
2383         for (j = 0; j < MAX_PIPES; j++) {
2384                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2385
2386                 if (plane_state == pipe_ctx->plane_state) {
2387                         return true;
2388                 }
2389         }
2390
2391         return false;
2392 }
2393
2394 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
2395 {
2396         union surface_update_flags *update_flags = &u->surface->update_flags;
2397         enum surface_update_type update_type = UPDATE_TYPE_FAST;
2398
2399         if (!u->plane_info)
2400                 return UPDATE_TYPE_FAST;
2401
2402         if (u->plane_info->color_space != u->surface->color_space) {
2403                 update_flags->bits.color_space_change = 1;
2404                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2405         }
2406
2407         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
2408                 update_flags->bits.horizontal_mirror_change = 1;
2409                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2410         }
2411
2412         if (u->plane_info->rotation != u->surface->rotation) {
2413                 update_flags->bits.rotation_change = 1;
2414                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2415         }
2416
2417         if (u->plane_info->format != u->surface->format) {
2418                 update_flags->bits.pixel_format_change = 1;
2419                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2420         }
2421
2422         if (u->plane_info->stereo_format != u->surface->stereo_format) {
2423                 update_flags->bits.stereo_format_change = 1;
2424                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2425         }
2426
2427         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
2428                 update_flags->bits.per_pixel_alpha_change = 1;
2429                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2430         }
2431
2432         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
2433                 update_flags->bits.global_alpha_change = 1;
2434                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2435         }
2436
2437         if (u->plane_info->dcc.enable != u->surface->dcc.enable
2438                         || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk
2439                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
2440                 /* During DCC on/off, stutter period is calculated before
2441                  * DCC has fully transitioned. This results in incorrect
2442                  * stutter period calculation. Triggering a full update will
2443                  * recalculate stutter period.
2444                  */
2445                 update_flags->bits.dcc_change = 1;
2446                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2447         }
2448
2449         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
2450                         resource_pixel_format_to_bpp(u->surface->format)) {
2451                 /* different bytes per element will require full bandwidth
2452                  * and DML calculation
2453                  */
2454                 update_flags->bits.bpp_change = 1;
2455                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2456         }
2457
2458         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
2459                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
2460                 update_flags->bits.plane_size_change = 1;
2461                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2462         }
2463
2464
2465         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
2466                         sizeof(union dc_tiling_info)) != 0) {
2467                 update_flags->bits.swizzle_change = 1;
2468                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2469
2470                 /* todo: below are HW dependent, we should add a hook to
2471                  * DCE/N resource and validated there.
2472                  */
2473                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
2474                         /* swizzled mode requires RQ to be setup properly,
2475                          * thus need to run DML to calculate RQ settings
2476                          */
2477                         update_flags->bits.bandwidth_change = 1;
2478                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2479                 }
2480         }
2481
2482         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
2483         return update_type;
2484 }
2485
2486 static enum surface_update_type get_scaling_info_update_type(
2487                 const struct dc *dc,
2488                 const struct dc_surface_update *u)
2489 {
2490         union surface_update_flags *update_flags = &u->surface->update_flags;
2491
2492         if (!u->scaling_info)
2493                 return UPDATE_TYPE_FAST;
2494
2495         if (u->scaling_info->dst_rect.width != u->surface->dst_rect.width
2496                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
2497                         || u->scaling_info->scaling_quality.integer_scaling !=
2498                                 u->surface->scaling_quality.integer_scaling
2499                         ) {
2500                 update_flags->bits.scaling_change = 1;
2501
2502                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
2503                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
2504                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
2505                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
2506                         /* Making dst rect smaller requires a bandwidth change */
2507                         update_flags->bits.bandwidth_change = 1;
2508         }
2509
2510         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2511                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2512
2513                 update_flags->bits.scaling_change = 1;
2514                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2515                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2516                         /* Making src rect bigger requires a bandwidth change */
2517                         update_flags->bits.clock_change = 1;
2518         }
2519
2520         if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width &&
2521                 (u->scaling_info->clip_rect.width > u->surface->clip_rect.width ||
2522                  u->scaling_info->clip_rect.height > u->surface->clip_rect.height))
2523                  /* Changing clip size of a large surface may result in MPC slice count change */
2524                 update_flags->bits.bandwidth_change = 1;
2525
2526         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2527                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
2528                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2529                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2530                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2531                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2532                 update_flags->bits.position_change = 1;
2533
2534         if (update_flags->bits.clock_change
2535                         || update_flags->bits.bandwidth_change
2536                         || update_flags->bits.scaling_change)
2537                 return UPDATE_TYPE_FULL;
2538
2539         if (update_flags->bits.position_change)
2540                 return UPDATE_TYPE_MED;
2541
2542         return UPDATE_TYPE_FAST;
2543 }
2544
2545 static enum surface_update_type det_surface_update(const struct dc *dc,
2546                 const struct dc_surface_update *u)
2547 {
2548         const struct dc_state *context = dc->current_state;
2549         enum surface_update_type type;
2550         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2551         union surface_update_flags *update_flags = &u->surface->update_flags;
2552
2553         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2554                 update_flags->raw = 0xFFFFFFFF;
2555                 return UPDATE_TYPE_FULL;
2556         }
2557
2558         update_flags->raw = 0; // Reset all flags
2559
2560         type = get_plane_info_update_type(u);
2561         elevate_update_type(&overall_type, type);
2562
2563         type = get_scaling_info_update_type(dc, u);
2564         elevate_update_type(&overall_type, type);
2565
2566         if (u->flip_addr) {
2567                 update_flags->bits.addr_update = 1;
2568                 if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) {
2569                         update_flags->bits.tmz_changed = 1;
2570                         elevate_update_type(&overall_type, UPDATE_TYPE_FULL);
2571                 }
2572         }
2573         if (u->in_transfer_func)
2574                 update_flags->bits.in_transfer_func_change = 1;
2575
2576         if (u->input_csc_color_matrix)
2577                 update_flags->bits.input_csc_change = 1;
2578
2579         if (u->coeff_reduction_factor)
2580                 update_flags->bits.coeff_reduction_change = 1;
2581
2582         if (u->gamut_remap_matrix)
2583                 update_flags->bits.gamut_remap_change = 1;
2584
2585         if (u->blend_tf)
2586                 update_flags->bits.gamma_change = 1;
2587
2588         if (u->gamma) {
2589                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2590
2591                 if (u->plane_info)
2592                         format = u->plane_info->format;
2593                 else if (u->surface)
2594                         format = u->surface->format;
2595
2596                 if (dce_use_lut(format))
2597                         update_flags->bits.gamma_change = 1;
2598         }
2599
2600         if (u->lut3d_func || u->func_shaper)
2601                 update_flags->bits.lut_3d = 1;
2602
2603         if (u->hdr_mult.value)
2604                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2605                         update_flags->bits.hdr_mult = 1;
2606                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2607                 }
2608
2609         if (update_flags->bits.in_transfer_func_change) {
2610                 type = UPDATE_TYPE_MED;
2611                 elevate_update_type(&overall_type, type);
2612         }
2613
2614         if (update_flags->bits.lut_3d) {
2615                 type = UPDATE_TYPE_FULL;
2616                 elevate_update_type(&overall_type, type);
2617         }
2618
2619         if (dc->debug.enable_legacy_fast_update &&
2620                         (update_flags->bits.gamma_change ||
2621                         update_flags->bits.gamut_remap_change ||
2622                         update_flags->bits.input_csc_change ||
2623                         update_flags->bits.coeff_reduction_change)) {
2624                 type = UPDATE_TYPE_FULL;
2625                 elevate_update_type(&overall_type, type);
2626         }
2627         return overall_type;
2628 }
2629
2630 static enum surface_update_type check_update_surfaces_for_stream(
2631                 struct dc *dc,
2632                 struct dc_surface_update *updates,
2633                 int surface_count,
2634                 struct dc_stream_update *stream_update,
2635                 const struct dc_stream_status *stream_status)
2636 {
2637         int i;
2638         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2639
2640         if (dc->idle_optimizations_allowed)
2641                 overall_type = UPDATE_TYPE_FULL;
2642
2643         if (stream_status == NULL || stream_status->plane_count != surface_count)
2644                 overall_type = UPDATE_TYPE_FULL;
2645
2646         if (stream_update && stream_update->pending_test_pattern) {
2647                 overall_type = UPDATE_TYPE_FULL;
2648         }
2649
2650         /* some stream updates require passive update */
2651         if (stream_update) {
2652                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2653
2654                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2655                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2656                         stream_update->integer_scaling_update)
2657                         su_flags->bits.scaling = 1;
2658
2659                 if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2660                         su_flags->bits.out_tf = 1;
2661
2662                 if (stream_update->abm_level)
2663                         su_flags->bits.abm_level = 1;
2664
2665                 if (stream_update->dpms_off)
2666                         su_flags->bits.dpms_off = 1;
2667
2668                 if (stream_update->gamut_remap)
2669                         su_flags->bits.gamut_remap = 1;
2670
2671                 if (stream_update->wb_update)
2672                         su_flags->bits.wb_update = 1;
2673
2674                 if (stream_update->dsc_config)
2675                         su_flags->bits.dsc_changed = 1;
2676
2677                 if (stream_update->mst_bw_update)
2678                         su_flags->bits.mst_bw = 1;
2679
2680                 if (stream_update->stream && stream_update->stream->freesync_on_desktop &&
2681                         (stream_update->vrr_infopacket || stream_update->allow_freesync ||
2682                                 stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
2683                         su_flags->bits.fams_changed = 1;
2684
2685                 if (su_flags->raw != 0)
2686                         overall_type = UPDATE_TYPE_FULL;
2687
2688                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2689                         su_flags->bits.out_csc = 1;
2690
2691                 /* Output transfer function changes do not require bandwidth recalculation,
2692                  * so don't trigger a full update
2693                  */
2694                 if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2695                         su_flags->bits.out_tf = 1;
2696         }
2697
2698         for (i = 0 ; i < surface_count; i++) {
2699                 enum surface_update_type type =
2700                                 det_surface_update(dc, &updates[i]);
2701
2702                 elevate_update_type(&overall_type, type);
2703         }
2704
2705         return overall_type;
2706 }
2707
2708 /*
2709  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2710  *
2711  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2712  */
2713 enum surface_update_type dc_check_update_surfaces_for_stream(
2714                 struct dc *dc,
2715                 struct dc_surface_update *updates,
2716                 int surface_count,
2717                 struct dc_stream_update *stream_update,
2718                 const struct dc_stream_status *stream_status)
2719 {
2720         int i;
2721         enum surface_update_type type;
2722
2723         if (stream_update)
2724                 stream_update->stream->update_flags.raw = 0;
2725         for (i = 0; i < surface_count; i++)
2726                 updates[i].surface->update_flags.raw = 0;
2727
2728         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2729         if (type == UPDATE_TYPE_FULL) {
2730                 if (stream_update) {
2731                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2732                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2733                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2734                 }
2735                 for (i = 0; i < surface_count; i++)
2736                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2737         }
2738
2739         if (type == UPDATE_TYPE_FAST) {
2740                 // If there's an available clock comparator, we use that.
2741                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2742                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2743                                 dc->optimized_required = true;
2744                 // Else we fallback to mem compare.
2745                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2746                         dc->optimized_required = true;
2747                 }
2748
2749                 dc->optimized_required |= dc->wm_optimized_required;
2750         }
2751
2752         return type;
2753 }
2754
2755 static struct dc_stream_status *stream_get_status(
2756         struct dc_state *ctx,
2757         struct dc_stream_state *stream)
2758 {
2759         uint8_t i;
2760
2761         for (i = 0; i < ctx->stream_count; i++) {
2762                 if (stream == ctx->streams[i]) {
2763                         return &ctx->stream_status[i];
2764                 }
2765         }
2766
2767         return NULL;
2768 }
2769
2770 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2771
2772 static void copy_surface_update_to_plane(
2773                 struct dc_plane_state *surface,
2774                 struct dc_surface_update *srf_update)
2775 {
2776         if (srf_update->flip_addr) {
2777                 surface->address = srf_update->flip_addr->address;
2778                 surface->flip_immediate =
2779                         srf_update->flip_addr->flip_immediate;
2780                 surface->time.time_elapsed_in_us[surface->time.index] =
2781                         srf_update->flip_addr->flip_timestamp_in_us -
2782                                 surface->time.prev_update_time_in_us;
2783                 surface->time.prev_update_time_in_us =
2784                         srf_update->flip_addr->flip_timestamp_in_us;
2785                 surface->time.index++;
2786                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2787                         surface->time.index = 0;
2788
2789                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2790         }
2791
2792         if (srf_update->scaling_info) {
2793                 surface->scaling_quality =
2794                                 srf_update->scaling_info->scaling_quality;
2795                 surface->dst_rect =
2796                                 srf_update->scaling_info->dst_rect;
2797                 surface->src_rect =
2798                                 srf_update->scaling_info->src_rect;
2799                 surface->clip_rect =
2800                                 srf_update->scaling_info->clip_rect;
2801         }
2802
2803         if (srf_update->plane_info) {
2804                 surface->color_space =
2805                                 srf_update->plane_info->color_space;
2806                 surface->format =
2807                                 srf_update->plane_info->format;
2808                 surface->plane_size =
2809                                 srf_update->plane_info->plane_size;
2810                 surface->rotation =
2811                                 srf_update->plane_info->rotation;
2812                 surface->horizontal_mirror =
2813                                 srf_update->plane_info->horizontal_mirror;
2814                 surface->stereo_format =
2815                                 srf_update->plane_info->stereo_format;
2816                 surface->tiling_info =
2817                                 srf_update->plane_info->tiling_info;
2818                 surface->visible =
2819                                 srf_update->plane_info->visible;
2820                 surface->per_pixel_alpha =
2821                                 srf_update->plane_info->per_pixel_alpha;
2822                 surface->global_alpha =
2823                                 srf_update->plane_info->global_alpha;
2824                 surface->global_alpha_value =
2825                                 srf_update->plane_info->global_alpha_value;
2826                 surface->dcc =
2827                                 srf_update->plane_info->dcc;
2828                 surface->layer_index =
2829                                 srf_update->plane_info->layer_index;
2830         }
2831
2832         if (srf_update->gamma &&
2833                         (surface->gamma_correction !=
2834                                         srf_update->gamma)) {
2835                 memcpy(&surface->gamma_correction->entries,
2836                         &srf_update->gamma->entries,
2837                         sizeof(struct dc_gamma_entries));
2838                 surface->gamma_correction->is_identity =
2839                         srf_update->gamma->is_identity;
2840                 surface->gamma_correction->num_entries =
2841                         srf_update->gamma->num_entries;
2842                 surface->gamma_correction->type =
2843                         srf_update->gamma->type;
2844         }
2845
2846         if (srf_update->in_transfer_func &&
2847                         (surface->in_transfer_func !=
2848                                 srf_update->in_transfer_func)) {
2849                 surface->in_transfer_func->sdr_ref_white_level =
2850                         srf_update->in_transfer_func->sdr_ref_white_level;
2851                 surface->in_transfer_func->tf =
2852                         srf_update->in_transfer_func->tf;
2853                 surface->in_transfer_func->type =
2854                         srf_update->in_transfer_func->type;
2855                 memcpy(&surface->in_transfer_func->tf_pts,
2856                         &srf_update->in_transfer_func->tf_pts,
2857                         sizeof(struct dc_transfer_func_distributed_points));
2858         }
2859
2860         if (srf_update->func_shaper &&
2861                         (surface->in_shaper_func !=
2862                         srf_update->func_shaper))
2863                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2864                 sizeof(*surface->in_shaper_func));
2865
2866         if (srf_update->lut3d_func &&
2867                         (surface->lut3d_func !=
2868                         srf_update->lut3d_func))
2869                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2870                 sizeof(*surface->lut3d_func));
2871
2872         if (srf_update->hdr_mult.value)
2873                 surface->hdr_mult =
2874                                 srf_update->hdr_mult;
2875
2876         if (srf_update->blend_tf &&
2877                         (surface->blend_tf !=
2878                         srf_update->blend_tf))
2879                 memcpy(surface->blend_tf, srf_update->blend_tf,
2880                 sizeof(*surface->blend_tf));
2881
2882         if (srf_update->input_csc_color_matrix)
2883                 surface->input_csc_color_matrix =
2884                         *srf_update->input_csc_color_matrix;
2885
2886         if (srf_update->coeff_reduction_factor)
2887                 surface->coeff_reduction_factor =
2888                         *srf_update->coeff_reduction_factor;
2889
2890         if (srf_update->gamut_remap_matrix)
2891                 surface->gamut_remap_matrix =
2892                         *srf_update->gamut_remap_matrix;
2893 }
2894
2895 static void copy_stream_update_to_stream(struct dc *dc,
2896                                          struct dc_state *context,
2897                                          struct dc_stream_state *stream,
2898                                          struct dc_stream_update *update)
2899 {
2900         struct dc_context *dc_ctx = dc->ctx;
2901
2902         if (update == NULL || stream == NULL)
2903                 return;
2904
2905         if (update->src.height && update->src.width)
2906                 stream->src = update->src;
2907
2908         if (update->dst.height && update->dst.width)
2909                 stream->dst = update->dst;
2910
2911         if (update->out_transfer_func &&
2912             stream->out_transfer_func != update->out_transfer_func) {
2913                 stream->out_transfer_func->sdr_ref_white_level =
2914                         update->out_transfer_func->sdr_ref_white_level;
2915                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2916                 stream->out_transfer_func->type =
2917                         update->out_transfer_func->type;
2918                 memcpy(&stream->out_transfer_func->tf_pts,
2919                        &update->out_transfer_func->tf_pts,
2920                        sizeof(struct dc_transfer_func_distributed_points));
2921         }
2922
2923         if (update->hdr_static_metadata)
2924                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2925
2926         if (update->abm_level)
2927                 stream->abm_level = *update->abm_level;
2928
2929         if (update->periodic_interrupt)
2930                 stream->periodic_interrupt = *update->periodic_interrupt;
2931
2932         if (update->gamut_remap)
2933                 stream->gamut_remap_matrix = *update->gamut_remap;
2934
2935         /* Note: this being updated after mode set is currently not a use case
2936          * however if it arises OCSC would need to be reprogrammed at the
2937          * minimum
2938          */
2939         if (update->output_color_space)
2940                 stream->output_color_space = *update->output_color_space;
2941
2942         if (update->output_csc_transform)
2943                 stream->csc_color_matrix = *update->output_csc_transform;
2944
2945         if (update->vrr_infopacket)
2946                 stream->vrr_infopacket = *update->vrr_infopacket;
2947
2948         if (update->allow_freesync)
2949                 stream->allow_freesync = *update->allow_freesync;
2950
2951         if (update->vrr_active_variable)
2952                 stream->vrr_active_variable = *update->vrr_active_variable;
2953
2954         if (update->vrr_active_fixed)
2955                 stream->vrr_active_fixed = *update->vrr_active_fixed;
2956
2957         if (update->crtc_timing_adjust)
2958                 stream->adjust = *update->crtc_timing_adjust;
2959
2960         if (update->dpms_off)
2961                 stream->dpms_off = *update->dpms_off;
2962
2963         if (update->hfvsif_infopacket)
2964                 stream->hfvsif_infopacket = *update->hfvsif_infopacket;
2965
2966         if (update->vtem_infopacket)
2967                 stream->vtem_infopacket = *update->vtem_infopacket;
2968
2969         if (update->vsc_infopacket)
2970                 stream->vsc_infopacket = *update->vsc_infopacket;
2971
2972         if (update->vsp_infopacket)
2973                 stream->vsp_infopacket = *update->vsp_infopacket;
2974
2975         if (update->adaptive_sync_infopacket)
2976                 stream->adaptive_sync_infopacket = *update->adaptive_sync_infopacket;
2977
2978         if (update->dither_option)
2979                 stream->dither_option = *update->dither_option;
2980
2981         if (update->pending_test_pattern)
2982                 stream->test_pattern = *update->pending_test_pattern;
2983         /* update current stream with writeback info */
2984         if (update->wb_update) {
2985                 int i;
2986
2987                 stream->num_wb_info = update->wb_update->num_wb_info;
2988                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2989                 for (i = 0; i < stream->num_wb_info; i++)
2990                         stream->writeback_info[i] =
2991                                 update->wb_update->writeback_info[i];
2992         }
2993         if (update->dsc_config) {
2994                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2995                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2996                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2997                                        update->dsc_config->num_slices_v != 0);
2998
2999                 /* Use temporarry context for validating new DSC config */
3000                 struct dc_state *dsc_validate_context = dc_create_state(dc);
3001
3002                 if (dsc_validate_context) {
3003                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
3004
3005                         stream->timing.dsc_cfg = *update->dsc_config;
3006                         stream->timing.flags.DSC = enable_dsc;
3007                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
3008                                 stream->timing.dsc_cfg = old_dsc_cfg;
3009                                 stream->timing.flags.DSC = old_dsc_enabled;
3010                                 update->dsc_config = NULL;
3011                         }
3012
3013                         dc_release_state(dsc_validate_context);
3014                 } else {
3015                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
3016                         update->dsc_config = NULL;
3017                 }
3018         }
3019 }
3020
3021 static void backup_plane_states_for_stream(
3022                 struct dc_plane_state plane_states[MAX_SURFACE_NUM],
3023                 struct dc_stream_state *stream)
3024 {
3025         int i;
3026         struct dc_stream_status *status = dc_stream_get_status(stream);
3027
3028         if (!status)
3029                 return;
3030
3031         for (i = 0; i < status->plane_count; i++)
3032                 plane_states[i] = *status->plane_states[i];
3033 }
3034
3035 static void restore_plane_states_for_stream(
3036                 struct dc_plane_state plane_states[MAX_SURFACE_NUM],
3037                 struct dc_stream_state *stream)
3038 {
3039         int i;
3040         struct dc_stream_status *status = dc_stream_get_status(stream);
3041
3042         if (!status)
3043                 return;
3044
3045         for (i = 0; i < status->plane_count; i++)
3046                 *status->plane_states[i] = plane_states[i];
3047 }
3048
3049 static bool update_planes_and_stream_state(struct dc *dc,
3050                 struct dc_surface_update *srf_updates, int surface_count,
3051                 struct dc_stream_state *stream,
3052                 struct dc_stream_update *stream_update,
3053                 enum surface_update_type *new_update_type,
3054                 struct dc_state **new_context)
3055 {
3056         struct dc_state *context;
3057         int i, j;
3058         enum surface_update_type update_type;
3059         const struct dc_stream_status *stream_status;
3060         struct dc_context *dc_ctx = dc->ctx;
3061
3062         stream_status = dc_stream_get_status(stream);
3063
3064         if (!stream_status) {
3065                 if (surface_count) /* Only an error condition if surf_count non-zero*/
3066                         ASSERT(false);
3067
3068                 return false; /* Cannot commit surface to stream that is not committed */
3069         }
3070
3071         context = dc->current_state;
3072         backup_plane_states_for_stream(dc->current_state->scratch.plane_states, stream);
3073         update_type = dc_check_update_surfaces_for_stream(
3074                         dc, srf_updates, surface_count, stream_update, stream_status);
3075
3076         /* update current stream with the new updates */
3077         copy_stream_update_to_stream(dc, context, stream, stream_update);
3078
3079         /* do not perform surface update if surface has invalid dimensions
3080          * (all zero) and no scaling_info is provided
3081          */
3082         if (surface_count > 0) {
3083                 for (i = 0; i < surface_count; i++) {
3084                         if ((srf_updates[i].surface->src_rect.width == 0 ||
3085                                  srf_updates[i].surface->src_rect.height == 0 ||
3086                                  srf_updates[i].surface->dst_rect.width == 0 ||
3087                                  srf_updates[i].surface->dst_rect.height == 0) &&
3088                                 (!srf_updates[i].scaling_info ||
3089                                   srf_updates[i].scaling_info->src_rect.width == 0 ||
3090                                   srf_updates[i].scaling_info->src_rect.height == 0 ||
3091                                   srf_updates[i].scaling_info->dst_rect.width == 0 ||
3092                                   srf_updates[i].scaling_info->dst_rect.height == 0)) {
3093                                 DC_ERROR("Invalid src/dst rects in surface update!\n");
3094                                 return false;
3095                         }
3096                 }
3097         }
3098
3099         if (update_type >= update_surface_trace_level)
3100                 update_surface_trace(dc, srf_updates, surface_count);
3101
3102         for (i = 0; i < surface_count; i++)
3103                 copy_surface_update_to_plane(srf_updates[i].surface, &srf_updates[i]);
3104
3105         if (update_type >= UPDATE_TYPE_FULL) {
3106                 struct dc_plane_state *new_planes[MAX_SURFACES] = {0};
3107
3108                 for (i = 0; i < surface_count; i++)
3109                         new_planes[i] = srf_updates[i].surface;
3110
3111                 /* initialize scratch memory for building context */
3112                 context = dc_create_state(dc);
3113                 if (context == NULL) {
3114                         DC_ERROR("Failed to allocate new validate context!\n");
3115                         return false;
3116                 }
3117
3118                 dc_resource_state_copy_construct(
3119                                 dc->current_state, context);
3120
3121                 /* For each full update, remove all existing phantom pipes first.
3122                  * Ensures that we have enough pipes for newly added MPO planes
3123                  */
3124                 if (dc->res_pool->funcs->remove_phantom_pipes)
3125                         dc->res_pool->funcs->remove_phantom_pipes(dc, context, false);
3126
3127                 /*remove old surfaces from context */
3128                 if (!dc_rem_all_planes_for_stream(dc, stream, context)) {
3129
3130                         BREAK_TO_DEBUGGER();
3131                         goto fail;
3132                 }
3133
3134                 /* add surface to context */
3135                 if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
3136
3137                         BREAK_TO_DEBUGGER();
3138                         goto fail;
3139                 }
3140         }
3141
3142         /* save update parameters into surface */
3143         for (i = 0; i < surface_count; i++) {
3144                 struct dc_plane_state *surface = srf_updates[i].surface;
3145
3146                 if (update_type >= UPDATE_TYPE_MED) {
3147                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3148                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3149
3150                                 if (pipe_ctx->plane_state != surface)
3151                                         continue;
3152
3153                                 resource_build_scaling_params(pipe_ctx);
3154                         }
3155                 }
3156         }
3157
3158         if (update_type == UPDATE_TYPE_FULL) {
3159                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
3160                         /* For phantom pipes we remove and create a new set of phantom pipes
3161                          * for each full update (because we don't know if we'll need phantom
3162                          * pipes until after the first round of validation). However, if validation
3163                          * fails we need to keep the existing phantom pipes (because we don't update
3164                          * the dc->current_state).
3165                          *
3166                          * The phantom stream/plane refcount is decremented for validation because
3167                          * we assume it'll be removed (the free comes when the dc_state is freed),
3168                          * but if validation fails we have to increment back the refcount so it's
3169                          * consistent.
3170                          */
3171                         if (dc->res_pool->funcs->retain_phantom_pipes)
3172                                 dc->res_pool->funcs->retain_phantom_pipes(dc, dc->current_state);
3173                         BREAK_TO_DEBUGGER();
3174                         goto fail;
3175                 }
3176
3177                 for (i = 0; i < context->stream_count; i++) {
3178                         struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx,
3179                                         context->streams[i]);
3180
3181                         if (otg_master->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)
3182                                 resource_build_test_pattern_params(&context->res_ctx, otg_master);
3183                 }
3184         }
3185
3186         *new_context = context;
3187         *new_update_type = update_type;
3188         backup_plane_states_for_stream(context->scratch.plane_states, stream);
3189
3190         return true;
3191
3192 fail:
3193         dc_release_state(context);
3194
3195         return false;
3196
3197 }
3198
3199 static void commit_planes_do_stream_update(struct dc *dc,
3200                 struct dc_stream_state *stream,
3201                 struct dc_stream_update *stream_update,
3202                 enum surface_update_type update_type,
3203                 struct dc_state *context)
3204 {
3205         int j;
3206
3207         // Stream updates
3208         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3209                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3210
3211                 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {
3212
3213                         if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
3214                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
3215
3216                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
3217                                         stream_update->vrr_infopacket ||
3218                                         stream_update->vsc_infopacket ||
3219                                         stream_update->vsp_infopacket ||
3220                                         stream_update->hfvsif_infopacket ||
3221                                         stream_update->adaptive_sync_infopacket ||
3222                                         stream_update->vtem_infopacket) {
3223                                 resource_build_info_frame(pipe_ctx);
3224                                 dc->hwss.update_info_frame(pipe_ctx);
3225
3226                                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3227                                         dc->link_srv->dp_trace_source_sequence(
3228                                                         pipe_ctx->stream->link,
3229                                                         DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
3230                         }
3231
3232                         if (stream_update->hdr_static_metadata &&
3233                                         stream->use_dynamic_meta &&
3234                                         dc->hwss.set_dmdata_attributes &&
3235                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
3236                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
3237
3238                         if (stream_update->gamut_remap)
3239                                 dc_stream_set_gamut_remap(dc, stream);
3240
3241                         if (stream_update->output_csc_transform)
3242                                 dc_stream_program_csc_matrix(dc, stream);
3243
3244                         if (stream_update->dither_option) {
3245                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
3246                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
3247                                                                         &pipe_ctx->stream->bit_depth_params);
3248                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
3249                                                 &stream->bit_depth_params,
3250                                                 &stream->clamping);
3251                                 while (odm_pipe) {
3252                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
3253                                                         &stream->bit_depth_params,
3254                                                         &stream->clamping);
3255                                         odm_pipe = odm_pipe->next_odm_pipe;
3256                                 }
3257                         }
3258
3259
3260                         /* Full fe update*/
3261                         if (update_type == UPDATE_TYPE_FAST)
3262                                 continue;
3263
3264                         if (stream_update->dsc_config)
3265                                 dc->link_srv->update_dsc_config(pipe_ctx);
3266
3267                         if (stream_update->mst_bw_update) {
3268                                 if (stream_update->mst_bw_update->is_increase)
3269                                         dc->link_srv->increase_mst_payload(pipe_ctx,
3270                                                         stream_update->mst_bw_update->mst_stream_bw);
3271                                 else
3272                                         dc->link_srv->reduce_mst_payload(pipe_ctx,
3273                                                         stream_update->mst_bw_update->mst_stream_bw);
3274                         }
3275
3276                         if (stream_update->pending_test_pattern) {
3277                                 dc_link_dp_set_test_pattern(stream->link,
3278                                         stream->test_pattern.type,
3279                                         stream->test_pattern.color_space,
3280                                         stream->test_pattern.p_link_settings,
3281                                         stream->test_pattern.p_custom_pattern,
3282                                         stream->test_pattern.cust_pattern_size);
3283                         }
3284
3285                         if (stream_update->dpms_off) {
3286                                 if (*stream_update->dpms_off) {
3287                                         dc->link_srv->set_dpms_off(pipe_ctx);
3288                                         /* for dpms, keep acquired resources*/
3289                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
3290                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
3291
3292                                         dc->optimized_required = true;
3293
3294                                 } else {
3295                                         if (get_seamless_boot_stream_count(context) == 0)
3296                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
3297                                         dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3298                                 }
3299                         } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space
3300                                         && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {
3301                                 /*
3302                                  * Workaround for firmware issue in some receivers where they don't pick up
3303                                  * correct output color space unless DP link is disabled/re-enabled
3304                                  */
3305                                 dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3306                         }
3307
3308                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
3309                                 bool should_program_abm = true;
3310
3311                                 // if otg funcs defined check if blanked before programming
3312                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
3313                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
3314                                                 should_program_abm = false;
3315
3316                                 if (should_program_abm) {
3317                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
3318                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
3319                                         } else {
3320                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
3321                                                         pipe_ctx->stream_res.abm, stream->abm_level);
3322                                         }
3323                                 }
3324                         }
3325                 }
3326         }
3327 }
3328
3329 static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
3330 {
3331         if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
3332                         || stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
3333                         && stream->ctx->dce_version >= DCN_VERSION_3_1)
3334                 return true;
3335
3336         if (stream->link->replay_settings.config.replay_supported)
3337                 return true;
3338
3339         return false;
3340 }
3341
3342 void dc_dmub_update_dirty_rect(struct dc *dc,
3343                                int surface_count,
3344                                struct dc_stream_state *stream,
3345                                struct dc_surface_update *srf_updates,
3346                                struct dc_state *context)
3347 {
3348         union dmub_rb_cmd cmd;
3349         struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3350         unsigned int i, j;
3351         unsigned int panel_inst = 0;
3352
3353         if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3354                 return;
3355
3356         if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3357                 return;
3358
3359         memset(&cmd, 0x0, sizeof(cmd));
3360         cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3361         cmd.update_dirty_rect.header.sub_type = 0;
3362         cmd.update_dirty_rect.header.payload_bytes =
3363                 sizeof(cmd.update_dirty_rect) -
3364                 sizeof(cmd.update_dirty_rect.header);
3365         update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3366         for (i = 0; i < surface_count; i++) {
3367                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3368                 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3369
3370                 if (!srf_updates[i].surface || !flip_addr)
3371                         continue;
3372                 /* Do not send in immediate flip mode */
3373                 if (srf_updates[i].surface->flip_immediate)
3374                         continue;
3375
3376                 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3377                 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3378                                 sizeof(flip_addr->dirty_rects));
3379                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3380                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3381
3382                         if (pipe_ctx->stream != stream)
3383                                 continue;
3384                         if (pipe_ctx->plane_state != plane_state)
3385                                 continue;
3386
3387                         update_dirty_rect->panel_inst = panel_inst;
3388                         update_dirty_rect->pipe_idx = j;
3389                         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
3390                 }
3391         }
3392 }
3393
3394 static void build_dmub_update_dirty_rect(
3395                 struct dc *dc,
3396                 int surface_count,
3397                 struct dc_stream_state *stream,
3398                 struct dc_surface_update *srf_updates,
3399                 struct dc_state *context,
3400                 struct dc_dmub_cmd dc_dmub_cmd[],
3401                 unsigned int *dmub_cmd_count)
3402 {
3403         union dmub_rb_cmd cmd;
3404         struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3405         unsigned int i, j;
3406         unsigned int panel_inst = 0;
3407
3408         if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3409                 return;
3410
3411         if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3412                 return;
3413
3414         memset(&cmd, 0x0, sizeof(cmd));
3415         cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3416         cmd.update_dirty_rect.header.sub_type = 0;
3417         cmd.update_dirty_rect.header.payload_bytes =
3418                 sizeof(cmd.update_dirty_rect) -
3419                 sizeof(cmd.update_dirty_rect.header);
3420         update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3421         for (i = 0; i < surface_count; i++) {
3422                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3423                 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3424
3425                 if (!srf_updates[i].surface || !flip_addr)
3426                         continue;
3427                 /* Do not send in immediate flip mode */
3428                 if (srf_updates[i].surface->flip_immediate)
3429                         continue;
3430                 update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
3431                 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3432                 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3433                                 sizeof(flip_addr->dirty_rects));
3434                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3435                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3436
3437                         if (pipe_ctx->stream != stream)
3438                                 continue;
3439                         if (pipe_ctx->plane_state != plane_state)
3440                                 continue;
3441                         update_dirty_rect->panel_inst = panel_inst;
3442                         update_dirty_rect->pipe_idx = j;
3443                         dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
3444                         dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
3445                         (*dmub_cmd_count)++;
3446                 }
3447         }
3448 }
3449
3450
3451 /**
3452  * build_dmub_cmd_list() - Build an array of DMCUB commands to be sent to DMCUB
3453  *
3454  * @dc: Current DC state
3455  * @srf_updates: Array of surface updates
3456  * @surface_count: Number of surfaces that have an updated
3457  * @stream: Corresponding stream to be updated in the current flip
3458  * @context: New DC state to be programmed
3459  *
3460  * @dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
3461  * @dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
3462  *
3463  * This function builds an array of DMCUB commands to be sent to DMCUB. This function is required
3464  * to build an array of commands and have them sent while the OTG lock is acquired.
3465  *
3466  * Return: void
3467  */
3468 static void build_dmub_cmd_list(struct dc *dc,
3469                 struct dc_surface_update *srf_updates,
3470                 int surface_count,
3471                 struct dc_stream_state *stream,
3472                 struct dc_state *context,
3473                 struct dc_dmub_cmd dc_dmub_cmd[],
3474                 unsigned int *dmub_cmd_count)
3475 {
3476         // Initialize cmd count to 0
3477         *dmub_cmd_count = 0;
3478         build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);
3479 }
3480
3481 static void commit_planes_for_stream_fast(struct dc *dc,
3482                 struct dc_surface_update *srf_updates,
3483                 int surface_count,
3484                 struct dc_stream_state *stream,
3485                 struct dc_stream_update *stream_update,
3486                 enum surface_update_type update_type,
3487                 struct dc_state *context)
3488 {
3489         int i, j;
3490         struct pipe_ctx *top_pipe_to_program = NULL;
3491         dc_z10_restore(dc);
3492
3493         top_pipe_to_program = resource_get_otg_master_for_stream(
3494                         &context->res_ctx,
3495                         stream);
3496
3497         if (dc->debug.visual_confirm) {
3498                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3499                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3500
3501                         if (pipe->stream && pipe->plane_state)
3502                                 dc_update_viusal_confirm_color(dc, context, pipe);
3503                 }
3504         }
3505
3506         for (i = 0; i < surface_count; i++) {
3507                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3508                 /*set logical flag for lock/unlock use*/
3509                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3510                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3511
3512                         if (!pipe_ctx->plane_state)
3513                                 continue;
3514                         if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3515                                 continue;
3516                         pipe_ctx->plane_state->triplebuffer_flips = false;
3517                         if (update_type == UPDATE_TYPE_FAST &&
3518                             dc->hwss.program_triplebuffer &&
3519                             !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3520                                 /*triple buffer for VUpdate  only*/
3521                                 pipe_ctx->plane_state->triplebuffer_flips = true;
3522                         }
3523                 }
3524         }
3525
3526         build_dmub_cmd_list(dc,
3527                         srf_updates,
3528                         surface_count,
3529                         stream,
3530                         context,
3531                         context->dc_dmub_cmd,
3532                         &(context->dmub_cmd_count));
3533         hwss_build_fast_sequence(dc,
3534                         context->dc_dmub_cmd,
3535                         context->dmub_cmd_count,
3536                         context->block_sequence,
3537                         &(context->block_sequence_steps),
3538                         top_pipe_to_program);
3539         hwss_execute_sequence(dc,
3540                         context->block_sequence,
3541                         context->block_sequence_steps);
3542         /* Clear update flags so next flip doesn't have redundant programming
3543          * (if there's no stream update, the update flags are not cleared).
3544          * Surface updates are cleared unconditionally at the beginning of each flip,
3545          * so no need to clear here.
3546          */
3547         if (top_pipe_to_program->stream)
3548                 top_pipe_to_program->stream->update_flags.raw = 0;
3549 }
3550
3551 static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state *dc_context)
3552 {
3553 /*
3554  * This function calls HWSS to wait for any potentially double buffered
3555  * operations to complete. It should be invoked as a pre-amble prior
3556  * to full update programming before asserting any HW locks.
3557  */
3558         int pipe_idx;
3559         int opp_inst;
3560         int opp_count = dc->res_pool->res_cap->num_opp;
3561         struct hubp *hubp;
3562         int mpcc_inst;
3563         const struct pipe_ctx *pipe_ctx;
3564
3565         for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
3566                 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
3567
3568                 if (!pipe_ctx->stream)
3569                         continue;
3570
3571                 if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
3572                         pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
3573
3574                 hubp = pipe_ctx->plane_res.hubp;
3575                 if (!hubp)
3576                         continue;
3577
3578                 mpcc_inst = hubp->inst;
3579                 // MPCC inst is equal to pipe index in practice
3580                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
3581                         if ((dc->res_pool->opps[opp_inst] != NULL) &&
3582                                 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
3583                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
3584                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
3585                                 break;
3586                         }
3587                 }
3588         }
3589 }
3590
3591 static void commit_planes_for_stream(struct dc *dc,
3592                 struct dc_surface_update *srf_updates,
3593                 int surface_count,
3594                 struct dc_stream_state *stream,
3595                 struct dc_stream_update *stream_update,
3596                 enum surface_update_type update_type,
3597                 struct dc_state *context)
3598 {
3599         int i, j;
3600         struct pipe_ctx *top_pipe_to_program = NULL;
3601         bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
3602         bool subvp_prev_use = false;
3603         bool subvp_curr_use = false;
3604         uint8_t current_stream_mask = 0;
3605
3606         // Once we apply the new subvp context to hardware it won't be in the
3607         // dc->current_state anymore, so we have to cache it before we apply
3608         // the new SubVP context
3609         subvp_prev_use = false;
3610         dc_z10_restore(dc);
3611         if (update_type == UPDATE_TYPE_FULL)
3612                 wait_for_outstanding_hw_updates(dc, context);
3613
3614         if (update_type == UPDATE_TYPE_FULL) {
3615                 dc_allow_idle_optimizations(dc, false);
3616
3617                 if (get_seamless_boot_stream_count(context) == 0)
3618                         dc->hwss.prepare_bandwidth(dc, context);
3619
3620                 if (dc->hwss.update_dsc_pg)
3621                         dc->hwss.update_dsc_pg(dc, context, false);
3622
3623                 context_clock_trace(dc, context);
3624         }
3625
3626         top_pipe_to_program = resource_get_otg_master_for_stream(
3627                                 &context->res_ctx,
3628                                 stream);
3629
3630         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3631                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3632
3633                 // Check old context for SubVP
3634                 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);
3635                 if (subvp_prev_use)
3636                         break;
3637         }
3638
3639         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3640                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3641
3642                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
3643                         subvp_curr_use = true;
3644                         break;
3645                 }
3646         }
3647
3648         if (dc->debug.visual_confirm)
3649                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3650                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3651
3652                         if (pipe->stream && pipe->plane_state)
3653                                 dc_update_viusal_confirm_color(dc, context, pipe);
3654                 }
3655
3656         if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
3657                 struct pipe_ctx *mpcc_pipe;
3658                 struct pipe_ctx *odm_pipe;
3659
3660                 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
3661                         for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3662                                 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
3663         }
3664
3665         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3666                 if (top_pipe_to_program &&
3667                         top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3668                         if (should_use_dmub_lock(stream->link)) {
3669                                 union dmub_hw_lock_flags hw_locks = { 0 };
3670                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3671
3672                                 hw_locks.bits.lock_dig = 1;
3673                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3674
3675                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3676                                                         true,
3677                                                         &hw_locks,
3678                                                         &inst_flags);
3679                         } else
3680                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
3681                                                 top_pipe_to_program->stream_res.tg);
3682                 }
3683
3684         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3685                 if (dc->hwss.subvp_pipe_control_lock)
3686                                 dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);
3687                 dc->hwss.interdependent_update_lock(dc, context, true);
3688
3689         } else {
3690                 if (dc->hwss.subvp_pipe_control_lock)
3691                         dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3692                 /* Lock the top pipe while updating plane addrs, since freesync requires
3693                  *  plane addr update event triggers to be synchronized.
3694                  *  top_pipe_to_program is expected to never be NULL
3695                  */
3696                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
3697         }
3698
3699         dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
3700
3701         // Stream updates
3702         if (stream_update)
3703                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
3704
3705         if (surface_count == 0) {
3706                 /*
3707                  * In case of turning off screen, no need to program front end a second time.
3708                  * just return after program blank.
3709                  */
3710                 if (dc->hwss.apply_ctx_for_surface)
3711                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
3712                 if (dc->hwss.program_front_end_for_ctx)
3713                         dc->hwss.program_front_end_for_ctx(dc, context);
3714
3715                 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3716                         dc->hwss.interdependent_update_lock(dc, context, false);
3717                 } else {
3718                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3719                 }
3720                 dc->hwss.post_unlock_program_front_end(dc, context);
3721
3722                 if (update_type != UPDATE_TYPE_FAST)
3723                         if (dc->hwss.commit_subvp_config)
3724                                 dc->hwss.commit_subvp_config(dc, context);
3725
3726                 /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3727                  * move the SubVP lock to after the phantom pipes have been setup
3728                  */
3729                 if (dc->hwss.subvp_pipe_control_lock)
3730                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,
3731                                                          NULL, subvp_prev_use);
3732                 return;
3733         }
3734
3735         if (update_type != UPDATE_TYPE_FAST) {
3736                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3737                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3738
3739                         if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||
3740                                 dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&
3741                                 pipe_ctx->stream && pipe_ctx->plane_state) {
3742                                 /* Only update visual confirm for SUBVP and Mclk switching here.
3743                                  * The bar appears on all pipes, so we need to update the bar on all displays,
3744                                  * so the information doesn't get stale.
3745                                  */
3746                                 dc->hwss.update_visual_confirm_color(dc, pipe_ctx,
3747                                                 pipe_ctx->plane_res.hubp->inst);
3748                         }
3749                 }
3750         }
3751
3752         for (i = 0; i < surface_count; i++) {
3753                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3754                 /*set logical flag for lock/unlock use*/
3755                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3756                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3757                         if (!pipe_ctx->plane_state)
3758                                 continue;
3759                         if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3760                                 continue;
3761                         pipe_ctx->plane_state->triplebuffer_flips = false;
3762                         if (update_type == UPDATE_TYPE_FAST &&
3763                                 dc->hwss.program_triplebuffer != NULL &&
3764                                 !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3765                                         /*triple buffer for VUpdate  only*/
3766                                         pipe_ctx->plane_state->triplebuffer_flips = true;
3767                         }
3768                 }
3769                 if (update_type == UPDATE_TYPE_FULL) {
3770                         /* force vsync flip when reconfiguring pipes to prevent underflow */
3771                         plane_state->flip_immediate = false;
3772                 }
3773         }
3774
3775         // Update Type FULL, Surface updates
3776         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3777                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3778
3779                 if (!pipe_ctx->top_pipe &&
3780                         !pipe_ctx->prev_odm_pipe &&
3781                         should_update_pipe_for_stream(context, pipe_ctx, stream)) {
3782                         struct dc_stream_status *stream_status = NULL;
3783
3784                         if (!pipe_ctx->plane_state)
3785                                 continue;
3786
3787                         /* Full fe update*/
3788                         if (update_type == UPDATE_TYPE_FAST)
3789                                 continue;
3790
3791                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
3792
3793                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3794                                 /*turn off triple buffer for full update*/
3795                                 dc->hwss.program_triplebuffer(
3796                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3797                         }
3798                         stream_status =
3799                                 stream_get_status(context, pipe_ctx->stream);
3800
3801                         if (dc->hwss.apply_ctx_for_surface)
3802                                 dc->hwss.apply_ctx_for_surface(
3803                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
3804                 }
3805         }
3806         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
3807                 dc->hwss.program_front_end_for_ctx(dc, context);
3808                 if (dc->debug.validate_dml_output) {
3809                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3810                                 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
3811                                 if (cur_pipe->stream == NULL)
3812                                         continue;
3813
3814                                 cur_pipe->plane_res.hubp->funcs->validate_dml_output(
3815                                                 cur_pipe->plane_res.hubp, dc->ctx,
3816                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
3817                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
3818                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
3819                         }
3820                 }
3821         }
3822
3823         // Update Type FAST, Surface updates
3824         if (update_type == UPDATE_TYPE_FAST) {
3825                 if (dc->hwss.set_flip_control_gsl)
3826                         for (i = 0; i < surface_count; i++) {
3827                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3828
3829                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3830                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3831
3832                                         if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3833                                                 continue;
3834
3835                                         if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3836                                                 continue;
3837
3838                                         // GSL has to be used for flip immediate
3839                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
3840                                                         pipe_ctx->plane_state->flip_immediate);
3841                                 }
3842                         }
3843
3844                 /* Perform requested Updates */
3845                 for (i = 0; i < surface_count; i++) {
3846                         struct dc_plane_state *plane_state = srf_updates[i].surface;
3847
3848                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3849                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3850
3851                                 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3852                                         continue;
3853
3854                                 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3855                                         continue;
3856
3857                                 /*program triple buffer after lock based on flip type*/
3858                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3859                                         /*only enable triplebuffer for  fast_update*/
3860                                         dc->hwss.program_triplebuffer(
3861                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3862                                 }
3863                                 if (pipe_ctx->plane_state->update_flags.bits.addr_update)
3864                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
3865                         }
3866                 }
3867         }
3868
3869         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3870                 dc->hwss.interdependent_update_lock(dc, context, false);
3871         } else {
3872                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3873         }
3874
3875         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3876                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3877                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3878                                 top_pipe_to_program->stream_res.tg,
3879                                 CRTC_STATE_VACTIVE);
3880                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3881                                 top_pipe_to_program->stream_res.tg,
3882                                 CRTC_STATE_VBLANK);
3883                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3884                                 top_pipe_to_program->stream_res.tg,
3885                                 CRTC_STATE_VACTIVE);
3886
3887                         if (should_use_dmub_lock(stream->link)) {
3888                                 union dmub_hw_lock_flags hw_locks = { 0 };
3889                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3890
3891                                 hw_locks.bits.lock_dig = 1;
3892                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3893
3894                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3895                                                         false,
3896                                                         &hw_locks,
3897                                                         &inst_flags);
3898                         } else
3899                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
3900                                         top_pipe_to_program->stream_res.tg);
3901                 }
3902
3903         if (subvp_curr_use) {
3904                 /* If enabling subvp or transitioning from subvp->subvp, enable the
3905                  * phantom streams before we program front end for the phantom pipes.
3906                  */
3907                 if (update_type != UPDATE_TYPE_FAST) {
3908                         if (dc->hwss.enable_phantom_streams)
3909                                 dc->hwss.enable_phantom_streams(dc, context);
3910                 }
3911         }
3912
3913         if (update_type != UPDATE_TYPE_FAST)
3914                 dc->hwss.post_unlock_program_front_end(dc, context);
3915
3916         if (subvp_prev_use && !subvp_curr_use) {
3917                 /* If disabling subvp, disable phantom streams after front end
3918                  * programming has completed (we turn on phantom OTG in order
3919                  * to complete the plane disable for phantom pipes).
3920                  */
3921                 dc->hwss.apply_ctx_to_hw(dc, context);
3922         }
3923
3924         if (update_type != UPDATE_TYPE_FAST)
3925                 if (dc->hwss.commit_subvp_config)
3926                         dc->hwss.commit_subvp_config(dc, context);
3927         /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3928          * move the SubVP lock to after the phantom pipes have been setup
3929          */
3930         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3931                 if (dc->hwss.subvp_pipe_control_lock)
3932                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);
3933         } else {
3934                 if (dc->hwss.subvp_pipe_control_lock)
3935                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3936         }
3937
3938         // Fire manual trigger only when bottom plane is flipped
3939         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3940                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3941
3942                 if (!pipe_ctx->plane_state)
3943                         continue;
3944
3945                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
3946                                 !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
3947                                 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
3948                                 pipe_ctx->plane_state->skip_manual_trigger)
3949                         continue;
3950
3951                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
3952                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
3953         }
3954
3955         current_stream_mask = get_stream_mask(dc, context);
3956         if (current_stream_mask != context->stream_mask) {
3957                 context->stream_mask = current_stream_mask;
3958                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, current_stream_mask);
3959         }
3960 }
3961
3962 /**
3963  * could_mpcc_tree_change_for_active_pipes - Check if an OPP associated with MPCC might change
3964  *
3965  * @dc: Used to get the current state status
3966  * @stream: Target stream, which we want to remove the attached planes
3967  * @srf_updates: Array of surface updates
3968  * @surface_count: Number of surface update
3969  * @is_plane_addition: [in] Fill out with true if it is a plane addition case
3970  *
3971  * DCN32x and newer support a feature named Dynamic ODM which can conflict with
3972  * the MPO if used simultaneously in some specific configurations (e.g.,
3973  * 4k@144). This function checks if the incoming context requires applying a
3974  * transition state with unnecessary pipe splitting and ODM disabled to
3975  * circumvent our hardware limitations to prevent this edge case. If the OPP
3976  * associated with an MPCC might change due to plane additions, this function
3977  * returns true.
3978  *
3979  * Return:
3980  * Return true if OPP and MPCC might change, otherwise, return false.
3981  */
3982 static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
3983                 struct dc_stream_state *stream,
3984                 struct dc_surface_update *srf_updates,
3985                 int surface_count,
3986                 bool *is_plane_addition)
3987 {
3988
3989         struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
3990         bool force_minimal_pipe_splitting = false;
3991         bool subvp_active = false;
3992         uint32_t i;
3993
3994         *is_plane_addition = false;
3995
3996         if (cur_stream_status &&
3997                         dc->current_state->stream_count > 0 &&
3998                         dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) {
3999                 /* determine if minimal transition is required due to MPC*/
4000                 if (surface_count > 0) {
4001                         if (cur_stream_status->plane_count > surface_count) {
4002                                 force_minimal_pipe_splitting = true;
4003                         } else if (cur_stream_status->plane_count < surface_count) {
4004                                 force_minimal_pipe_splitting = true;
4005                                 *is_plane_addition = true;
4006                         }
4007                 }
4008         }
4009
4010         if (cur_stream_status &&
4011                         dc->current_state->stream_count == 1 &&
4012                         dc->debug.enable_single_display_2to1_odm_policy) {
4013                 /* determine if minimal transition is required due to dynamic ODM*/
4014                 if (surface_count > 0) {
4015                         if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) {
4016                                 force_minimal_pipe_splitting = true;
4017                         } else if (surface_count > 2 && cur_stream_status->plane_count < surface_count) {
4018                                 force_minimal_pipe_splitting = true;
4019                                 *is_plane_addition = true;
4020                         }
4021                 }
4022         }
4023
4024         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4025                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4026
4027                 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
4028                         subvp_active = true;
4029                         break;
4030                 }
4031         }
4032
4033         /* For SubVP when adding or removing planes we need to add a minimal transition
4034          * (even when disabling all planes). Whenever disabling a phantom pipe, we
4035          * must use the minimal transition path to disable the pipe correctly.
4036          *
4037          * We want to use the minimal transition whenever subvp is active, not only if
4038          * a plane is being added / removed from a subvp stream (MPO plane can be added
4039          * to a DRR pipe of SubVP + DRR config, in which case we still want to run through
4040          * a min transition to disable subvp.
4041          */
4042         if (cur_stream_status && subvp_active) {
4043                 /* determine if minimal transition is required due to SubVP*/
4044                 if (cur_stream_status->plane_count > surface_count) {
4045                         force_minimal_pipe_splitting = true;
4046                 } else if (cur_stream_status->plane_count < surface_count) {
4047                         force_minimal_pipe_splitting = true;
4048                         *is_plane_addition = true;
4049                 }
4050         }
4051
4052         return force_minimal_pipe_splitting;
4053 }
4054
4055 struct pipe_split_policy_backup {
4056         bool dynamic_odm_policy;
4057         bool subvp_policy;
4058         enum pipe_split_policy mpc_policy;
4059 };
4060
4061 static void release_minimal_transition_state(struct dc *dc,
4062                 struct dc_state *context, struct pipe_split_policy_backup *policy)
4063 {
4064         dc_release_state(context);
4065         /* restore previous pipe split and odm policy */
4066         if (!dc->config.is_vmin_only_asic)
4067                 dc->debug.pipe_split_policy = policy->mpc_policy;
4068         dc->debug.enable_single_display_2to1_odm_policy = policy->dynamic_odm_policy;
4069         dc->debug.force_disable_subvp = policy->subvp_policy;
4070 }
4071
4072 static struct dc_state *create_minimal_transition_state(struct dc *dc,
4073                 struct dc_state *base_context, struct pipe_split_policy_backup *policy)
4074 {
4075         struct dc_state *minimal_transition_context = dc_create_state(dc);
4076         unsigned int i, j;
4077
4078         if (!dc->config.is_vmin_only_asic) {
4079                 policy->mpc_policy = dc->debug.pipe_split_policy;
4080                 dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
4081         }
4082         policy->dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy;
4083         dc->debug.enable_single_display_2to1_odm_policy = false;
4084         policy->subvp_policy = dc->debug.force_disable_subvp;
4085         dc->debug.force_disable_subvp = true;
4086
4087         dc_resource_state_copy_construct(base_context, minimal_transition_context);
4088
4089         /* commit minimal state */
4090         if (dc->res_pool->funcs->validate_bandwidth(dc, minimal_transition_context, false)) {
4091                 for (i = 0; i < minimal_transition_context->stream_count; i++) {
4092                         struct dc_stream_status *stream_status = &minimal_transition_context->stream_status[i];
4093
4094                         for (j = 0; j < stream_status->plane_count; j++) {
4095                                 struct dc_plane_state *plane_state = stream_status->plane_states[j];
4096
4097                                 /* force vsync flip when reconfiguring pipes to prevent underflow
4098                                  * and corruption
4099                                  */
4100                                 plane_state->flip_immediate = false;
4101                         }
4102                 }
4103         } else {
4104                 /* this should never happen */
4105                 release_minimal_transition_state(dc, minimal_transition_context, policy);
4106                 BREAK_TO_DEBUGGER();
4107                 minimal_transition_context = NULL;
4108         }
4109         return minimal_transition_context;
4110 }
4111
4112 static bool commit_minimal_transition_state_for_windowed_mpo_odm(struct dc *dc,
4113                 struct dc_state *context,
4114                 struct dc_stream_state *stream)
4115 {
4116         bool success = false;
4117         struct dc_state *minimal_transition_context;
4118         struct pipe_split_policy_backup policy;
4119         struct mall_temp_config mall_temp_config;
4120
4121         /* commit based on new context */
4122         /* Since all phantom pipes are removed in full validation,
4123          * we have to save and restore the subvp/mall config when
4124          * we do a minimal transition since the flags marking the
4125          * pipe as subvp/phantom will be cleared (dc copy constructor
4126          * creates a shallow copy).
4127          */
4128         if (dc->res_pool->funcs->save_mall_state)
4129                 dc->res_pool->funcs->save_mall_state(dc, context, &mall_temp_config);
4130         minimal_transition_context = create_minimal_transition_state(dc,
4131                         context, &policy);
4132         if (minimal_transition_context) {
4133                 if (dc->hwss.is_pipe_topology_transition_seamless(
4134                                         dc, dc->current_state, minimal_transition_context) &&
4135                         dc->hwss.is_pipe_topology_transition_seamless(
4136                                         dc, minimal_transition_context, context)) {
4137                         DC_LOG_DC("%s base = new state\n", __func__);
4138
4139                         success = dc_commit_state_no_check(dc, minimal_transition_context) == DC_OK;
4140                 }
4141                 release_minimal_transition_state(dc, minimal_transition_context, &policy);
4142                 if (dc->res_pool->funcs->restore_mall_state)
4143                         dc->res_pool->funcs->restore_mall_state(dc, context, &mall_temp_config);
4144                 /* If we do a minimal transition with plane removal and the context
4145                  * has subvp we also have to retain back the phantom stream / planes
4146                  * since the refcount is decremented as part of the min transition
4147                  * (we commit a state with no subvp, so the phantom streams / planes
4148                  * had to be removed).
4149                  */
4150                 if (dc->res_pool->funcs->retain_phantom_pipes)
4151                         dc->res_pool->funcs->retain_phantom_pipes(dc, context);
4152         }
4153
4154         if (!success) {
4155                 /* commit based on current context */
4156                 restore_plane_states_for_stream(dc->current_state->scratch.plane_states, stream);
4157                 minimal_transition_context = create_minimal_transition_state(dc,
4158                                 dc->current_state, &policy);
4159                 if (minimal_transition_context) {
4160                         if (dc->hwss.is_pipe_topology_transition_seamless(
4161                                         dc, dc->current_state, minimal_transition_context) &&
4162                                 dc->hwss.is_pipe_topology_transition_seamless(
4163                                                 dc, minimal_transition_context, context)) {
4164                                 DC_LOG_DC("%s base = current state\n", __func__);
4165                                 success = dc_commit_state_no_check(dc, minimal_transition_context) == DC_OK;
4166                         }
4167                         release_minimal_transition_state(dc, minimal_transition_context, &policy);
4168                 }
4169                 restore_plane_states_for_stream(context->scratch.plane_states, stream);
4170         }
4171
4172         ASSERT(success);
4173         return success;
4174 }
4175
4176 /**
4177  * commit_minimal_transition_state - Create a transition pipe split state
4178  *
4179  * @dc: Used to get the current state status
4180  * @transition_base_context: New transition state
4181  *
4182  * In some specific configurations, such as pipe split on multi-display with
4183  * MPO and/or Dynamic ODM, removing a plane may cause unsupported pipe
4184  * programming when moving to new planes. To mitigate those types of problems,
4185  * this function adds a transition state that minimizes pipe usage before
4186  * programming the new configuration. When adding a new plane, the current
4187  * state requires the least pipes, so it is applied without splitting. When
4188  * removing a plane, the new state requires the least pipes, so it is applied
4189  * without splitting.
4190  *
4191  * Return:
4192  * Return false if something is wrong in the transition state.
4193  */
4194 static bool commit_minimal_transition_state(struct dc *dc,
4195                 struct dc_state *transition_base_context)
4196 {
4197         struct dc_state *transition_context;
4198         struct pipe_split_policy_backup policy;
4199         enum dc_status ret = DC_ERROR_UNEXPECTED;
4200         unsigned int i, j;
4201         unsigned int pipe_in_use = 0;
4202         bool subvp_in_use = false;
4203         bool odm_in_use = false;
4204
4205         /* check current pipes in use*/
4206         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4207                 struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
4208
4209                 if (pipe->plane_state)
4210                         pipe_in_use++;
4211         }
4212
4213         /* If SubVP is enabled and we are adding or removing planes from any main subvp
4214          * pipe, we must use the minimal transition.
4215          */
4216         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4217                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4218
4219                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
4220                         subvp_in_use = true;
4221                         break;
4222                 }
4223         }
4224
4225         /* If ODM is enabled and we are adding or removing planes from any ODM
4226          * pipe, we must use the minimal transition.
4227          */
4228         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4229                 struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
4230
4231                 if (resource_is_pipe_type(pipe, OTG_MASTER)) {
4232                         odm_in_use = resource_get_odm_slice_count(pipe) > 1;
4233                         break;
4234                 }
4235         }
4236
4237         /* When the OS add a new surface if we have been used all of pipes with odm combine
4238          * and mpc split feature, it need use commit_minimal_transition_state to transition safely.
4239          * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need
4240          * call it again. Otherwise return true to skip.
4241          *
4242          * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially
4243          * enter/exit MPO when DCN still have enough resources.
4244          */
4245         if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use)
4246                 return true;
4247
4248         DC_LOG_DC("%s base = %s state, reason = %s\n", __func__,
4249                         dc->current_state == transition_base_context ? "current" : "new",
4250                         subvp_in_use ? "Subvp In Use" :
4251                         odm_in_use ? "ODM in Use" :
4252                         dc->debug.pipe_split_policy != MPC_SPLIT_AVOID ? "MPC in Use" :
4253                         "Unknown");
4254
4255         transition_context = create_minimal_transition_state(dc,
4256                         transition_base_context, &policy);
4257         if (transition_context) {
4258                 ret = dc_commit_state_no_check(dc, transition_context);
4259                 release_minimal_transition_state(dc, transition_context, &policy);
4260         }
4261
4262         if (ret != DC_OK) {
4263                 /* this should never happen */
4264                 BREAK_TO_DEBUGGER();
4265                 return false;
4266         }
4267
4268         /* force full surface update */
4269         for (i = 0; i < dc->current_state->stream_count; i++) {
4270                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
4271                         dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF;
4272                 }
4273         }
4274
4275         return true;
4276 }
4277
4278 /**
4279  * update_seamless_boot_flags() - Helper function for updating seamless boot flags
4280  *
4281  * @dc: Current DC state
4282  * @context: New DC state to be programmed
4283  * @surface_count: Number of surfaces that have an updated
4284  * @stream: Corresponding stream to be updated in the current flip
4285  *
4286  * Updating seamless boot flags do not need to be part of the commit sequence. This
4287  * helper function will update the seamless boot flags on each flip (if required)
4288  * outside of the HW commit sequence (fast or slow).
4289  *
4290  * Return: void
4291  */
4292 static void update_seamless_boot_flags(struct dc *dc,
4293                 struct dc_state *context,
4294                 int surface_count,
4295                 struct dc_stream_state *stream)
4296 {
4297         if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
4298                 /* Optimize seamless boot flag keeps clocks and watermarks high until
4299                  * first flip. After first flip, optimization is required to lower
4300                  * bandwidth. Important to note that it is expected UEFI will
4301                  * only light up a single display on POST, therefore we only expect
4302                  * one stream with seamless boot flag set.
4303                  */
4304                 if (stream->apply_seamless_boot_optimization) {
4305                         stream->apply_seamless_boot_optimization = false;
4306
4307                         if (get_seamless_boot_stream_count(context) == 0)
4308                                 dc->optimized_required = true;
4309                 }
4310         }
4311 }
4312
4313 static void populate_fast_updates(struct dc_fast_update *fast_update,
4314                 struct dc_surface_update *srf_updates,
4315                 int surface_count,
4316                 struct dc_stream_update *stream_update)
4317 {
4318         int i = 0;
4319
4320         if (stream_update) {
4321                 fast_update[0].out_transfer_func = stream_update->out_transfer_func;
4322                 fast_update[0].output_csc_transform = stream_update->output_csc_transform;
4323         }
4324
4325         for (i = 0; i < surface_count; i++) {
4326                 fast_update[i].flip_addr = srf_updates[i].flip_addr;
4327                 fast_update[i].gamma = srf_updates[i].gamma;
4328                 fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix;
4329                 fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix;
4330                 fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor;
4331         }
4332 }
4333
4334 static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_count)
4335 {
4336         int i;
4337
4338         if (fast_update[0].out_transfer_func ||
4339                 fast_update[0].output_csc_transform)
4340                 return true;
4341
4342         for (i = 0; i < surface_count; i++) {
4343                 if (fast_update[i].flip_addr ||
4344                                 fast_update[i].gamma ||
4345                                 fast_update[i].gamut_remap_matrix ||
4346                                 fast_update[i].input_csc_color_matrix ||
4347                                 fast_update[i].coeff_reduction_factor)
4348                         return true;
4349         }
4350
4351         return false;
4352 }
4353
4354 static bool full_update_required(struct dc *dc,
4355                 struct dc_surface_update *srf_updates,
4356                 int surface_count,
4357                 struct dc_stream_update *stream_update,
4358                 struct dc_stream_state *stream)
4359 {
4360
4361         int i;
4362         struct dc_stream_status *stream_status;
4363         const struct dc_state *context = dc->current_state;
4364
4365         for (i = 0; i < surface_count; i++) {
4366                 if (srf_updates &&
4367                                 (srf_updates[i].plane_info ||
4368                                 srf_updates[i].scaling_info ||
4369                                 (srf_updates[i].hdr_mult.value &&
4370                                 srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) ||
4371                                 srf_updates[i].in_transfer_func ||
4372                                 srf_updates[i].func_shaper ||
4373                                 srf_updates[i].lut3d_func ||
4374                                 srf_updates[i].surface->force_full_update ||
4375                                 (srf_updates[i].flip_addr &&
4376                                 srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) ||
4377                                 !is_surface_in_context(context, srf_updates[i].surface)))
4378                         return true;
4379         }
4380
4381         if (stream_update &&
4382                         (((stream_update->src.height != 0 && stream_update->src.width != 0) ||
4383                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
4384                         stream_update->integer_scaling_update) ||
4385                         stream_update->hdr_static_metadata ||
4386                         stream_update->abm_level ||
4387                         stream_update->periodic_interrupt ||
4388                         stream_update->vrr_infopacket ||
4389                         stream_update->vsc_infopacket ||
4390                         stream_update->vsp_infopacket ||
4391                         stream_update->hfvsif_infopacket ||
4392                         stream_update->vtem_infopacket ||
4393                         stream_update->adaptive_sync_infopacket ||
4394                         stream_update->dpms_off ||
4395                         stream_update->allow_freesync ||
4396                         stream_update->vrr_active_variable ||
4397                         stream_update->vrr_active_fixed ||
4398                         stream_update->gamut_remap ||
4399                         stream_update->output_color_space ||
4400                         stream_update->dither_option ||
4401                         stream_update->wb_update ||
4402                         stream_update->dsc_config ||
4403                         stream_update->mst_bw_update ||
4404                         stream_update->func_shaper ||
4405                         stream_update->lut3d_func ||
4406                         stream_update->pending_test_pattern ||
4407                         stream_update->crtc_timing_adjust))
4408                 return true;
4409
4410         if (stream) {
4411                 stream_status = dc_stream_get_status(stream);
4412                 if (stream_status == NULL || stream_status->plane_count != surface_count)
4413                         return true;
4414         }
4415         if (dc->idle_optimizations_allowed)
4416                 return true;
4417
4418         return false;
4419 }
4420
4421 static bool fast_update_only(struct dc *dc,
4422                 struct dc_fast_update *fast_update,
4423                 struct dc_surface_update *srf_updates,
4424                 int surface_count,
4425                 struct dc_stream_update *stream_update,
4426                 struct dc_stream_state *stream)
4427 {
4428         return fast_updates_exist(fast_update, surface_count)
4429                         && !full_update_required(dc, srf_updates, surface_count, stream_update, stream);
4430 }
4431
4432 static bool should_commit_minimal_transition_for_windowed_mpo_odm(struct dc *dc,
4433                 struct dc_stream_state *stream,
4434                 struct dc_state *context)
4435 {
4436         struct pipe_ctx *cur_pipe, *new_pipe;
4437         bool cur_is_odm_in_use, new_is_odm_in_use;
4438         struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
4439         struct dc_stream_status *new_stream_status = stream_get_status(context, stream);
4440
4441         if (!dc->debug.enable_single_display_2to1_odm_policy ||
4442                         !dc->config.enable_windowed_mpo_odm)
4443                 /* skip the check if windowed MPO ODM or dynamic ODM is turned
4444                  * off.
4445                  */
4446                 return false;
4447
4448         if (context == dc->current_state)
4449                 /* skip the check for fast update */
4450                 return false;
4451
4452         if (new_stream_status->plane_count != cur_stream_status->plane_count)
4453                 /* plane count changed, not a plane scaling update so not the
4454                  * case we are looking for
4455                  */
4456                 return false;
4457
4458         cur_pipe = resource_get_otg_master_for_stream(&dc->current_state->res_ctx, stream);
4459         new_pipe = resource_get_otg_master_for_stream(&context->res_ctx, stream);
4460         cur_is_odm_in_use = resource_get_odm_slice_count(cur_pipe) > 1;
4461         new_is_odm_in_use = resource_get_odm_slice_count(new_pipe) > 1;
4462         if (cur_is_odm_in_use == new_is_odm_in_use)
4463                 /* ODM state isn't changed, not the case we are looking for */
4464                 return false;
4465
4466         if (dc->hwss.is_pipe_topology_transition_seamless &&
4467                         dc->hwss.is_pipe_topology_transition_seamless(
4468                                         dc, dc->current_state, context))
4469                 /* transition can be achieved without the need for committing
4470                  * minimal transition state first
4471                  */
4472                 return false;
4473
4474         return true;
4475 }
4476
4477 bool dc_update_planes_and_stream(struct dc *dc,
4478                 struct dc_surface_update *srf_updates, int surface_count,
4479                 struct dc_stream_state *stream,
4480                 struct dc_stream_update *stream_update)
4481 {
4482         struct dc_state *context;
4483         enum surface_update_type update_type;
4484         int i;
4485         struct mall_temp_config mall_temp_config;
4486         struct dc_fast_update fast_update[MAX_SURFACES] = {0};
4487
4488         /* In cases where MPO and split or ODM are used transitions can
4489          * cause underflow. Apply stream configuration with minimal pipe
4490          * split first to avoid unsupported transitions for active pipes.
4491          */
4492         bool force_minimal_pipe_splitting = 0;
4493         bool is_plane_addition = 0;
4494         bool is_fast_update_only;
4495
4496         populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
4497         is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,
4498                         surface_count, stream_update, stream);
4499         force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
4500                         dc,
4501                         stream,
4502                         srf_updates,
4503                         surface_count,
4504                         &is_plane_addition);
4505
4506         /* on plane addition, minimal state is the current one */
4507         if (force_minimal_pipe_splitting && is_plane_addition &&
4508                 !commit_minimal_transition_state(dc, dc->current_state))
4509                                 return false;
4510
4511         if (!update_planes_and_stream_state(
4512                         dc,
4513                         srf_updates,
4514                         surface_count,
4515                         stream,
4516                         stream_update,
4517                         &update_type,
4518                         &context))
4519                 return false;
4520
4521         /* on plane removal, minimal state is the new one */
4522         if (force_minimal_pipe_splitting && !is_plane_addition) {
4523                 /* Since all phantom pipes are removed in full validation,
4524                  * we have to save and restore the subvp/mall config when
4525                  * we do a minimal transition since the flags marking the
4526                  * pipe as subvp/phantom will be cleared (dc copy constructor
4527                  * creates a shallow copy).
4528                  */
4529                 if (dc->res_pool->funcs->save_mall_state)
4530                         dc->res_pool->funcs->save_mall_state(dc, context, &mall_temp_config);
4531                 if (!commit_minimal_transition_state(dc, context)) {
4532                         dc_release_state(context);
4533                         return false;
4534                 }
4535                 if (dc->res_pool->funcs->restore_mall_state)
4536                         dc->res_pool->funcs->restore_mall_state(dc, context, &mall_temp_config);
4537
4538                 /* If we do a minimal transition with plane removal and the context
4539                  * has subvp we also have to retain back the phantom stream / planes
4540                  * since the refcount is decremented as part of the min transition
4541                  * (we commit a state with no subvp, so the phantom streams / planes
4542                  * had to be removed).
4543                  */
4544                 if (dc->res_pool->funcs->retain_phantom_pipes)
4545                         dc->res_pool->funcs->retain_phantom_pipes(dc, context);
4546                 update_type = UPDATE_TYPE_FULL;
4547         }
4548
4549         /* when windowed MPO ODM is supported, we need to handle a special case
4550          * where we can transition between ODM combine and MPC combine due to
4551          * plane scaling update. This transition will require us to commit
4552          * minimal transition state. The condition to trigger this update can't
4553          * be predicted by could_mpcc_tree_change_for_active_pipes because we
4554          * can only determine it after DML validation. Therefore we can't rely
4555          * on the existing commit minimal transition state sequence. Instead
4556          * we have to add additional handling here to handle this transition
4557          * with its own special sequence.
4558          */
4559         if (should_commit_minimal_transition_for_windowed_mpo_odm(dc, stream, context))
4560                 commit_minimal_transition_state_for_windowed_mpo_odm(dc,
4561                                 context, stream);
4562         update_seamless_boot_flags(dc, context, surface_count, stream);
4563         if (is_fast_update_only && !dc->debug.enable_legacy_fast_update) {
4564                 commit_planes_for_stream_fast(dc,
4565                                 srf_updates,
4566                                 surface_count,
4567                                 stream,
4568                                 stream_update,
4569                                 update_type,
4570                                 context);
4571         } else {
4572                 if (!stream_update &&
4573                                 dc->hwss.is_pipe_topology_transition_seamless &&
4574                                 !dc->hwss.is_pipe_topology_transition_seamless(
4575                                                 dc, dc->current_state, context)) {
4576                         DC_LOG_ERROR("performing non-seamless pipe topology transition with surface only update!\n");
4577                         BREAK_TO_DEBUGGER();
4578                 }
4579                 commit_planes_for_stream(
4580                                 dc,
4581                                 srf_updates,
4582                                 surface_count,
4583                                 stream,
4584                                 stream_update,
4585                                 update_type,
4586                                 context);
4587         }
4588
4589         if (dc->current_state != context) {
4590
4591                 /* Since memory free requires elevated IRQL, an interrupt
4592                  * request is generated by mem free. If this happens
4593                  * between freeing and reassigning the context, our vsync
4594                  * interrupt will call into dc and cause a memory
4595                  * corruption BSOD. Hence, we first reassign the context,
4596                  * then free the old context.
4597                  */
4598
4599                 struct dc_state *old = dc->current_state;
4600
4601                 dc->current_state = context;
4602                 dc_release_state(old);
4603
4604                 // clear any forced full updates
4605                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4606                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4607
4608                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4609                                 pipe_ctx->plane_state->force_full_update = false;
4610                 }
4611         }
4612         return true;
4613 }
4614
4615 void dc_commit_updates_for_stream(struct dc *dc,
4616                 struct dc_surface_update *srf_updates,
4617                 int surface_count,
4618                 struct dc_stream_state *stream,
4619                 struct dc_stream_update *stream_update,
4620                 struct dc_state *state)
4621 {
4622         const struct dc_stream_status *stream_status;
4623         enum surface_update_type update_type;
4624         struct dc_state *context;
4625         struct dc_context *dc_ctx = dc->ctx;
4626         int i, j;
4627         struct dc_fast_update fast_update[MAX_SURFACES] = {0};
4628
4629         populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
4630         stream_status = dc_stream_get_status(stream);
4631         context = dc->current_state;
4632
4633         update_type = dc_check_update_surfaces_for_stream(
4634                                 dc, srf_updates, surface_count, stream_update, stream_status);
4635
4636         /* TODO: Since change commit sequence can have a huge impact,
4637          * we decided to only enable it for DCN3x. However, as soon as
4638          * we get more confident about this change we'll need to enable
4639          * the new sequence for all ASICs.
4640          */
4641         if (dc->ctx->dce_version >= DCN_VERSION_3_2) {
4642                 /*
4643                  * Previous frame finished and HW is ready for optimization.
4644                  */
4645                 if (update_type == UPDATE_TYPE_FAST)
4646                         dc_post_update_surfaces_to_stream(dc);
4647
4648                 dc_update_planes_and_stream(dc, srf_updates,
4649                                             surface_count, stream,
4650                                             stream_update);
4651                 return;
4652         }
4653
4654         if (update_type >= update_surface_trace_level)
4655                 update_surface_trace(dc, srf_updates, surface_count);
4656
4657
4658         if (update_type >= UPDATE_TYPE_FULL) {
4659
4660                 /* initialize scratch memory for building context */
4661                 context = dc_create_state(dc);
4662                 if (context == NULL) {
4663                         DC_ERROR("Failed to allocate new validate context!\n");
4664                         return;
4665                 }
4666
4667                 dc_resource_state_copy_construct(state, context);
4668
4669                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4670                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
4671                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4672
4673                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
4674                                 new_pipe->plane_state->force_full_update = true;
4675                 }
4676         } else if (update_type == UPDATE_TYPE_FAST) {
4677                 /*
4678                  * Previous frame finished and HW is ready for optimization.
4679                  */
4680                 dc_post_update_surfaces_to_stream(dc);
4681         }
4682
4683
4684         for (i = 0; i < surface_count; i++) {
4685                 struct dc_plane_state *surface = srf_updates[i].surface;
4686
4687                 copy_surface_update_to_plane(surface, &srf_updates[i]);
4688
4689                 if (update_type >= UPDATE_TYPE_MED) {
4690                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
4691                                 struct pipe_ctx *pipe_ctx =
4692                                         &context->res_ctx.pipe_ctx[j];
4693
4694                                 if (pipe_ctx->plane_state != surface)
4695                                         continue;
4696
4697                                 resource_build_scaling_params(pipe_ctx);
4698                         }
4699                 }
4700         }
4701
4702         copy_stream_update_to_stream(dc, context, stream, stream_update);
4703
4704         if (update_type >= UPDATE_TYPE_FULL) {
4705                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
4706                         DC_ERROR("Mode validation failed for stream update!\n");
4707                         dc_release_state(context);
4708                         return;
4709                 }
4710         }
4711
4712         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
4713
4714         update_seamless_boot_flags(dc, context, surface_count, stream);
4715         if (fast_update_only(dc, fast_update, srf_updates, surface_count, stream_update, stream) &&
4716                         !dc->debug.enable_legacy_fast_update) {
4717                 commit_planes_for_stream_fast(dc,
4718                                 srf_updates,
4719                                 surface_count,
4720                                 stream,
4721                                 stream_update,
4722                                 update_type,
4723                                 context);
4724         } else {
4725                 commit_planes_for_stream(
4726                                 dc,
4727                                 srf_updates,
4728                                 surface_count,
4729                                 stream,
4730                                 stream_update,
4731                                 update_type,
4732                                 context);
4733         }
4734         /*update current_State*/
4735         if (dc->current_state != context) {
4736
4737                 struct dc_state *old = dc->current_state;
4738
4739                 dc->current_state = context;
4740                 dc_release_state(old);
4741
4742                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4743                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4744
4745                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4746                                 pipe_ctx->plane_state->force_full_update = false;
4747                 }
4748         }
4749
4750         /* Legacy optimization path for DCE. */
4751         if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {
4752                 dc_post_update_surfaces_to_stream(dc);
4753                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
4754         }
4755
4756         return;
4757
4758 }
4759
4760 uint8_t dc_get_current_stream_count(struct dc *dc)
4761 {
4762         return dc->current_state->stream_count;
4763 }
4764
4765 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
4766 {
4767         if (i < dc->current_state->stream_count)
4768                 return dc->current_state->streams[i];
4769         return NULL;
4770 }
4771
4772 enum dc_irq_source dc_interrupt_to_irq_source(
4773                 struct dc *dc,
4774                 uint32_t src_id,
4775                 uint32_t ext_id)
4776 {
4777         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
4778 }
4779
4780 /*
4781  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
4782  */
4783 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
4784 {
4785
4786         if (dc == NULL)
4787                 return false;
4788
4789         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
4790 }
4791
4792 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
4793 {
4794         dal_irq_service_ack(dc->res_pool->irqs, src);
4795 }
4796
4797 void dc_power_down_on_boot(struct dc *dc)
4798 {
4799         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
4800                         dc->hwss.power_down_on_boot)
4801                 dc->hwss.power_down_on_boot(dc);
4802 }
4803
4804 void dc_set_power_state(
4805         struct dc *dc,
4806         enum dc_acpi_cm_power_state power_state)
4807 {
4808         if (!dc->current_state)
4809                 return;
4810
4811         switch (power_state) {
4812         case DC_ACPI_CM_POWER_STATE_D0:
4813                 dc_resource_state_construct(dc, dc->current_state);
4814
4815                 dc_z10_restore(dc);
4816
4817                 dc->hwss.init_hw(dc);
4818
4819                 if (dc->hwss.init_sys_ctx != NULL &&
4820                         dc->vm_pa_config.valid) {
4821                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
4822                 }
4823
4824                 break;
4825         default:
4826                 ASSERT(dc->current_state->stream_count == 0);
4827
4828                 dc_resource_state_destruct(dc->current_state);
4829
4830                 break;
4831         }
4832 }
4833
4834 void dc_resume(struct dc *dc)
4835 {
4836         uint32_t i;
4837
4838         for (i = 0; i < dc->link_count; i++)
4839                 dc->link_srv->resume(dc->links[i]);
4840 }
4841
4842 bool dc_is_dmcu_initialized(struct dc *dc)
4843 {
4844         struct dmcu *dmcu = dc->res_pool->dmcu;
4845
4846         if (dmcu)
4847                 return dmcu->funcs->is_dmcu_initialized(dmcu);
4848         return false;
4849 }
4850
4851 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
4852 {
4853         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
4854         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
4855         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
4856         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
4857         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
4858         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
4859         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
4860         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
4861         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
4862 }
4863 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
4864 {
4865         if (dc->hwss.set_clock)
4866                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
4867         return DC_ERROR_UNEXPECTED;
4868 }
4869 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
4870 {
4871         if (dc->hwss.get_clock)
4872                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
4873 }
4874
4875 /* enable/disable eDP PSR without specify stream for eDP */
4876 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
4877 {
4878         int i;
4879         bool allow_active;
4880
4881         for (i = 0; i < dc->current_state->stream_count ; i++) {
4882                 struct dc_link *link;
4883                 struct dc_stream_state *stream = dc->current_state->streams[i];
4884
4885                 link = stream->link;
4886                 if (!link)
4887                         continue;
4888
4889                 if (link->psr_settings.psr_feature_enabled) {
4890                         if (enable && !link->psr_settings.psr_allow_active) {
4891                                 allow_active = true;
4892                                 if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))
4893                                         return false;
4894                         } else if (!enable && link->psr_settings.psr_allow_active) {
4895                                 allow_active = false;
4896                                 if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))
4897                                         return false;
4898                         }
4899                 }
4900         }
4901
4902         return true;
4903 }
4904
4905 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
4906 {
4907         if (dc->debug.disable_idle_power_optimizations)
4908                 return;
4909
4910         if (dc->caps.ips_support && (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
4911                 return;
4912
4913         if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
4914                 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
4915                         return;
4916
4917         if (allow == dc->idle_optimizations_allowed)
4918                 return;
4919
4920         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
4921                 dc->idle_optimizations_allowed = allow;
4922 }
4923
4924 bool dc_dmub_is_ips_idle_state(struct dc *dc)
4925 {
4926         uint32_t idle_state = 0;
4927
4928         if (dc->debug.disable_idle_power_optimizations)
4929                 return false;
4930
4931         if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
4932                 return false;
4933
4934         if (dc->hwss.get_idle_state)
4935                 idle_state = dc->hwss.get_idle_state(dc);
4936
4937         if ((idle_state & DMUB_IPS1_ALLOW_MASK) ||
4938                 (idle_state & DMUB_IPS2_ALLOW_MASK))
4939                 return true;
4940
4941         return false;
4942 }
4943
4944 /* set min and max memory clock to lowest and highest DPM level, respectively */
4945 void dc_unlock_memory_clock_frequency(struct dc *dc)
4946 {
4947         if (dc->clk_mgr->funcs->set_hard_min_memclk)
4948                 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
4949
4950         if (dc->clk_mgr->funcs->set_hard_max_memclk)
4951                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
4952 }
4953
4954 /* set min memory clock to the min required for current mode, max to maxDPM */
4955 void dc_lock_memory_clock_frequency(struct dc *dc)
4956 {
4957         if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
4958                 dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
4959
4960         if (dc->clk_mgr->funcs->set_hard_min_memclk)
4961                 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
4962
4963         if (dc->clk_mgr->funcs->set_hard_max_memclk)
4964                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
4965 }
4966
4967 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
4968 {
4969         struct dc_state *context = dc->current_state;
4970         struct hubp *hubp;
4971         struct pipe_ctx *pipe;
4972         int i;
4973
4974         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4975                 pipe = &context->res_ctx.pipe_ctx[i];
4976
4977                 if (pipe->stream != NULL) {
4978                         dc->hwss.disable_pixel_data(dc, pipe, true);
4979
4980                         // wait for double buffer
4981                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
4982                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
4983                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
4984
4985                         hubp = pipe->plane_res.hubp;
4986                         hubp->funcs->set_blank_regs(hubp, true);
4987                 }
4988         }
4989
4990         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
4991         dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
4992
4993         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4994                 pipe = &context->res_ctx.pipe_ctx[i];
4995
4996                 if (pipe->stream != NULL) {
4997                         dc->hwss.disable_pixel_data(dc, pipe, false);
4998
4999                         hubp = pipe->plane_res.hubp;
5000                         hubp->funcs->set_blank_regs(hubp, false);
5001                 }
5002         }
5003 }
5004
5005
5006 /**
5007  * dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode
5008  * @dc: pointer to dc of the dm calling this
5009  * @enable: True = transition to DC mode, false = transition back to AC mode
5010  *
5011  * Some SoCs define additional clock limits when in DC mode, DM should
5012  * invoke this function when the platform undergoes a power source transition
5013  * so DC can apply/unapply the limit. This interface may be disruptive to
5014  * the onscreen content.
5015  *
5016  * Context: Triggered by OS through DM interface, or manually by escape calls.
5017  * Need to hold a dclock when doing so.
5018  *
5019  * Return: none (void function)
5020  *
5021  */
5022 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
5023 {
5024         unsigned int softMax = 0, maxDPM = 0, funcMin = 0, i;
5025         bool p_state_change_support;
5026
5027         if (!dc->config.dc_mode_clk_limit_support)
5028                 return;
5029
5030         softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;
5031         for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) {
5032                 if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM)
5033                         maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
5034         }
5035         funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;
5036         p_state_change_support = dc->clk_mgr->clks.p_state_change_support;
5037
5038         if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {
5039                 if (p_state_change_support) {
5040                         if (funcMin <= softMax)
5041                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);
5042                         // else: No-Op
5043                 } else {
5044                         if (funcMin <= softMax)
5045                                 blank_and_force_memclk(dc, true, softMax);
5046                         // else: No-Op
5047                 }
5048         } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {
5049                 if (p_state_change_support) {
5050                         if (funcMin <= softMax)
5051                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);
5052                         // else: No-Op
5053                 } else {
5054                         if (funcMin <= softMax)
5055                                 blank_and_force_memclk(dc, true, maxDPM);
5056                         // else: No-Op
5057                 }
5058         }
5059         dc->clk_mgr->dc_mode_softmax_enabled = enable;
5060 }
5061 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
5062                 struct dc_cursor_attributes *cursor_attr)
5063 {
5064         if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
5065                 return true;
5066         return false;
5067 }
5068
5069 /* cleanup on driver unload */
5070 void dc_hardware_release(struct dc *dc)
5071 {
5072         dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc);
5073
5074         if (dc->hwss.hardware_release)
5075                 dc->hwss.hardware_release(dc);
5076 }
5077
5078 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
5079 {
5080         if (dc->current_state)
5081                 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;
5082 }
5083
5084 /**
5085  * dc_is_dmub_outbox_supported - Check if DMUB firmware support outbox notification
5086  *
5087  * @dc: [in] dc structure
5088  *
5089  * Checks whether DMUB FW supports outbox notifications, if supported DM
5090  * should register outbox interrupt prior to actually enabling interrupts
5091  * via dc_enable_dmub_outbox
5092  *
5093  * Return:
5094  * True if DMUB FW supports outbox notifications, False otherwise
5095  */
5096 bool dc_is_dmub_outbox_supported(struct dc *dc)
5097 {
5098         /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
5099         if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
5100             dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
5101             !dc->debug.dpia_debug.bits.disable_dpia)
5102                 return true;
5103
5104         if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 &&
5105             !dc->debug.dpia_debug.bits.disable_dpia)
5106                 return true;
5107
5108         /* dmub aux needs dmub notifications to be enabled */
5109         return dc->debug.enable_dmub_aux_for_legacy_ddc;
5110 }
5111
5112 /**
5113  * dc_enable_dmub_notifications - Check if dmub fw supports outbox
5114  *
5115  * @dc: [in] dc structure
5116  *
5117  * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox
5118  * notifications. All DMs shall switch to dc_is_dmub_outbox_supported.  This
5119  * API shall be removed after switching.
5120  *
5121  * Return:
5122  * True if DMUB FW supports outbox notifications, False otherwise
5123  */
5124 bool dc_enable_dmub_notifications(struct dc *dc)
5125 {
5126         return dc_is_dmub_outbox_supported(dc);
5127 }
5128
5129 /**
5130  * dc_enable_dmub_outbox - Enables DMUB unsolicited notification
5131  *
5132  * @dc: [in] dc structure
5133  *
5134  * Enables DMUB unsolicited notifications to x86 via outbox.
5135  */
5136 void dc_enable_dmub_outbox(struct dc *dc)
5137 {
5138         struct dc_context *dc_ctx = dc->ctx;
5139
5140         dmub_enable_outbox_notification(dc_ctx->dmub_srv);
5141         DC_LOG_DC("%s: dmub outbox notifications enabled\n", __func__);
5142 }
5143
5144 /**
5145  * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
5146  *                                      Sets port index appropriately for legacy DDC
5147  * @dc: dc structure
5148  * @link_index: link index
5149  * @payload: aux payload
5150  *
5151  * Returns: True if successful, False if failure
5152  */
5153 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
5154                                 uint32_t link_index,
5155                                 struct aux_payload *payload)
5156 {
5157         uint8_t action;
5158         union dmub_rb_cmd cmd = {0};
5159
5160         ASSERT(payload->length <= 16);
5161
5162         cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
5163         cmd.dp_aux_access.header.payload_bytes = 0;
5164         /* For dpia, ddc_pin is set to NULL */
5165         if (!dc->links[link_index]->ddc->ddc_pin)
5166                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA;
5167         else
5168                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
5169
5170         cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
5171         cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
5172         cmd.dp_aux_access.aux_control.timeout = 0;
5173         cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
5174         cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
5175         cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
5176
5177         /* set aux action */
5178         if (payload->i2c_over_aux) {
5179                 if (payload->write) {
5180                         if (payload->mot)
5181                                 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
5182                         else
5183                                 action = DP_AUX_REQ_ACTION_I2C_WRITE;
5184                 } else {
5185                         if (payload->mot)
5186                                 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
5187                         else
5188                                 action = DP_AUX_REQ_ACTION_I2C_READ;
5189                         }
5190         } else {
5191                 if (payload->write)
5192                         action = DP_AUX_REQ_ACTION_DPCD_WRITE;
5193                 else
5194                         action = DP_AUX_REQ_ACTION_DPCD_READ;
5195         }
5196
5197         cmd.dp_aux_access.aux_control.dpaux.action = action;
5198
5199         if (payload->length && payload->write) {
5200                 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
5201                         payload->data,
5202                         payload->length
5203                         );
5204         }
5205
5206         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
5207
5208         return true;
5209 }
5210
5211 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
5212                                             uint8_t dpia_port_index)
5213 {
5214         uint8_t index, link_index = 0xFF;
5215
5216         for (index = 0; index < dc->link_count; index++) {
5217                 /* ddc_hw_inst has dpia port index for dpia links
5218                  * and ddc instance for legacy links
5219                  */
5220                 if (!dc->links[index]->ddc->ddc_pin) {
5221                         if (dc->links[index]->ddc_hw_inst == dpia_port_index) {
5222                                 link_index = index;
5223                                 break;
5224                         }
5225                 }
5226         }
5227         ASSERT(link_index != 0xFF);
5228         return link_index;
5229 }
5230
5231 /**
5232  * dc_process_dmub_set_config_async - Submits set_config command
5233  *
5234  * @dc: [in] dc structure
5235  * @link_index: [in] link_index: link index
5236  * @payload: [in] aux payload
5237  * @notify: [out] set_config immediate reply
5238  *
5239  * Submits set_config command to dmub via inbox message.
5240  *
5241  * Return:
5242  * True if successful, False if failure
5243  */
5244 bool dc_process_dmub_set_config_async(struct dc *dc,
5245                                 uint32_t link_index,
5246                                 struct set_config_cmd_payload *payload,
5247                                 struct dmub_notification *notify)
5248 {
5249         union dmub_rb_cmd cmd = {0};
5250         bool is_cmd_complete = true;
5251
5252         /* prepare SET_CONFIG command */
5253         cmd.set_config_access.header.type = DMUB_CMD__DPIA;
5254         cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
5255
5256         cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
5257         cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
5258         cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
5259
5260         if (!dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {
5261                 /* command is not processed by dmub */
5262                 notify->sc_status = SET_CONFIG_UNKNOWN_ERROR;
5263                 return is_cmd_complete;
5264         }
5265
5266         /* command processed by dmub, if ret_status is 1, it is completed instantly */
5267         if (cmd.set_config_access.header.ret_status == 1)
5268                 notify->sc_status = cmd.set_config_access.set_config_control.immed_status;
5269         else
5270                 /* cmd pending, will receive notification via outbox */
5271                 is_cmd_complete = false;
5272
5273         return is_cmd_complete;
5274 }
5275
5276 /**
5277  * dc_process_dmub_set_mst_slots - Submits MST solt allocation
5278  *
5279  * @dc: [in] dc structure
5280  * @link_index: [in] link index
5281  * @mst_alloc_slots: [in] mst slots to be allotted
5282  * @mst_slots_in_use: [out] mst slots in use returned in failure case
5283  *
5284  * Submits mst slot allocation command to dmub via inbox message
5285  *
5286  * Return:
5287  * DC_OK if successful, DC_ERROR if failure
5288  */
5289 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
5290                                 uint32_t link_index,
5291                                 uint8_t mst_alloc_slots,
5292                                 uint8_t *mst_slots_in_use)
5293 {
5294         union dmub_rb_cmd cmd = {0};
5295
5296         /* prepare MST_ALLOC_SLOTS command */
5297         cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
5298         cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
5299
5300         cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
5301         cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
5302
5303         if (!dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
5304                 /* command is not processed by dmub */
5305                 return DC_ERROR_UNEXPECTED;
5306
5307         /* command processed by dmub, if ret_status is 1 */
5308         if (cmd.set_config_access.header.ret_status != 1)
5309                 /* command processing error */
5310                 return DC_ERROR_UNEXPECTED;
5311
5312         /* command processed and we have a status of 2, mst not enabled in dpia */
5313         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2)
5314                 return DC_FAIL_UNSUPPORTED_1;
5315
5316         /* previously configured mst alloc and used slots did not match */
5317         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) {
5318                 *mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use;
5319                 return DC_NOT_SUPPORTED;
5320         }
5321
5322         return DC_OK;
5323 }
5324
5325 /**
5326  * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption
5327  *
5328  * @dc: [in] dc structure
5329  * @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable
5330  *
5331  * Submits dpia hpd int enable command to dmub via inbox message
5332  */
5333 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
5334                                 uint32_t hpd_int_enable)
5335 {
5336         union dmub_rb_cmd cmd = {0};
5337
5338         cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE;
5339         cmd.dpia_hpd_int_enable.enable = hpd_int_enable;
5340
5341         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
5342
5343         DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable);
5344 }
5345
5346 /**
5347  * dc_print_dmub_diagnostic_data - Print DMUB diagnostic data for debugging
5348  *
5349  * @dc: [in] dc structure
5350  *
5351  *
5352  */
5353 void dc_print_dmub_diagnostic_data(const struct dc *dc)
5354 {
5355         dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);
5356 }
5357
5358 /**
5359  * dc_disable_accelerated_mode - disable accelerated mode
5360  * @dc: dc structure
5361  */
5362 void dc_disable_accelerated_mode(struct dc *dc)
5363 {
5364         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
5365 }
5366
5367
5368 /**
5369  *  dc_notify_vsync_int_state - notifies vsync enable/disable state
5370  *  @dc: dc structure
5371  *  @stream: stream where vsync int state changed
5372  *  @enable: whether vsync is enabled or disabled
5373  *
5374  *  Called when vsync is enabled/disabled Will notify DMUB to start/stop ABM
5375  *  interrupts after steady state is reached.
5376  */
5377 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
5378 {
5379         int i;
5380         int edp_num;
5381         struct pipe_ctx *pipe = NULL;
5382         struct dc_link *link = stream->sink->link;
5383         struct dc_link *edp_links[MAX_NUM_EDP];
5384
5385
5386         if (link->psr_settings.psr_feature_enabled)
5387                 return;
5388
5389         if (link->replay_settings.replay_feature_enabled)
5390                 return;
5391
5392         /*find primary pipe associated with stream*/
5393         for (i = 0; i < MAX_PIPES; i++) {
5394                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
5395
5396                 if (pipe->stream == stream && pipe->stream_res.tg)
5397                         break;
5398         }
5399
5400         if (i == MAX_PIPES) {
5401                 ASSERT(0);
5402                 return;
5403         }
5404
5405         dc_get_edp_links(dc, edp_links, &edp_num);
5406
5407         /* Determine panel inst */
5408         for (i = 0; i < edp_num; i++) {
5409                 if (edp_links[i] == link)
5410                         break;
5411         }
5412
5413         if (i == edp_num) {
5414                 return;
5415         }
5416
5417         if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)
5418                 pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
5419 }
5420
5421 /*****************************************************************************
5422  *  dc_abm_save_restore() - Interface to DC for save+pause and restore+un-pause
5423  *                          ABM
5424  *  @dc: dc structure
5425  *      @stream: stream where vsync int state changed
5426  *  @pData: abm hw states
5427  *
5428  ****************************************************************************/
5429 bool dc_abm_save_restore(
5430                 struct dc *dc,
5431                 struct dc_stream_state *stream,
5432                 struct abm_save_restore *pData)
5433 {
5434         int i;
5435         int edp_num;
5436         struct pipe_ctx *pipe = NULL;
5437         struct dc_link *link = stream->sink->link;
5438         struct dc_link *edp_links[MAX_NUM_EDP];
5439
5440
5441         /*find primary pipe associated with stream*/
5442         for (i = 0; i < MAX_PIPES; i++) {
5443                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
5444
5445                 if (pipe->stream == stream && pipe->stream_res.tg)
5446                         break;
5447         }
5448
5449         if (i == MAX_PIPES) {
5450                 ASSERT(0);
5451                 return false;
5452         }
5453
5454         dc_get_edp_links(dc, edp_links, &edp_num);
5455
5456         /* Determine panel inst */
5457         for (i = 0; i < edp_num; i++)
5458                 if (edp_links[i] == link)
5459                         break;
5460
5461         if (i == edp_num)
5462                 return false;
5463
5464         if (pipe->stream_res.abm &&
5465                 pipe->stream_res.abm->funcs->save_restore)
5466                 return pipe->stream_res.abm->funcs->save_restore(
5467                                 pipe->stream_res.abm,
5468                                 i,
5469                                 pData);
5470         return false;
5471 }
5472
5473 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties)
5474 {
5475         unsigned int i;
5476         bool subvp_sw_cursor_req = false;
5477
5478         for (i = 0; i < dc->current_state->stream_count; i++) {
5479                 if (check_subvp_sw_cursor_fallback_req(dc, dc->current_state->streams[i])) {
5480                         subvp_sw_cursor_req = true;
5481                         break;
5482                 }
5483         }
5484         properties->cursor_size_limit = subvp_sw_cursor_req ? 64 : dc->caps.max_cursor_size;
5485 }
5486
5487 /**
5488  * dc_set_edp_power() - DM controls eDP power to be ON/OFF
5489  *
5490  * Called when DM wants to power on/off eDP.
5491  *     Only work on links with flag skip_implict_edp_power_control is set.
5492  *
5493  * @dc: Current DC state
5494  * @edp_link: a link with eDP connector signal type
5495  * @powerOn: power on/off eDP
5496  *
5497  * Return: void
5498  */
5499 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
5500                                  bool powerOn)
5501 {
5502         if (edp_link->connector_signal != SIGNAL_TYPE_EDP)
5503                 return;
5504
5505         if (edp_link->skip_implict_edp_power_control == false)
5506                 return;
5507
5508         edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);
5509 }
5510
5511 /*
5512  *****************************************************************************
5513  * dc_get_power_profile_for_dc_state() - extracts power profile from dc state
5514  *
5515  * Called when DM wants to make power policy decisions based on dc_state
5516  *
5517  *****************************************************************************
5518  */
5519 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context)
5520 {
5521         struct dc_power_profile profile = { 0 };
5522
5523         profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support;
5524
5525         return profile;
5526 }
5527