drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28
  29 #include "ObjectID.h"
  30 #include "atomfirmware.h"
  31
  32 #include "dc_bios_types.h"
  33 #include "include/grph_object_ctrl_defs.h"
  34 #include "include/bios_parser_interface.h"
  35 #include "include/logger_interface.h"
  36
  37 #include "command_table2.h"
  38
  39 #include "bios_parser_helper.h"
  40 #include "command_table_helper2.h"
  41 #include "bios_parser2.h"
  42 #include "bios_parser_types_internal2.h"
  43 #include "bios_parser_interface.h"
  44
  45 #include "bios_parser_common.h"
  46
  47 #define DC_LOGGER \
  48         bp->base.ctx->logger
  49
  50 #define LAST_RECORD_TYPE 0xff
  51 #define SMU9_SYSPLL0_ID  0
  52
  53 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
  54         struct atom_i2c_record *record,
  55         struct graphics_object_i2c_info *info);
  56
  57 static enum bp_result bios_parser_get_firmware_info(
  58         struct dc_bios *dcb,
  59         struct dc_firmware_info *info);
  60
  61 static enum bp_result bios_parser_get_encoder_cap_info(
  62         struct dc_bios *dcb,
  63         struct graphics_object_id object_id,
  64         struct bp_encoder_cap_info *info);
  65
  66 static enum bp_result get_firmware_info_v3_1(
  67         struct bios_parser *bp,
  68         struct dc_firmware_info *info);
  69
  70 static enum bp_result get_firmware_info_v3_2(
  71         struct bios_parser *bp,
  72         struct dc_firmware_info *info);
  73
  74 static enum bp_result get_firmware_info_v3_4(
  75         struct bios_parser *bp,
  76         struct dc_firmware_info *info);
  77
  78 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
  79                 struct atom_display_object_path_v2 *object);
  80
  81 static struct atom_encoder_caps_record *get_encoder_cap_record(
  82         struct bios_parser *bp,
  83         struct atom_display_object_path_v2 *object);
  84
  85 #define BIOS_IMAGE_SIZE_OFFSET 2
  86 #define BIOS_IMAGE_SIZE_UNIT 512
  87
  88 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
  89
  90 static void bios_parser2_destruct(struct bios_parser *bp)
  91 {
  92         kfree(bp->base.bios_local_image);
  93         kfree(bp->base.integrated_info);
  94 }
  95
  96 static void firmware_parser_destroy(struct dc_bios **dcb)
  97 {
  98         struct bios_parser *bp = BP_FROM_DCB(*dcb);
  99
 100         if (!bp) {
 101                 BREAK_TO_DEBUGGER();
 102                 return;
 103         }
 104
 105         bios_parser2_destruct(bp);
 106
 107         kfree(bp);
 108         *dcb = NULL;
 109 }
 110
 111 static void get_atom_data_table_revision(
 112         struct atom_common_table_header *atom_data_tbl,
 113         struct atom_data_revision *tbl_revision)
 114 {
 115         if (!tbl_revision)
 116                 return;
 117
 118         /* initialize the revision to 0 which is invalid revision */
 119         tbl_revision->major = 0;
 120         tbl_revision->minor = 0;
 121
 122         if (!atom_data_tbl)
 123                 return;
 124
 125         tbl_revision->major =
 126                         (uint32_t) atom_data_tbl->format_revision & 0x3f;
 127         tbl_revision->minor =
 128                         (uint32_t) atom_data_tbl->content_revision & 0x3f;
 129 }
 130
 131 /* BIOS oject table displaypath is per connector.
 132  * There is extra path not for connector. BIOS fill its encoderid as 0
 133  */
 134 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
 135 {
 136         struct bios_parser *bp = BP_FROM_DCB(dcb);
 137         unsigned int count = 0;
 138         unsigned int i;
 139
 140         switch (bp->object_info_tbl.revision.minor) {
 141         default:
 142         case 4:
 143                 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++)
 144                         if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
 145                                 count++;
 146
 147                 break;
 148
 149         case 5:
 150                 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++)
 151                         if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0)
 152                                 count++;
 153
 154                 break;
 155         }
 156         return count;
 157 }
 158
 159 static struct graphics_object_id bios_parser_get_connector_id(
 160         struct dc_bios *dcb,
 161         uint8_t i)
 162 {
 163         struct bios_parser *bp = BP_FROM_DCB(dcb);
 164         struct graphics_object_id object_id = dal_graphics_object_id_init(
 165                 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
 166         struct object_info_table *tbl = &bp->object_info_tbl;
 167         struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
 168
 169         struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5;
 170
 171         switch (bp->object_info_tbl.revision.minor) {
 172         default:
 173         case 4:
 174                 if (v1_4->number_of_path > i) {
 175                         /* If display_objid is generic object id,  the encoderObj
 176                          * /extencoderobjId should be 0
 177                          */
 178                         if (v1_4->display_path[i].encoderobjid != 0 &&
 179                             v1_4->display_path[i].display_objid != 0)
 180                                 object_id = object_id_from_bios_object_id(
 181                                         v1_4->display_path[i].display_objid);
 182                 }
 183                 break;
 184
 185         case 5:
 186                 if (v1_5->number_of_path > i) {
 187                         /* If display_objid is generic object id,  the encoderObjId
 188                  * should be 0
 189                  */
 190                         if (v1_5->display_path[i].encoderobjid != 0 &&
 191                             v1_5->display_path[i].display_objid != 0)
 192                                 object_id = object_id_from_bios_object_id(
 193                                         v1_5->display_path[i].display_objid);
 194                 }
 195                 break;
 196         }
 197         return object_id;
 198 }
 199
 200 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
 201         struct graphics_object_id object_id, uint32_t index,
 202         struct graphics_object_id *src_object_id)
 203 {
 204         struct bios_parser *bp = BP_FROM_DCB(dcb);
 205         unsigned int i;
 206         enum bp_result bp_result = BP_RESULT_BADINPUT;
 207         struct graphics_object_id obj_id = { 0 };
 208         struct object_info_table *tbl = &bp->object_info_tbl;
 209
 210         if (!src_object_id)
 211                 return bp_result;
 212
 213         switch (object_id.type) {
 214         /* Encoder's Source is GPU.  BIOS does not provide GPU, since all
 215          * displaypaths point to same GPU (0x1100).  Hardcode GPU object type
 216          */
 217         case OBJECT_TYPE_ENCODER:
 218                 /* TODO: since num of src must be less than 2.
 219                  * If found in for loop, should break.
 220                  * DAL2 implementation may be changed too
 221                  */
 222                 switch (bp->object_info_tbl.revision.minor) {
 223                 default:
 224                 case 4:
 225                         for (i = 0; i < tbl->v1_4->number_of_path; i++) {
 226                                 obj_id = object_id_from_bios_object_id(
 227                                         tbl->v1_4->display_path[i].encoderobjid);
 228                                 if (object_id.type == obj_id.type &&
 229                                     object_id.id == obj_id.id &&
 230                                     object_id.enum_id == obj_id.enum_id) {
 231                                         *src_object_id =
 232                                                 object_id_from_bios_object_id(
 233                                                         0x1100);
 234                                         /* break; */
 235                                 }
 236                         }
 237                         bp_result = BP_RESULT_OK;
 238                         break;
 239
 240                 case 5:
 241                         for (i = 0; i < tbl->v1_5->number_of_path; i++) {
 242                                 obj_id = object_id_from_bios_object_id(
 243                                         tbl->v1_5->display_path[i].encoderobjid);
 244                                 if (object_id.type == obj_id.type &&
 245                                     object_id.id == obj_id.id &&
 246                                     object_id.enum_id == obj_id.enum_id) {
 247                                         *src_object_id =
 248                                                 object_id_from_bios_object_id(
 249                                                         0x1100);
 250                                         /* break; */
 251                                 }
 252                         }
 253                         bp_result = BP_RESULT_OK;
 254                         break;
 255                 }
 256                 break;
 257         case OBJECT_TYPE_CONNECTOR:
 258                 switch (bp->object_info_tbl.revision.minor) {
 259                 default:
 260                 case 4:
 261                         for (i = 0; i < tbl->v1_4->number_of_path; i++) {
 262                                 obj_id = object_id_from_bios_object_id(
 263                                         tbl->v1_4->display_path[i]
 264                                                 .display_objid);
 265
 266                                 if (object_id.type == obj_id.type &&
 267                                     object_id.id == obj_id.id &&
 268                                     object_id.enum_id == obj_id.enum_id) {
 269                                         *src_object_id =
 270                                                 object_id_from_bios_object_id(
 271                                                         tbl->v1_4
 272                                                                 ->display_path[i]
 273                                                                 .encoderobjid);
 274                                         /* break; */
 275                                 }
 276                         }
 277                         bp_result = BP_RESULT_OK;
 278                         break;
 279                 }
 280                 bp_result = BP_RESULT_OK;
 281                 break;
 282                 case 5:
 283                         for (i = 0; i < tbl->v1_5->number_of_path; i++) {
 284                                 obj_id = object_id_from_bios_object_id(
 285                                                                        tbl->v1_5->display_path[i].display_objid);
 286
 287                                 if (object_id.type == obj_id.type &&
 288                                     object_id.id == obj_id.id &&
 289                                     object_id.enum_id == obj_id.enum_id) {
 290                                         *src_object_id = object_id_from_bios_object_id(
 291                                                                                        tbl->v1_5->display_path[i].encoderobjid);
 292                                         /* break; */
 293                                 }
 294                         }
 295                 bp_result = BP_RESULT_OK;
 296                 break;
 297
 298         default:
 299                 bp_result = BP_RESULT_OK;
 300                 break;
 301         }
 302
 303         return bp_result;
 304 }
 305
 306 /* from graphics_object_id, find display path which includes the object_id */
 307 static struct atom_display_object_path_v2 *get_bios_object(
 308                 struct bios_parser *bp,
 309                 struct graphics_object_id id)
 310 {
 311         unsigned int i;
 312         struct graphics_object_id obj_id = {0};
 313
 314         switch (id.type) {
 315         case OBJECT_TYPE_ENCODER:
 316                 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
 317                         obj_id = object_id_from_bios_object_id(
 318                                         bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
 319                         if (id.type == obj_id.type && id.id == obj_id.id
 320                                         && id.enum_id == obj_id.enum_id)
 321                                 return &bp->object_info_tbl.v1_4->display_path[i];
 322                 }
 323                 fallthrough;
 324         case OBJECT_TYPE_CONNECTOR:
 325         case OBJECT_TYPE_GENERIC:
 326                 /* Both Generic and Connector Object ID
 327                  * will be stored on display_objid
 328                  */
 329                 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
 330                         obj_id = object_id_from_bios_object_id(
 331                                         bp->object_info_tbl.v1_4->display_path[i].display_objid);
 332                         if (id.type == obj_id.type && id.id == obj_id.id
 333                                         && id.enum_id == obj_id.enum_id)
 334                                 return &bp->object_info_tbl.v1_4->display_path[i];
 335                 }
 336                 fallthrough;
 337         default:
 338                 return NULL;
 339         }
 340 }
 341
 342 /* from graphics_object_id, find display path which includes the object_id */
 343 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(struct bios_parser *bp,
 344                                                                         struct graphics_object_id id)
 345 {
 346         unsigned int i;
 347         struct graphics_object_id obj_id = {0};
 348
 349         switch (id.type) {
 350         case OBJECT_TYPE_ENCODER:
 351                 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
 352                         obj_id = object_id_from_bios_object_id(
 353                                         bp->object_info_tbl.v1_5->display_path[i].encoderobjid);
 354                         if (id.type == obj_id.type && id.id == obj_id.id
 355                                         && id.enum_id == obj_id.enum_id)
 356                                 return &bp->object_info_tbl.v1_5->display_path[i];
 357                 }
 358         break;
 359
 360         case OBJECT_TYPE_CONNECTOR:
 361         case OBJECT_TYPE_GENERIC:
 362                 /* Both Generic and Connector Object ID
 363                  * will be stored on display_objid
 364                  */
 365                 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
 366                         obj_id = object_id_from_bios_object_id(
 367                                         bp->object_info_tbl.v1_5->display_path[i].display_objid);
 368                         if (id.type == obj_id.type && id.id == obj_id.id
 369                                         && id.enum_id == obj_id.enum_id)
 370                                 return &bp->object_info_tbl.v1_5->display_path[i];
 371                 }
 372         break;
 373
 374         default:
 375                 return NULL;
 376         }
 377
 378         return NULL;
 379 }
 380
 381 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
 382         struct graphics_object_id id,
 383         struct graphics_object_i2c_info *info)
 384 {
 385         uint32_t offset;
 386         struct atom_display_object_path_v2 *object;
 387
 388         struct atom_display_object_path_v3 *object_path_v3;
 389
 390         struct atom_common_record_header *header;
 391         struct atom_i2c_record *record;
 392         struct atom_i2c_record dummy_record = {0};
 393         struct bios_parser *bp = BP_FROM_DCB(dcb);
 394
 395         if (!info)
 396                 return BP_RESULT_BADINPUT;
 397
 398         if (id.type == OBJECT_TYPE_GENERIC) {
 399                 dummy_record.i2c_id = id.id;
 400
 401                 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
 402                         return BP_RESULT_OK;
 403                 else
 404                         return BP_RESULT_NORECORD;
 405         }
 406
 407         switch (bp->object_info_tbl.revision.minor) {
 408         case 4:
 409         default:
 410                 object = get_bios_object(bp, id);
 411
 412                 if (!object)
 413                         return BP_RESULT_BADINPUT;
 414
 415                 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
 416                 break;
 417         case 5:
 418                 object_path_v3 = get_bios_object_from_path_v3(bp, id);
 419
 420                 if (!object_path_v3)
 421                         return BP_RESULT_BADINPUT;
 422
 423                 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset;
 424                 break;
 425         }
 426
 427         for (;;) {
 428                 header = GET_IMAGE(struct atom_common_record_header, offset);
 429
 430                 if (!header)
 431                         return BP_RESULT_BADBIOSTABLE;
 432
 433                 if (header->record_type == LAST_RECORD_TYPE ||
 434                         !header->record_size)
 435                         break;
 436
 437                 if (header->record_type == ATOM_I2C_RECORD_TYPE
 438                         && sizeof(struct atom_i2c_record) <=
 439                                                         header->record_size) {
 440                         /* get the I2C info */
 441                         record = (struct atom_i2c_record *) header;
 442
 443                         if (get_gpio_i2c_info(bp, record, info) ==
 444                                                                 BP_RESULT_OK)
 445                                 return BP_RESULT_OK;
 446                 }
 447
 448                 offset += header->record_size;
 449         }
 450
 451         return BP_RESULT_NORECORD;
 452 }
 453
 454 static enum bp_result get_gpio_i2c_info(
 455         struct bios_parser *bp,
 456         struct atom_i2c_record *record,
 457         struct graphics_object_i2c_info *info)
 458 {
 459         struct atom_gpio_pin_lut_v2_1 *header;
 460         uint32_t count = 0;
 461         unsigned int table_index = 0;
 462         bool find_valid = false;
 463         struct atom_gpio_pin_assignment *pin;
 464
 465         if (!info)
 466                 return BP_RESULT_BADINPUT;
 467
 468         /* get the GPIO_I2C info */
 469         if (!DATA_TABLES(gpio_pin_lut))
 470                 return BP_RESULT_BADBIOSTABLE;
 471
 472         header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
 473                                         DATA_TABLES(gpio_pin_lut));
 474         if (!header)
 475                 return BP_RESULT_BADBIOSTABLE;
 476
 477         if (sizeof(struct atom_common_table_header) +
 478                         sizeof(struct atom_gpio_pin_assignment) >
 479                         le16_to_cpu(header->table_header.structuresize))
 480                 return BP_RESULT_BADBIOSTABLE;
 481
 482         /* TODO: is version change? */
 483         if (header->table_header.content_revision != 1)
 484                 return BP_RESULT_UNSUPPORTED;
 485
 486         /* get data count */
 487         count = (le16_to_cpu(header->table_header.structuresize)
 488                         - sizeof(struct atom_common_table_header))
 489                                 / sizeof(struct atom_gpio_pin_assignment);
 490
 491         pin = (struct atom_gpio_pin_assignment *) header->gpio_pin;
 492
 493         for (table_index = 0; table_index < count; table_index++) {
 494                 if (((record->i2c_id & I2C_HW_CAP)                              == (pin->gpio_id & I2C_HW_CAP)) &&
 495                     ((record->i2c_id & I2C_HW_ENGINE_ID_MASK)   == (pin->gpio_id & I2C_HW_ENGINE_ID_MASK)) &&
 496                     ((record->i2c_id & I2C_HW_LANE_MUX)                 == (pin->gpio_id & I2C_HW_LANE_MUX))) {
 497                         /* still valid */
 498                         find_valid = true;
 499                         break;
 500                 }
 501                 pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment));
 502         }
 503
 504         /* If we don't find the entry that we are looking for then
 505          *  we will return BP_Result_BadBiosTable.
 506          */
 507         if (find_valid == false)
 508                 return BP_RESULT_BADBIOSTABLE;
 509
 510         /* get the GPIO_I2C_INFO */
 511         info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
 512         info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
 513         info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
 514         info->i2c_slave_address = record->i2c_slave_addr;
 515
 516         /* TODO: check how to get register offset for en, Y, etc. */
 517         info->gpio_info.clk_a_register_index = le16_to_cpu(pin->data_a_reg_index);
 518         info->gpio_info.clk_a_shift = pin->gpio_bitshift;
 519
 520         return BP_RESULT_OK;
 521 }
 522
 523 static struct atom_hpd_int_record *get_hpd_record_for_path_v3(struct bios_parser *bp,
 524                                                               struct atom_display_object_path_v3 *object)
 525 {
 526         struct atom_common_record_header *header;
 527         uint32_t offset;
 528
 529         if (!object) {
 530                 BREAK_TO_DEBUGGER(); /* Invalid object */
 531                 return NULL;
 532         }
 533
 534         offset = object->disp_recordoffset + bp->object_info_tbl_offset;
 535
 536         for (;;) {
 537                 header = GET_IMAGE(struct atom_common_record_header, offset);
 538
 539                 if (!header)
 540                         return NULL;
 541
 542                 if (header->record_type == ATOM_RECORD_END_TYPE ||
 543                         !header->record_size)
 544                         break;
 545
 546                 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
 547                         && sizeof(struct atom_hpd_int_record) <=
 548                                                         header->record_size)
 549                         return (struct atom_hpd_int_record *) header;
 550
 551                 offset += header->record_size;
 552         }
 553
 554         return NULL;
 555 }
 556
 557 static enum bp_result bios_parser_get_hpd_info(
 558         struct dc_bios *dcb,
 559         struct graphics_object_id id,
 560         struct graphics_object_hpd_info *info)
 561 {
 562         struct bios_parser *bp = BP_FROM_DCB(dcb);
 563         struct atom_display_object_path_v2 *object;
 564         struct atom_display_object_path_v3 *object_path_v3;
 565         struct atom_hpd_int_record *record = NULL;
 566
 567         if (!info)
 568                 return BP_RESULT_BADINPUT;
 569
 570         switch (bp->object_info_tbl.revision.minor) {
 571         case 4:
 572         default:
 573                 object = get_bios_object(bp, id);
 574
 575                 if (!object)
 576                         return BP_RESULT_BADINPUT;
 577
 578                 record = get_hpd_record(bp, object);
 579                 break;
 580         case 5:
 581                 object_path_v3 = get_bios_object_from_path_v3(bp, id);
 582
 583                 if (!object_path_v3)
 584                         return BP_RESULT_BADINPUT;
 585
 586                 record = get_hpd_record_for_path_v3(bp, object_path_v3);
 587                 break;
 588         }
 589
 590         if (record != NULL) {
 591                 info->hpd_int_gpio_uid = record->pin_id;
 592                 info->hpd_active = record->plugin_pin_state;
 593                 return BP_RESULT_OK;
 594         }
 595
 596         return BP_RESULT_NORECORD;
 597 }
 598
 599 static struct atom_hpd_int_record *get_hpd_record(
 600         struct bios_parser *bp,
 601         struct atom_display_object_path_v2 *object)
 602 {
 603         struct atom_common_record_header *header;
 604         uint32_t offset;
 605
 606         if (!object) {
 607                 BREAK_TO_DEBUGGER(); /* Invalid object */
 608                 return NULL;
 609         }
 610
 611         offset = le16_to_cpu(object->disp_recordoffset)
 612                         + bp->object_info_tbl_offset;
 613
 614         for (;;) {
 615                 header = GET_IMAGE(struct atom_common_record_header, offset);
 616
 617                 if (!header)
 618                         return NULL;
 619
 620                 if (header->record_type == LAST_RECORD_TYPE ||
 621                         !header->record_size)
 622                         break;
 623
 624                 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
 625                         && sizeof(struct atom_hpd_int_record) <=
 626                                                         header->record_size)
 627                         return (struct atom_hpd_int_record *) header;
 628
 629                 offset += header->record_size;
 630         }
 631
 632         return NULL;
 633 }
 634
 635 /**
 636  * bios_parser_get_gpio_pin_info
 637  * Get GpioPin information of input gpio id
 638  *
 639  * @dcb:     pointer to the DC BIOS
 640  * @gpio_id: GPIO ID
 641  * @info:    GpioPin information structure
 642  * return: Bios parser result code
 643  * note:
 644  *  to get the GPIO PIN INFO, we need:
 645  *  1. get the GPIO_ID from other object table, see GetHPDInfo()
 646  *  2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
 647  *      to get the registerA  offset/mask
 648  */
 649 static enum bp_result bios_parser_get_gpio_pin_info(
 650         struct dc_bios *dcb,
 651         uint32_t gpio_id,
 652         struct gpio_pin_info *info)
 653 {
 654         struct bios_parser *bp = BP_FROM_DCB(dcb);
 655         struct atom_gpio_pin_lut_v2_1 *header;
 656         uint32_t count = 0;
 657         uint32_t i = 0;
 658
 659         if (!DATA_TABLES(gpio_pin_lut))
 660                 return BP_RESULT_BADBIOSTABLE;
 661
 662         header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
 663                                                 DATA_TABLES(gpio_pin_lut));
 664         if (!header)
 665                 return BP_RESULT_BADBIOSTABLE;
 666
 667         if (sizeof(struct atom_common_table_header) +
 668                         sizeof(struct atom_gpio_pin_assignment)
 669                         > le16_to_cpu(header->table_header.structuresize))
 670                 return BP_RESULT_BADBIOSTABLE;
 671
 672         if (header->table_header.content_revision != 1)
 673                 return BP_RESULT_UNSUPPORTED;
 674
 675         /* Temporary hard code gpio pin info */
 676         count = (le16_to_cpu(header->table_header.structuresize)
 677                         - sizeof(struct atom_common_table_header))
 678                                 / sizeof(struct atom_gpio_pin_assignment);
 679         for (i = 0; i < count; ++i) {
 680                 if (header->gpio_pin[i].gpio_id != gpio_id)
 681                         continue;
 682
 683                 info->offset =
 684                         (uint32_t) le16_to_cpu(
 685                                         header->gpio_pin[i].data_a_reg_index);
 686                 info->offset_y = info->offset + 2;
 687                 info->offset_en = info->offset + 1;
 688                 info->offset_mask = info->offset - 1;
 689
 690                 info->mask = (uint32_t) (1 <<
 691                         header->gpio_pin[i].gpio_bitshift);
 692                 info->mask_y = info->mask + 2;
 693                 info->mask_en = info->mask + 1;
 694                 info->mask_mask = info->mask - 1;
 695
 696                 return BP_RESULT_OK;
 697         }
 698
 699         return BP_RESULT_NORECORD;
 700 }
 701
 702 static struct device_id device_type_from_device_id(uint16_t device_id)
 703 {
 704
 705         struct device_id result_device_id;
 706
 707         result_device_id.raw_device_tag = device_id;
 708
 709         switch (device_id) {
 710         case ATOM_DISPLAY_LCD1_SUPPORT:
 711                 result_device_id.device_type = DEVICE_TYPE_LCD;
 712                 result_device_id.enum_id = 1;
 713                 break;
 714
 715         case ATOM_DISPLAY_LCD2_SUPPORT:
 716                 result_device_id.device_type = DEVICE_TYPE_LCD;
 717                 result_device_id.enum_id = 2;
 718                 break;
 719
 720         case ATOM_DISPLAY_DFP1_SUPPORT:
 721                 result_device_id.device_type = DEVICE_TYPE_DFP;
 722                 result_device_id.enum_id = 1;
 723                 break;
 724
 725         case ATOM_DISPLAY_DFP2_SUPPORT:
 726                 result_device_id.device_type = DEVICE_TYPE_DFP;
 727                 result_device_id.enum_id = 2;
 728                 break;
 729
 730         case ATOM_DISPLAY_DFP3_SUPPORT:
 731                 result_device_id.device_type = DEVICE_TYPE_DFP;
 732                 result_device_id.enum_id = 3;
 733                 break;
 734
 735         case ATOM_DISPLAY_DFP4_SUPPORT:
 736                 result_device_id.device_type = DEVICE_TYPE_DFP;
 737                 result_device_id.enum_id = 4;
 738                 break;
 739
 740         case ATOM_DISPLAY_DFP5_SUPPORT:
 741                 result_device_id.device_type = DEVICE_TYPE_DFP;
 742                 result_device_id.enum_id = 5;
 743                 break;
 744
 745         case ATOM_DISPLAY_DFP6_SUPPORT:
 746                 result_device_id.device_type = DEVICE_TYPE_DFP;
 747                 result_device_id.enum_id = 6;
 748                 break;
 749
 750         default:
 751                 BREAK_TO_DEBUGGER(); /* Invalid device Id */
 752                 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
 753                 result_device_id.enum_id = 0;
 754         }
 755         return result_device_id;
 756 }
 757
 758 static enum bp_result bios_parser_get_device_tag(
 759         struct dc_bios *dcb,
 760         struct graphics_object_id connector_object_id,
 761         uint32_t device_tag_index,
 762         struct connector_device_tag_info *info)
 763 {
 764         struct bios_parser *bp = BP_FROM_DCB(dcb);
 765         struct atom_display_object_path_v2 *object;
 766
 767         struct atom_display_object_path_v3 *object_path_v3;
 768
 769
 770         if (!info)
 771                 return BP_RESULT_BADINPUT;
 772
 773         switch (bp->object_info_tbl.revision.minor) {
 774         case 4:
 775         default:
 776                 /* getBiosObject will return MXM object */
 777                 object = get_bios_object(bp, connector_object_id);
 778
 779                 if (!object) {
 780                         BREAK_TO_DEBUGGER(); /* Invalid object id */
 781                         return BP_RESULT_BADINPUT;
 782                 }
 783
 784                 info->acpi_device = 0; /* BIOS no longer provides this */
 785                 info->dev_id = device_type_from_device_id(object->device_tag);
 786                 break;
 787         case 5:
 788                 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id);
 789
 790                 if (!object_path_v3) {
 791                         BREAK_TO_DEBUGGER(); /* Invalid object id */
 792                         return BP_RESULT_BADINPUT;
 793                 }
 794                 info->acpi_device = 0; /* BIOS no longer provides this */
 795                 info->dev_id = device_type_from_device_id(object_path_v3->device_tag);
 796                 break;
 797         }
 798
 799         return BP_RESULT_OK;
 800 }
 801
 802 static enum bp_result get_ss_info_v4_1(
 803         struct bios_parser *bp,
 804         uint32_t id,
 805         uint32_t index,
 806         struct spread_spectrum_info *ss_info)
 807 {
 808         enum bp_result result = BP_RESULT_OK;
 809         struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
 810         struct atom_smu_info_v3_3 *smu_info = NULL;
 811
 812         if (!ss_info)
 813                 return BP_RESULT_BADINPUT;
 814
 815         if (!DATA_TABLES(dce_info))
 816                 return BP_RESULT_BADBIOSTABLE;
 817
 818         disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_1,
 819                                                         DATA_TABLES(dce_info));
 820         if (!disp_cntl_tbl)
 821                 return BP_RESULT_BADBIOSTABLE;
 822
 823
 824         ss_info->type.STEP_AND_DELAY_INFO = false;
 825         ss_info->spread_percentage_divider = 1000;
 826         /* BIOS no longer uses target clock.  Always enable for now */
 827         ss_info->target_clock_range = 0xffffffff;
 828
 829         switch (id) {
 830         case AS_SIGNAL_TYPE_DVI:
 831                 ss_info->spread_spectrum_percentage =
 832                                 disp_cntl_tbl->dvi_ss_percentage;
 833                 ss_info->spread_spectrum_range =
 834                                 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
 835                 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 836                         ss_info->type.CENTER_MODE = true;
 837
 838                 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
 839                 break;
 840         case AS_SIGNAL_TYPE_HDMI:
 841                 ss_info->spread_spectrum_percentage =
 842                                 disp_cntl_tbl->hdmi_ss_percentage;
 843                 ss_info->spread_spectrum_range =
 844                                 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
 845                 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 846                         ss_info->type.CENTER_MODE = true;
 847
 848                 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
 849                 break;
 850         /* TODO LVDS not support anymore? */
 851         case AS_SIGNAL_TYPE_DISPLAY_PORT:
 852                 ss_info->spread_spectrum_percentage =
 853                                 disp_cntl_tbl->dp_ss_percentage;
 854                 ss_info->spread_spectrum_range =
 855                                 disp_cntl_tbl->dp_ss_rate_10hz * 10;
 856                 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 857                         ss_info->type.CENTER_MODE = true;
 858
 859                 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
 860                 break;
 861         case AS_SIGNAL_TYPE_GPU_PLL:
 862                 /* atom_firmware: DAL only get data from dce_info table.
 863                  * if data within smu_info is needed for DAL, VBIOS should
 864                  * copy it into dce_info
 865                  */
 866                 result = BP_RESULT_UNSUPPORTED;
 867                 break;
 868         case AS_SIGNAL_TYPE_XGMI:
 869                 smu_info =  GET_IMAGE(struct atom_smu_info_v3_3,
 870                                       DATA_TABLES(smu_info));
 871                 if (!smu_info)
 872                         return BP_RESULT_BADBIOSTABLE;
 873                 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
 874                 ss_info->spread_spectrum_percentage =
 875                                 smu_info->waflclk_ss_percentage;
 876                 ss_info->spread_spectrum_range =
 877                                 smu_info->gpuclk_ss_rate_10hz * 10;
 878                 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 879                         ss_info->type.CENTER_MODE = true;
 880
 881                 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
 882                 break;
 883         default:
 884                 result = BP_RESULT_UNSUPPORTED;
 885         }
 886
 887         return result;
 888 }
 889
 890 static enum bp_result get_ss_info_v4_2(
 891         struct bios_parser *bp,
 892         uint32_t id,
 893         uint32_t index,
 894         struct spread_spectrum_info *ss_info)
 895 {
 896         enum bp_result result = BP_RESULT_OK;
 897         struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
 898         struct atom_smu_info_v3_1 *smu_info = NULL;
 899
 900         if (!ss_info)
 901                 return BP_RESULT_BADINPUT;
 902
 903         if (!DATA_TABLES(dce_info))
 904                 return BP_RESULT_BADBIOSTABLE;
 905
 906         if (!DATA_TABLES(smu_info))
 907                 return BP_RESULT_BADBIOSTABLE;
 908
 909         disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_2,
 910                                                         DATA_TABLES(dce_info));
 911         if (!disp_cntl_tbl)
 912                 return BP_RESULT_BADBIOSTABLE;
 913
 914         smu_info =  GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
 915         if (!smu_info)
 916                 return BP_RESULT_BADBIOSTABLE;
 917
 918         DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
 919         ss_info->type.STEP_AND_DELAY_INFO = false;
 920         ss_info->spread_percentage_divider = 1000;
 921         /* BIOS no longer uses target clock.  Always enable for now */
 922         ss_info->target_clock_range = 0xffffffff;
 923
 924         switch (id) {
 925         case AS_SIGNAL_TYPE_DVI:
 926                 ss_info->spread_spectrum_percentage =
 927                                 disp_cntl_tbl->dvi_ss_percentage;
 928                 ss_info->spread_spectrum_range =
 929                                 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
 930                 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 931                         ss_info->type.CENTER_MODE = true;
 932
 933                 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
 934                 break;
 935         case AS_SIGNAL_TYPE_HDMI:
 936                 ss_info->spread_spectrum_percentage =
 937                                 disp_cntl_tbl->hdmi_ss_percentage;
 938                 ss_info->spread_spectrum_range =
 939                                 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
 940                 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 941                         ss_info->type.CENTER_MODE = true;
 942
 943                 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
 944                 break;
 945         /* TODO LVDS not support anymore? */
 946         case AS_SIGNAL_TYPE_DISPLAY_PORT:
 947                 ss_info->spread_spectrum_percentage =
 948                                 smu_info->gpuclk_ss_percentage;
 949                 ss_info->spread_spectrum_range =
 950                                 smu_info->gpuclk_ss_rate_10hz * 10;
 951                 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 952                         ss_info->type.CENTER_MODE = true;
 953
 954                 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
 955                 break;
 956         case AS_SIGNAL_TYPE_GPU_PLL:
 957                 /* atom_firmware: DAL only get data from dce_info table.
 958                  * if data within smu_info is needed for DAL, VBIOS should
 959                  * copy it into dce_info
 960                  */
 961                 result = BP_RESULT_UNSUPPORTED;
 962                 break;
 963         default:
 964                 result = BP_RESULT_UNSUPPORTED;
 965         }
 966
 967         return result;
 968 }
 969
 970 static enum bp_result get_ss_info_v4_5(
 971         struct bios_parser *bp,
 972         uint32_t id,
 973         uint32_t index,
 974         struct spread_spectrum_info *ss_info)
 975 {
 976         enum bp_result result = BP_RESULT_OK;
 977         struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
 978
 979         if (!ss_info)
 980                 return BP_RESULT_BADINPUT;
 981
 982         if (!DATA_TABLES(dce_info))
 983                 return BP_RESULT_BADBIOSTABLE;
 984
 985         disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_5,
 986                                                         DATA_TABLES(dce_info));
 987         if (!disp_cntl_tbl)
 988                 return BP_RESULT_BADBIOSTABLE;
 989
 990         ss_info->type.STEP_AND_DELAY_INFO = false;
 991         ss_info->spread_percentage_divider = 1000;
 992         /* BIOS no longer uses target clock.  Always enable for now */
 993         ss_info->target_clock_range = 0xffffffff;
 994
 995         switch (id) {
 996         case AS_SIGNAL_TYPE_DVI:
 997                 ss_info->spread_spectrum_percentage =
 998                                 disp_cntl_tbl->dvi_ss_percentage;
 999                 ss_info->spread_spectrum_range =
1000                                 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
1001                 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1002                         ss_info->type.CENTER_MODE = true;
1003
1004                 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1005                 break;
1006         case AS_SIGNAL_TYPE_HDMI:
1007                 ss_info->spread_spectrum_percentage =
1008                                 disp_cntl_tbl->hdmi_ss_percentage;
1009                 ss_info->spread_spectrum_range =
1010                                 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
1011                 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1012                         ss_info->type.CENTER_MODE = true;
1013
1014                 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1015                 break;
1016         case AS_SIGNAL_TYPE_DISPLAY_PORT:
1017                 ss_info->spread_spectrum_percentage =
1018                                 disp_cntl_tbl->dp_ss_percentage;
1019                 ss_info->spread_spectrum_range =
1020                                 disp_cntl_tbl->dp_ss_rate_10hz * 10;
1021                 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1022                         ss_info->type.CENTER_MODE = true;
1023
1024                 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1025                 break;
1026         case AS_SIGNAL_TYPE_GPU_PLL:
1027                 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore.
1028                  * SMU Display PLL supposed to be without spread.
1029                  * Better place for it would be in atom_display_controller_info_v4_5 table.
1030                  */
1031                 result = BP_RESULT_UNSUPPORTED;
1032                 break;
1033         default:
1034                 result = BP_RESULT_UNSUPPORTED;
1035                 break;
1036         }
1037
1038         return result;
1039 }
1040
1041 /**
1042  * bios_parser_get_spread_spectrum_info
1043  * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
1044  * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
1045  * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
1046  * ver 3.1,
1047  * there is only one entry for each signal /ss id.  However, there is
1048  * no planning of supporting multiple spread Sprectum entry for EverGreen
1049  * @dcb:     pointer to the DC BIOS
1050  * @signal:  ASSignalType to be converted to info index
1051  * @index:   number of entries that match the converted info index
1052  * @ss_info: sprectrum information structure,
1053  * return: Bios parser result code
1054  */
1055 static enum bp_result bios_parser_get_spread_spectrum_info(
1056         struct dc_bios *dcb,
1057         enum as_signal_type signal,
1058         uint32_t index,
1059         struct spread_spectrum_info *ss_info)
1060 {
1061         struct bios_parser *bp = BP_FROM_DCB(dcb);
1062         enum bp_result result = BP_RESULT_UNSUPPORTED;
1063         struct atom_common_table_header *header;
1064         struct atom_data_revision tbl_revision;
1065
1066         if (!ss_info) /* check for bad input */
1067                 return BP_RESULT_BADINPUT;
1068
1069         if (!DATA_TABLES(dce_info))
1070                 return BP_RESULT_UNSUPPORTED;
1071
1072         header = GET_IMAGE(struct atom_common_table_header,
1073                                                 DATA_TABLES(dce_info));
1074         get_atom_data_table_revision(header, &tbl_revision);
1075
1076         switch (tbl_revision.major) {
1077         case 4:
1078                 switch (tbl_revision.minor) {
1079                 case 1:
1080                         return get_ss_info_v4_1(bp, signal, index, ss_info);
1081                 case 2:
1082                 case 3:
1083                 case 4:
1084                         return get_ss_info_v4_2(bp, signal, index, ss_info);
1085                 case 5:
1086                         return get_ss_info_v4_5(bp, signal, index, ss_info);
1087
1088                 default:
1089                         ASSERT(0);
1090                         break;
1091                 }
1092                 break;
1093         default:
1094                 break;
1095         }
1096         /* there can not be more then one entry for SS Info table */
1097         return result;
1098 }
1099
1100 static enum bp_result get_soc_bb_info_v4_4(
1101         struct bios_parser *bp,
1102         struct bp_soc_bb_info *soc_bb_info)
1103 {
1104         enum bp_result result = BP_RESULT_OK;
1105         struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1106
1107         if (!soc_bb_info)
1108                 return BP_RESULT_BADINPUT;
1109
1110         if (!DATA_TABLES(dce_info))
1111                 return BP_RESULT_BADBIOSTABLE;
1112
1113         if (!DATA_TABLES(smu_info))
1114                 return BP_RESULT_BADBIOSTABLE;
1115
1116         disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_4,
1117                                                         DATA_TABLES(dce_info));
1118         if (!disp_cntl_tbl)
1119                 return BP_RESULT_BADBIOSTABLE;
1120
1121         soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1122         soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1123         soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1124
1125         return result;
1126 }
1127
1128 static enum bp_result get_soc_bb_info_v4_5(
1129         struct bios_parser *bp,
1130         struct bp_soc_bb_info *soc_bb_info)
1131 {
1132         enum bp_result result = BP_RESULT_OK;
1133         struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1134
1135         if (!soc_bb_info)
1136                 return BP_RESULT_BADINPUT;
1137
1138         if (!DATA_TABLES(dce_info))
1139                 return BP_RESULT_BADBIOSTABLE;
1140
1141         disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_5,
1142                                                         DATA_TABLES(dce_info));
1143         if (!disp_cntl_tbl)
1144                 return BP_RESULT_BADBIOSTABLE;
1145
1146         soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1147         soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1148         soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1149
1150         return result;
1151 }
1152
1153 static enum bp_result bios_parser_get_soc_bb_info(
1154         struct dc_bios *dcb,
1155         struct bp_soc_bb_info *soc_bb_info)
1156 {
1157         struct bios_parser *bp = BP_FROM_DCB(dcb);
1158         enum bp_result result = BP_RESULT_UNSUPPORTED;
1159         struct atom_common_table_header *header;
1160         struct atom_data_revision tbl_revision;
1161
1162         if (!soc_bb_info) /* check for bad input */
1163                 return BP_RESULT_BADINPUT;
1164
1165         if (!DATA_TABLES(dce_info))
1166                 return BP_RESULT_UNSUPPORTED;
1167
1168         header = GET_IMAGE(struct atom_common_table_header,
1169                                                 DATA_TABLES(dce_info));
1170         get_atom_data_table_revision(header, &tbl_revision);
1171
1172         switch (tbl_revision.major) {
1173         case 4:
1174                 switch (tbl_revision.minor) {
1175                 case 1:
1176                 case 2:
1177                 case 3:
1178                         break;
1179                 case 4:
1180                         result = get_soc_bb_info_v4_4(bp, soc_bb_info);
1181                         break;
1182                 case 5:
1183                         result = get_soc_bb_info_v4_5(bp, soc_bb_info);
1184                         break;
1185                 default:
1186                         break;
1187                 }
1188                 break;
1189         default:
1190                 break;
1191         }
1192
1193         return result;
1194 }
1195
1196 static enum bp_result get_disp_caps_v4_1(
1197         struct bios_parser *bp,
1198         uint8_t *dce_caps)
1199 {
1200         enum bp_result result = BP_RESULT_OK;
1201         struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
1202
1203         if (!dce_caps)
1204                 return BP_RESULT_BADINPUT;
1205
1206         if (!DATA_TABLES(dce_info))
1207                 return BP_RESULT_BADBIOSTABLE;
1208
1209         disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
1210                                                         DATA_TABLES(dce_info));
1211
1212         if (!disp_cntl_tbl)
1213                 return BP_RESULT_BADBIOSTABLE;
1214
1215         *dce_caps = disp_cntl_tbl->display_caps;
1216
1217         return result;
1218 }
1219
1220 static enum bp_result get_disp_caps_v4_2(
1221         struct bios_parser *bp,
1222         uint8_t *dce_caps)
1223 {
1224         enum bp_result result = BP_RESULT_OK;
1225         struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
1226
1227         if (!dce_caps)
1228                 return BP_RESULT_BADINPUT;
1229
1230         if (!DATA_TABLES(dce_info))
1231                 return BP_RESULT_BADBIOSTABLE;
1232
1233         disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
1234                                                         DATA_TABLES(dce_info));
1235
1236         if (!disp_cntl_tbl)
1237                 return BP_RESULT_BADBIOSTABLE;
1238
1239         *dce_caps = disp_cntl_tbl->display_caps;
1240
1241         return result;
1242 }
1243
1244 static enum bp_result get_disp_caps_v4_3(
1245         struct bios_parser *bp,
1246         uint8_t *dce_caps)
1247 {
1248         enum bp_result result = BP_RESULT_OK;
1249         struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
1250
1251         if (!dce_caps)
1252                 return BP_RESULT_BADINPUT;
1253
1254         if (!DATA_TABLES(dce_info))
1255                 return BP_RESULT_BADBIOSTABLE;
1256
1257         disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
1258                                                         DATA_TABLES(dce_info));
1259
1260         if (!disp_cntl_tbl)
1261                 return BP_RESULT_BADBIOSTABLE;
1262
1263         *dce_caps = disp_cntl_tbl->display_caps;
1264
1265         return result;
1266 }
1267
1268 static enum bp_result get_disp_caps_v4_4(
1269         struct bios_parser *bp,
1270         uint8_t *dce_caps)
1271 {
1272         enum bp_result result = BP_RESULT_OK;
1273         struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1274
1275         if (!dce_caps)
1276                 return BP_RESULT_BADINPUT;
1277
1278         if (!DATA_TABLES(dce_info))
1279                 return BP_RESULT_BADBIOSTABLE;
1280
1281         disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1282                                                         DATA_TABLES(dce_info));
1283
1284         if (!disp_cntl_tbl)
1285                 return BP_RESULT_BADBIOSTABLE;
1286
1287         *dce_caps = disp_cntl_tbl->display_caps;
1288
1289         return result;
1290 }
1291
1292 static enum bp_result get_disp_caps_v4_5(
1293         struct bios_parser *bp,
1294         uint8_t *dce_caps)
1295 {
1296         enum bp_result result = BP_RESULT_OK;
1297         struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1298
1299         if (!dce_caps)
1300                 return BP_RESULT_BADINPUT;
1301
1302         if (!DATA_TABLES(dce_info))
1303                 return BP_RESULT_BADBIOSTABLE;
1304
1305         disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1306                                                         DATA_TABLES(dce_info));
1307
1308         if (!disp_cntl_tbl)
1309                 return BP_RESULT_BADBIOSTABLE;
1310
1311         *dce_caps = disp_cntl_tbl->display_caps;
1312
1313         return result;
1314 }
1315
1316 static enum bp_result bios_parser_get_lttpr_interop(
1317         struct dc_bios *dcb,
1318         uint8_t *dce_caps)
1319 {
1320         struct bios_parser *bp = BP_FROM_DCB(dcb);
1321         enum bp_result result = BP_RESULT_UNSUPPORTED;
1322         struct atom_common_table_header *header;
1323         struct atom_data_revision tbl_revision;
1324
1325         if (!DATA_TABLES(dce_info))
1326                 return BP_RESULT_UNSUPPORTED;
1327
1328         header = GET_IMAGE(struct atom_common_table_header,
1329                                                 DATA_TABLES(dce_info));
1330         get_atom_data_table_revision(header, &tbl_revision);
1331         switch (tbl_revision.major) {
1332         case 4:
1333                 switch (tbl_revision.minor) {
1334                 case 1:
1335                         result = get_disp_caps_v4_1(bp, dce_caps);
1336                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1337                         break;
1338                 case 2:
1339                         result = get_disp_caps_v4_2(bp, dce_caps);
1340                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1341                         break;
1342                 case 3:
1343                         result = get_disp_caps_v4_3(bp, dce_caps);
1344                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1345                         break;
1346                 case 4:
1347                         result = get_disp_caps_v4_4(bp, dce_caps);
1348                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1349                         break;
1350                 case 5:
1351                         result = get_disp_caps_v4_5(bp, dce_caps);
1352                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1353                         break;
1354
1355                 default:
1356                         break;
1357                 }
1358                 break;
1359         default:
1360                 break;
1361         }
1362         DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1363         return result;
1364 }
1365
1366 static enum bp_result bios_parser_get_lttpr_caps(
1367         struct dc_bios *dcb,
1368         uint8_t *dce_caps)
1369 {
1370         struct bios_parser *bp = BP_FROM_DCB(dcb);
1371         enum bp_result result = BP_RESULT_UNSUPPORTED;
1372         struct atom_common_table_header *header;
1373         struct atom_data_revision tbl_revision;
1374
1375         if (!DATA_TABLES(dce_info))
1376                 return BP_RESULT_UNSUPPORTED;
1377
1378         *dce_caps  = 0;
1379         header = GET_IMAGE(struct atom_common_table_header,
1380                                                 DATA_TABLES(dce_info));
1381         get_atom_data_table_revision(header, &tbl_revision);
1382         switch (tbl_revision.major) {
1383         case 4:
1384                 switch (tbl_revision.minor) {
1385                 case 1:
1386                         result = get_disp_caps_v4_1(bp, dce_caps);
1387                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1388                         break;
1389                 case 2:
1390                         result = get_disp_caps_v4_2(bp, dce_caps);
1391                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1392                         break;
1393                 case 3:
1394                         result = get_disp_caps_v4_3(bp, dce_caps);
1395                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1396                         break;
1397                 case 4:
1398                         result = get_disp_caps_v4_4(bp, dce_caps);
1399                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1400                         break;
1401                 case 5:
1402                         result = get_disp_caps_v4_5(bp, dce_caps);
1403                         *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1404                         break;
1405                 default:
1406                         break;
1407                 }
1408                 break;
1409         default:
1410                 break;
1411         }
1412         DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1413         if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {
1414                 *dce_caps = 1;
1415                 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled");
1416         }
1417         return result;
1418 }
1419
1420 static enum bp_result get_embedded_panel_info_v2_1(
1421                 struct bios_parser *bp,
1422                 struct embedded_panel_info *info)
1423 {
1424         struct lcd_info_v2_1 *lvds;
1425
1426         if (!info)
1427                 return BP_RESULT_BADINPUT;
1428
1429         if (!DATA_TABLES(lcd_info))
1430                 return BP_RESULT_UNSUPPORTED;
1431
1432         lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
1433
1434         if (!lvds)
1435                 return BP_RESULT_BADBIOSTABLE;
1436
1437         /* TODO: previous vv1_3, should v2_1 */
1438         if (!((lvds->table_header.format_revision == 2)
1439                         && (lvds->table_header.content_revision >= 1)))
1440                 return BP_RESULT_UNSUPPORTED;
1441
1442         memset(info, 0, sizeof(struct embedded_panel_info));
1443
1444         /* We need to convert from 10KHz units into KHz units */
1445         info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
1446         /* usHActive does not include borders, according to VBIOS team */
1447         info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
1448         /* usHBlanking_Time includes borders, so we should really be
1449          * subtractingborders duing this translation, but LVDS generally
1450          * doesn't have borders, so we should be okay leaving this as is for
1451          * now.  May need to revisit if we ever have LVDS with borders
1452          */
1453         info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
1454         /* usVActive does not include borders, according to VBIOS team*/
1455         info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
1456         /* usVBlanking_Time includes borders, so we should really be
1457          * subtracting borders duing this translation, but LVDS generally
1458          * doesn't have borders, so we should be okay leaving this as is for
1459          * now. May need to revisit if we ever have LVDS with borders
1460          */
1461         info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
1462         info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
1463         info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
1464         info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
1465         info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
1466         info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
1467         info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
1468
1469         /* not provided by VBIOS */
1470         info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
1471
1472         info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1473                         & ATOM_HSYNC_POLARITY);
1474         info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1475                         & ATOM_VSYNC_POLARITY);
1476
1477         /* not provided by VBIOS */
1478         info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
1479
1480         info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1481                         & ATOM_H_REPLICATIONBY2);
1482         info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1483                         & ATOM_V_REPLICATIONBY2);
1484         info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
1485                         & ATOM_COMPOSITESYNC);
1486         info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
1487
1488         /* not provided by VBIOS*/
1489         info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
1490         /* not provided by VBIOS*/
1491         info->ss_id = 0;
1492
1493         info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
1494
1495         return BP_RESULT_OK;
1496 }
1497
1498 static enum bp_result bios_parser_get_embedded_panel_info(
1499                 struct dc_bios *dcb,
1500                 struct embedded_panel_info *info)
1501 {
1502         struct bios_parser
1503         *bp = BP_FROM_DCB(dcb);
1504         struct atom_common_table_header *header;
1505         struct atom_data_revision tbl_revision;
1506
1507         if (!DATA_TABLES(lcd_info))
1508                 return BP_RESULT_FAILURE;
1509
1510         header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
1511
1512         if (!header)
1513                 return BP_RESULT_BADBIOSTABLE;
1514
1515         get_atom_data_table_revision(header, &tbl_revision);
1516
1517         switch (tbl_revision.major) {
1518         case 2:
1519                 switch (tbl_revision.minor) {
1520                 case 1:
1521                         return get_embedded_panel_info_v2_1(bp, info);
1522                 default:
1523                         break;
1524                 }
1525                 break;
1526         default:
1527                 break;
1528         }
1529
1530         return BP_RESULT_FAILURE;
1531 }
1532
1533 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1534 {
1535         enum dal_device_type device_type = device_id.device_type;
1536         uint32_t enum_id = device_id.enum_id;
1537
1538         switch (device_type) {
1539         case DEVICE_TYPE_LCD:
1540                 switch (enum_id) {
1541                 case 1:
1542                         return ATOM_DISPLAY_LCD1_SUPPORT;
1543                 default:
1544                         break;
1545                 }
1546                 break;
1547         case DEVICE_TYPE_DFP:
1548                 switch (enum_id) {
1549                 case 1:
1550                         return ATOM_DISPLAY_DFP1_SUPPORT;
1551                 case 2:
1552                         return ATOM_DISPLAY_DFP2_SUPPORT;
1553                 case 3:
1554                         return ATOM_DISPLAY_DFP3_SUPPORT;
1555                 case 4:
1556                         return ATOM_DISPLAY_DFP4_SUPPORT;
1557                 case 5:
1558                         return ATOM_DISPLAY_DFP5_SUPPORT;
1559                 case 6:
1560                         return ATOM_DISPLAY_DFP6_SUPPORT;
1561                 default:
1562                         break;
1563                 }
1564                 break;
1565         default:
1566                 break;
1567         }
1568
1569         /* Unidentified device ID, return empty support mask. */
1570         return 0;
1571 }
1572
1573 static bool bios_parser_is_device_id_supported(
1574         struct dc_bios *dcb,
1575         struct device_id id)
1576 {
1577         struct bios_parser *bp = BP_FROM_DCB(dcb);
1578
1579         uint32_t mask = get_support_mask_for_device_id(id);
1580
1581         switch (bp->object_info_tbl.revision.minor) {
1582         case 4:
1583         default:
1584                 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;
1585                 break;
1586         case 5:
1587                 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;
1588                 break;
1589         }
1590
1591         return false;
1592 }
1593
1594 static uint32_t bios_parser_get_ss_entry_number(
1595         struct dc_bios *dcb,
1596         enum as_signal_type signal)
1597 {
1598         /* TODO: DAL2 atomfirmware implementation does not need this.
1599          * why DAL3 need this?
1600          */
1601         return 1;
1602 }
1603
1604 static enum bp_result bios_parser_transmitter_control(
1605         struct dc_bios *dcb,
1606         struct bp_transmitter_control *cntl)
1607 {
1608         struct bios_parser *bp = BP_FROM_DCB(dcb);
1609
1610         if (!bp->cmd_tbl.transmitter_control)
1611                 return BP_RESULT_FAILURE;
1612
1613         return bp->cmd_tbl.transmitter_control(bp, cntl);
1614 }
1615
1616 static enum bp_result bios_parser_encoder_control(
1617         struct dc_bios *dcb,
1618         struct bp_encoder_control *cntl)
1619 {
1620         struct bios_parser *bp = BP_FROM_DCB(dcb);
1621
1622         if (!bp->cmd_tbl.dig_encoder_control)
1623                 return BP_RESULT_FAILURE;
1624
1625         return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1626 }
1627
1628 static enum bp_result bios_parser_set_pixel_clock(
1629         struct dc_bios *dcb,
1630         struct bp_pixel_clock_parameters *bp_params)
1631 {
1632         struct bios_parser *bp = BP_FROM_DCB(dcb);
1633
1634         if (!bp->cmd_tbl.set_pixel_clock)
1635                 return BP_RESULT_FAILURE;
1636
1637         return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1638 }
1639
1640 static enum bp_result bios_parser_set_dce_clock(
1641         struct dc_bios *dcb,
1642         struct bp_set_dce_clock_parameters *bp_params)
1643 {
1644         struct bios_parser *bp = BP_FROM_DCB(dcb);
1645
1646         if (!bp->cmd_tbl.set_dce_clock)
1647                 return BP_RESULT_FAILURE;
1648
1649         return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1650 }
1651
1652 static enum bp_result bios_parser_program_crtc_timing(
1653         struct dc_bios *dcb,
1654         struct bp_hw_crtc_timing_parameters *bp_params)
1655 {
1656         struct bios_parser *bp = BP_FROM_DCB(dcb);
1657
1658         if (!bp->cmd_tbl.set_crtc_timing)
1659                 return BP_RESULT_FAILURE;
1660
1661         return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1662 }
1663
1664 static enum bp_result bios_parser_enable_crtc(
1665         struct dc_bios *dcb,
1666         enum controller_id id,
1667         bool enable)
1668 {
1669         struct bios_parser *bp = BP_FROM_DCB(dcb);
1670
1671         if (!bp->cmd_tbl.enable_crtc)
1672                 return BP_RESULT_FAILURE;
1673
1674         return bp->cmd_tbl.enable_crtc(bp, id, enable);
1675 }
1676
1677 static enum bp_result bios_parser_enable_disp_power_gating(
1678         struct dc_bios *dcb,
1679         enum controller_id controller_id,
1680         enum bp_pipe_control_action action)
1681 {
1682         struct bios_parser *bp = BP_FROM_DCB(dcb);
1683
1684         if (!bp->cmd_tbl.enable_disp_power_gating)
1685                 return BP_RESULT_FAILURE;
1686
1687         return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1688                 action);
1689 }
1690
1691 static enum bp_result bios_parser_enable_lvtma_control(
1692         struct dc_bios *dcb,
1693         uint8_t uc_pwr_on,
1694         uint8_t panel_instance,
1695         uint8_t bypass_panel_control_wait)
1696 {
1697         struct bios_parser *bp = BP_FROM_DCB(dcb);
1698
1699         if (!bp->cmd_tbl.enable_lvtma_control)
1700                 return BP_RESULT_FAILURE;
1701
1702         return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance, bypass_panel_control_wait);
1703 }
1704
1705 static bool bios_parser_is_accelerated_mode(
1706         struct dc_bios *dcb)
1707 {
1708         return bios_is_accelerated_mode(dcb);
1709 }
1710
1711 /**
1712  * bios_parser_set_scratch_critical_state - update critical state bit
1713  *                                          in VBIOS scratch register
1714  *
1715  * @dcb:   pointer to the DC BIO
1716  * @state: set or reset state
1717  */
1718 static void bios_parser_set_scratch_critical_state(
1719         struct dc_bios *dcb,
1720         bool state)
1721 {
1722         bios_set_scratch_critical_state(dcb, state);
1723 }
1724
1725 static enum bp_result bios_parser_get_firmware_info(
1726         struct dc_bios *dcb,
1727         struct dc_firmware_info *info)
1728 {
1729         struct bios_parser *bp = BP_FROM_DCB(dcb);
1730         static enum bp_result result = BP_RESULT_BADBIOSTABLE;
1731         struct atom_common_table_header *header;
1732
1733         struct atom_data_revision revision;
1734
1735         if (info && DATA_TABLES(firmwareinfo)) {
1736                 header = GET_IMAGE(struct atom_common_table_header,
1737                                 DATA_TABLES(firmwareinfo));
1738                 get_atom_data_table_revision(header, &revision);
1739                 switch (revision.major) {
1740                 case 3:
1741                         switch (revision.minor) {
1742                         case 1:
1743                                 result = get_firmware_info_v3_1(bp, info);
1744                                 break;
1745                         case 2:
1746                         case 3:
1747                                 result = get_firmware_info_v3_2(bp, info);
1748                                 break;
1749                         case 4:
1750                                 result = get_firmware_info_v3_4(bp, info);
1751                                 break;
1752                         default:
1753                                 break;
1754                         }
1755                         break;
1756                 default:
1757                         break;
1758                 }
1759         }
1760
1761         return result;
1762 }
1763
1764 static enum bp_result get_firmware_info_v3_1(
1765         struct bios_parser *bp,
1766         struct dc_firmware_info *info)
1767 {
1768         struct atom_firmware_info_v3_1 *firmware_info;
1769         struct atom_display_controller_info_v4_1 *dce_info = NULL;
1770
1771         if (!info)
1772                 return BP_RESULT_BADINPUT;
1773
1774         firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1775                         DATA_TABLES(firmwareinfo));
1776
1777         dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1778                         DATA_TABLES(dce_info));
1779
1780         if (!firmware_info || !dce_info)
1781                 return BP_RESULT_BADBIOSTABLE;
1782
1783         memset(info, 0, sizeof(*info));
1784
1785         /* Pixel clock pll information. */
1786          /* We need to convert from 10KHz units into KHz units */
1787         info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1788         info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1789
1790          /* 27MHz for Vega10: */
1791         info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1792
1793         /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1794         if (info->pll_info.crystal_frequency == 0)
1795                 info->pll_info.crystal_frequency = 27000;
1796         /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1797         info->dp_phy_ref_clk     = dce_info->dpphy_refclk_10khz * 10;
1798         info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1799
1800         /* Get GPU PLL VCO Clock */
1801
1802         if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1803                 /* VBIOS gives in 10KHz */
1804                 info->smu_gpu_pll_output_freq =
1805                                 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1806         }
1807
1808         info->oem_i2c_present = false;
1809
1810         return BP_RESULT_OK;
1811 }
1812
1813 static enum bp_result get_firmware_info_v3_2(
1814         struct bios_parser *bp,
1815         struct dc_firmware_info *info)
1816 {
1817         struct atom_firmware_info_v3_2 *firmware_info;
1818         struct atom_display_controller_info_v4_1 *dce_info = NULL;
1819         struct atom_common_table_header *header;
1820         struct atom_data_revision revision;
1821         struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1822         struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1823
1824         if (!info)
1825                 return BP_RESULT_BADINPUT;
1826
1827         firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1828                         DATA_TABLES(firmwareinfo));
1829
1830         dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1831                         DATA_TABLES(dce_info));
1832
1833         if (!firmware_info || !dce_info)
1834                 return BP_RESULT_BADBIOSTABLE;
1835
1836         memset(info, 0, sizeof(*info));
1837
1838         header = GET_IMAGE(struct atom_common_table_header,
1839                                         DATA_TABLES(smu_info));
1840         get_atom_data_table_revision(header, &revision);
1841
1842         if (revision.minor == 2) {
1843                 /* Vega12 */
1844                 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1845                                                         DATA_TABLES(smu_info));
1846                 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage);
1847                 if (!smu_info_v3_2)
1848                         return BP_RESULT_BADBIOSTABLE;
1849
1850                 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1851         } else if (revision.minor == 3) {
1852                 /* Vega20 */
1853                 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1854                                                         DATA_TABLES(smu_info));
1855                 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage);
1856                 if (!smu_info_v3_3)
1857                         return BP_RESULT_BADBIOSTABLE;
1858
1859                 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1860         }
1861
1862          // We need to convert from 10KHz units into KHz units.
1863         info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1864
1865          /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1866         info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1867         /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1868         if (info->pll_info.crystal_frequency == 0) {
1869                 if (revision.minor == 2)
1870                         info->pll_info.crystal_frequency = 27000;
1871                 else if (revision.minor == 3)
1872                         info->pll_info.crystal_frequency = 100000;
1873         }
1874         /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1875         info->dp_phy_ref_clk     = dce_info->dpphy_refclk_10khz * 10;
1876         info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1877
1878         /* Get GPU PLL VCO Clock */
1879         if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1880                 if (revision.minor == 2)
1881                         info->smu_gpu_pll_output_freq =
1882                                         bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1883                 else if (revision.minor == 3)
1884                         info->smu_gpu_pll_output_freq =
1885                                         bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1886         }
1887
1888         if (firmware_info->board_i2c_feature_id == 0x2) {
1889                 info->oem_i2c_present = true;
1890                 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1891         } else {
1892                 info->oem_i2c_present = false;
1893         }
1894
1895         return BP_RESULT_OK;
1896 }
1897
1898 static enum bp_result get_firmware_info_v3_4(
1899         struct bios_parser *bp,
1900         struct dc_firmware_info *info)
1901 {
1902         struct atom_firmware_info_v3_4 *firmware_info;
1903         struct atom_common_table_header *header;
1904         struct atom_data_revision revision;
1905         struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
1906         struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
1907
1908         struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL;
1909         struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
1910         struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL;
1911
1912         if (!info)
1913                 return BP_RESULT_BADINPUT;
1914
1915         firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4,
1916                         DATA_TABLES(firmwareinfo));
1917
1918         if (!firmware_info)
1919                 return BP_RESULT_BADBIOSTABLE;
1920
1921         memset(info, 0, sizeof(*info));
1922
1923         header = GET_IMAGE(struct atom_common_table_header,
1924                                         DATA_TABLES(dce_info));
1925
1926         get_atom_data_table_revision(header, &revision);
1927
1928         switch (revision.major) {
1929         case 4:
1930                 switch (revision.minor) {
1931                 case 5:
1932                         dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
1933                                                         DATA_TABLES(dce_info));
1934
1935                         if (!dce_info_v4_5)
1936                                 return BP_RESULT_BADBIOSTABLE;
1937
1938                          /* 100MHz expected */
1939                         info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
1940                         info->dp_phy_ref_clk             = dce_info_v4_5->dpphy_refclk_10khz * 10;
1941                          /* 50MHz expected */
1942                         info->i2c_engine_ref_clk         = dce_info_v4_5->i2c_engine_refclk_10khz * 10;
1943
1944                         /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */
1945                         break;
1946
1947                 case 4:
1948                         dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
1949                                                         DATA_TABLES(dce_info));
1950
1951                         if (!dce_info_v4_4)
1952                                 return BP_RESULT_BADBIOSTABLE;
1953
1954                         /* 100MHz expected */
1955                         info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;
1956                         info->dp_phy_ref_clk             = dce_info_v4_4->dpphy_refclk_10khz * 10;
1957                         /* 50MHz expected */
1958                         info->i2c_engine_ref_clk         = dce_info_v4_4->i2c_engine_refclk_10khz * 10;
1959
1960                         /* Get SMU Display PLL VCO Frequency in KHz*/
1961                         info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10;
1962                         break;
1963
1964                 default:
1965                         /* should not come here, keep as backup, as was before */
1966                         dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1,
1967                                                         DATA_TABLES(dce_info));
1968
1969                         if (!dce_info_v4_1)
1970                                 return BP_RESULT_BADBIOSTABLE;
1971
1972                         info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;
1973                         info->dp_phy_ref_clk             = dce_info_v4_1->dpphy_refclk_10khz * 10;
1974                         info->i2c_engine_ref_clk         = dce_info_v4_1->i2c_engine_refclk_10khz * 10;
1975                         break;
1976                 }
1977                 break;
1978
1979         default:
1980                 ASSERT(0);
1981                 break;
1982         }
1983
1984         header = GET_IMAGE(struct atom_common_table_header,
1985                                         DATA_TABLES(smu_info));
1986         get_atom_data_table_revision(header, &revision);
1987
1988         switch (revision.major) {
1989         case 3:
1990                 switch (revision.minor) {
1991                 case 5:
1992                         smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5,
1993                                                         DATA_TABLES(smu_info));
1994
1995                         if (!smu_info_v3_5)
1996                                 return BP_RESULT_BADBIOSTABLE;
1997                         DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage);
1998                         info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10;
1999                         break;
2000
2001                 default:
2002                         break;
2003                 }
2004                 break;
2005
2006         case 4:
2007                 switch (revision.minor) {
2008                 case 0:
2009                         smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0,
2010                                                         DATA_TABLES(smu_info));
2011
2012                         if (!smu_info_v4_0)
2013                                 return BP_RESULT_BADBIOSTABLE;
2014
2015                         /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */
2016                         break;
2017
2018                 default:
2019                         break;
2020                 }
2021                 break;
2022
2023         default:
2024                 break;
2025         }
2026
2027          // We need to convert from 10KHz units into KHz units.
2028         info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
2029
2030         if (firmware_info->board_i2c_feature_id == 0x2) {
2031                 info->oem_i2c_present = true;
2032                 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
2033         } else {
2034                 info->oem_i2c_present = false;
2035         }
2036
2037         return BP_RESULT_OK;
2038 }
2039
2040 static enum bp_result bios_parser_get_encoder_cap_info(
2041         struct dc_bios *dcb,
2042         struct graphics_object_id object_id,
2043         struct bp_encoder_cap_info *info)
2044 {
2045         struct bios_parser *bp = BP_FROM_DCB(dcb);
2046         struct atom_display_object_path_v2 *object;
2047         struct atom_encoder_caps_record *record = NULL;
2048
2049         if (!info)
2050                 return BP_RESULT_BADINPUT;
2051
2052 #if defined(CONFIG_DRM_AMD_DC_FP)
2053         /* encoder cap record not available in v1_5 */
2054         if (bp->object_info_tbl.revision.minor == 5)
2055                 return BP_RESULT_NORECORD;
2056 #endif
2057
2058         object = get_bios_object(bp, object_id);
2059
2060         if (!object)
2061                 return BP_RESULT_BADINPUT;
2062
2063         record = get_encoder_cap_record(bp, object);
2064         if (!record)
2065                 return BP_RESULT_NORECORD;
2066         DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id);
2067
2068         info->DP_HBR2_CAP = (record->encodercaps &
2069                         ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
2070         info->DP_HBR2_EN = (record->encodercaps &
2071                         ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
2072         info->DP_HBR3_EN = (record->encodercaps &
2073                         ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
2074         info->HDMI_6GB_EN = (record->encodercaps &
2075                         ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
2076         info->IS_DP2_CAPABLE = (record->encodercaps &
2077                         ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;
2078         info->DP_UHBR10_EN = (record->encodercaps &
2079                         ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0;
2080         info->DP_UHBR13_5_EN = (record->encodercaps &
2081                         ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;
2082         info->DP_UHBR20_EN = (record->encodercaps &
2083                         ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
2084         info->DP_IS_USB_C = (record->encodercaps &
2085                         ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
2086         DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C);
2087
2088         return BP_RESULT_OK;
2089 }
2090
2091
2092 static struct atom_encoder_caps_record *get_encoder_cap_record(
2093         struct bios_parser *bp,
2094         struct atom_display_object_path_v2 *object)
2095 {
2096         struct atom_common_record_header *header;
2097         uint32_t offset;
2098
2099         if (!object) {
2100                 BREAK_TO_DEBUGGER(); /* Invalid object */
2101                 return NULL;
2102         }
2103
2104         offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
2105
2106         for (;;) {
2107                 header = GET_IMAGE(struct atom_common_record_header, offset);
2108
2109                 if (!header)
2110                         return NULL;
2111
2112                 offset += header->record_size;
2113
2114                 if (header->record_type == LAST_RECORD_TYPE ||
2115                                 !header->record_size)
2116                         break;
2117
2118                 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
2119                         continue;
2120
2121                 if (sizeof(struct atom_encoder_caps_record) <=
2122                                                         header->record_size)
2123                         return (struct atom_encoder_caps_record *)header;
2124         }
2125
2126         return NULL;
2127 }
2128
2129 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
2130         struct bios_parser *bp,
2131         struct atom_display_object_path_v2 *object)
2132 {
2133         struct atom_common_record_header *header;
2134         uint32_t offset;
2135
2136         if (!object) {
2137                 BREAK_TO_DEBUGGER(); /* Invalid object */
2138                 return NULL;
2139         }
2140
2141         offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2142
2143         for (;;) {
2144                 header = GET_IMAGE(struct atom_common_record_header, offset);
2145
2146                 if (!header)
2147                         return NULL;
2148
2149                 offset += header->record_size;
2150
2151                 if (header->record_type == LAST_RECORD_TYPE ||
2152                                 !header->record_size)
2153                         break;
2154
2155                 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE)
2156                         continue;
2157
2158                 if (sizeof(struct atom_disp_connector_caps_record) <=
2159                                                         header->record_size)
2160                         return (struct atom_disp_connector_caps_record *)header;
2161         }
2162
2163         return NULL;
2164 }
2165
2166 static struct atom_connector_caps_record *get_connector_caps_record(struct bios_parser *bp,
2167                                                                     struct atom_display_object_path_v3 *object)
2168 {
2169         struct atom_common_record_header *header;
2170         uint32_t offset;
2171
2172         if (!object) {
2173                 BREAK_TO_DEBUGGER(); /* Invalid object */
2174                 return NULL;
2175         }
2176
2177         offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2178
2179         for (;;) {
2180                 header = GET_IMAGE(struct atom_common_record_header, offset);
2181
2182                 if (!header)
2183                         return NULL;
2184
2185                 offset += header->record_size;
2186
2187                 if (header->record_type == ATOM_RECORD_END_TYPE ||
2188                                 !header->record_size)
2189                         break;
2190
2191                 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE)
2192                         continue;
2193
2194                 if (sizeof(struct atom_connector_caps_record) <= header->record_size)
2195                         return (struct atom_connector_caps_record *)header;
2196         }
2197
2198         return NULL;
2199 }
2200
2201 static enum bp_result bios_parser_get_disp_connector_caps_info(
2202         struct dc_bios *dcb,
2203         struct graphics_object_id object_id,
2204         struct bp_disp_connector_caps_info *info)
2205 {
2206         struct bios_parser *bp = BP_FROM_DCB(dcb);
2207         struct atom_display_object_path_v2 *object;
2208         struct atom_display_object_path_v3 *object_path_v3;
2209         struct atom_connector_caps_record *record_path_v3;
2210         struct atom_disp_connector_caps_record *record = NULL;
2211
2212         if (!info)
2213                 return BP_RESULT_BADINPUT;
2214
2215         switch (bp->object_info_tbl.revision.minor) {
2216         case 4:
2217             default:
2218                     object = get_bios_object(bp, object_id);
2219
2220                     if (!object)
2221                             return BP_RESULT_BADINPUT;
2222
2223                     record = get_disp_connector_caps_record(bp, object);
2224                     if (!record)
2225                             return BP_RESULT_NORECORD;
2226
2227                     info->INTERNAL_DISPLAY =
2228                             (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;
2229                     info->INTERNAL_DISPLAY_BL =
2230                             (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;
2231                     break;
2232             case 5:
2233                 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2234
2235                 if (!object_path_v3)
2236                         return BP_RESULT_BADINPUT;
2237
2238                 record_path_v3 = get_connector_caps_record(bp, object_path_v3);
2239                 if (!record_path_v3)
2240                         return BP_RESULT_NORECORD;
2241
2242                 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
2243                                                                         ? 1 : 0;
2244                 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
2245                                                                                 ? 1 : 0;
2246                 break;
2247         }
2248
2249         return BP_RESULT_OK;
2250 }
2251
2252 static struct atom_connector_speed_record *get_connector_speed_cap_record(struct bios_parser *bp,
2253                                                                           struct atom_display_object_path_v3 *object)
2254 {
2255         struct atom_common_record_header *header;
2256         uint32_t offset;
2257
2258         if (!object) {
2259                 BREAK_TO_DEBUGGER(); /* Invalid object */
2260                 return NULL;
2261         }
2262
2263         offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2264
2265         for (;;) {
2266                 header = GET_IMAGE(struct atom_common_record_header, offset);
2267
2268                 if (!header)
2269                         return NULL;
2270
2271                 offset += header->record_size;
2272
2273                 if (header->record_type == ATOM_RECORD_END_TYPE ||
2274                                 !header->record_size)
2275                         break;
2276
2277                 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO)
2278                         continue;
2279
2280                 if (sizeof(struct atom_connector_speed_record) <= header->record_size)
2281                         return (struct atom_connector_speed_record *)header;
2282         }
2283
2284         return NULL;
2285 }
2286
2287 static enum bp_result bios_parser_get_connector_speed_cap_info(
2288         struct dc_bios *dcb,
2289         struct graphics_object_id object_id,
2290         struct bp_connector_speed_cap_info *info)
2291 {
2292         struct bios_parser *bp = BP_FROM_DCB(dcb);
2293         struct atom_display_object_path_v3 *object_path_v3;
2294         //struct atom_connector_speed_record *record = NULL;
2295         struct atom_connector_speed_record *record;
2296
2297         if (!info)
2298                 return BP_RESULT_BADINPUT;
2299
2300         object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2301
2302         if (!object_path_v3)
2303                 return BP_RESULT_BADINPUT;
2304
2305         record = get_connector_speed_cap_record(bp, object_path_v3);
2306         if (!record)
2307                 return BP_RESULT_NORECORD;
2308
2309         info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0;
2310         info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0;
2311         info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0;
2312         info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0;
2313         info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0;
2314         info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0;
2315         return BP_RESULT_OK;
2316 }
2317
2318 static enum bp_result get_vram_info_v23(
2319         struct bios_parser *bp,
2320         struct dc_vram_info *info)
2321 {
2322         struct atom_vram_info_header_v2_3 *info_v23;
2323         static enum bp_result result = BP_RESULT_OK;
2324
2325         info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
2326                                                 DATA_TABLES(vram_info));
2327
2328         if (info_v23 == NULL)
2329                 return BP_RESULT_BADBIOSTABLE;
2330
2331         info->num_chans = info_v23->vram_module[0].channel_num;
2332         info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
2333
2334         return result;
2335 }
2336
2337 static enum bp_result get_vram_info_v24(
2338         struct bios_parser *bp,
2339         struct dc_vram_info *info)
2340 {
2341         struct atom_vram_info_header_v2_4 *info_v24;
2342         static enum bp_result result = BP_RESULT_OK;
2343
2344         info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
2345                                                 DATA_TABLES(vram_info));
2346
2347         if (info_v24 == NULL)
2348                 return BP_RESULT_BADBIOSTABLE;
2349
2350         info->num_chans = info_v24->vram_module[0].channel_num;
2351         info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
2352
2353         return result;
2354 }
2355
2356 static enum bp_result get_vram_info_v25(
2357         struct bios_parser *bp,
2358         struct dc_vram_info *info)
2359 {
2360         struct atom_vram_info_header_v2_5 *info_v25;
2361         static enum bp_result result = BP_RESULT_OK;
2362
2363         info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
2364                                                 DATA_TABLES(vram_info));
2365
2366         if (info_v25 == NULL)
2367                 return BP_RESULT_BADBIOSTABLE;
2368
2369         info->num_chans = info_v25->vram_module[0].channel_num;
2370         info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
2371
2372         return result;
2373 }
2374
2375 static enum bp_result get_vram_info_v30(
2376         struct bios_parser *bp,
2377         struct dc_vram_info *info)
2378 {
2379         struct atom_vram_info_header_v3_0 *info_v30;
2380         enum bp_result result = BP_RESULT_OK;
2381
2382         info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0,
2383                                                 DATA_TABLES(vram_info));
2384
2385         if (info_v30 == NULL)
2386                 return BP_RESULT_BADBIOSTABLE;
2387
2388         info->num_chans = info_v30->channel_num;
2389         info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2390
2391         return result;
2392 }
2393
2394
2395 /*
2396  * get_integrated_info_v11
2397  *
2398  * @brief
2399  * Get V8 integrated BIOS information
2400  *
2401  * @param
2402  * bios_parser *bp - [in]BIOS parser handler to get master data table
2403  * integrated_info *info - [out] store and output integrated info
2404  *
2405  * @return
2406  * static enum bp_result - BP_RESULT_OK if information is available,
2407  *                  BP_RESULT_BADBIOSTABLE otherwise.
2408  */
2409 static enum bp_result get_integrated_info_v11(
2410         struct bios_parser *bp,
2411         struct integrated_info *info)
2412 {
2413         struct atom_integrated_system_info_v1_11 *info_v11;
2414         uint32_t i;
2415
2416         info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
2417                                         DATA_TABLES(integratedsysteminfo));
2418
2419         DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage);
2420         if (info_v11 == NULL)
2421                 return BP_RESULT_BADBIOSTABLE;
2422
2423         info->gpu_cap_info =
2424         le32_to_cpu(info_v11->gpucapinfo);
2425         /*
2426         * system_config: Bit[0] = 0 : PCIE power gating disabled
2427         *                       = 1 : PCIE power gating enabled
2428         *                Bit[1] = 0 : DDR-PLL shut down disabled
2429         *                       = 1 : DDR-PLL shut down enabled
2430         *                Bit[2] = 0 : DDR-PLL power down disabled
2431         *                       = 1 : DDR-PLL power down enabled
2432         */
2433         info->system_config = le32_to_cpu(info_v11->system_config);
2434         info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
2435         info->memory_type = info_v11->memorytype;
2436         info->ma_channel_number = info_v11->umachannelnumber;
2437         info->lvds_ss_percentage =
2438         le16_to_cpu(info_v11->lvds_ss_percentage);
2439         info->dp_ss_control =
2440         le16_to_cpu(info_v11->reserved1);
2441         info->lvds_sspread_rate_in_10hz =
2442         le16_to_cpu(info_v11->lvds_ss_rate_10hz);
2443         info->hdmi_ss_percentage =
2444         le16_to_cpu(info_v11->hdmi_ss_percentage);
2445         info->hdmi_sspread_rate_in_10hz =
2446         le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
2447         info->dvi_ss_percentage =
2448         le16_to_cpu(info_v11->dvi_ss_percentage);
2449         info->dvi_sspread_rate_in_10_hz =
2450         le16_to_cpu(info_v11->dvi_ss_rate_10hz);
2451         info->lvds_misc = info_v11->lvds_misc;
2452         for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2453                 info->ext_disp_conn_info.gu_id[i] =
2454                                 info_v11->extdispconninfo.guid[i];
2455         }
2456
2457         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2458                 info->ext_disp_conn_info.path[i].device_connector_id =
2459                 object_id_from_bios_object_id(
2460                 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
2461
2462                 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2463                 object_id_from_bios_object_id(
2464                         le16_to_cpu(
2465                         info_v11->extdispconninfo.path[i].ext_encoder_objid));
2466
2467                 info->ext_disp_conn_info.path[i].device_tag =
2468                         le16_to_cpu(
2469                                 info_v11->extdispconninfo.path[i].device_tag);
2470                 info->ext_disp_conn_info.path[i].device_acpi_enum =
2471                 le16_to_cpu(
2472                         info_v11->extdispconninfo.path[i].device_acpi_enum);
2473                 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2474                         info_v11->extdispconninfo.path[i].auxddclut_index;
2475                 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2476                         info_v11->extdispconninfo.path[i].hpdlut_index;
2477                 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2478                         info_v11->extdispconninfo.path[i].channelmapping;
2479                 info->ext_disp_conn_info.path[i].caps =
2480                                 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
2481         }
2482         info->ext_disp_conn_info.checksum =
2483         info_v11->extdispconninfo.checksum;
2484
2485         info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
2486         info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
2487         for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2488                 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2489                                 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2490                 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2491                                 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2492         }
2493         info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
2494         for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2495                 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2496                                 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2497                 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2498                                 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2499         }
2500
2501         info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
2502         info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
2503         for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2504                 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2505                                 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2506                 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2507                                 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2508         }
2509         info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
2510         for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2511                 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2512                                 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2513                 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2514                                 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2515         }
2516
2517         info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
2518         info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
2519         for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2520                 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2521                                 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2522                 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2523                                 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2524         }
2525         info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
2526         for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2527                 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2528                                 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2529                 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2530                                 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2531         }
2532
2533         info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
2534         info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
2535         for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2536                 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2537                                 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2538                 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2539                                 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2540         }
2541         info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
2542         for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2543                 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2544                                 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2545                 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2546                                 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2547         }
2548
2549
2550         /** TODO - review **/
2551         #if 0
2552         info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
2553                                                                         * 10;
2554         info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
2555         info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
2556
2557         for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
2558                 /* Convert [10KHz] into [KHz] */
2559                 info->disp_clk_voltage[i].max_supported_clk =
2560                 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
2561                         ulMaximumSupportedCLK) * 10;
2562                 info->disp_clk_voltage[i].voltage_index =
2563                 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
2564         }
2565
2566         info->boot_up_req_display_vector =
2567                         le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
2568         info->boot_up_nb_voltage =
2569                         le16_to_cpu(info_v11->usBootUpNBVoltage);
2570         info->ext_disp_conn_info_offset =
2571                         le16_to_cpu(info_v11->usExtDispConnInfoOffset);
2572         info->gmc_restore_reset_time =
2573                         le32_to_cpu(info_v11->ulGMCRestoreResetTime);
2574         info->minimum_n_clk =
2575                         le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
2576         for (i = 1; i < 4; ++i)
2577                 info->minimum_n_clk =
2578                                 info->minimum_n_clk <
2579                                 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
2580                                 info->minimum_n_clk : le32_to_cpu(
2581                                         info_v11->ulNbpStateNClkFreq[i]);
2582
2583         info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
2584         info->ddr_dll_power_up_time =
2585             le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
2586         info->ddr_pll_power_up_time =
2587                 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
2588         info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
2589         info->max_lvds_pclk_freq_in_single_link =
2590                 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2591         info->max_lvds_pclk_freq_in_single_link =
2592                 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2593         info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
2594                 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
2595         info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
2596                 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
2597         info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
2598                 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
2599         info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
2600                 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
2601         info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
2602                 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
2603         info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
2604                 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
2605         info->lvds_off_to_on_delay_in_4ms =
2606                 info_v11->ucLVDSOffToOnDelay_in4Ms;
2607         info->lvds_bit_depth_control_val =
2608                 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
2609
2610         for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
2611                 /* Convert [10KHz] into [KHz] */
2612                 info->avail_s_clk[i].supported_s_clk =
2613                         le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
2614                                                                         * 10;
2615                 info->avail_s_clk[i].voltage_index =
2616                         le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
2617                 info->avail_s_clk[i].voltage_id =
2618                         le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
2619         }
2620         #endif /* TODO*/
2621
2622         return BP_RESULT_OK;
2623 }
2624
2625 static enum bp_result get_integrated_info_v2_1(
2626         struct bios_parser *bp,
2627         struct integrated_info *info)
2628 {
2629         struct atom_integrated_system_info_v2_1 *info_v2_1;
2630         uint32_t i;
2631
2632         info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
2633                                         DATA_TABLES(integratedsysteminfo));
2634         DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage);
2635
2636         if (info_v2_1 == NULL)
2637                 return BP_RESULT_BADBIOSTABLE;
2638
2639         info->gpu_cap_info =
2640         le32_to_cpu(info_v2_1->gpucapinfo);
2641         /*
2642         * system_config: Bit[0] = 0 : PCIE power gating disabled
2643         *                       = 1 : PCIE power gating enabled
2644         *                Bit[1] = 0 : DDR-PLL shut down disabled
2645         *                       = 1 : DDR-PLL shut down enabled
2646         *                Bit[2] = 0 : DDR-PLL power down disabled
2647         *                       = 1 : DDR-PLL power down enabled
2648         */
2649         info->system_config = le32_to_cpu(info_v2_1->system_config);
2650         info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
2651         info->memory_type = info_v2_1->memorytype;
2652         info->ma_channel_number = info_v2_1->umachannelnumber;
2653         info->dp_ss_control =
2654                 le16_to_cpu(info_v2_1->reserved1);
2655
2656         for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2657                 info->ext_disp_conn_info.gu_id[i] =
2658                                 info_v2_1->extdispconninfo.guid[i];
2659         }
2660
2661         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2662                 info->ext_disp_conn_info.path[i].device_connector_id =
2663                 object_id_from_bios_object_id(
2664                 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
2665
2666                 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2667                 object_id_from_bios_object_id(
2668                         le16_to_cpu(
2669                         info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
2670
2671                 info->ext_disp_conn_info.path[i].device_tag =
2672                         le16_to_cpu(
2673                                 info_v2_1->extdispconninfo.path[i].device_tag);
2674                 info->ext_disp_conn_info.path[i].device_acpi_enum =
2675                 le16_to_cpu(
2676                         info_v2_1->extdispconninfo.path[i].device_acpi_enum);
2677                 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2678                         info_v2_1->extdispconninfo.path[i].auxddclut_index;
2679                 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2680                         info_v2_1->extdispconninfo.path[i].hpdlut_index;
2681                 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2682                         info_v2_1->extdispconninfo.path[i].channelmapping;
2683                 info->ext_disp_conn_info.path[i].caps =
2684                                 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
2685         }
2686
2687         info->ext_disp_conn_info.checksum =
2688                 info_v2_1->extdispconninfo.checksum;
2689         info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
2690         info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
2691         for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2692                 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2693                                 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2694                 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2695                                 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2696         }
2697         info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
2698         for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2699                 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2700                                 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2701                 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2702                                 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2703         }
2704         info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
2705         info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
2706         for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2707                 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2708                                 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2709                 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2710                                 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2711         }
2712         info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
2713         for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2714                 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2715                                 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2716                 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2717                                 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2718         }
2719         info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
2720         info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
2721         for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2722                 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2723                                 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2724                 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2725                                 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2726         }
2727         info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
2728         for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2729                 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2730                                 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2731                 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2732                                 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2733         }
2734         info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
2735         info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
2736         for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2737                 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2738                                 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2739                 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2740                                 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2741         }
2742         info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
2743         for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2744                 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2745                                 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2746                 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2747                                 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2748         }
2749
2750         info->edp1_info.edp_backlight_pwm_hz =
2751         le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
2752         info->edp1_info.edp_ss_percentage =
2753         le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
2754         info->edp1_info.edp_ss_rate_10hz =
2755         le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
2756         info->edp1_info.edp_pwr_on_off_delay =
2757                 info_v2_1->edp1_info.edp_pwr_on_off_delay;
2758         info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2759                 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
2760         info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2761                 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2762         info->edp1_info.edp_panel_bpc =
2763                 info_v2_1->edp1_info.edp_panel_bpc;
2764         info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level;
2765
2766         info->edp2_info.edp_backlight_pwm_hz =
2767         le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
2768         info->edp2_info.edp_ss_percentage =
2769         le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
2770         info->edp2_info.edp_ss_rate_10hz =
2771         le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
2772         info->edp2_info.edp_pwr_on_off_delay =
2773                 info_v2_1->edp2_info.edp_pwr_on_off_delay;
2774         info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2775                 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
2776         info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2777                 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2778         info->edp2_info.edp_panel_bpc =
2779                 info_v2_1->edp2_info.edp_panel_bpc;
2780         info->edp2_info.edp_bootup_bl_level =
2781                 info_v2_1->edp2_info.edp_bootup_bl_level;
2782
2783         return BP_RESULT_OK;
2784 }
2785
2786 static enum bp_result get_integrated_info_v2_2(
2787         struct bios_parser *bp,
2788         struct integrated_info *info)
2789 {
2790         struct atom_integrated_system_info_v2_2 *info_v2_2;
2791         uint32_t i;
2792
2793         info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
2794                                         DATA_TABLES(integratedsysteminfo));
2795
2796         DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage);
2797
2798         if (info_v2_2 == NULL)
2799                 return BP_RESULT_BADBIOSTABLE;
2800
2801         info->gpu_cap_info =
2802         le32_to_cpu(info_v2_2->gpucapinfo);
2803         /*
2804         * system_config: Bit[0] = 0 : PCIE power gating disabled
2805         *                       = 1 : PCIE power gating enabled
2806         *                Bit[1] = 0 : DDR-PLL shut down disabled
2807         *                       = 1 : DDR-PLL shut down enabled
2808         *                Bit[2] = 0 : DDR-PLL power down disabled
2809         *                       = 1 : DDR-PLL power down enabled
2810         */
2811         info->system_config = le32_to_cpu(info_v2_2->system_config);
2812         info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo);
2813         info->memory_type = info_v2_2->memorytype;
2814         info->ma_channel_number = info_v2_2->umachannelnumber;
2815         info->dp_ss_control =
2816                 le16_to_cpu(info_v2_2->reserved1);
2817
2818         for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2819                 info->ext_disp_conn_info.gu_id[i] =
2820                                 info_v2_2->extdispconninfo.guid[i];
2821         }
2822
2823         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2824                 info->ext_disp_conn_info.path[i].device_connector_id =
2825                 object_id_from_bios_object_id(
2826                 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid));
2827
2828                 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2829                 object_id_from_bios_object_id(
2830                         le16_to_cpu(
2831                         info_v2_2->extdispconninfo.path[i].ext_encoder_objid));
2832
2833                 info->ext_disp_conn_info.path[i].device_tag =
2834                         le16_to_cpu(
2835                                 info_v2_2->extdispconninfo.path[i].device_tag);
2836                 info->ext_disp_conn_info.path[i].device_acpi_enum =
2837                 le16_to_cpu(
2838                         info_v2_2->extdispconninfo.path[i].device_acpi_enum);
2839                 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2840                         info_v2_2->extdispconninfo.path[i].auxddclut_index;
2841                 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2842                         info_v2_2->extdispconninfo.path[i].hpdlut_index;
2843                 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2844                         info_v2_2->extdispconninfo.path[i].channelmapping;
2845                 info->ext_disp_conn_info.path[i].caps =
2846                                 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
2847         }
2848
2849         info->ext_disp_conn_info.checksum =
2850                 info_v2_2->extdispconninfo.checksum;
2851         info->ext_disp_conn_info.fixdpvoltageswing =
2852                 info_v2_2->extdispconninfo.fixdpvoltageswing;
2853
2854         info->edp1_info.edp_backlight_pwm_hz =
2855         le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);
2856         info->edp1_info.edp_ss_percentage =
2857         le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage);
2858         info->edp1_info.edp_ss_rate_10hz =
2859         le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz);
2860         info->edp1_info.edp_pwr_on_off_delay =
2861                 info_v2_2->edp1_info.edp_pwr_on_off_delay;
2862         info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2863                 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon;
2864         info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2865                 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2866         info->edp1_info.edp_panel_bpc =
2867                 info_v2_2->edp1_info.edp_panel_bpc;
2868         info->edp1_info.edp_bootup_bl_level =
2869
2870         info->edp2_info.edp_backlight_pwm_hz =
2871         le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
2872         info->edp2_info.edp_ss_percentage =
2873         le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage);
2874         info->edp2_info.edp_ss_rate_10hz =
2875         le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz);
2876         info->edp2_info.edp_pwr_on_off_delay =
2877                 info_v2_2->edp2_info.edp_pwr_on_off_delay;
2878         info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2879                 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon;
2880         info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2881                 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2882         info->edp2_info.edp_panel_bpc =
2883                 info_v2_2->edp2_info.edp_panel_bpc;
2884         info->edp2_info.edp_bootup_bl_level =
2885                 info_v2_2->edp2_info.edp_bootup_bl_level;
2886
2887         return BP_RESULT_OK;
2888 }
2889
2890 /*
2891  * construct_integrated_info
2892  *
2893  * @brief
2894  * Get integrated BIOS information based on table revision
2895  *
2896  * @param
2897  * bios_parser *bp - [in]BIOS parser handler to get master data table
2898  * integrated_info *info - [out] store and output integrated info
2899  *
2900  * @return
2901  * static enum bp_result - BP_RESULT_OK if information is available,
2902  *                  BP_RESULT_BADBIOSTABLE otherwise.
2903  */
2904 static enum bp_result construct_integrated_info(
2905         struct bios_parser *bp,
2906         struct integrated_info *info)
2907 {
2908         static enum bp_result result = BP_RESULT_BADBIOSTABLE;
2909
2910         struct atom_common_table_header *header;
2911         struct atom_data_revision revision;
2912
2913         uint32_t i;
2914         uint32_t j;
2915
2916         if (info && DATA_TABLES(integratedsysteminfo)) {
2917                 header = GET_IMAGE(struct atom_common_table_header,
2918                                         DATA_TABLES(integratedsysteminfo));
2919
2920                 get_atom_data_table_revision(header, &revision);
2921
2922                 switch (revision.major) {
2923                 case 1:
2924                         switch (revision.minor) {
2925                         case 11:
2926                         case 12:
2927                                 result = get_integrated_info_v11(bp, info);
2928                                 break;
2929                         default:
2930                                 return result;
2931                         }
2932                         break;
2933                 case 2:
2934                         switch (revision.minor) {
2935                         case 1:
2936                                 result = get_integrated_info_v2_1(bp, info);
2937                                 break;
2938                         case 2:
2939                                 result = get_integrated_info_v2_2(bp, info);
2940                                 break;
2941                         default:
2942                                 return result;
2943                         }
2944                         break;
2945                 default:
2946                         return result;
2947                 }
2948                 if (result == BP_RESULT_OK) {
2949
2950                         DC_LOG_BIOS("edp1:\n"
2951                                                 "\tedp_pwr_on_off_delay = %d\n"
2952                                                 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
2953                                                 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
2954                                                 "\tedp_bootup_bl_level = %d\n",
2955                                                 info->edp1_info.edp_pwr_on_off_delay,
2956                                                 info->edp1_info.edp_pwr_on_vary_bl_to_blon,
2957                                                 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff,
2958                                                 info->edp1_info.edp_bootup_bl_level);
2959                         DC_LOG_BIOS("edp2:\n"
2960                                                 "\tedp_pwr_on_off_delayv = %d\n"
2961                                                 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
2962                                                 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
2963                                                 "\tedp_bootup_bl_level = %d\n",
2964                                                 info->edp2_info.edp_pwr_on_off_delay,
2965                                                 info->edp2_info.edp_pwr_on_vary_bl_to_blon,
2966                                                 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff,
2967                                                 info->edp2_info.edp_bootup_bl_level);
2968                 }
2969         }
2970
2971         if (result != BP_RESULT_OK)
2972                 return result;
2973         else {
2974                 // Log each external path
2975                 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
2976                         if (info->ext_disp_conn_info.path[i].device_tag != 0)
2977                                 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n"
2978                                                 "DEVICE_TAG: 0x%x\n"
2979                                                 "DEVICE_ACPI_ENUM: 0x%x\n"
2980                                                 "DEVICE_CONNECTOR_ID: 0x%x\n"
2981                                                 "EXT_AUX_DDC_LUT_INDEX: %d\n"
2982                                                 "EXT_HPD_PIN_LUT_INDEX: %d\n"
2983                                                 "EXT_ENCODER_OBJ_ID: 0x%x\n"
2984                                                 "Encoder CAPS: 0x%x\n",
2985                                                 i,
2986                                                 info->ext_disp_conn_info.path[i].device_tag,
2987                                                 info->ext_disp_conn_info.path[i].device_acpi_enum,
2988                                                 info->ext_disp_conn_info.path[i].device_connector_id.id,
2989                                                 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index,
2990                                                 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index,
2991                                                 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id,
2992                                                 info->ext_disp_conn_info.path[i].caps
2993                                                 );
2994                         if (info->ext_disp_conn_info.path[i].caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
2995                                 DC_LOG_BIOS("BIOS EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
2996                         else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {
2997                                 info->ext_disp_conn_info.path[i].caps |= EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;
2998                                 DC_LOG_BIOS("driver forced EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
2999                         }
3000                 }
3001                 // Log the Checksum and Voltage Swing
3002                 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n"
3003                                         "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n",
3004                                         info->ext_disp_conn_info.checksum,
3005                                         info->ext_disp_conn_info.fixdpvoltageswing);
3006                 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {
3007                         info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;
3008                         DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing);
3009                 }
3010         }
3011         /* Sort voltage table from low to high*/
3012         for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
3013                 for (j = i; j > 0; --j) {
3014                         if (info->disp_clk_voltage[j].max_supported_clk <
3015                             info->disp_clk_voltage[j-1].max_supported_clk)
3016                                 swap(info->disp_clk_voltage[j-1], info->disp_clk_voltage[j]);
3017                 }
3018         }
3019
3020         return result;
3021 }
3022
3023 static enum bp_result bios_parser_get_vram_info(
3024                 struct dc_bios *dcb,
3025                 struct dc_vram_info *info)
3026 {
3027         struct bios_parser *bp = BP_FROM_DCB(dcb);
3028         static enum bp_result result = BP_RESULT_BADBIOSTABLE;
3029         struct atom_common_table_header *header;
3030         struct atom_data_revision revision;
3031
3032         if (info && DATA_TABLES(vram_info)) {
3033                 header = GET_IMAGE(struct atom_common_table_header,
3034                                         DATA_TABLES(vram_info));
3035
3036                 get_atom_data_table_revision(header, &revision);
3037
3038                 switch (revision.major) {
3039                 case 2:
3040                         switch (revision.minor) {
3041                         case 3:
3042                                 result = get_vram_info_v23(bp, info);
3043                                 break;
3044                         case 4:
3045                                 result = get_vram_info_v24(bp, info);
3046                                 break;
3047                         case 5:
3048                                 result = get_vram_info_v25(bp, info);
3049                                 break;
3050                         default:
3051                                 break;
3052                         }
3053                         break;
3054
3055                 case 3:
3056                         switch (revision.minor) {
3057                         case 0:
3058                                 result = get_vram_info_v30(bp, info);
3059                                 break;
3060                         default:
3061                                 break;
3062                         }
3063                         break;
3064
3065                 default:
3066                         return result;
3067                 }
3068
3069         }
3070         return result;
3071 }
3072
3073 static struct integrated_info *bios_parser_create_integrated_info(
3074         struct dc_bios *dcb)
3075 {
3076         struct bios_parser *bp = BP_FROM_DCB(dcb);
3077         struct integrated_info *info;
3078
3079         info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
3080
3081         if (info == NULL) {
3082                 ASSERT_CRITICAL(0);
3083                 return NULL;
3084         }
3085
3086         if (construct_integrated_info(bp, info) == BP_RESULT_OK)
3087                 return info;
3088
3089         kfree(info);
3090
3091         return NULL;
3092 }
3093
3094 static enum bp_result update_slot_layout_info(
3095         struct dc_bios *dcb,
3096         unsigned int i,
3097         struct slot_layout_info *slot_layout_info)
3098 {
3099         unsigned int record_offset;
3100         unsigned int j;
3101         struct atom_display_object_path_v2 *object;
3102         struct atom_bracket_layout_record *record;
3103         struct atom_common_record_header *record_header;
3104         static enum bp_result result;
3105         struct bios_parser *bp;
3106         struct object_info_table *tbl;
3107         struct display_object_info_table_v1_4 *v1_4;
3108
3109         record = NULL;
3110         record_header = NULL;
3111         result = BP_RESULT_NORECORD;
3112
3113         bp = BP_FROM_DCB(dcb);
3114         tbl = &bp->object_info_tbl;
3115         v1_4 = tbl->v1_4;
3116
3117         object = &v1_4->display_path[i];
3118         record_offset = (unsigned int)
3119                 (object->disp_recordoffset) +
3120                 (unsigned int)(bp->object_info_tbl_offset);
3121
3122         for (;;) {
3123
3124                 record_header = (struct atom_common_record_header *)
3125                         GET_IMAGE(struct atom_common_record_header,
3126                         record_offset);
3127                 if (record_header == NULL) {
3128                         result = BP_RESULT_BADBIOSTABLE;
3129                         break;
3130                 }
3131
3132                 /* the end of the list */
3133                 if (record_header->record_type == 0xff ||
3134                         record_header->record_size == 0)        {
3135                         break;
3136                 }
3137
3138                 if (record_header->record_type ==
3139                         ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
3140                         sizeof(struct atom_bracket_layout_record)
3141                         <= record_header->record_size) {
3142                         record = (struct atom_bracket_layout_record *)
3143                                 (record_header);
3144                         result = BP_RESULT_OK;
3145                         break;
3146                 }
3147
3148                 record_offset += record_header->record_size;
3149         }
3150
3151         /* return if the record not found */
3152         if (result != BP_RESULT_OK)
3153                 return result;
3154
3155         /* get slot sizes */
3156         slot_layout_info->length = record->bracketlen;
3157         slot_layout_info->width = record->bracketwidth;
3158
3159         /* get info for each connector in the slot */
3160         slot_layout_info->num_of_connectors = record->conn_num;
3161         for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
3162                 slot_layout_info->connectors[j].connector_type =
3163                         (enum connector_layout_type)
3164                         (record->conn_info[j].connector_type);
3165                 switch (record->conn_info[j].connector_type) {
3166                 case CONNECTOR_TYPE_DVI_D:
3167                         slot_layout_info->connectors[j].connector_type =
3168                                 CONNECTOR_LAYOUT_TYPE_DVI_D;
3169                         slot_layout_info->connectors[j].length =
3170                                 CONNECTOR_SIZE_DVI;
3171                         break;
3172
3173                 case CONNECTOR_TYPE_HDMI:
3174                         slot_layout_info->connectors[j].connector_type =
3175                                 CONNECTOR_LAYOUT_TYPE_HDMI;
3176                         slot_layout_info->connectors[j].length =
3177                                 CONNECTOR_SIZE_HDMI;
3178                         break;
3179
3180                 case CONNECTOR_TYPE_DISPLAY_PORT:
3181                         slot_layout_info->connectors[j].connector_type =
3182                                 CONNECTOR_LAYOUT_TYPE_DP;
3183                         slot_layout_info->connectors[j].length =
3184                                 CONNECTOR_SIZE_DP;
3185                         break;
3186
3187                 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
3188                         slot_layout_info->connectors[j].connector_type =
3189                                 CONNECTOR_LAYOUT_TYPE_MINI_DP;
3190                         slot_layout_info->connectors[j].length =
3191                                 CONNECTOR_SIZE_MINI_DP;
3192                         break;
3193
3194                 default:
3195                         slot_layout_info->connectors[j].connector_type =
3196                                 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3197                         slot_layout_info->connectors[j].length =
3198                                 CONNECTOR_SIZE_UNKNOWN;
3199                 }
3200
3201                 slot_layout_info->connectors[j].position =
3202                         record->conn_info[j].position;
3203                 slot_layout_info->connectors[j].connector_id =
3204                         object_id_from_bios_object_id(
3205                                 record->conn_info[j].connectorobjid);
3206         }
3207         return result;
3208 }
3209
3210 static enum bp_result update_slot_layout_info_v2(
3211         struct dc_bios *dcb,
3212         unsigned int i,
3213         struct slot_layout_info *slot_layout_info)
3214 {
3215         unsigned int record_offset;
3216         struct atom_display_object_path_v3 *object;
3217         struct atom_bracket_layout_record_v2 *record;
3218         struct atom_common_record_header *record_header;
3219         static enum bp_result result;
3220         struct bios_parser *bp;
3221         struct object_info_table *tbl;
3222         struct display_object_info_table_v1_5 *v1_5;
3223         struct graphics_object_id connector_id;
3224
3225         record = NULL;
3226         record_header = NULL;
3227         result = BP_RESULT_NORECORD;
3228
3229         bp = BP_FROM_DCB(dcb);
3230         tbl = &bp->object_info_tbl;
3231         v1_5 = tbl->v1_5;
3232
3233         object = &v1_5->display_path[i];
3234         record_offset = (unsigned int)
3235                 (object->disp_recordoffset) +
3236                 (unsigned int)(bp->object_info_tbl_offset);
3237
3238         for (;;) {
3239
3240                 record_header = (struct atom_common_record_header *)
3241                         GET_IMAGE(struct atom_common_record_header,
3242                         record_offset);
3243                 if (record_header == NULL) {
3244                         result = BP_RESULT_BADBIOSTABLE;
3245                         break;
3246                 }
3247
3248                 /* the end of the list */
3249                 if (record_header->record_type == ATOM_RECORD_END_TYPE ||
3250                         record_header->record_size == 0)        {
3251                         break;
3252                 }
3253
3254                 if (record_header->record_type ==
3255                         ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE &&
3256                         sizeof(struct atom_bracket_layout_record_v2)
3257                         <= record_header->record_size) {
3258                         record = (struct atom_bracket_layout_record_v2 *)
3259                                 (record_header);
3260                         result = BP_RESULT_OK;
3261                         break;
3262                 }
3263
3264                 record_offset += record_header->record_size;
3265         }
3266
3267         /* return if the record not found */
3268         if (result != BP_RESULT_OK)
3269                 return result;
3270
3271         /* get slot sizes */
3272         connector_id = object_id_from_bios_object_id(object->display_objid);
3273
3274         slot_layout_info->length = record->bracketlen;
3275         slot_layout_info->width = record->bracketwidth;
3276         slot_layout_info->num_of_connectors = v1_5->number_of_path;
3277         slot_layout_info->connectors[i].position = record->conn_num;
3278         slot_layout_info->connectors[i].connector_id = connector_id;
3279
3280         switch (connector_id.id) {
3281         case CONNECTOR_ID_SINGLE_LINK_DVID:
3282         case CONNECTOR_ID_DUAL_LINK_DVID:
3283                 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D;
3284                 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI;
3285                 break;
3286
3287         case CONNECTOR_ID_HDMI_TYPE_A:
3288                 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI;
3289                 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI;
3290                 break;
3291
3292         case CONNECTOR_ID_DISPLAY_PORT:
3293         case CONNECTOR_ID_USBC:
3294                 if (record->mini_type == MINI_TYPE_NORMAL) {
3295                         slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
3296                         slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
3297                 } else {
3298                         slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP;
3299                         slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP;
3300                 }
3301                 break;
3302
3303         default:
3304                 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3305                 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN;
3306         }
3307         return result;
3308 }
3309
3310 static enum bp_result get_bracket_layout_record(
3311         struct dc_bios *dcb,
3312         unsigned int bracket_layout_id,
3313         struct slot_layout_info *slot_layout_info)
3314 {
3315         unsigned int i;
3316         struct bios_parser *bp = BP_FROM_DCB(dcb);
3317         static enum bp_result result;
3318         struct object_info_table *tbl;
3319         struct display_object_info_table_v1_4 *v1_4;
3320         struct display_object_info_table_v1_5 *v1_5;
3321
3322         if (slot_layout_info == NULL) {
3323                 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
3324                 return BP_RESULT_BADINPUT;
3325         }
3326         tbl = &bp->object_info_tbl;
3327         v1_4 = tbl->v1_4;
3328         v1_5 = tbl->v1_5;
3329
3330         result = BP_RESULT_NORECORD;
3331         switch (bp->object_info_tbl.revision.minor) {
3332                 case 4:
3333                 default:
3334                         for (i = 0; i < v1_4->number_of_path; ++i)      {
3335                                 if (bracket_layout_id ==
3336                                         v1_4->display_path[i].display_objid) {
3337                                         result = update_slot_layout_info(dcb, i, slot_layout_info);
3338                                         break;
3339                                 }
3340                         }
3341                     break;
3342                 case 5:
3343                         for (i = 0; i < v1_5->number_of_path; ++i)
3344                                 result = update_slot_layout_info_v2(dcb, i, slot_layout_info);
3345                         break;
3346         }
3347         return result;
3348 }
3349
3350 static enum bp_result bios_get_board_layout_info(
3351         struct dc_bios *dcb,
3352         struct board_layout_info *board_layout_info)
3353 {
3354         unsigned int i;
3355
3356         struct bios_parser *bp;
3357
3358         static enum bp_result record_result;
3359         unsigned int max_slots;
3360
3361         const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
3362                 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
3363                 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
3364                 0, 0
3365         };
3366
3367
3368         bp = BP_FROM_DCB(dcb);
3369
3370         if (board_layout_info == NULL) {
3371                 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
3372                 return BP_RESULT_BADINPUT;
3373         }
3374
3375         board_layout_info->num_of_slots = 0;
3376         max_slots = MAX_BOARD_SLOTS;
3377
3378         // Assume single slot on v1_5
3379         if (bp->object_info_tbl.revision.minor == 5) {
3380                 max_slots = 1;
3381         }
3382
3383         for (i = 0; i < max_slots; ++i) {
3384                 record_result = get_bracket_layout_record(dcb,
3385                         slot_index_to_vbios_id[i],
3386                         &board_layout_info->slots[i]);
3387
3388                 if (record_result == BP_RESULT_NORECORD && i > 0)
3389                         break; /* no more slots present in bios */
3390                 else if (record_result != BP_RESULT_OK)
3391                         return record_result;  /* fail */
3392
3393                 ++board_layout_info->num_of_slots;
3394         }
3395
3396         /* all data is valid */
3397         board_layout_info->is_number_of_slots_valid = 1;
3398         board_layout_info->is_slots_size_valid = 1;
3399         board_layout_info->is_connector_offsets_valid = 1;
3400         board_layout_info->is_connector_lengths_valid = 1;
3401
3402         return BP_RESULT_OK;
3403 }
3404
3405
3406 static uint16_t bios_parser_pack_data_tables(
3407         struct dc_bios *dcb,
3408         void *dst)
3409 {
3410         // TODO: There is data bytes alignment issue, disable it for now.
3411         return 0;
3412 }
3413
3414 static struct atom_dc_golden_table_v1 *bios_get_golden_table(
3415                 struct bios_parser *bp,
3416                 uint32_t rev_major,
3417                 uint32_t rev_minor,
3418                 uint16_t *dc_golden_table_ver)
3419 {
3420         struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;
3421         uint32_t dc_golden_offset = 0;
3422         *dc_golden_table_ver = 0;
3423
3424         if (!DATA_TABLES(dce_info))
3425                 return NULL;
3426
3427         /* ver.4.4 or higher */
3428         switch (rev_major) {
3429         case 4:
3430                 switch (rev_minor) {
3431                 case 4:
3432                         disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
3433                                                                         DATA_TABLES(dce_info));
3434                         if (!disp_cntl_tbl_4_4)
3435                                 return NULL;
3436                         dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
3437                         *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
3438                         break;
3439                 case 5:
3440                 default:
3441                         /* For atom_display_controller_info_v4_5 there is no need to get golden table from
3442                          * dc_golden_table_offset as all these fields previously in golden table used for AUX
3443                          * pre-charge settings are now available directly in atom_display_controller_info_v4_5.
3444                          */
3445                         break;
3446                 }
3447                 break;
3448         }
3449
3450         if (!dc_golden_offset)
3451                 return NULL;
3452
3453         if (*dc_golden_table_ver != 1)
3454                 return NULL;
3455
3456         return GET_IMAGE(struct atom_dc_golden_table_v1,
3457                         dc_golden_offset);
3458 }
3459
3460 static enum bp_result bios_get_atom_dc_golden_table(
3461         struct dc_bios *dcb)
3462 {
3463         struct bios_parser *bp = BP_FROM_DCB(dcb);
3464         enum bp_result result = BP_RESULT_OK;
3465         struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;
3466         struct atom_common_table_header *header;
3467         struct atom_data_revision tbl_revision;
3468         uint16_t dc_golden_table_ver = 0;
3469
3470         header = GET_IMAGE(struct atom_common_table_header,
3471                                                         DATA_TABLES(dce_info));
3472         if (!header)
3473                 return BP_RESULT_UNSUPPORTED;
3474
3475         get_atom_data_table_revision(header, &tbl_revision);
3476
3477         atom_dc_golden_table = bios_get_golden_table(bp,
3478                         tbl_revision.major,
3479                         tbl_revision.minor,
3480                         &dc_golden_table_ver);
3481
3482         if (!atom_dc_golden_table)
3483                 return BP_RESULT_UNSUPPORTED;
3484
3485         dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;
3486         dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;
3487         dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;
3488         dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;
3489         dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;
3490         dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;
3491         dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;
3492         dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;
3493         dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;
3494         dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;
3495
3496         return result;
3497 }
3498
3499
3500 static const struct dc_vbios_funcs vbios_funcs = {
3501         .get_connectors_number = bios_parser_get_connectors_number,
3502
3503         .get_connector_id = bios_parser_get_connector_id,
3504
3505         .get_src_obj = bios_parser_get_src_obj,
3506
3507         .get_i2c_info = bios_parser_get_i2c_info,
3508
3509         .get_hpd_info = bios_parser_get_hpd_info,
3510
3511         .get_device_tag = bios_parser_get_device_tag,
3512
3513         .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
3514
3515         .get_ss_entry_number = bios_parser_get_ss_entry_number,
3516
3517         .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
3518
3519         .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
3520
3521         .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
3522
3523         .is_device_id_supported = bios_parser_is_device_id_supported,
3524
3525         .is_accelerated_mode = bios_parser_is_accelerated_mode,
3526
3527         .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
3528
3529
3530 /*       COMMANDS */
3531         .encoder_control = bios_parser_encoder_control,
3532
3533         .transmitter_control = bios_parser_transmitter_control,
3534
3535         .enable_crtc = bios_parser_enable_crtc,
3536
3537         .set_pixel_clock = bios_parser_set_pixel_clock,
3538
3539         .set_dce_clock = bios_parser_set_dce_clock,
3540
3541         .program_crtc_timing = bios_parser_program_crtc_timing,
3542
3543         .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
3544
3545         .bios_parser_destroy = firmware_parser_destroy,
3546
3547         .get_board_layout_info = bios_get_board_layout_info,
3548         /* TODO: use this fn in hw init?*/
3549         .pack_data_tables = bios_parser_pack_data_tables,
3550
3551         .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
3552
3553         .enable_lvtma_control = bios_parser_enable_lvtma_control,
3554
3555         .get_soc_bb_info = bios_parser_get_soc_bb_info,
3556
3557         .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
3558
3559         .get_lttpr_caps = bios_parser_get_lttpr_caps,
3560
3561         .get_lttpr_interop = bios_parser_get_lttpr_interop,
3562
3563         .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info,
3564 };
3565
3566 static bool bios_parser2_construct(
3567         struct bios_parser *bp,
3568         struct bp_init_data *init,
3569         enum dce_version dce_version)
3570 {
3571         uint16_t *rom_header_offset = NULL;
3572         struct atom_rom_header_v2_2 *rom_header = NULL;
3573         struct display_object_info_table_v1_4 *object_info_tbl;
3574         struct atom_data_revision tbl_rev = {0};
3575
3576         if (!init)
3577                 return false;
3578
3579         if (!init->bios)
3580                 return false;
3581
3582         bp->base.funcs = &vbios_funcs;
3583         bp->base.bios = init->bios;
3584         bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
3585
3586         bp->base.ctx = init->ctx;
3587
3588         bp->base.bios_local_image = NULL;
3589
3590         rom_header_offset =
3591                         GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
3592
3593         if (!rom_header_offset)
3594                 return false;
3595
3596         rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
3597
3598         if (!rom_header)
3599                 return false;
3600
3601         get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
3602         if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
3603                 return false;
3604
3605         bp->master_data_tbl =
3606                 GET_IMAGE(struct atom_master_data_table_v2_1,
3607                                 rom_header->masterdatatable_offset);
3608
3609         if (!bp->master_data_tbl)
3610                 return false;
3611
3612         bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
3613
3614         if (!bp->object_info_tbl_offset)
3615                 return false;
3616
3617         object_info_tbl =
3618                         GET_IMAGE(struct display_object_info_table_v1_4,
3619                                                 bp->object_info_tbl_offset);
3620
3621         if (!object_info_tbl)
3622                 return false;
3623
3624         get_atom_data_table_revision(&object_info_tbl->table_header,
3625                 &bp->object_info_tbl.revision);
3626
3627         if (bp->object_info_tbl.revision.major == 1
3628                 && bp->object_info_tbl.revision.minor == 4) {
3629                 struct display_object_info_table_v1_4 *tbl_v1_4;
3630
3631                 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
3632                         bp->object_info_tbl_offset);
3633                 if (!tbl_v1_4)
3634                         return false;
3635
3636                 bp->object_info_tbl.v1_4 = tbl_v1_4;
3637         } else if (bp->object_info_tbl.revision.major == 1
3638                 && bp->object_info_tbl.revision.minor == 5) {
3639                 struct display_object_info_table_v1_5 *tbl_v1_5;
3640
3641                 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5,
3642                         bp->object_info_tbl_offset);
3643                 if (!tbl_v1_5)
3644                         return false;
3645
3646                 bp->object_info_tbl.v1_5 = tbl_v1_5;
3647         } else {
3648                 ASSERT(0);
3649                 return false;
3650         }
3651
3652         dal_firmware_parser_init_cmd_tbl(bp);
3653         dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
3654
3655         bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
3656         bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
3657         bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
3658
3659         return true;
3660 }
3661
3662 struct dc_bios *firmware_parser_create(
3663         struct bp_init_data *init,
3664         enum dce_version dce_version)
3665 {
3666         struct bios_parser *bp;
3667
3668         bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
3669         if (!bp)
3670                 return NULL;
3671
3672         if (bios_parser2_construct(bp, init, dce_version))
3673                 return &bp->base;
3674
3675         kfree(bp);
3676         return NULL;
3677 }
3678
3679