drivers/gpu/drm/amd/amdgpu/vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/slab.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_atombios.h"
  27 #include "amdgpu_ih.h"
  28 #include "amdgpu_uvd.h"
  29 #include "amdgpu_vce.h"
  30 #include "amdgpu_ucode.h"
  31 #include "atom.h"
  32 #include "amd_pcie.h"
  33
  34 #include "gmc/gmc_8_1_d.h"
  35 #include "gmc/gmc_8_1_sh_mask.h"
  36
  37 #include "oss/oss_3_0_d.h"
  38 #include "oss/oss_3_0_sh_mask.h"
  39
  40 #include "bif/bif_5_0_d.h"
  41 #include "bif/bif_5_0_sh_mask.h"
  42
  43 #include "gca/gfx_8_0_d.h"
  44 #include "gca/gfx_8_0_sh_mask.h"
  45
  46 #include "smu/smu_7_1_1_d.h"
  47 #include "smu/smu_7_1_1_sh_mask.h"
  48
  49 #include "uvd/uvd_5_0_d.h"
  50 #include "uvd/uvd_5_0_sh_mask.h"
  51
  52 #include "vce/vce_3_0_d.h"
  53 #include "vce/vce_3_0_sh_mask.h"
  54
  55 #include "dce/dce_10_0_d.h"
  56 #include "dce/dce_10_0_sh_mask.h"
  57
  58 #include "vid.h"
  59 #include "vi.h"
  60 #include "vi_dpm.h"
  61 #include "gmc_v8_0.h"
  62 #include "gmc_v7_0.h"
  63 #include "gfx_v8_0.h"
  64 #include "sdma_v2_4.h"
  65 #include "sdma_v3_0.h"
  66 #include "dce_v10_0.h"
  67 #include "dce_v11_0.h"
  68 #include "iceland_ih.h"
  69 #include "tonga_ih.h"
  70 #include "cz_ih.h"
  71 #include "uvd_v5_0.h"
  72 #include "uvd_v6_0.h"
  73 #include "vce_v3_0.h"
  74 #if defined(CONFIG_DRM_AMD_ACP)
  75 #include "amdgpu_acp.h"
  76 #endif
  77 #include "dce_virtual.h"
  78 #include "mxgpu_vi.h"
  79 #include "amdgpu_dm.h"
  80
  81 /*
  82  * Indirect registers accessor
  83  */
  84 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  85 {
  86         unsigned long flags;
  87         u32 r;
  88
  89         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  90         WREG32(mmPCIE_INDEX, reg);
  91         (void)RREG32(mmPCIE_INDEX);
  92         r = RREG32(mmPCIE_DATA);
  93         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  94         return r;
  95 }
  96
  97 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  98 {
  99         unsigned long flags;
 100
 101         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 102         WREG32(mmPCIE_INDEX, reg);
 103         (void)RREG32(mmPCIE_INDEX);
 104         WREG32(mmPCIE_DATA, v);
 105         (void)RREG32(mmPCIE_DATA);
 106         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 107 }
 108
 109 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
 110 {
 111         unsigned long flags;
 112         u32 r;
 113
 114         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 115         WREG32(mmSMC_IND_INDEX_11, (reg));
 116         r = RREG32(mmSMC_IND_DATA_11);
 117         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 118         return r;
 119 }
 120
 121 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 122 {
 123         unsigned long flags;
 124
 125         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 126         WREG32(mmSMC_IND_INDEX_11, (reg));
 127         WREG32(mmSMC_IND_DATA_11, (v));
 128         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 129 }
 130
 131 /* smu_8_0_d.h */
 132 #define mmMP0PUB_IND_INDEX                                                      0x180
 133 #define mmMP0PUB_IND_DATA                                                       0x181
 134
 135 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
 136 {
 137         unsigned long flags;
 138         u32 r;
 139
 140         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 141         WREG32(mmMP0PUB_IND_INDEX, (reg));
 142         r = RREG32(mmMP0PUB_IND_DATA);
 143         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 144         return r;
 145 }
 146
 147 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 148 {
 149         unsigned long flags;
 150
 151         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 152         WREG32(mmMP0PUB_IND_INDEX, (reg));
 153         WREG32(mmMP0PUB_IND_DATA, (v));
 154         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 155 }
 156
 157 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 158 {
 159         unsigned long flags;
 160         u32 r;
 161
 162         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 163         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 164         r = RREG32(mmUVD_CTX_DATA);
 165         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 166         return r;
 167 }
 168
 169 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 170 {
 171         unsigned long flags;
 172
 173         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 174         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 175         WREG32(mmUVD_CTX_DATA, (v));
 176         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 177 }
 178
 179 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
 180 {
 181         unsigned long flags;
 182         u32 r;
 183
 184         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 185         WREG32(mmDIDT_IND_INDEX, (reg));
 186         r = RREG32(mmDIDT_IND_DATA);
 187         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 188         return r;
 189 }
 190
 191 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 192 {
 193         unsigned long flags;
 194
 195         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 196         WREG32(mmDIDT_IND_INDEX, (reg));
 197         WREG32(mmDIDT_IND_DATA, (v));
 198         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 199 }
 200
 201 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 202 {
 203         unsigned long flags;
 204         u32 r;
 205
 206         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 207         WREG32(mmGC_CAC_IND_INDEX, (reg));
 208         r = RREG32(mmGC_CAC_IND_DATA);
 209         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 210         return r;
 211 }
 212
 213 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 214 {
 215         unsigned long flags;
 216
 217         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 218         WREG32(mmGC_CAC_IND_INDEX, (reg));
 219         WREG32(mmGC_CAC_IND_DATA, (v));
 220         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 221 }
 222
 223
 224 static const u32 tonga_mgcg_cgcg_init[] =
 225 {
 226         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 227         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 228         mmPCIE_DATA, 0x000f0000, 0x00000000,
 229         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 230         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 231         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 232         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 233 };
 234
 235 static const u32 fiji_mgcg_cgcg_init[] =
 236 {
 237         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 238         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 239         mmPCIE_DATA, 0x000f0000, 0x00000000,
 240         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 241         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 242         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 243         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 244 };
 245
 246 static const u32 iceland_mgcg_cgcg_init[] =
 247 {
 248         mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
 249         mmPCIE_DATA, 0x000f0000, 0x00000000,
 250         mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
 251         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 252         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 253 };
 254
 255 static const u32 cz_mgcg_cgcg_init[] =
 256 {
 257         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 258         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 259         mmPCIE_DATA, 0x000f0000, 0x00000000,
 260         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 261         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 262 };
 263
 264 static const u32 stoney_mgcg_cgcg_init[] =
 265 {
 266         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
 267         mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
 268         mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
 269 };
 270
 271 static void vi_init_golden_registers(struct amdgpu_device *adev)
 272 {
 273         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 274         mutex_lock(&adev->grbm_idx_mutex);
 275
 276         if (amdgpu_sriov_vf(adev)) {
 277                 xgpu_vi_init_golden_registers(adev);
 278                 mutex_unlock(&adev->grbm_idx_mutex);
 279                 return;
 280         }
 281
 282         switch (adev->asic_type) {
 283         case CHIP_TOPAZ:
 284                 amdgpu_device_program_register_sequence(adev,
 285                                                         iceland_mgcg_cgcg_init,
 286                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
 287                 break;
 288         case CHIP_FIJI:
 289                 amdgpu_device_program_register_sequence(adev,
 290                                                         fiji_mgcg_cgcg_init,
 291                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 292                 break;
 293         case CHIP_TONGA:
 294                 amdgpu_device_program_register_sequence(adev,
 295                                                         tonga_mgcg_cgcg_init,
 296                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 297                 break;
 298         case CHIP_CARRIZO:
 299                 amdgpu_device_program_register_sequence(adev,
 300                                                         cz_mgcg_cgcg_init,
 301                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 302                 break;
 303         case CHIP_STONEY:
 304                 amdgpu_device_program_register_sequence(adev,
 305                                                         stoney_mgcg_cgcg_init,
 306                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 307                 break;
 308         case CHIP_POLARIS11:
 309         case CHIP_POLARIS10:
 310         case CHIP_POLARIS12:
 311         default:
 312                 break;
 313         }
 314         mutex_unlock(&adev->grbm_idx_mutex);
 315 }
 316
 317 /**
 318  * vi_get_xclk - get the xclk
 319  *
 320  * @adev: amdgpu_device pointer
 321  *
 322  * Returns the reference clock used by the gfx engine
 323  * (VI).
 324  */
 325 static u32 vi_get_xclk(struct amdgpu_device *adev)
 326 {
 327         u32 reference_clock = adev->clock.spll.reference_freq;
 328         u32 tmp;
 329
 330         if (adev->flags & AMD_IS_APU)
 331                 return reference_clock;
 332
 333         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
 334         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
 335                 return 1000;
 336
 337         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
 338         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
 339                 return reference_clock / 4;
 340
 341         return reference_clock;
 342 }
 343
 344 /**
 345  * vi_srbm_select - select specific register instances
 346  *
 347  * @adev: amdgpu_device pointer
 348  * @me: selected ME (micro engine)
 349  * @pipe: pipe
 350  * @queue: queue
 351  * @vmid: VMID
 352  *
 353  * Switches the currently active registers instances.  Some
 354  * registers are instanced per VMID, others are instanced per
 355  * me/pipe/queue combination.
 356  */
 357 void vi_srbm_select(struct amdgpu_device *adev,
 358                      u32 me, u32 pipe, u32 queue, u32 vmid)
 359 {
 360         u32 srbm_gfx_cntl = 0;
 361         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
 362         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
 363         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
 364         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
 365         WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
 366 }
 367
 368 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
 369 {
 370         /* todo */
 371 }
 372
 373 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
 374 {
 375         u32 bus_cntl;
 376         u32 d1vga_control = 0;
 377         u32 d2vga_control = 0;
 378         u32 vga_render_control = 0;
 379         u32 rom_cntl;
 380         bool r;
 381
 382         bus_cntl = RREG32(mmBUS_CNTL);
 383         if (adev->mode_info.num_crtc) {
 384                 d1vga_control = RREG32(mmD1VGA_CONTROL);
 385                 d2vga_control = RREG32(mmD2VGA_CONTROL);
 386                 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 387         }
 388         rom_cntl = RREG32_SMC(ixROM_CNTL);
 389
 390         /* enable the rom */
 391         WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
 392         if (adev->mode_info.num_crtc) {
 393                 /* Disable VGA mode */
 394                 WREG32(mmD1VGA_CONTROL,
 395                        (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 396                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 397                 WREG32(mmD2VGA_CONTROL,
 398                        (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
 399                                           D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
 400                 WREG32(mmVGA_RENDER_CONTROL,
 401                        (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
 402         }
 403         WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
 404
 405         r = amdgpu_read_bios(adev);
 406
 407         /* restore regs */
 408         WREG32(mmBUS_CNTL, bus_cntl);
 409         if (adev->mode_info.num_crtc) {
 410                 WREG32(mmD1VGA_CONTROL, d1vga_control);
 411                 WREG32(mmD2VGA_CONTROL, d2vga_control);
 412                 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
 413         }
 414         WREG32_SMC(ixROM_CNTL, rom_cntl);
 415         return r;
 416 }
 417
 418 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
 419                                   u8 *bios, u32 length_bytes)
 420 {
 421         u32 *dw_ptr;
 422         unsigned long flags;
 423         u32 i, length_dw;
 424
 425         if (bios == NULL)
 426                 return false;
 427         if (length_bytes == 0)
 428                 return false;
 429         /* APU vbios image is part of sbios image */
 430         if (adev->flags & AMD_IS_APU)
 431                 return false;
 432
 433         dw_ptr = (u32 *)bios;
 434         length_dw = ALIGN(length_bytes, 4) / 4;
 435         /* take the smc lock since we are using the smc index */
 436         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 437         /* set rom index to 0 */
 438         WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
 439         WREG32(mmSMC_IND_DATA_11, 0);
 440         /* set index to data for continous read */
 441         WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
 442         for (i = 0; i < length_dw; i++)
 443                 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
 444         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 445
 446         return true;
 447 }
 448
 449 static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
 450 {
 451         uint32_t reg = 0;
 452
 453         if (adev->asic_type == CHIP_TONGA ||
 454             adev->asic_type == CHIP_FIJI) {
 455                reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
 456                /* bit0: 0 means pf and 1 means vf */
 457                if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
 458                        adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 459                /* bit31: 0 means disable IOV and 1 means enable */
 460                if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
 461                        adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 462         }
 463
 464         if (reg == 0) {
 465                 if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
 466                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 467         }
 468 }
 469
 470 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
 471         {mmGRBM_STATUS},
 472         {mmGRBM_STATUS2},
 473         {mmGRBM_STATUS_SE0},
 474         {mmGRBM_STATUS_SE1},
 475         {mmGRBM_STATUS_SE2},
 476         {mmGRBM_STATUS_SE3},
 477         {mmSRBM_STATUS},
 478         {mmSRBM_STATUS2},
 479         {mmSRBM_STATUS3},
 480         {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
 481         {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
 482         {mmCP_STAT},
 483         {mmCP_STALLED_STAT1},
 484         {mmCP_STALLED_STAT2},
 485         {mmCP_STALLED_STAT3},
 486         {mmCP_CPF_BUSY_STAT},
 487         {mmCP_CPF_STALLED_STAT1},
 488         {mmCP_CPF_STATUS},
 489         {mmCP_CPC_BUSY_STAT},
 490         {mmCP_CPC_STALLED_STAT1},
 491         {mmCP_CPC_STATUS},
 492         {mmGB_ADDR_CONFIG},
 493         {mmMC_ARB_RAMCFG},
 494         {mmGB_TILE_MODE0},
 495         {mmGB_TILE_MODE1},
 496         {mmGB_TILE_MODE2},
 497         {mmGB_TILE_MODE3},
 498         {mmGB_TILE_MODE4},
 499         {mmGB_TILE_MODE5},
 500         {mmGB_TILE_MODE6},
 501         {mmGB_TILE_MODE7},
 502         {mmGB_TILE_MODE8},
 503         {mmGB_TILE_MODE9},
 504         {mmGB_TILE_MODE10},
 505         {mmGB_TILE_MODE11},
 506         {mmGB_TILE_MODE12},
 507         {mmGB_TILE_MODE13},
 508         {mmGB_TILE_MODE14},
 509         {mmGB_TILE_MODE15},
 510         {mmGB_TILE_MODE16},
 511         {mmGB_TILE_MODE17},
 512         {mmGB_TILE_MODE18},
 513         {mmGB_TILE_MODE19},
 514         {mmGB_TILE_MODE20},
 515         {mmGB_TILE_MODE21},
 516         {mmGB_TILE_MODE22},
 517         {mmGB_TILE_MODE23},
 518         {mmGB_TILE_MODE24},
 519         {mmGB_TILE_MODE25},
 520         {mmGB_TILE_MODE26},
 521         {mmGB_TILE_MODE27},
 522         {mmGB_TILE_MODE28},
 523         {mmGB_TILE_MODE29},
 524         {mmGB_TILE_MODE30},
 525         {mmGB_TILE_MODE31},
 526         {mmGB_MACROTILE_MODE0},
 527         {mmGB_MACROTILE_MODE1},
 528         {mmGB_MACROTILE_MODE2},
 529         {mmGB_MACROTILE_MODE3},
 530         {mmGB_MACROTILE_MODE4},
 531         {mmGB_MACROTILE_MODE5},
 532         {mmGB_MACROTILE_MODE6},
 533         {mmGB_MACROTILE_MODE7},
 534         {mmGB_MACROTILE_MODE8},
 535         {mmGB_MACROTILE_MODE9},
 536         {mmGB_MACROTILE_MODE10},
 537         {mmGB_MACROTILE_MODE11},
 538         {mmGB_MACROTILE_MODE12},
 539         {mmGB_MACROTILE_MODE13},
 540         {mmGB_MACROTILE_MODE14},
 541         {mmGB_MACROTILE_MODE15},
 542         {mmCC_RB_BACKEND_DISABLE, true},
 543         {mmGC_USER_RB_BACKEND_DISABLE, true},
 544         {mmGB_BACKEND_MAP, false},
 545         {mmPA_SC_RASTER_CONFIG, true},
 546         {mmPA_SC_RASTER_CONFIG_1, true},
 547 };
 548
 549 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
 550                                       bool indexed, u32 se_num,
 551                                       u32 sh_num, u32 reg_offset)
 552 {
 553         if (indexed) {
 554                 uint32_t val;
 555                 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
 556                 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
 557
 558                 switch (reg_offset) {
 559                 case mmCC_RB_BACKEND_DISABLE:
 560                         return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
 561                 case mmGC_USER_RB_BACKEND_DISABLE:
 562                         return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
 563                 case mmPA_SC_RASTER_CONFIG:
 564                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
 565                 case mmPA_SC_RASTER_CONFIG_1:
 566                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
 567                 }
 568
 569                 mutex_lock(&adev->grbm_idx_mutex);
 570                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 571                         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 572
 573                 val = RREG32(reg_offset);
 574
 575                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 576                         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 577                 mutex_unlock(&adev->grbm_idx_mutex);
 578                 return val;
 579         } else {
 580                 unsigned idx;
 581
 582                 switch (reg_offset) {
 583                 case mmGB_ADDR_CONFIG:
 584                         return adev->gfx.config.gb_addr_config;
 585                 case mmMC_ARB_RAMCFG:
 586                         return adev->gfx.config.mc_arb_ramcfg;
 587                 case mmGB_TILE_MODE0:
 588                 case mmGB_TILE_MODE1:
 589                 case mmGB_TILE_MODE2:
 590                 case mmGB_TILE_MODE3:
 591                 case mmGB_TILE_MODE4:
 592                 case mmGB_TILE_MODE5:
 593                 case mmGB_TILE_MODE6:
 594                 case mmGB_TILE_MODE7:
 595                 case mmGB_TILE_MODE8:
 596                 case mmGB_TILE_MODE9:
 597                 case mmGB_TILE_MODE10:
 598                 case mmGB_TILE_MODE11:
 599                 case mmGB_TILE_MODE12:
 600                 case mmGB_TILE_MODE13:
 601                 case mmGB_TILE_MODE14:
 602                 case mmGB_TILE_MODE15:
 603                 case mmGB_TILE_MODE16:
 604                 case mmGB_TILE_MODE17:
 605                 case mmGB_TILE_MODE18:
 606                 case mmGB_TILE_MODE19:
 607                 case mmGB_TILE_MODE20:
 608                 case mmGB_TILE_MODE21:
 609                 case mmGB_TILE_MODE22:
 610                 case mmGB_TILE_MODE23:
 611                 case mmGB_TILE_MODE24:
 612                 case mmGB_TILE_MODE25:
 613                 case mmGB_TILE_MODE26:
 614                 case mmGB_TILE_MODE27:
 615                 case mmGB_TILE_MODE28:
 616                 case mmGB_TILE_MODE29:
 617                 case mmGB_TILE_MODE30:
 618                 case mmGB_TILE_MODE31:
 619                         idx = (reg_offset - mmGB_TILE_MODE0);
 620                         return adev->gfx.config.tile_mode_array[idx];
 621                 case mmGB_MACROTILE_MODE0:
 622                 case mmGB_MACROTILE_MODE1:
 623                 case mmGB_MACROTILE_MODE2:
 624                 case mmGB_MACROTILE_MODE3:
 625                 case mmGB_MACROTILE_MODE4:
 626                 case mmGB_MACROTILE_MODE5:
 627                 case mmGB_MACROTILE_MODE6:
 628                 case mmGB_MACROTILE_MODE7:
 629                 case mmGB_MACROTILE_MODE8:
 630                 case mmGB_MACROTILE_MODE9:
 631                 case mmGB_MACROTILE_MODE10:
 632                 case mmGB_MACROTILE_MODE11:
 633                 case mmGB_MACROTILE_MODE12:
 634                 case mmGB_MACROTILE_MODE13:
 635                 case mmGB_MACROTILE_MODE14:
 636                 case mmGB_MACROTILE_MODE15:
 637                         idx = (reg_offset - mmGB_MACROTILE_MODE0);
 638                         return adev->gfx.config.macrotile_mode_array[idx];
 639                 default:
 640                         return RREG32(reg_offset);
 641                 }
 642         }
 643 }
 644
 645 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 646                             u32 sh_num, u32 reg_offset, u32 *value)
 647 {
 648         uint32_t i;
 649
 650         *value = 0;
 651         for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
 652                 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
 653
 654                 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
 655                         continue;
 656
 657                 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
 658                                                reg_offset);
 659                 return 0;
 660         }
 661         return -EINVAL;
 662 }
 663
 664 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
 665 {
 666         u32 i;
 667
 668         dev_info(adev->dev, "GPU pci config reset\n");
 669
 670         /* disable BM */
 671         pci_clear_master(adev->pdev);
 672         /* reset */
 673         amdgpu_device_pci_config_reset(adev);
 674
 675         udelay(100);
 676
 677         /* wait for asic to come out of reset */
 678         for (i = 0; i < adev->usec_timeout; i++) {
 679                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
 680                         /* enable BM */
 681                         pci_set_master(adev->pdev);
 682                         adev->has_hw_reset = true;
 683                         return 0;
 684                 }
 685                 udelay(1);
 686         }
 687         return -EINVAL;
 688 }
 689
 690 /**
 691  * vi_asic_reset - soft reset GPU
 692  *
 693  * @adev: amdgpu_device pointer
 694  *
 695  * Look up which blocks are hung and attempt
 696  * to reset them.
 697  * Returns 0 for success.
 698  */
 699 static int vi_asic_reset(struct amdgpu_device *adev)
 700 {
 701         int r;
 702
 703         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 704
 705         r = vi_gpu_pci_config_reset(adev);
 706
 707         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 708
 709         return r;
 710 }
 711
 712 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
 713 {
 714         return RREG32(mmCONFIG_MEMSIZE);
 715 }
 716
 717 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 718                         u32 cntl_reg, u32 status_reg)
 719 {
 720         int r, i;
 721         struct atom_clock_dividers dividers;
 722         uint32_t tmp;
 723
 724         r = amdgpu_atombios_get_clock_dividers(adev,
 725                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 726                                                clock, false, &dividers);
 727         if (r)
 728                 return r;
 729
 730         tmp = RREG32_SMC(cntl_reg);
 731
 732         if (adev->flags & AMD_IS_APU)
 733                 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
 734         else
 735                 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
 736                                 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
 737         tmp |= dividers.post_divider;
 738         WREG32_SMC(cntl_reg, tmp);
 739
 740         for (i = 0; i < 100; i++) {
 741                 tmp = RREG32_SMC(status_reg);
 742                 if (adev->flags & AMD_IS_APU) {
 743                         if (tmp & 0x10000)
 744                                 break;
 745                 } else {
 746                         if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
 747                                 break;
 748                 }
 749                 mdelay(10);
 750         }
 751         if (i == 100)
 752                 return -ETIMEDOUT;
 753         return 0;
 754 }
 755
 756 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0
 757 #define ixGNB_CLK1_STATUS   0xD822010C
 758 #define ixGNB_CLK2_DFS_CNTL 0xD8220110
 759 #define ixGNB_CLK2_STATUS   0xD822012C
 760 #define ixGNB_CLK3_DFS_CNTL 0xD8220130
 761 #define ixGNB_CLK3_STATUS   0xD822014C
 762
 763 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 764 {
 765         int r;
 766
 767         if (adev->flags & AMD_IS_APU) {
 768                 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
 769                 if (r)
 770                         return r;
 771
 772                 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
 773                 if (r)
 774                         return r;
 775         } else {
 776                 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 777                 if (r)
 778                         return r;
 779
 780                 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 781                 if (r)
 782                         return r;
 783         }
 784
 785         return 0;
 786 }
 787
 788 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 789 {
 790         int r, i;
 791         struct atom_clock_dividers dividers;
 792         u32 tmp;
 793         u32 reg_ctrl;
 794         u32 reg_status;
 795         u32 status_mask;
 796         u32 reg_mask;
 797
 798         if (adev->flags & AMD_IS_APU) {
 799                 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
 800                 reg_status = ixGNB_CLK3_STATUS;
 801                 status_mask = 0x00010000;
 802                 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
 803         } else {
 804                 reg_ctrl = ixCG_ECLK_CNTL;
 805                 reg_status = ixCG_ECLK_STATUS;
 806                 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
 807                 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
 808         }
 809
 810         r = amdgpu_atombios_get_clock_dividers(adev,
 811                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 812                                                ecclk, false, &dividers);
 813         if (r)
 814                 return r;
 815
 816         for (i = 0; i < 100; i++) {
 817                 if (RREG32_SMC(reg_status) & status_mask)
 818                         break;
 819                 mdelay(10);
 820         }
 821
 822         if (i == 100)
 823                 return -ETIMEDOUT;
 824
 825         tmp = RREG32_SMC(reg_ctrl);
 826         tmp &= ~reg_mask;
 827         tmp |= dividers.post_divider;
 828         WREG32_SMC(reg_ctrl, tmp);
 829
 830         for (i = 0; i < 100; i++) {
 831                 if (RREG32_SMC(reg_status) & status_mask)
 832                         break;
 833                 mdelay(10);
 834         }
 835
 836         if (i == 100)
 837                 return -ETIMEDOUT;
 838
 839         return 0;
 840 }
 841
 842 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
 843 {
 844         if (pci_is_root_bus(adev->pdev->bus))
 845                 return;
 846
 847         if (amdgpu_pcie_gen2 == 0)
 848                 return;
 849
 850         if (adev->flags & AMD_IS_APU)
 851                 return;
 852
 853         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 854                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 855                 return;
 856
 857         /* todo */
 858 }
 859
 860 static void vi_program_aspm(struct amdgpu_device *adev)
 861 {
 862
 863         if (amdgpu_aspm == 0)
 864                 return;
 865
 866         /* todo */
 867 }
 868
 869 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
 870                                         bool enable)
 871 {
 872         u32 tmp;
 873
 874         /* not necessary on CZ */
 875         if (adev->flags & AMD_IS_APU)
 876                 return;
 877
 878         tmp = RREG32(mmBIF_DOORBELL_APER_EN);
 879         if (enable)
 880                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
 881         else
 882                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
 883
 884         WREG32(mmBIF_DOORBELL_APER_EN, tmp);
 885 }
 886
 887 #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
 888 #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
 889 #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
 890
 891 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
 892 {
 893         if (adev->flags & AMD_IS_APU)
 894                 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
 895                         >> ATI_REV_ID_FUSE_MACRO__SHIFT;
 896         else
 897                 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
 898                         >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
 899 }
 900
 901 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 902 {
 903         if (!ring || !ring->funcs->emit_wreg) {
 904                 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
 905                 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
 906         } else {
 907                 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
 908         }
 909 }
 910
 911 static void vi_invalidate_hdp(struct amdgpu_device *adev,
 912                               struct amdgpu_ring *ring)
 913 {
 914         if (!ring || !ring->funcs->emit_wreg) {
 915                 WREG32(mmHDP_DEBUG0, 1);
 916                 RREG32(mmHDP_DEBUG0);
 917         } else {
 918                 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
 919         }
 920 }
 921
 922 static bool vi_need_full_reset(struct amdgpu_device *adev)
 923 {
 924         switch (adev->asic_type) {
 925         case CHIP_CARRIZO:
 926         case CHIP_STONEY:
 927                 /* CZ has hang issues with full reset at the moment */
 928                 return false;
 929         case CHIP_FIJI:
 930         case CHIP_TONGA:
 931                 /* XXX: soft reset should work on fiji and tonga */
 932                 return true;
 933         case CHIP_POLARIS10:
 934         case CHIP_POLARIS11:
 935         case CHIP_POLARIS12:
 936         case CHIP_TOPAZ:
 937         default:
 938                 /* change this when we support soft reset */
 939                 return true;
 940         }
 941 }
 942
 943 static const struct amdgpu_asic_funcs vi_asic_funcs =
 944 {
 945         .read_disabled_bios = &vi_read_disabled_bios,
 946         .read_bios_from_rom = &vi_read_bios_from_rom,
 947         .read_register = &vi_read_register,
 948         .reset = &vi_asic_reset,
 949         .set_vga_state = &vi_vga_set_state,
 950         .get_xclk = &vi_get_xclk,
 951         .set_uvd_clocks = &vi_set_uvd_clocks,
 952         .set_vce_clocks = &vi_set_vce_clocks,
 953         .get_config_memsize = &vi_get_config_memsize,
 954         .flush_hdp = &vi_flush_hdp,
 955         .invalidate_hdp = &vi_invalidate_hdp,
 956         .need_full_reset = &vi_need_full_reset,
 957 };
 958
 959 #define CZ_REV_BRISTOL(rev)      \
 960         ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
 961
 962 static int vi_common_early_init(void *handle)
 963 {
 964         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 965
 966         if (adev->flags & AMD_IS_APU) {
 967                 adev->smc_rreg = &cz_smc_rreg;
 968                 adev->smc_wreg = &cz_smc_wreg;
 969         } else {
 970                 adev->smc_rreg = &vi_smc_rreg;
 971                 adev->smc_wreg = &vi_smc_wreg;
 972         }
 973         adev->pcie_rreg = &vi_pcie_rreg;
 974         adev->pcie_wreg = &vi_pcie_wreg;
 975         adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
 976         adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
 977         adev->didt_rreg = &vi_didt_rreg;
 978         adev->didt_wreg = &vi_didt_wreg;
 979         adev->gc_cac_rreg = &vi_gc_cac_rreg;
 980         adev->gc_cac_wreg = &vi_gc_cac_wreg;
 981
 982         adev->asic_funcs = &vi_asic_funcs;
 983
 984         adev->rev_id = vi_get_rev_id(adev);
 985         adev->external_rev_id = 0xFF;
 986         switch (adev->asic_type) {
 987         case CHIP_TOPAZ:
 988                 adev->cg_flags = 0;
 989                 adev->pg_flags = 0;
 990                 adev->external_rev_id = 0x1;
 991                 break;
 992         case CHIP_FIJI:
 993                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 994                         AMD_CG_SUPPORT_GFX_MGLS |
 995                         AMD_CG_SUPPORT_GFX_RLC_LS |
 996                         AMD_CG_SUPPORT_GFX_CP_LS |
 997                         AMD_CG_SUPPORT_GFX_CGTS |
 998                         AMD_CG_SUPPORT_GFX_CGTS_LS |
 999                         AMD_CG_SUPPORT_GFX_CGCG |
1000                         AMD_CG_SUPPORT_GFX_CGLS |
1001                         AMD_CG_SUPPORT_SDMA_MGCG |
1002                         AMD_CG_SUPPORT_SDMA_LS |
1003                         AMD_CG_SUPPORT_BIF_LS |
1004                         AMD_CG_SUPPORT_HDP_MGCG |
1005                         AMD_CG_SUPPORT_HDP_LS |
1006                         AMD_CG_SUPPORT_ROM_MGCG |
1007                         AMD_CG_SUPPORT_MC_MGCG |
1008                         AMD_CG_SUPPORT_MC_LS |
1009                         AMD_CG_SUPPORT_UVD_MGCG;
1010                 adev->pg_flags = 0;
1011                 adev->external_rev_id = adev->rev_id + 0x3c;
1012                 break;
1013         case CHIP_TONGA:
1014                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1015                         AMD_CG_SUPPORT_GFX_CGCG |
1016                         AMD_CG_SUPPORT_GFX_CGLS |
1017                         AMD_CG_SUPPORT_SDMA_MGCG |
1018                         AMD_CG_SUPPORT_SDMA_LS |
1019                         AMD_CG_SUPPORT_BIF_LS |
1020                         AMD_CG_SUPPORT_HDP_MGCG |
1021                         AMD_CG_SUPPORT_HDP_LS |
1022                         AMD_CG_SUPPORT_ROM_MGCG |
1023                         AMD_CG_SUPPORT_MC_MGCG |
1024                         AMD_CG_SUPPORT_MC_LS |
1025                         AMD_CG_SUPPORT_DRM_LS |
1026                         AMD_CG_SUPPORT_UVD_MGCG;
1027                 adev->pg_flags = 0;
1028                 adev->external_rev_id = adev->rev_id + 0x14;
1029                 break;
1030         case CHIP_POLARIS11:
1031                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1032                         AMD_CG_SUPPORT_GFX_RLC_LS |
1033                         AMD_CG_SUPPORT_GFX_CP_LS |
1034                         AMD_CG_SUPPORT_GFX_CGCG |
1035                         AMD_CG_SUPPORT_GFX_CGLS |
1036                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1037                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1038                         AMD_CG_SUPPORT_SDMA_MGCG |
1039                         AMD_CG_SUPPORT_SDMA_LS |
1040                         AMD_CG_SUPPORT_BIF_MGCG |
1041                         AMD_CG_SUPPORT_BIF_LS |
1042                         AMD_CG_SUPPORT_HDP_MGCG |
1043                         AMD_CG_SUPPORT_HDP_LS |
1044                         AMD_CG_SUPPORT_ROM_MGCG |
1045                         AMD_CG_SUPPORT_MC_MGCG |
1046                         AMD_CG_SUPPORT_MC_LS |
1047                         AMD_CG_SUPPORT_DRM_LS |
1048                         AMD_CG_SUPPORT_UVD_MGCG |
1049                         AMD_CG_SUPPORT_VCE_MGCG;
1050                 adev->pg_flags = 0;
1051                 adev->external_rev_id = adev->rev_id + 0x5A;
1052                 break;
1053         case CHIP_POLARIS10:
1054                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1055                         AMD_CG_SUPPORT_GFX_RLC_LS |
1056                         AMD_CG_SUPPORT_GFX_CP_LS |
1057                         AMD_CG_SUPPORT_GFX_CGCG |
1058                         AMD_CG_SUPPORT_GFX_CGLS |
1059                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1060                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1061                         AMD_CG_SUPPORT_SDMA_MGCG |
1062                         AMD_CG_SUPPORT_SDMA_LS |
1063                         AMD_CG_SUPPORT_BIF_MGCG |
1064                         AMD_CG_SUPPORT_BIF_LS |
1065                         AMD_CG_SUPPORT_HDP_MGCG |
1066                         AMD_CG_SUPPORT_HDP_LS |
1067                         AMD_CG_SUPPORT_ROM_MGCG |
1068                         AMD_CG_SUPPORT_MC_MGCG |
1069                         AMD_CG_SUPPORT_MC_LS |
1070                         AMD_CG_SUPPORT_DRM_LS |
1071                         AMD_CG_SUPPORT_UVD_MGCG |
1072                         AMD_CG_SUPPORT_VCE_MGCG;
1073                 adev->pg_flags = 0;
1074                 adev->external_rev_id = adev->rev_id + 0x50;
1075                 break;
1076         case CHIP_POLARIS12:
1077                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1078                         AMD_CG_SUPPORT_GFX_RLC_LS |
1079                         AMD_CG_SUPPORT_GFX_CP_LS |
1080                         AMD_CG_SUPPORT_GFX_CGCG |
1081                         AMD_CG_SUPPORT_GFX_CGLS |
1082                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1083                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1084                         AMD_CG_SUPPORT_SDMA_MGCG |
1085                         AMD_CG_SUPPORT_SDMA_LS |
1086                         AMD_CG_SUPPORT_BIF_MGCG |
1087                         AMD_CG_SUPPORT_BIF_LS |
1088                         AMD_CG_SUPPORT_HDP_MGCG |
1089                         AMD_CG_SUPPORT_HDP_LS |
1090                         AMD_CG_SUPPORT_ROM_MGCG |
1091                         AMD_CG_SUPPORT_MC_MGCG |
1092                         AMD_CG_SUPPORT_MC_LS |
1093                         AMD_CG_SUPPORT_DRM_LS |
1094                         AMD_CG_SUPPORT_UVD_MGCG |
1095                         AMD_CG_SUPPORT_VCE_MGCG;
1096                 adev->pg_flags = 0;
1097                 adev->external_rev_id = adev->rev_id + 0x64;
1098                 break;
1099         case CHIP_CARRIZO:
1100                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1101                         AMD_CG_SUPPORT_GFX_MGCG |
1102                         AMD_CG_SUPPORT_GFX_MGLS |
1103                         AMD_CG_SUPPORT_GFX_RLC_LS |
1104                         AMD_CG_SUPPORT_GFX_CP_LS |
1105                         AMD_CG_SUPPORT_GFX_CGTS |
1106                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1107                         AMD_CG_SUPPORT_GFX_CGCG |
1108                         AMD_CG_SUPPORT_GFX_CGLS |
1109                         AMD_CG_SUPPORT_BIF_LS |
1110                         AMD_CG_SUPPORT_HDP_MGCG |
1111                         AMD_CG_SUPPORT_HDP_LS |
1112                         AMD_CG_SUPPORT_SDMA_MGCG |
1113                         AMD_CG_SUPPORT_SDMA_LS |
1114                         AMD_CG_SUPPORT_VCE_MGCG;
1115                 /* rev0 hardware requires workarounds to support PG */
1116                 adev->pg_flags = 0;
1117                 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1118                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1119                                 AMD_PG_SUPPORT_GFX_PIPELINE |
1120                                 AMD_PG_SUPPORT_CP |
1121                                 AMD_PG_SUPPORT_UVD |
1122                                 AMD_PG_SUPPORT_VCE;
1123                 }
1124                 adev->external_rev_id = adev->rev_id + 0x1;
1125                 break;
1126         case CHIP_STONEY:
1127                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1128                         AMD_CG_SUPPORT_GFX_MGCG |
1129                         AMD_CG_SUPPORT_GFX_MGLS |
1130                         AMD_CG_SUPPORT_GFX_RLC_LS |
1131                         AMD_CG_SUPPORT_GFX_CP_LS |
1132                         AMD_CG_SUPPORT_GFX_CGTS |
1133                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1134                         AMD_CG_SUPPORT_GFX_CGLS |
1135                         AMD_CG_SUPPORT_BIF_LS |
1136                         AMD_CG_SUPPORT_HDP_MGCG |
1137                         AMD_CG_SUPPORT_HDP_LS |
1138                         AMD_CG_SUPPORT_SDMA_MGCG |
1139                         AMD_CG_SUPPORT_SDMA_LS |
1140                         AMD_CG_SUPPORT_VCE_MGCG;
1141                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1142                         AMD_PG_SUPPORT_GFX_SMG |
1143                         AMD_PG_SUPPORT_GFX_PIPELINE |
1144                         AMD_PG_SUPPORT_CP |
1145                         AMD_PG_SUPPORT_UVD |
1146                         AMD_PG_SUPPORT_VCE;
1147                 adev->external_rev_id = adev->rev_id + 0x61;
1148                 break;
1149         default:
1150                 /* FIXME: not supported yet */
1151                 return -EINVAL;
1152         }
1153
1154         if (amdgpu_sriov_vf(adev)) {
1155                 amdgpu_virt_init_setting(adev);
1156                 xgpu_vi_mailbox_set_irq_funcs(adev);
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int vi_common_late_init(void *handle)
1163 {
1164         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1165
1166         if (amdgpu_sriov_vf(adev))
1167                 xgpu_vi_mailbox_get_irq(adev);
1168
1169         return 0;
1170 }
1171
1172 static int vi_common_sw_init(void *handle)
1173 {
1174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175
1176         if (amdgpu_sriov_vf(adev))
1177                 xgpu_vi_mailbox_add_irq_id(adev);
1178
1179         return 0;
1180 }
1181
1182 static int vi_common_sw_fini(void *handle)
1183 {
1184         return 0;
1185 }
1186
1187 static int vi_common_hw_init(void *handle)
1188 {
1189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190
1191         /* move the golden regs per IP block */
1192         vi_init_golden_registers(adev);
1193         /* enable pcie gen2/3 link */
1194         vi_pcie_gen3_enable(adev);
1195         /* enable aspm */
1196         vi_program_aspm(adev);
1197         /* enable the doorbell aperture */
1198         vi_enable_doorbell_aperture(adev, true);
1199
1200         return 0;
1201 }
1202
1203 static int vi_common_hw_fini(void *handle)
1204 {
1205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206
1207         /* enable the doorbell aperture */
1208         vi_enable_doorbell_aperture(adev, false);
1209
1210         if (amdgpu_sriov_vf(adev))
1211                 xgpu_vi_mailbox_put_irq(adev);
1212
1213         return 0;
1214 }
1215
1216 static int vi_common_suspend(void *handle)
1217 {
1218         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1219
1220         return vi_common_hw_fini(adev);
1221 }
1222
1223 static int vi_common_resume(void *handle)
1224 {
1225         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1226
1227         return vi_common_hw_init(adev);
1228 }
1229
1230 static bool vi_common_is_idle(void *handle)
1231 {
1232         return true;
1233 }
1234
1235 static int vi_common_wait_for_idle(void *handle)
1236 {
1237         return 0;
1238 }
1239
1240 static int vi_common_soft_reset(void *handle)
1241 {
1242         return 0;
1243 }
1244
1245 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1246                                                    bool enable)
1247 {
1248         uint32_t temp, data;
1249
1250         temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1251
1252         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1253                 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1254                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1255                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1256         else
1257                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1258                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1259                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1260
1261         if (temp != data)
1262                 WREG32_PCIE(ixPCIE_CNTL2, data);
1263 }
1264
1265 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1266                                                     bool enable)
1267 {
1268         uint32_t temp, data;
1269
1270         temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1271
1272         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1273                 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1274         else
1275                 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1276
1277         if (temp != data)
1278                 WREG32(mmHDP_HOST_PATH_CNTL, data);
1279 }
1280
1281 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1282                                       bool enable)
1283 {
1284         uint32_t temp, data;
1285
1286         temp = data = RREG32(mmHDP_MEM_POWER_LS);
1287
1288         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1289                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1290         else
1291                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1292
1293         if (temp != data)
1294                 WREG32(mmHDP_MEM_POWER_LS, data);
1295 }
1296
1297 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1298                                       bool enable)
1299 {
1300         uint32_t temp, data;
1301
1302         temp = data = RREG32(0x157a);
1303
1304         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1305                 data |= 1;
1306         else
1307                 data &= ~1;
1308
1309         if (temp != data)
1310                 WREG32(0x157a, data);
1311 }
1312
1313
1314 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1315                                                     bool enable)
1316 {
1317         uint32_t temp, data;
1318
1319         temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1320
1321         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1322                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1323                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1324         else
1325                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1326                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1327
1328         if (temp != data)
1329                 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1330 }
1331
1332 static int vi_common_set_clockgating_state_by_smu(void *handle,
1333                                            enum amd_clockgating_state state)
1334 {
1335         uint32_t msg_id, pp_state = 0;
1336         uint32_t pp_support_state = 0;
1337         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338
1339         if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1340                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1341                         pp_support_state = AMD_CG_SUPPORT_MC_LS;
1342                         pp_state = PP_STATE_LS;
1343                 }
1344                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1345                         pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
1346                         pp_state |= PP_STATE_CG;
1347                 }
1348                 if (state == AMD_CG_STATE_UNGATE)
1349                         pp_state = 0;
1350                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1351                                PP_BLOCK_SYS_MC,
1352                                pp_support_state,
1353                                pp_state);
1354                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1355                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1356         }
1357
1358         if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1359                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1360                         pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
1361                         pp_state = PP_STATE_LS;
1362                 }
1363                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1364                         pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
1365                         pp_state |= PP_STATE_CG;
1366                 }
1367                 if (state == AMD_CG_STATE_UNGATE)
1368                         pp_state = 0;
1369                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1370                                PP_BLOCK_SYS_SDMA,
1371                                pp_support_state,
1372                                pp_state);
1373                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1374                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1375         }
1376
1377         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1378                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1379                         pp_support_state = AMD_CG_SUPPORT_HDP_LS;
1380                         pp_state = PP_STATE_LS;
1381                 }
1382                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1383                         pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
1384                         pp_state |= PP_STATE_CG;
1385                 }
1386                 if (state == AMD_CG_STATE_UNGATE)
1387                         pp_state = 0;
1388                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1389                                PP_BLOCK_SYS_HDP,
1390                                pp_support_state,
1391                                pp_state);
1392                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1393                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1394         }
1395
1396
1397         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1398                 if (state == AMD_CG_STATE_UNGATE)
1399                         pp_state = 0;
1400                 else
1401                         pp_state = PP_STATE_LS;
1402
1403                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1404                                PP_BLOCK_SYS_BIF,
1405                                PP_STATE_SUPPORT_LS,
1406                                 pp_state);
1407                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1408                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1409         }
1410         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1411                 if (state == AMD_CG_STATE_UNGATE)
1412                         pp_state = 0;
1413                 else
1414                         pp_state = PP_STATE_CG;
1415
1416                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1417                                PP_BLOCK_SYS_BIF,
1418                                PP_STATE_SUPPORT_CG,
1419                                pp_state);
1420                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1421                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1422         }
1423
1424         if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1425
1426                 if (state == AMD_CG_STATE_UNGATE)
1427                         pp_state = 0;
1428                 else
1429                         pp_state = PP_STATE_LS;
1430
1431                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1432                                PP_BLOCK_SYS_DRM,
1433                                PP_STATE_SUPPORT_LS,
1434                                pp_state);
1435                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1436                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1437         }
1438
1439         if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1440
1441                 if (state == AMD_CG_STATE_UNGATE)
1442                         pp_state = 0;
1443                 else
1444                         pp_state = PP_STATE_CG;
1445
1446                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1447                                PP_BLOCK_SYS_ROM,
1448                                PP_STATE_SUPPORT_CG,
1449                                pp_state);
1450                 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1451                         amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1452         }
1453         return 0;
1454 }
1455
1456 static int vi_common_set_clockgating_state(void *handle,
1457                                            enum amd_clockgating_state state)
1458 {
1459         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1460
1461         if (amdgpu_sriov_vf(adev))
1462                 return 0;
1463
1464         switch (adev->asic_type) {
1465         case CHIP_FIJI:
1466                 vi_update_bif_medium_grain_light_sleep(adev,
1467                                 state == AMD_CG_STATE_GATE);
1468                 vi_update_hdp_medium_grain_clock_gating(adev,
1469                                 state == AMD_CG_STATE_GATE);
1470                 vi_update_hdp_light_sleep(adev,
1471                                 state == AMD_CG_STATE_GATE);
1472                 vi_update_rom_medium_grain_clock_gating(adev,
1473                                 state == AMD_CG_STATE_GATE);
1474                 break;
1475         case CHIP_CARRIZO:
1476         case CHIP_STONEY:
1477                 vi_update_bif_medium_grain_light_sleep(adev,
1478                                 state == AMD_CG_STATE_GATE);
1479                 vi_update_hdp_medium_grain_clock_gating(adev,
1480                                 state == AMD_CG_STATE_GATE);
1481                 vi_update_hdp_light_sleep(adev,
1482                                 state == AMD_CG_STATE_GATE);
1483                 vi_update_drm_light_sleep(adev,
1484                                 state == AMD_CG_STATE_GATE);
1485                 break;
1486         case CHIP_TONGA:
1487         case CHIP_POLARIS10:
1488         case CHIP_POLARIS11:
1489         case CHIP_POLARIS12:
1490                 vi_common_set_clockgating_state_by_smu(adev, state);
1491         default:
1492                 break;
1493         }
1494         return 0;
1495 }
1496
1497 static int vi_common_set_powergating_state(void *handle,
1498                                             enum amd_powergating_state state)
1499 {
1500         return 0;
1501 }
1502
1503 static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1504 {
1505         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1506         int data;
1507
1508         if (amdgpu_sriov_vf(adev))
1509                 *flags = 0;
1510
1511         /* AMD_CG_SUPPORT_BIF_LS */
1512         data = RREG32_PCIE(ixPCIE_CNTL2);
1513         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1514                 *flags |= AMD_CG_SUPPORT_BIF_LS;
1515
1516         /* AMD_CG_SUPPORT_HDP_LS */
1517         data = RREG32(mmHDP_MEM_POWER_LS);
1518         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1519                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1520
1521         /* AMD_CG_SUPPORT_HDP_MGCG */
1522         data = RREG32(mmHDP_HOST_PATH_CNTL);
1523         if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1524                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1525
1526         /* AMD_CG_SUPPORT_ROM_MGCG */
1527         data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1528         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1529                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1530 }
1531
1532 static const struct amd_ip_funcs vi_common_ip_funcs = {
1533         .name = "vi_common",
1534         .early_init = vi_common_early_init,
1535         .late_init = vi_common_late_init,
1536         .sw_init = vi_common_sw_init,
1537         .sw_fini = vi_common_sw_fini,
1538         .hw_init = vi_common_hw_init,
1539         .hw_fini = vi_common_hw_fini,
1540         .suspend = vi_common_suspend,
1541         .resume = vi_common_resume,
1542         .is_idle = vi_common_is_idle,
1543         .wait_for_idle = vi_common_wait_for_idle,
1544         .soft_reset = vi_common_soft_reset,
1545         .set_clockgating_state = vi_common_set_clockgating_state,
1546         .set_powergating_state = vi_common_set_powergating_state,
1547         .get_clockgating_state = vi_common_get_clockgating_state,
1548 };
1549
1550 static const struct amdgpu_ip_block_version vi_common_ip_block =
1551 {
1552         .type = AMD_IP_BLOCK_TYPE_COMMON,
1553         .major = 1,
1554         .minor = 0,
1555         .rev = 0,
1556         .funcs = &vi_common_ip_funcs,
1557 };
1558
1559 int vi_set_ip_blocks(struct amdgpu_device *adev)
1560 {
1561         /* in early init stage, vbios code won't work */
1562         vi_detect_hw_virtualization(adev);
1563
1564         if (amdgpu_sriov_vf(adev))
1565                 adev->virt.ops = &xgpu_vi_virt_ops;
1566
1567         switch (adev->asic_type) {
1568         case CHIP_TOPAZ:
1569                 /* topaz has no DCE, UVD, VCE */
1570                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1571                 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1572                 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1573                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1574                 if (adev->enable_virtual_display)
1575                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1576                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1577                 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
1578                 break;
1579         case CHIP_FIJI:
1580                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1581                 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1582                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1583                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1584                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1585                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1586 #if defined(CONFIG_DRM_AMD_DC)
1587                 else if (amdgpu_device_has_dc_support(adev))
1588                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1589 #endif
1590                 else
1591                         amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1592                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1593                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1594                 if (!amdgpu_sriov_vf(adev)) {
1595                         amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1596                         amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1597                 }
1598                 break;
1599         case CHIP_TONGA:
1600                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1601                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1602                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1603                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1604                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1605                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1606 #if defined(CONFIG_DRM_AMD_DC)
1607                 else if (amdgpu_device_has_dc_support(adev))
1608                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1609 #endif
1610                 else
1611                         amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1612                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1613                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1614                 if (!amdgpu_sriov_vf(adev)) {
1615                         amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1616                         amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1617                 }
1618                 break;
1619         case CHIP_POLARIS11:
1620         case CHIP_POLARIS10:
1621         case CHIP_POLARIS12:
1622                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1623                 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1624                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1625                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1626                 if (adev->enable_virtual_display)
1627                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1628 #if defined(CONFIG_DRM_AMD_DC)
1629                 else if (amdgpu_device_has_dc_support(adev))
1630                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1631 #endif
1632                 else
1633                         amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1634                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1635                 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
1636                 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1637                 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1638                 break;
1639         case CHIP_CARRIZO:
1640                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1641                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1642                 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1643                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1644                 if (adev->enable_virtual_display)
1645                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1646 #if defined(CONFIG_DRM_AMD_DC)
1647                 else if (amdgpu_device_has_dc_support(adev))
1648                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1649 #endif
1650                 else
1651                         amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1652                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1653                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1654                 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1655                 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
1656 #if defined(CONFIG_DRM_AMD_ACP)
1657                 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1658 #endif
1659                 break;
1660         case CHIP_STONEY:
1661                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1662                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1663                 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1664                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1665                 if (adev->enable_virtual_display)
1666                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1667 #if defined(CONFIG_DRM_AMD_DC)
1668                 else if (amdgpu_device_has_dc_support(adev))
1669                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1670 #endif
1671                 else
1672                         amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1673                 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1674                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1675                 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1676                 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1677 #if defined(CONFIG_DRM_AMD_ACP)
1678                 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1679 #endif
1680                 break;
1681         default:
1682                 /* FIXME: not supported yet */
1683                 return -EINVAL;
1684         }
1685
1686         return 0;
1687 }