drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39 #include "amdgpu_amdkfd.h"
  40
  41 static bool amdgpu_need_backup(struct amdgpu_device *adev)
  42 {
  43         if (adev->flags & AMD_IS_APU)
  44                 return false;
  45
  46         if (amdgpu_gpu_recovery == 0 ||
  47             (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))
  48                 return false;
  49
  50         return true;
  51 }
  52
  53 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  54 {
  55         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  56         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  57
  58         if (bo->kfd_bo)
  59                 amdgpu_amdkfd_unreserve_system_memory_limit(bo);
  60
  61         amdgpu_bo_kunmap(bo);
  62
  63         if (bo->gem_base.import_attach)
  64                 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
  65         drm_gem_object_release(&bo->gem_base);
  66         amdgpu_bo_unref(&bo->parent);
  67         if (!list_empty(&bo->shadow_list)) {
  68                 mutex_lock(&adev->shadow_list_lock);
  69                 list_del_init(&bo->shadow_list);
  70                 mutex_unlock(&adev->shadow_list_lock);
  71         }
  72         kfree(bo->metadata);
  73         kfree(bo);
  74 }
  75
  76 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  77 {
  78         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  79                 return true;
  80         return false;
  81 }
  82
  83 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  84 {
  85         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  86         struct ttm_placement *placement = &abo->placement;
  87         struct ttm_place *places = abo->placements;
  88         u64 flags = abo->flags;
  89         u32 c = 0;
  90
  91         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  92                 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
  93
  94                 places[c].fpfn = 0;
  95                 places[c].lpfn = 0;
  96                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  97                         TTM_PL_FLAG_VRAM;
  98
  99                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 100                         places[c].lpfn = visible_pfn;
 101                 else
 102                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 103
 104                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 105                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 106                 c++;
 107         }
 108
 109         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 110                 places[c].fpfn = 0;
 111                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
 112                         places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 113                 else
 114                         places[c].lpfn = 0;
 115                 places[c].flags = TTM_PL_FLAG_TT;
 116                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 117                         places[c].flags |= TTM_PL_FLAG_WC |
 118                                 TTM_PL_FLAG_UNCACHED;
 119                 else
 120                         places[c].flags |= TTM_PL_FLAG_CACHED;
 121                 c++;
 122         }
 123
 124         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 125                 places[c].fpfn = 0;
 126                 places[c].lpfn = 0;
 127                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 128                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 129                         places[c].flags |= TTM_PL_FLAG_WC |
 130                                 TTM_PL_FLAG_UNCACHED;
 131                 else
 132                         places[c].flags |= TTM_PL_FLAG_CACHED;
 133                 c++;
 134         }
 135
 136         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 137                 places[c].fpfn = 0;
 138                 places[c].lpfn = 0;
 139                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 140                 c++;
 141         }
 142
 143         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 144                 places[c].fpfn = 0;
 145                 places[c].lpfn = 0;
 146                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 147                 c++;
 148         }
 149
 150         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 151                 places[c].fpfn = 0;
 152                 places[c].lpfn = 0;
 153                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 154                 c++;
 155         }
 156
 157         if (!c) {
 158                 places[c].fpfn = 0;
 159                 places[c].lpfn = 0;
 160                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 161                 c++;
 162         }
 163
 164         placement->num_placement = c;
 165         placement->placement = places;
 166
 167         placement->num_busy_placement = c;
 168         placement->busy_placement = places;
 169 }
 170
 171 /**
 172  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 173  *
 174  * @adev: amdgpu device object
 175  * @size: size for the new BO
 176  * @align: alignment for the new BO
 177  * @domain: where to place it
 178  * @bo_ptr: used to initialize BOs in structures
 179  * @gpu_addr: GPU addr of the pinned BO
 180  * @cpu_addr: optional CPU address mapping
 181  *
 182  * Allocates and pins a BO for kernel internal use, and returns it still
 183  * reserved.
 184  *
 185  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 186  *
 187  * Returns 0 on success, negative error code otherwise.
 188  */
 189 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 190                               unsigned long size, int align,
 191                               u32 domain, struct amdgpu_bo **bo_ptr,
 192                               u64 *gpu_addr, void **cpu_addr)
 193 {
 194         struct amdgpu_bo_param bp;
 195         bool free = false;
 196         int r;
 197
 198         memset(&bp, 0, sizeof(bp));
 199         bp.size = size;
 200         bp.byte_align = align;
 201         bp.domain = domain;
 202         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 203                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 204         bp.type = ttm_bo_type_kernel;
 205         bp.resv = NULL;
 206
 207         if (!*bo_ptr) {
 208                 r = amdgpu_bo_create(adev, &bp, bo_ptr);
 209                 if (r) {
 210                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 211                                 r);
 212                         return r;
 213                 }
 214                 free = true;
 215         }
 216
 217         r = amdgpu_bo_reserve(*bo_ptr, false);
 218         if (r) {
 219                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 220                 goto error_free;
 221         }
 222
 223         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 224         if (r) {
 225                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 226                 goto error_unreserve;
 227         }
 228
 229         if (cpu_addr) {
 230                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 231                 if (r) {
 232                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 233                         goto error_unreserve;
 234                 }
 235         }
 236
 237         return 0;
 238
 239 error_unreserve:
 240         amdgpu_bo_unreserve(*bo_ptr);
 241
 242 error_free:
 243         if (free)
 244                 amdgpu_bo_unref(bo_ptr);
 245
 246         return r;
 247 }
 248
 249 /**
 250  * amdgpu_bo_create_kernel - create BO for kernel use
 251  *
 252  * @adev: amdgpu device object
 253  * @size: size for the new BO
 254  * @align: alignment for the new BO
 255  * @domain: where to place it
 256  * @bo_ptr:  used to initialize BOs in structures
 257  * @gpu_addr: GPU addr of the pinned BO
 258  * @cpu_addr: optional CPU address mapping
 259  *
 260  * Allocates and pins a BO for kernel internal use.
 261  *
 262  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 263  *
 264  * Returns 0 on success, negative error code otherwise.
 265  */
 266 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 267                             unsigned long size, int align,
 268                             u32 domain, struct amdgpu_bo **bo_ptr,
 269                             u64 *gpu_addr, void **cpu_addr)
 270 {
 271         int r;
 272
 273         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 274                                       gpu_addr, cpu_addr);
 275
 276         if (r)
 277                 return r;
 278
 279         amdgpu_bo_unreserve(*bo_ptr);
 280
 281         return 0;
 282 }
 283
 284 /**
 285  * amdgpu_bo_free_kernel - free BO for kernel use
 286  *
 287  * @bo: amdgpu BO to free
 288  *
 289  * unmaps and unpin a BO for kernel internal use.
 290  */
 291 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 292                            void **cpu_addr)
 293 {
 294         if (*bo == NULL)
 295                 return;
 296
 297         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 298                 if (cpu_addr)
 299                         amdgpu_bo_kunmap(*bo);
 300
 301                 amdgpu_bo_unpin(*bo);
 302                 amdgpu_bo_unreserve(*bo);
 303         }
 304         amdgpu_bo_unref(bo);
 305
 306         if (gpu_addr)
 307                 *gpu_addr = 0;
 308
 309         if (cpu_addr)
 310                 *cpu_addr = NULL;
 311 }
 312
 313 /* Validate bo size is bit bigger then the request domain */
 314 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 315                                           unsigned long size, u32 domain)
 316 {
 317         struct ttm_mem_type_manager *man = NULL;
 318
 319         /*
 320          * If GTT is part of requested domains the check must succeed to
 321          * allow fall back to GTT
 322          */
 323         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 324                 man = &adev->mman.bdev.man[TTM_PL_TT];
 325
 326                 if (size < (man->size << PAGE_SHIFT))
 327                         return true;
 328                 else
 329                         goto fail;
 330         }
 331
 332         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 333                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 334
 335                 if (size < (man->size << PAGE_SHIFT))
 336                         return true;
 337                 else
 338                         goto fail;
 339         }
 340
 341
 342         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 343         return true;
 344
 345 fail:
 346         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 347                   man->size << PAGE_SHIFT);
 348         return false;
 349 }
 350
 351 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 352                                struct amdgpu_bo_param *bp,
 353                                struct amdgpu_bo **bo_ptr)
 354 {
 355         struct ttm_operation_ctx ctx = {
 356                 .interruptible = (bp->type != ttm_bo_type_kernel),
 357                 .no_wait_gpu = false,
 358                 .resv = bp->resv,
 359                 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 360         };
 361         struct amdgpu_bo *bo;
 362         unsigned long page_align, size = bp->size;
 363         size_t acc_size;
 364         int r;
 365
 366         page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 367         size = ALIGN(size, PAGE_SIZE);
 368
 369         if (!amdgpu_bo_validate_size(adev, size, bp->domain))
 370                 return -ENOMEM;
 371
 372         *bo_ptr = NULL;
 373
 374         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 375                                        sizeof(struct amdgpu_bo));
 376
 377         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 378         if (bo == NULL)
 379                 return -ENOMEM;
 380         drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 381         INIT_LIST_HEAD(&bo->shadow_list);
 382         INIT_LIST_HEAD(&bo->va);
 383         bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
 384                 bp->domain;
 385         bo->allowed_domains = bo->preferred_domains;
 386         if (bp->type != ttm_bo_type_kernel &&
 387             bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 388                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 389
 390         bo->flags = bp->flags;
 391
 392 #ifdef CONFIG_X86_32
 393         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 394          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 395          */
 396         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 397 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 398         /* Don't try to enable write-combining when it can't work, or things
 399          * may be slow
 400          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 401          */
 402
 403 #ifndef CONFIG_COMPILE_TEST
 404 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 405          thanks to write-combining
 406 #endif
 407
 408         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 409                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 410                               "better performance thanks to write-combining\n");
 411         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 412 #else
 413         /* For architectures that don't support WC memory,
 414          * mask out the WC flag from the BO
 415          */
 416         if (!drm_arch_can_wc_memory())
 417                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 418 #endif
 419
 420         bo->tbo.bdev = &adev->mman.bdev;
 421         amdgpu_ttm_placement_from_domain(bo, bp->domain);
 422
 423         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
 424                                  &bo->placement, page_align, &ctx, acc_size,
 425                                  NULL, bp->resv, &amdgpu_ttm_bo_destroy);
 426         if (unlikely(r != 0))
 427                 return r;
 428
 429         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 430             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 431             bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 432                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 433                                              ctx.bytes_moved);
 434         else
 435                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 436
 437         if (bp->type == ttm_bo_type_kernel)
 438                 bo->tbo.priority = 1;
 439
 440         if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 441             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 442                 struct dma_fence *fence;
 443
 444                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 445                 if (unlikely(r))
 446                         goto fail_unreserve;
 447
 448                 amdgpu_bo_fence(bo, fence, false);
 449                 dma_fence_put(bo->tbo.moving);
 450                 bo->tbo.moving = dma_fence_get(fence);
 451                 dma_fence_put(fence);
 452         }
 453         if (!bp->resv)
 454                 amdgpu_bo_unreserve(bo);
 455         *bo_ptr = bo;
 456
 457         trace_amdgpu_bo_create(bo);
 458
 459         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 460         if (bp->type == ttm_bo_type_device)
 461                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 462
 463         return 0;
 464
 465 fail_unreserve:
 466         if (!bp->resv)
 467                 ww_mutex_unlock(&bo->tbo.resv->lock);
 468         amdgpu_bo_unref(&bo);
 469         return r;
 470 }
 471
 472 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 473                                    unsigned long size, int byte_align,
 474                                    struct amdgpu_bo *bo)
 475 {
 476         struct amdgpu_bo_param bp;
 477         int r;
 478
 479         if (bo->shadow)
 480                 return 0;
 481
 482         memset(&bp, 0, sizeof(bp));
 483         bp.size = size;
 484         bp.byte_align = byte_align;
 485         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 486         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 487                 AMDGPU_GEM_CREATE_SHADOW;
 488         bp.type = ttm_bo_type_kernel;
 489         bp.resv = bo->tbo.resv;
 490
 491         r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
 492         if (!r) {
 493                 bo->shadow->parent = amdgpu_bo_ref(bo);
 494                 mutex_lock(&adev->shadow_list_lock);
 495                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 496                 mutex_unlock(&adev->shadow_list_lock);
 497         }
 498
 499         return r;
 500 }
 501
 502 int amdgpu_bo_create(struct amdgpu_device *adev,
 503                      struct amdgpu_bo_param *bp,
 504                      struct amdgpu_bo **bo_ptr)
 505 {
 506         u64 flags = bp->flags;
 507         int r;
 508
 509         bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
 510         r = amdgpu_bo_do_create(adev, bp, bo_ptr);
 511         if (r)
 512                 return r;
 513
 514         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 515                 if (!bp->resv)
 516                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 517                                                         NULL));
 518
 519                 r = amdgpu_bo_create_shadow(adev, bp->size, bp->byte_align, (*bo_ptr));
 520
 521                 if (!bp->resv)
 522                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 523
 524                 if (r)
 525                         amdgpu_bo_unref(bo_ptr);
 526         }
 527
 528         return r;
 529 }
 530
 531 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 532                                struct amdgpu_ring *ring,
 533                                struct amdgpu_bo *bo,
 534                                struct reservation_object *resv,
 535                                struct dma_fence **fence,
 536                                bool direct)
 537
 538 {
 539         struct amdgpu_bo *shadow = bo->shadow;
 540         uint64_t bo_addr, shadow_addr;
 541         int r;
 542
 543         if (!shadow)
 544                 return -EINVAL;
 545
 546         bo_addr = amdgpu_bo_gpu_offset(bo);
 547         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 548
 549         r = reservation_object_reserve_shared(bo->tbo.resv);
 550         if (r)
 551                 goto err;
 552
 553         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 554                                amdgpu_bo_size(bo), resv, fence,
 555                                direct, false);
 556         if (!r)
 557                 amdgpu_bo_fence(bo, *fence, true);
 558
 559 err:
 560         return r;
 561 }
 562
 563 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 564 {
 565         struct ttm_operation_ctx ctx = { false, false };
 566         uint32_t domain;
 567         int r;
 568
 569         if (bo->pin_count)
 570                 return 0;
 571
 572         domain = bo->preferred_domains;
 573
 574 retry:
 575         amdgpu_ttm_placement_from_domain(bo, domain);
 576         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 577         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 578                 domain = bo->allowed_domains;
 579                 goto retry;
 580         }
 581
 582         return r;
 583 }
 584
 585 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 586                                   struct amdgpu_ring *ring,
 587                                   struct amdgpu_bo *bo,
 588                                   struct reservation_object *resv,
 589                                   struct dma_fence **fence,
 590                                   bool direct)
 591
 592 {
 593         struct amdgpu_bo *shadow = bo->shadow;
 594         uint64_t bo_addr, shadow_addr;
 595         int r;
 596
 597         if (!shadow)
 598                 return -EINVAL;
 599
 600         bo_addr = amdgpu_bo_gpu_offset(bo);
 601         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 602
 603         r = reservation_object_reserve_shared(bo->tbo.resv);
 604         if (r)
 605                 goto err;
 606
 607         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 608                                amdgpu_bo_size(bo), resv, fence,
 609                                direct, false);
 610         if (!r)
 611                 amdgpu_bo_fence(bo, *fence, true);
 612
 613 err:
 614         return r;
 615 }
 616
 617 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 618 {
 619         void *kptr;
 620         long r;
 621
 622         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 623                 return -EPERM;
 624
 625         kptr = amdgpu_bo_kptr(bo);
 626         if (kptr) {
 627                 if (ptr)
 628                         *ptr = kptr;
 629                 return 0;
 630         }
 631
 632         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 633                                                 MAX_SCHEDULE_TIMEOUT);
 634         if (r < 0)
 635                 return r;
 636
 637         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 638         if (r)
 639                 return r;
 640
 641         if (ptr)
 642                 *ptr = amdgpu_bo_kptr(bo);
 643
 644         return 0;
 645 }
 646
 647 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 648 {
 649         bool is_iomem;
 650
 651         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 652 }
 653
 654 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 655 {
 656         if (bo->kmap.bo)
 657                 ttm_bo_kunmap(&bo->kmap);
 658 }
 659
 660 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 661 {
 662         if (bo == NULL)
 663                 return NULL;
 664
 665         ttm_bo_reference(&bo->tbo);
 666         return bo;
 667 }
 668
 669 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 670 {
 671         struct ttm_buffer_object *tbo;
 672
 673         if ((*bo) == NULL)
 674                 return;
 675
 676         tbo = &((*bo)->tbo);
 677         ttm_bo_unref(&tbo);
 678         if (tbo == NULL)
 679                 *bo = NULL;
 680 }
 681
 682 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 683                              u64 min_offset, u64 max_offset,
 684                              u64 *gpu_addr)
 685 {
 686         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 687         struct ttm_operation_ctx ctx = { false, false };
 688         int r, i;
 689
 690         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 691                 return -EPERM;
 692
 693         if (WARN_ON_ONCE(min_offset > max_offset))
 694                 return -EINVAL;
 695
 696         /* A shared bo cannot be migrated to VRAM */
 697         if (bo->prime_shared_count) {
 698                 if (domain & AMDGPU_GEM_DOMAIN_GTT)
 699                         domain = AMDGPU_GEM_DOMAIN_GTT;
 700                 else
 701                         return -EINVAL;
 702         }
 703
 704         /* This assumes only APU display buffers are pinned with (VRAM|GTT).
 705          * See function amdgpu_display_supported_domains()
 706          */
 707         if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
 708                 domain = AMDGPU_GEM_DOMAIN_VRAM;
 709                 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
 710                         domain = AMDGPU_GEM_DOMAIN_GTT;
 711         }
 712
 713         if (bo->pin_count) {
 714                 uint32_t mem_type = bo->tbo.mem.mem_type;
 715
 716                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 717                         return -EINVAL;
 718
 719                 bo->pin_count++;
 720                 if (gpu_addr)
 721                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 722
 723                 if (max_offset != 0) {
 724                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 725                         WARN_ON_ONCE(max_offset <
 726                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 727                 }
 728
 729                 return 0;
 730         }
 731
 732         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 733         /* force to pin into visible video ram */
 734         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 735                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 736         amdgpu_ttm_placement_from_domain(bo, domain);
 737         for (i = 0; i < bo->placement.num_placement; i++) {
 738                 unsigned fpfn, lpfn;
 739
 740                 fpfn = min_offset >> PAGE_SHIFT;
 741                 lpfn = max_offset >> PAGE_SHIFT;
 742
 743                 if (fpfn > bo->placements[i].fpfn)
 744                         bo->placements[i].fpfn = fpfn;
 745                 if (!bo->placements[i].lpfn ||
 746                     (lpfn && lpfn < bo->placements[i].lpfn))
 747                         bo->placements[i].lpfn = lpfn;
 748                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 749         }
 750
 751         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 752         if (unlikely(r)) {
 753                 dev_err(adev->dev, "%p pin failed\n", bo);
 754                 goto error;
 755         }
 756
 757         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 758         if (unlikely(r)) {
 759                 dev_err(adev->dev, "%p bind failed\n", bo);
 760                 goto error;
 761         }
 762
 763         bo->pin_count = 1;
 764         if (gpu_addr != NULL)
 765                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 766
 767         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 768         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 769                 adev->vram_pin_size += amdgpu_bo_size(bo);
 770                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 771                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 772         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 773                 adev->gart_pin_size += amdgpu_bo_size(bo);
 774         }
 775
 776 error:
 777         return r;
 778 }
 779
 780 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 781 {
 782         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 783 }
 784
 785 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 786 {
 787         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 788         struct ttm_operation_ctx ctx = { false, false };
 789         int r, i;
 790
 791         if (!bo->pin_count) {
 792                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 793                 return 0;
 794         }
 795         bo->pin_count--;
 796         if (bo->pin_count)
 797                 return 0;
 798         for (i = 0; i < bo->placement.num_placement; i++) {
 799                 bo->placements[i].lpfn = 0;
 800                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 801         }
 802         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 803         if (unlikely(r)) {
 804                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 805                 goto error;
 806         }
 807
 808         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 809                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 810                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 811                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 812         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 813                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 814         }
 815
 816 error:
 817         return r;
 818 }
 819
 820 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 821 {
 822         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 823         if (0 && (adev->flags & AMD_IS_APU)) {
 824                 /* Useless to evict on IGP chips */
 825                 return 0;
 826         }
 827         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 828 }
 829
 830 static const char *amdgpu_vram_names[] = {
 831         "UNKNOWN",
 832         "GDDR1",
 833         "DDR2",
 834         "GDDR3",
 835         "GDDR4",
 836         "GDDR5",
 837         "HBM",
 838         "DDR3",
 839         "DDR4",
 840 };
 841
 842 int amdgpu_bo_init(struct amdgpu_device *adev)
 843 {
 844         /* reserve PAT memory space to WC for VRAM */
 845         arch_io_reserve_memtype_wc(adev->gmc.aper_base,
 846                                    adev->gmc.aper_size);
 847
 848         /* Add an MTRR for the VRAM */
 849         adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
 850                                               adev->gmc.aper_size);
 851         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 852                  adev->gmc.mc_vram_size >> 20,
 853                  (unsigned long long)adev->gmc.aper_size >> 20);
 854         DRM_INFO("RAM width %dbits %s\n",
 855                  adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
 856         return amdgpu_ttm_init(adev);
 857 }
 858
 859 int amdgpu_bo_late_init(struct amdgpu_device *adev)
 860 {
 861         amdgpu_ttm_late_init(adev);
 862
 863         return 0;
 864 }
 865
 866 void amdgpu_bo_fini(struct amdgpu_device *adev)
 867 {
 868         amdgpu_ttm_fini(adev);
 869         arch_phys_wc_del(adev->gmc.vram_mtrr);
 870         arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
 871 }
 872
 873 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 874                              struct vm_area_struct *vma)
 875 {
 876         return ttm_fbdev_mmap(vma, &bo->tbo);
 877 }
 878
 879 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 880 {
 881         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 882
 883         if (adev->family <= AMDGPU_FAMILY_CZ &&
 884             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 885                 return -EINVAL;
 886
 887         bo->tiling_flags = tiling_flags;
 888         return 0;
 889 }
 890
 891 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 892 {
 893         lockdep_assert_held(&bo->tbo.resv->lock.base);
 894
 895         if (tiling_flags)
 896                 *tiling_flags = bo->tiling_flags;
 897 }
 898
 899 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 900                             uint32_t metadata_size, uint64_t flags)
 901 {
 902         void *buffer;
 903
 904         if (!metadata_size) {
 905                 if (bo->metadata_size) {
 906                         kfree(bo->metadata);
 907                         bo->metadata = NULL;
 908                         bo->metadata_size = 0;
 909                 }
 910                 return 0;
 911         }
 912
 913         if (metadata == NULL)
 914                 return -EINVAL;
 915
 916         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 917         if (buffer == NULL)
 918                 return -ENOMEM;
 919
 920         kfree(bo->metadata);
 921         bo->metadata_flags = flags;
 922         bo->metadata = buffer;
 923         bo->metadata_size = metadata_size;
 924
 925         return 0;
 926 }
 927
 928 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 929                            size_t buffer_size, uint32_t *metadata_size,
 930                            uint64_t *flags)
 931 {
 932         if (!buffer && !metadata_size)
 933                 return -EINVAL;
 934
 935         if (buffer) {
 936                 if (buffer_size < bo->metadata_size)
 937                         return -EINVAL;
 938
 939                 if (bo->metadata_size)
 940                         memcpy(buffer, bo->metadata, bo->metadata_size);
 941         }
 942
 943         if (metadata_size)
 944                 *metadata_size = bo->metadata_size;
 945         if (flags)
 946                 *flags = bo->metadata_flags;
 947
 948         return 0;
 949 }
 950
 951 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 952                            bool evict,
 953                            struct ttm_mem_reg *new_mem)
 954 {
 955         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 956         struct amdgpu_bo *abo;
 957         struct ttm_mem_reg *old_mem = &bo->mem;
 958
 959         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 960                 return;
 961
 962         abo = ttm_to_amdgpu_bo(bo);
 963         amdgpu_vm_bo_invalidate(adev, abo, evict);
 964
 965         amdgpu_bo_kunmap(abo);
 966
 967         /* remember the eviction */
 968         if (evict)
 969                 atomic64_inc(&adev->num_evictions);
 970
 971         /* update statistics */
 972         if (!new_mem)
 973                 return;
 974
 975         /* move_notify is called before move happens */
 976         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 977 }
 978
 979 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 980 {
 981         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 982         struct ttm_operation_ctx ctx = { false, false };
 983         struct amdgpu_bo *abo;
 984         unsigned long offset, size;
 985         int r;
 986
 987         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 988                 return 0;
 989
 990         abo = ttm_to_amdgpu_bo(bo);
 991
 992         /* Remember that this BO was accessed by the CPU */
 993         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 994
 995         if (bo->mem.mem_type != TTM_PL_VRAM)
 996                 return 0;
 997
 998         size = bo->mem.num_pages << PAGE_SHIFT;
 999         offset = bo->mem.start << PAGE_SHIFT;
1000         if ((offset + size) <= adev->gmc.visible_vram_size)
1001                 return 0;
1002
1003         /* Can't move a pinned BO to visible VRAM */
1004         if (abo->pin_count > 0)
1005                 return -EINVAL;
1006
1007         /* hurrah the memory is not visible ! */
1008         atomic64_inc(&adev->num_vram_cpu_page_faults);
1009         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1010                                          AMDGPU_GEM_DOMAIN_GTT);
1011
1012         /* Avoid costly evictions; only set GTT as a busy placement */
1013         abo->placement.num_busy_placement = 1;
1014         abo->placement.busy_placement = &abo->placements[1];
1015
1016         r = ttm_bo_validate(bo, &abo->placement, &ctx);
1017         if (unlikely(r != 0))
1018                 return r;
1019
1020         offset = bo->mem.start << PAGE_SHIFT;
1021         /* this should never happen */
1022         if (bo->mem.mem_type == TTM_PL_VRAM &&
1023             (offset + size) > adev->gmc.visible_vram_size)
1024                 return -EINVAL;
1025
1026         return 0;
1027 }
1028
1029 /**
1030  * amdgpu_bo_fence - add fence to buffer object
1031  *
1032  * @bo: buffer object in question
1033  * @fence: fence to add
1034  * @shared: true if fence should be added shared
1035  *
1036  */
1037 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1038                      bool shared)
1039 {
1040         struct reservation_object *resv = bo->tbo.resv;
1041
1042         if (shared)
1043                 reservation_object_add_shared_fence(resv, fence);
1044         else
1045                 reservation_object_add_excl_fence(resv, fence);
1046 }
1047
1048 /**
1049  * amdgpu_bo_gpu_offset - return GPU offset of bo
1050  * @bo: amdgpu object for which we query the offset
1051  *
1052  * Returns current GPU offset of the object.
1053  *
1054  * Note: object should either be pinned or reserved when calling this
1055  * function, it might be useful to add check for this for debugging.
1056  */
1057 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1058 {
1059         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1060         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1061                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1062         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1063                      !bo->pin_count);
1064         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1065         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1066                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1067
1068         return bo->tbo.offset;
1069 }