drivers/gpu/ipu-v3/ipu-prg.c

   1 /*
   2  * Copyright (c) 2016-2017 Lucas Stach, Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  */
  13
  14 #include <drm/drm_fourcc.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regmap.h>
  25 #include <video/imx-ipu-v3.h>
  26
  27 #include "ipu-prv.h"
  28
  29 #define IPU_PRG_CTL                             0x00
  30 #define  IPU_PRG_CTL_BYPASS(i)                  (1 << (0 + i))
  31 #define  IPU_PRG_CTL_SOFT_ARID_MASK             0x3
  32 #define  IPU_PRG_CTL_SOFT_ARID_SHIFT(i)         (8 + i * 2)
  33 #define  IPU_PRG_CTL_SOFT_ARID(i, v)            ((v & 0x3) << (8 + 2 * i))
  34 #define  IPU_PRG_CTL_SO(i)                      (1 << (16 + i))
  35 #define  IPU_PRG_CTL_VFLIP(i)                   (1 << (19 + i))
  36 #define  IPU_PRG_CTL_BLOCK_MODE(i)              (1 << (22 + i))
  37 #define  IPU_PRG_CTL_CNT_LOAD_EN(i)             (1 << (25 + i))
  38 #define  IPU_PRG_CTL_SOFTRST                    (1 << 30)
  39 #define  IPU_PRG_CTL_SHADOW_EN                  (1 << 31)
  40
  41 #define IPU_PRG_STATUS                          0x04
  42 #define  IPU_PRG_STATUS_BUFFER0_READY(i)        (1 << (0 + i * 2))
  43 #define  IPU_PRG_STATUS_BUFFER1_READY(i)        (1 << (1 + i * 2))
  44
  45 #define IPU_PRG_QOS                             0x08
  46 #define  IPU_PRG_QOS_ARID_MASK                  0xf
  47 #define  IPU_PRG_QOS_ARID_SHIFT(i)              (0 + i * 4)
  48
  49 #define IPU_PRG_REG_UPDATE                      0x0c
  50 #define  IPU_PRG_REG_UPDATE_REG_UPDATE          (1 << 0)
  51
  52 #define IPU_PRG_STRIDE(i)                       (0x10 + i * 0x4)
  53 #define  IPU_PRG_STRIDE_STRIDE_MASK             0x3fff
  54
  55 #define IPU_PRG_CROP_LINE                       0x1c
  56
  57 #define IPU_PRG_THD                             0x20
  58
  59 #define IPU_PRG_BADDR(i)                        (0x24 + i * 0x4)
  60
  61 #define IPU_PRG_OFFSET(i)                       (0x30 + i * 0x4)
  62
  63 #define IPU_PRG_ILO(i)                          (0x3c + i * 0x4)
  64
  65 #define IPU_PRG_HEIGHT(i)                       (0x48 + i * 0x4)
  66 #define  IPU_PRG_HEIGHT_PRE_HEIGHT_MASK         0xfff
  67 #define  IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT        0
  68 #define  IPU_PRG_HEIGHT_IPU_HEIGHT_MASK         0xfff
  69 #define  IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT        16
  70
  71 struct ipu_prg_channel {
  72         bool                    enabled;
  73         int                     used_pre;
  74 };
  75
  76 struct ipu_prg {
  77         struct list_head        list;
  78         struct device           *dev;
  79         int                     id;
  80
  81         void __iomem            *regs;
  82         struct clk              *clk_ipg, *clk_axi;
  83         struct regmap           *iomuxc_gpr;
  84         struct ipu_pre          *pres[3];
  85
  86         struct ipu_prg_channel  chan[3];
  87 };
  88
  89 static DEFINE_MUTEX(ipu_prg_list_mutex);
  90 static LIST_HEAD(ipu_prg_list);
  91
  92 struct ipu_prg *
  93 ipu_prg_lookup_by_phandle(struct device *dev, const char *name, int ipu_id)
  94 {
  95         struct device_node *prg_node = of_parse_phandle(dev->of_node,
  96                                                         name, 0);
  97         struct ipu_prg *prg;
  98
  99         mutex_lock(&ipu_prg_list_mutex);
 100         list_for_each_entry(prg, &ipu_prg_list, list) {
 101                 if (prg_node == prg->dev->of_node) {
 102                         mutex_unlock(&ipu_prg_list_mutex);
 103                         device_link_add(dev, prg->dev, DL_FLAG_AUTOREMOVE);
 104                         prg->id = ipu_id;
 105                         return prg;
 106                 }
 107         }
 108         mutex_unlock(&ipu_prg_list_mutex);
 109
 110         return NULL;
 111 }
 112
 113 int ipu_prg_max_active_channels(void)
 114 {
 115         return ipu_pre_get_available_count();
 116 }
 117 EXPORT_SYMBOL_GPL(ipu_prg_max_active_channels);
 118
 119 bool ipu_prg_present(struct ipu_soc *ipu)
 120 {
 121         if (ipu->prg_priv)
 122                 return true;
 123
 124         return false;
 125 }
 126 EXPORT_SYMBOL_GPL(ipu_prg_present);
 127
 128 bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
 129                               uint64_t modifier)
 130 {
 131         const struct drm_format_info *info = drm_format_info(format);
 132
 133         if (info->num_planes != 1)
 134                 return false;
 135
 136         switch (modifier) {
 137         case DRM_FORMAT_MOD_LINEAR:
 138         case DRM_FORMAT_MOD_VIVANTE_TILED:
 139         case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED:
 140                 return true;
 141         default:
 142                 return false;
 143         }
 144 }
 145 EXPORT_SYMBOL_GPL(ipu_prg_format_supported);
 146
 147 int ipu_prg_enable(struct ipu_soc *ipu)
 148 {
 149         struct ipu_prg *prg = ipu->prg_priv;
 150
 151         if (!prg)
 152                 return 0;
 153
 154         return pm_runtime_get_sync(prg->dev);
 155 }
 156 EXPORT_SYMBOL_GPL(ipu_prg_enable);
 157
 158 void ipu_prg_disable(struct ipu_soc *ipu)
 159 {
 160         struct ipu_prg *prg = ipu->prg_priv;
 161
 162         if (!prg)
 163                 return;
 164
 165         pm_runtime_put(prg->dev);
 166 }
 167 EXPORT_SYMBOL_GPL(ipu_prg_disable);
 168
 169 /*
 170  * The channel configuartion functions below are not thread safe, as they
 171  * must be only called from the atomic commit path in the DRM driver, which
 172  * is properly serialized.
 173  */
 174 static int ipu_prg_ipu_to_prg_chan(int ipu_chan)
 175 {
 176         /*
 177          * This isn't clearly documented in the RM, but IPU to PRG channel
 178          * assignment is fixed, as only with this mapping the control signals
 179          * match up.
 180          */
 181         switch (ipu_chan) {
 182         case IPUV3_CHANNEL_MEM_BG_SYNC:
 183                 return 0;
 184         case IPUV3_CHANNEL_MEM_FG_SYNC:
 185                 return 1;
 186         case IPUV3_CHANNEL_MEM_DC_SYNC:
 187                 return 2;
 188         default:
 189                 return -EINVAL;
 190         }
 191 }
 192
 193 static int ipu_prg_get_pre(struct ipu_prg *prg, int prg_chan)
 194 {
 195         int i, ret;
 196
 197         /* channel 0 is special as it is hardwired to one of the PREs */
 198         if (prg_chan == 0) {
 199                 ret = ipu_pre_get(prg->pres[0]);
 200                 if (ret)
 201                         goto fail;
 202                 prg->chan[prg_chan].used_pre = 0;
 203                 return 0;
 204         }
 205
 206         for (i = 1; i < 3; i++) {
 207                 ret = ipu_pre_get(prg->pres[i]);
 208                 if (!ret) {
 209                         u32 val, mux;
 210                         int shift;
 211
 212                         prg->chan[prg_chan].used_pre = i;
 213
 214                         /* configure the PRE to PRG channel mux */
 215                         shift = (i == 1) ? 12 : 14;
 216                         mux = (prg->id << 1) | (prg_chan - 1);
 217                         regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
 218                                            0x3 << shift, mux << shift);
 219
 220                         /* check other mux, must not point to same channel */
 221                         shift = (i == 1) ? 14 : 12;
 222                         regmap_read(prg->iomuxc_gpr, IOMUXC_GPR5, &val);
 223                         if (((val >> shift) & 0x3) == mux) {
 224                                 regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
 225                                                    0x3 << shift,
 226                                                    (mux ^ 0x1) << shift);
 227                         }
 228
 229                         return 0;
 230                 }
 231         }
 232
 233 fail:
 234         dev_err(prg->dev, "could not get PRE for PRG chan %d", prg_chan);
 235         return ret;
 236 }
 237
 238 static void ipu_prg_put_pre(struct ipu_prg *prg, int prg_chan)
 239 {
 240         struct ipu_prg_channel *chan = &prg->chan[prg_chan];
 241
 242         ipu_pre_put(prg->pres[chan->used_pre]);
 243         chan->used_pre = -1;
 244 }
 245
 246 void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan)
 247 {
 248         int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
 249         struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
 250         struct ipu_prg_channel *chan = &prg->chan[prg_chan];
 251         u32 val;
 252
 253         if (!chan->enabled || prg_chan < 0)
 254                 return;
 255
 256         pm_runtime_get_sync(prg->dev);
 257
 258         val = readl(prg->regs + IPU_PRG_CTL);
 259         val |= IPU_PRG_CTL_BYPASS(prg_chan);
 260         writel(val, prg->regs + IPU_PRG_CTL);
 261
 262         val = IPU_PRG_REG_UPDATE_REG_UPDATE;
 263         writel(val, prg->regs + IPU_PRG_REG_UPDATE);
 264
 265         pm_runtime_put(prg->dev);
 266
 267         ipu_prg_put_pre(prg, prg_chan);
 268
 269         chan->enabled = false;
 270 }
 271 EXPORT_SYMBOL_GPL(ipu_prg_channel_disable);
 272
 273 int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
 274                               unsigned int axi_id, unsigned int width,
 275                               unsigned int height, unsigned int stride,
 276                               u32 format, uint64_t modifier, unsigned long *eba)
 277 {
 278         int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
 279         struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
 280         struct ipu_prg_channel *chan = &prg->chan[prg_chan];
 281         u32 val;
 282         int ret;
 283
 284         if (prg_chan < 0)
 285                 return prg_chan;
 286
 287         if (chan->enabled) {
 288                 ipu_pre_update(prg->pres[chan->used_pre], *eba);
 289                 return 0;
 290         }
 291
 292         ret = ipu_prg_get_pre(prg, prg_chan);
 293         if (ret)
 294                 return ret;
 295
 296         ipu_pre_configure(prg->pres[chan->used_pre],
 297                           width, height, stride, format, modifier, *eba);
 298
 299
 300         pm_runtime_get_sync(prg->dev);
 301
 302         val = (stride - 1) & IPU_PRG_STRIDE_STRIDE_MASK;
 303         writel(val, prg->regs + IPU_PRG_STRIDE(prg_chan));
 304
 305         val = ((height & IPU_PRG_HEIGHT_PRE_HEIGHT_MASK) <<
 306                IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT) |
 307               ((height & IPU_PRG_HEIGHT_IPU_HEIGHT_MASK) <<
 308                IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT);
 309         writel(val, prg->regs + IPU_PRG_HEIGHT(prg_chan));
 310
 311         val = ipu_pre_get_baddr(prg->pres[chan->used_pre]);
 312         *eba = val;
 313         writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
 314
 315         val = readl(prg->regs + IPU_PRG_CTL);
 316         /* config AXI ID */
 317         val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
 318                  IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));
 319         val |= IPU_PRG_CTL_SOFT_ARID(prg_chan, axi_id);
 320         /* enable channel */
 321         val &= ~IPU_PRG_CTL_BYPASS(prg_chan);
 322         writel(val, prg->regs + IPU_PRG_CTL);
 323
 324         val = IPU_PRG_REG_UPDATE_REG_UPDATE;
 325         writel(val, prg->regs + IPU_PRG_REG_UPDATE);
 326
 327         /* wait for both double buffers to be filled */
 328         readl_poll_timeout(prg->regs + IPU_PRG_STATUS, val,
 329                            (val & IPU_PRG_STATUS_BUFFER0_READY(prg_chan)) &&
 330                            (val & IPU_PRG_STATUS_BUFFER1_READY(prg_chan)),
 331                            5, 1000);
 332
 333         pm_runtime_put(prg->dev);
 334
 335         chan->enabled = true;
 336         return 0;
 337 }
 338 EXPORT_SYMBOL_GPL(ipu_prg_channel_configure);
 339
 340 static int ipu_prg_probe(struct platform_device *pdev)
 341 {
 342         struct device *dev = &pdev->dev;
 343         struct resource *res;
 344         struct ipu_prg *prg;
 345         u32 val;
 346         int i, ret;
 347
 348         prg = devm_kzalloc(dev, sizeof(*prg), GFP_KERNEL);
 349         if (!prg)
 350                 return -ENOMEM;
 351
 352         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 353         prg->regs = devm_ioremap_resource(&pdev->dev, res);
 354         if (IS_ERR(prg->regs))
 355                 return PTR_ERR(prg->regs);
 356
 357
 358         prg->clk_ipg = devm_clk_get(dev, "ipg");
 359         if (IS_ERR(prg->clk_ipg))
 360                 return PTR_ERR(prg->clk_ipg);
 361
 362         prg->clk_axi = devm_clk_get(dev, "axi");
 363         if (IS_ERR(prg->clk_axi))
 364                 return PTR_ERR(prg->clk_axi);
 365
 366         prg->iomuxc_gpr =
 367                 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 368         if (IS_ERR(prg->iomuxc_gpr))
 369                 return PTR_ERR(prg->iomuxc_gpr);
 370
 371         for (i = 0; i < 3; i++) {
 372                 prg->pres[i] = ipu_pre_lookup_by_phandle(dev, "fsl,pres", i);
 373                 if (!prg->pres[i])
 374                         return -EPROBE_DEFER;
 375         }
 376
 377         ret = clk_prepare_enable(prg->clk_ipg);
 378         if (ret)
 379                 return ret;
 380
 381         ret = clk_prepare_enable(prg->clk_axi);
 382         if (ret) {
 383                 clk_disable_unprepare(prg->clk_ipg);
 384                 return ret;
 385         }
 386
 387         /* init to free running mode */
 388         val = readl(prg->regs + IPU_PRG_CTL);
 389         val |= IPU_PRG_CTL_SHADOW_EN;
 390         writel(val, prg->regs + IPU_PRG_CTL);
 391
 392         /* disable address threshold */
 393         writel(0xffffffff, prg->regs + IPU_PRG_THD);
 394
 395         pm_runtime_set_active(dev);
 396         pm_runtime_enable(dev);
 397
 398         prg->dev = dev;
 399         platform_set_drvdata(pdev, prg);
 400         mutex_lock(&ipu_prg_list_mutex);
 401         list_add(&prg->list, &ipu_prg_list);
 402         mutex_unlock(&ipu_prg_list_mutex);
 403
 404         return 0;
 405 }
 406
 407 static int ipu_prg_remove(struct platform_device *pdev)
 408 {
 409         struct ipu_prg *prg = platform_get_drvdata(pdev);
 410
 411         mutex_lock(&ipu_prg_list_mutex);
 412         list_del(&prg->list);
 413         mutex_unlock(&ipu_prg_list_mutex);
 414
 415         return 0;
 416 }
 417
 418 #ifdef CONFIG_PM
 419 static int prg_suspend(struct device *dev)
 420 {
 421         struct ipu_prg *prg = dev_get_drvdata(dev);
 422
 423         clk_disable_unprepare(prg->clk_axi);
 424         clk_disable_unprepare(prg->clk_ipg);
 425
 426         return 0;
 427 }
 428
 429 static int prg_resume(struct device *dev)
 430 {
 431         struct ipu_prg *prg = dev_get_drvdata(dev);
 432         int ret;
 433
 434         ret = clk_prepare_enable(prg->clk_ipg);
 435         if (ret)
 436                 return ret;
 437
 438         ret = clk_prepare_enable(prg->clk_axi);
 439         if (ret) {
 440                 clk_disable_unprepare(prg->clk_ipg);
 441                 return ret;
 442         }
 443
 444         return 0;
 445 }
 446 #endif
 447
 448 static const struct dev_pm_ops prg_pm_ops = {
 449         SET_RUNTIME_PM_OPS(prg_suspend, prg_resume, NULL)
 450 };
 451
 452 static const struct of_device_id ipu_prg_dt_ids[] = {
 453         { .compatible = "fsl,imx6qp-prg", },
 454         { /* sentinel */ },
 455 };
 456
 457 struct platform_driver ipu_prg_drv = {
 458         .probe          = ipu_prg_probe,
 459         .remove         = ipu_prg_remove,
 460         .driver         = {
 461                 .name   = "imx-ipu-prg",
 462                 .pm     = &prg_pm_ops,
 463                 .of_match_table = ipu_prg_dt_ids,
 464         },
 465 };