2 * Sonics Silicon Backplane
10 * Copyright (C) 2006 Broadcom Corporation.
12 * Licensed under the GNU/GPL. See COPYING for details.
15 #include <linux/ssb/ssb.h>
16 #include <linux/ssb/ssb_regs.h>
17 #include <linux/pci.h>
20 #include <pcmcia/cistpl.h>
21 #include <pcmcia/ds.h>
23 #include "ssb_private.h"
26 const char *ssb_core_name(u16 coreid)
29 case SSB_DEV_CHIPCOMMON:
39 case SSB_DEV_ETHERNET:
40 return "Fast Ethernet";
43 case SSB_DEV_USB11_HOSTDEV:
44 return "USB 1.1 Hostdev";
47 case SSB_DEV_ILINE100:
53 case SSB_DEV_INTERNAL_MEM:
54 return "Internal Memory";
55 case SSB_DEV_MEMC_SDRAM:
61 case SSB_DEV_MIPS_3302:
63 case SSB_DEV_USB11_HOST:
64 return "USB 1.1 Host";
65 case SSB_DEV_USB11_DEV:
66 return "USB 1.1 Device";
67 case SSB_DEV_USB20_HOST:
68 return "USB 2.0 Host";
69 case SSB_DEV_USB20_DEV:
70 return "USB 2.0 Device";
71 case SSB_DEV_SDIO_HOST:
73 case SSB_DEV_ROBOSWITCH:
75 case SSB_DEV_PARA_ATA:
77 case SSB_DEV_SATA_XORDMA:
78 return "SATA XOR-DMA";
79 case SSB_DEV_ETHERNET_GBIT:
80 return "GBit Ethernet";
83 case SSB_DEV_MIMO_PHY:
85 case SSB_DEV_SRAM_CTRLR:
86 return "SRAM Controller";
87 case SSB_DEV_MINI_MACPHY:
89 case SSB_DEV_ARM_1176:
91 case SSB_DEV_ARM_7TDMI:
97 static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
99 u16 chipid_fallback = 0;
101 switch (pci_dev->device) {
103 chipid_fallback = 0x4301;
105 case 0x4305 ... 0x4307:
106 chipid_fallback = 0x4307;
109 chipid_fallback = 0x4402;
111 case 0x4610 ... 0x4615:
112 chipid_fallback = 0x4610;
114 case 0x4710 ... 0x4715:
115 chipid_fallback = 0x4710;
117 case 0x4320 ... 0x4325:
118 chipid_fallback = 0x4309;
120 case PCI_DEVICE_ID_BCM4401:
121 case PCI_DEVICE_ID_BCM4401B0:
122 case PCI_DEVICE_ID_BCM4401B1:
123 chipid_fallback = 0x4401;
126 ssb_printk(KERN_ERR PFX
127 "PCI-ID not in fallback list\n");
130 return chipid_fallback;
133 static u8 chipid_to_nrcores(u16 chipid)
153 ssb_printk(KERN_ERR PFX
154 "CHIPID not in nrcores fallback list\n");
160 static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
165 switch (bus->bustype) {
166 case SSB_BUSTYPE_SSB:
167 offset += current_coreidx * SSB_CORE_SIZE;
169 case SSB_BUSTYPE_PCI:
171 case SSB_BUSTYPE_PCMCIA:
172 if (offset >= 0x800) {
173 ssb_pcmcia_switch_segment(bus, 1);
176 ssb_pcmcia_switch_segment(bus, 0);
177 lo = readw(bus->mmio + offset);
178 hi = readw(bus->mmio + offset + 2);
179 return lo | (hi << 16);
180 case SSB_BUSTYPE_SDIO:
181 offset += current_coreidx * SSB_CORE_SIZE;
182 return ssb_sdio_scan_read32(bus, offset);
184 return readl(bus->mmio + offset);
187 static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
189 switch (bus->bustype) {
190 case SSB_BUSTYPE_SSB:
192 case SSB_BUSTYPE_PCI:
193 return ssb_pci_switch_coreidx(bus, coreidx);
194 case SSB_BUSTYPE_PCMCIA:
195 return ssb_pcmcia_switch_coreidx(bus, coreidx);
196 case SSB_BUSTYPE_SDIO:
197 return ssb_sdio_scan_switch_coreidx(bus, coreidx);
202 void ssb_iounmap(struct ssb_bus *bus)
204 switch (bus->bustype) {
205 case SSB_BUSTYPE_SSB:
206 case SSB_BUSTYPE_PCMCIA:
209 case SSB_BUSTYPE_PCI:
210 #ifdef CONFIG_SSB_PCIHOST
211 pci_iounmap(bus->host_pci, bus->mmio);
213 SSB_BUG_ON(1); /* Can't reach this code. */
216 case SSB_BUSTYPE_SDIO:
220 bus->mapped_device = NULL;
223 static void __iomem *ssb_ioremap(struct ssb_bus *bus,
224 unsigned long baseaddr)
226 void __iomem *mmio = NULL;
228 switch (bus->bustype) {
229 case SSB_BUSTYPE_SSB:
230 /* Only map the first core for now. */
232 case SSB_BUSTYPE_PCMCIA:
233 mmio = ioremap(baseaddr, SSB_CORE_SIZE);
235 case SSB_BUSTYPE_PCI:
236 #ifdef CONFIG_SSB_PCIHOST
237 mmio = pci_iomap(bus->host_pci, 0, ~0UL);
239 SSB_BUG_ON(1); /* Can't reach this code. */
242 case SSB_BUSTYPE_SDIO:
243 /* Nothing to ioremap in the SDIO case, just fake it */
244 mmio = (void __iomem *)baseaddr;
251 static int we_support_multiple_80211_cores(struct ssb_bus *bus)
253 /* More than one 802.11 core is only supported by special chips.
254 * There are chips with two 802.11 cores, but with dangling
255 * pins on the second core. Be careful and reject them here.
258 #ifdef CONFIG_SSB_PCIHOST
259 if (bus->bustype == SSB_BUSTYPE_PCI) {
260 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
261 ((bus->host_pci->device == 0x4313) ||
262 (bus->host_pci->device == 0x431A) ||
263 (bus->host_pci->device == 0x4321) ||
264 (bus->host_pci->device == 0x4324)))
267 #endif /* CONFIG_SSB_PCIHOST */
271 int ssb_bus_scan(struct ssb_bus *bus,
272 unsigned long baseaddr)
276 u32 idhi, cc, rev, tmp;
278 struct ssb_device *dev;
279 int nr_80211_cores = 0;
281 mmio = ssb_ioremap(bus, baseaddr);
286 err = scan_switchcore(bus, 0); /* Switch to first core */
290 idhi = scan_read32(bus, 0, SSB_IDHIGH);
291 cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
292 rev = (idhi & SSB_IDHIGH_RCLO);
293 rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
296 if (cc == SSB_DEV_CHIPCOMMON) {
297 tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
299 bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
300 bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
302 bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
303 SSB_CHIPCO_PACKSHIFT;
305 bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
306 SSB_CHIPCO_NRCORESSHIFT;
308 tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
309 bus->chipco.capabilities = tmp;
311 if (bus->bustype == SSB_BUSTYPE_PCI) {
312 bus->chip_id = pcidev_to_chipid(bus->host_pci);
313 bus->chip_rev = bus->host_pci->revision;
314 bus->chip_package = 0;
316 bus->chip_id = 0x4710;
318 bus->chip_package = 0;
321 if (!bus->nr_devices)
322 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
323 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
324 ssb_printk(KERN_ERR PFX
325 "More than %d ssb cores found (%d)\n",
326 SSB_MAX_NR_CORES, bus->nr_devices);
329 if (bus->bustype == SSB_BUSTYPE_SSB) {
330 /* Now that we know the number of cores,
331 * remap the whole IO space for all cores.
335 mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
341 /* Fetch basic information about each core/device */
342 for (i = 0, dev_i = 0; i < bus->nr_devices; i++) {
343 err = scan_switchcore(bus, i);
346 dev = &(bus->devices[dev_i]);
348 idhi = scan_read32(bus, i, SSB_IDHIGH);
349 dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
350 dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
351 dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
352 dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
357 printk(KERN_DEBUG PFX
359 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
360 i, ssb_core_name(dev->id.coreid),
361 dev->id.coreid, dev->id.revision, dev->id.vendor);
363 switch (dev->id.coreid) {
366 if (nr_80211_cores > 1) {
367 if (!we_support_multiple_80211_cores(bus)) {
368 ssb_dprintk(KERN_INFO PFX "Ignoring additional "
375 #ifdef CONFIG_SSB_DRIVER_EXTIF
376 if (bus->extif.dev) {
377 ssb_printk(KERN_WARNING PFX
378 "WARNING: Multiple EXTIFs found\n");
381 bus->extif.dev = dev;
382 #endif /* CONFIG_SSB_DRIVER_EXTIF */
384 case SSB_DEV_CHIPCOMMON:
385 if (bus->chipco.dev) {
386 ssb_printk(KERN_WARNING PFX
387 "WARNING: Multiple ChipCommon found\n");
390 bus->chipco.dev = dev;
393 case SSB_DEV_MIPS_3302:
394 #ifdef CONFIG_SSB_DRIVER_MIPS
395 if (bus->mipscore.dev) {
396 ssb_printk(KERN_WARNING PFX
397 "WARNING: Multiple MIPS cores found\n");
400 bus->mipscore.dev = dev;
401 #endif /* CONFIG_SSB_DRIVER_MIPS */
405 #ifdef CONFIG_SSB_DRIVER_PCICORE
406 if (bus->bustype == SSB_BUSTYPE_PCI) {
407 /* Ignore PCI cores on PCI-E cards.
408 * Ignore PCI-E cores on PCI cards. */
409 if (dev->id.coreid == SSB_DEV_PCI) {
410 if (pci_is_pcie(bus->host_pci))
413 if (!pci_is_pcie(bus->host_pci))
417 if (bus->pcicore.dev) {
418 ssb_printk(KERN_WARNING PFX
419 "WARNING: Multiple PCI(E) cores found\n");
422 bus->pcicore.dev = dev;
423 #endif /* CONFIG_SSB_DRIVER_PCICORE */
425 case SSB_DEV_ETHERNET:
426 if (bus->bustype == SSB_BUSTYPE_PCI) {
427 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
428 (bus->host_pci->device & 0xFF00) == 0x4300) {
429 /* This is a dangling ethernet core on a
430 * wireless device. Ignore it. */
441 bus->nr_devices = dev_i;