drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "gc/gc_9_0_sh_mask.h"
  35 #include "dce/dce_12_0_offset.h"
  36 #include "dce/dce_12_0_sh_mask.h"
  37 #include "vega10_enum.h"
  38 #include "mmhub/mmhub_1_0_offset.h"
  39 #include "athub/athub_1_0_sh_mask.h"
  40 #include "athub/athub_1_0_offset.h"
  41 #include "oss/osssys_4_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "mmhub_v9_4.h"
  53 #include "umc_v6_1.h"
  54 #include "umc_v6_0.h"
  55
  56 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  57
  58 #include "amdgpu_ras.h"
  59 #include "amdgpu_xgmi.h"
  60
  61 /* add these here since we already include dce12 headers and these are for DCN */
  62 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  63 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  68 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d
  69 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
  70
  71
  72 static const char *gfxhub_client_ids[] = {
  73         "CB",
  74         "DB",
  75         "IA",
  76         "WD",
  77         "CPF",
  78         "CPC",
  79         "CPG",
  80         "RLC",
  81         "TCP",
  82         "SQC (inst)",
  83         "SQC (data)",
  84         "SQG",
  85         "PA",
  86 };
  87
  88 static const char *mmhub_client_ids_raven[][2] = {
  89         [0][0] = "MP1",
  90         [1][0] = "MP0",
  91         [2][0] = "VCN",
  92         [3][0] = "VCNU",
  93         [4][0] = "HDP",
  94         [5][0] = "DCE",
  95         [13][0] = "UTCL2",
  96         [19][0] = "TLS",
  97         [26][0] = "OSS",
  98         [27][0] = "SDMA0",
  99         [0][1] = "MP1",
 100         [1][1] = "MP0",
 101         [2][1] = "VCN",
 102         [3][1] = "VCNU",
 103         [4][1] = "HDP",
 104         [5][1] = "XDP",
 105         [6][1] = "DBGU0",
 106         [7][1] = "DCE",
 107         [8][1] = "DCEDWB0",
 108         [9][1] = "DCEDWB1",
 109         [26][1] = "OSS",
 110         [27][1] = "SDMA0",
 111 };
 112
 113 static const char *mmhub_client_ids_renoir[][2] = {
 114         [0][0] = "MP1",
 115         [1][0] = "MP0",
 116         [2][0] = "HDP",
 117         [4][0] = "DCEDMC",
 118         [5][0] = "DCEVGA",
 119         [13][0] = "UTCL2",
 120         [19][0] = "TLS",
 121         [26][0] = "OSS",
 122         [27][0] = "SDMA0",
 123         [28][0] = "VCN",
 124         [29][0] = "VCNU",
 125         [30][0] = "JPEG",
 126         [0][1] = "MP1",
 127         [1][1] = "MP0",
 128         [2][1] = "HDP",
 129         [3][1] = "XDP",
 130         [6][1] = "DBGU0",
 131         [7][1] = "DCEDMC",
 132         [8][1] = "DCEVGA",
 133         [9][1] = "DCEDWB",
 134         [26][1] = "OSS",
 135         [27][1] = "SDMA0",
 136         [28][1] = "VCN",
 137         [29][1] = "VCNU",
 138         [30][1] = "JPEG",
 139 };
 140
 141 static const char *mmhub_client_ids_vega10[][2] = {
 142         [0][0] = "MP0",
 143         [1][0] = "UVD",
 144         [2][0] = "UVDU",
 145         [3][0] = "HDP",
 146         [13][0] = "UTCL2",
 147         [14][0] = "OSS",
 148         [15][0] = "SDMA1",
 149         [32+0][0] = "VCE0",
 150         [32+1][0] = "VCE0U",
 151         [32+2][0] = "XDMA",
 152         [32+3][0] = "DCE",
 153         [32+4][0] = "MP1",
 154         [32+14][0] = "SDMA0",
 155         [0][1] = "MP0",
 156         [1][1] = "UVD",
 157         [2][1] = "UVDU",
 158         [3][1] = "DBGU0",
 159         [4][1] = "HDP",
 160         [5][1] = "XDP",
 161         [14][1] = "OSS",
 162         [15][1] = "SDMA0",
 163         [32+0][1] = "VCE0",
 164         [32+1][1] = "VCE0U",
 165         [32+2][1] = "XDMA",
 166         [32+3][1] = "DCE",
 167         [32+4][1] = "DCEDWB",
 168         [32+5][1] = "MP1",
 169         [32+6][1] = "DBGU1",
 170         [32+14][1] = "SDMA1",
 171 };
 172
 173 static const char *mmhub_client_ids_vega12[][2] = {
 174         [0][0] = "MP0",
 175         [1][0] = "VCE0",
 176         [2][0] = "VCE0U",
 177         [3][0] = "HDP",
 178         [13][0] = "UTCL2",
 179         [14][0] = "OSS",
 180         [15][0] = "SDMA1",
 181         [32+0][0] = "DCE",
 182         [32+1][0] = "XDMA",
 183         [32+2][0] = "UVD",
 184         [32+3][0] = "UVDU",
 185         [32+4][0] = "MP1",
 186         [32+15][0] = "SDMA0",
 187         [0][1] = "MP0",
 188         [1][1] = "VCE0",
 189         [2][1] = "VCE0U",
 190         [3][1] = "DBGU0",
 191         [4][1] = "HDP",
 192         [5][1] = "XDP",
 193         [14][1] = "OSS",
 194         [15][1] = "SDMA0",
 195         [32+0][1] = "DCE",
 196         [32+1][1] = "DCEDWB",
 197         [32+2][1] = "XDMA",
 198         [32+3][1] = "UVD",
 199         [32+4][1] = "UVDU",
 200         [32+5][1] = "MP1",
 201         [32+6][1] = "DBGU1",
 202         [32+15][1] = "SDMA1",
 203 };
 204
 205 static const char *mmhub_client_ids_vega20[][2] = {
 206         [0][0] = "XDMA",
 207         [1][0] = "DCE",
 208         [2][0] = "VCE0",
 209         [3][0] = "VCE0U",
 210         [4][0] = "UVD",
 211         [5][0] = "UVD1U",
 212         [13][0] = "OSS",
 213         [14][0] = "HDP",
 214         [15][0] = "SDMA0",
 215         [32+0][0] = "UVD",
 216         [32+1][0] = "UVDU",
 217         [32+2][0] = "MP1",
 218         [32+3][0] = "MP0",
 219         [32+12][0] = "UTCL2",
 220         [32+14][0] = "SDMA1",
 221         [0][1] = "XDMA",
 222         [1][1] = "DCE",
 223         [2][1] = "DCEDWB",
 224         [3][1] = "VCE0",
 225         [4][1] = "VCE0U",
 226         [5][1] = "UVD1",
 227         [6][1] = "UVD1U",
 228         [7][1] = "DBGU0",
 229         [8][1] = "XDP",
 230         [13][1] = "OSS",
 231         [14][1] = "HDP",
 232         [15][1] = "SDMA0",
 233         [32+0][1] = "UVD",
 234         [32+1][1] = "UVDU",
 235         [32+2][1] = "DBGU1",
 236         [32+3][1] = "MP1",
 237         [32+4][1] = "MP0",
 238         [32+14][1] = "SDMA1",
 239 };
 240
 241 static const char *mmhub_client_ids_arcturus[][2] = {
 242         [0][0] = "DBGU1",
 243         [1][0] = "XDP",
 244         [2][0] = "MP1",
 245         [14][0] = "HDP",
 246         [171][0] = "JPEG",
 247         [172][0] = "VCN",
 248         [173][0] = "VCNU",
 249         [203][0] = "JPEG1",
 250         [204][0] = "VCN1",
 251         [205][0] = "VCN1U",
 252         [256][0] = "SDMA0",
 253         [257][0] = "SDMA1",
 254         [258][0] = "SDMA2",
 255         [259][0] = "SDMA3",
 256         [260][0] = "SDMA4",
 257         [261][0] = "SDMA5",
 258         [262][0] = "SDMA6",
 259         [263][0] = "SDMA7",
 260         [384][0] = "OSS",
 261         [0][1] = "DBGU1",
 262         [1][1] = "XDP",
 263         [2][1] = "MP1",
 264         [14][1] = "HDP",
 265         [171][1] = "JPEG",
 266         [172][1] = "VCN",
 267         [173][1] = "VCNU",
 268         [203][1] = "JPEG1",
 269         [204][1] = "VCN1",
 270         [205][1] = "VCN1U",
 271         [256][1] = "SDMA0",
 272         [257][1] = "SDMA1",
 273         [258][1] = "SDMA2",
 274         [259][1] = "SDMA3",
 275         [260][1] = "SDMA4",
 276         [261][1] = "SDMA5",
 277         [262][1] = "SDMA6",
 278         [263][1] = "SDMA7",
 279         [384][1] = "OSS",
 280 };
 281
 282 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
 283 {
 284         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
 285         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 286 };
 287
 288 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
 289 {
 290         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
 291         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 292 };
 293
 294 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
 295         (0x000143c0 + 0x00000000),
 296         (0x000143c0 + 0x00000800),
 297         (0x000143c0 + 0x00001000),
 298         (0x000143c0 + 0x00001800),
 299         (0x000543c0 + 0x00000000),
 300         (0x000543c0 + 0x00000800),
 301         (0x000543c0 + 0x00001000),
 302         (0x000543c0 + 0x00001800),
 303         (0x000943c0 + 0x00000000),
 304         (0x000943c0 + 0x00000800),
 305         (0x000943c0 + 0x00001000),
 306         (0x000943c0 + 0x00001800),
 307         (0x000d43c0 + 0x00000000),
 308         (0x000d43c0 + 0x00000800),
 309         (0x000d43c0 + 0x00001000),
 310         (0x000d43c0 + 0x00001800),
 311         (0x001143c0 + 0x00000000),
 312         (0x001143c0 + 0x00000800),
 313         (0x001143c0 + 0x00001000),
 314         (0x001143c0 + 0x00001800),
 315         (0x001543c0 + 0x00000000),
 316         (0x001543c0 + 0x00000800),
 317         (0x001543c0 + 0x00001000),
 318         (0x001543c0 + 0x00001800),
 319         (0x001943c0 + 0x00000000),
 320         (0x001943c0 + 0x00000800),
 321         (0x001943c0 + 0x00001000),
 322         (0x001943c0 + 0x00001800),
 323         (0x001d43c0 + 0x00000000),
 324         (0x001d43c0 + 0x00000800),
 325         (0x001d43c0 + 0x00001000),
 326         (0x001d43c0 + 0x00001800),
 327 };
 328
 329 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 330         (0x000143e0 + 0x00000000),
 331         (0x000143e0 + 0x00000800),
 332         (0x000143e0 + 0x00001000),
 333         (0x000143e0 + 0x00001800),
 334         (0x000543e0 + 0x00000000),
 335         (0x000543e0 + 0x00000800),
 336         (0x000543e0 + 0x00001000),
 337         (0x000543e0 + 0x00001800),
 338         (0x000943e0 + 0x00000000),
 339         (0x000943e0 + 0x00000800),
 340         (0x000943e0 + 0x00001000),
 341         (0x000943e0 + 0x00001800),
 342         (0x000d43e0 + 0x00000000),
 343         (0x000d43e0 + 0x00000800),
 344         (0x000d43e0 + 0x00001000),
 345         (0x000d43e0 + 0x00001800),
 346         (0x001143e0 + 0x00000000),
 347         (0x001143e0 + 0x00000800),
 348         (0x001143e0 + 0x00001000),
 349         (0x001143e0 + 0x00001800),
 350         (0x001543e0 + 0x00000000),
 351         (0x001543e0 + 0x00000800),
 352         (0x001543e0 + 0x00001000),
 353         (0x001543e0 + 0x00001800),
 354         (0x001943e0 + 0x00000000),
 355         (0x001943e0 + 0x00000800),
 356         (0x001943e0 + 0x00001000),
 357         (0x001943e0 + 0x00001800),
 358         (0x001d43e0 + 0x00000000),
 359         (0x001d43e0 + 0x00000800),
 360         (0x001d43e0 + 0x00001000),
 361         (0x001d43e0 + 0x00001800),
 362 };
 363
 364 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 365                 struct amdgpu_irq_src *src,
 366                 unsigned type,
 367                 enum amdgpu_interrupt_state state)
 368 {
 369         u32 bits, i, tmp, reg;
 370
 371         /* Devices newer then VEGA10/12 shall have these programming
 372              sequences performed by PSP BL */
 373         if (adev->asic_type >= CHIP_VEGA20)
 374                 return 0;
 375
 376         bits = 0x7f;
 377
 378         switch (state) {
 379         case AMDGPU_IRQ_STATE_DISABLE:
 380                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 381                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 382                         tmp = RREG32(reg);
 383                         tmp &= ~bits;
 384                         WREG32(reg, tmp);
 385                 }
 386                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 387                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 388                         tmp = RREG32(reg);
 389                         tmp &= ~bits;
 390                         WREG32(reg, tmp);
 391                 }
 392                 break;
 393         case AMDGPU_IRQ_STATE_ENABLE:
 394                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 395                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 396                         tmp = RREG32(reg);
 397                         tmp |= bits;
 398                         WREG32(reg, tmp);
 399                 }
 400                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 401                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 402                         tmp = RREG32(reg);
 403                         tmp |= bits;
 404                         WREG32(reg, tmp);
 405                 }
 406                 break;
 407         default:
 408                 break;
 409         }
 410
 411         return 0;
 412 }
 413
 414 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 415                                         struct amdgpu_irq_src *src,
 416                                         unsigned type,
 417                                         enum amdgpu_interrupt_state state)
 418 {
 419         struct amdgpu_vmhub *hub;
 420         u32 tmp, reg, bits, i, j;
 421
 422         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 423                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 424                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 425                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 426                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 427                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 428                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 429
 430         switch (state) {
 431         case AMDGPU_IRQ_STATE_DISABLE:
 432                 for (j = 0; j < adev->num_vmhubs; j++) {
 433                         hub = &adev->vmhub[j];
 434                         for (i = 0; i < 16; i++) {
 435                                 reg = hub->vm_context0_cntl + i;
 436                                 tmp = RREG32(reg);
 437                                 tmp &= ~bits;
 438                                 WREG32(reg, tmp);
 439                         }
 440                 }
 441                 break;
 442         case AMDGPU_IRQ_STATE_ENABLE:
 443                 for (j = 0; j < adev->num_vmhubs; j++) {
 444                         hub = &adev->vmhub[j];
 445                         for (i = 0; i < 16; i++) {
 446                                 reg = hub->vm_context0_cntl + i;
 447                                 tmp = RREG32(reg);
 448                                 tmp |= bits;
 449                                 WREG32(reg, tmp);
 450                         }
 451                 }
 452                 break;
 453         default:
 454                 break;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 461                                       struct amdgpu_irq_src *source,
 462                                       struct amdgpu_iv_entry *entry)
 463 {
 464         bool retry_fault = !!(entry->src_data[1] & 0x80);
 465         uint32_t status = 0, cid = 0, rw = 0;
 466         struct amdgpu_task_info task_info;
 467         struct amdgpu_vmhub *hub;
 468         const char *mmhub_cid;
 469         const char *hub_name;
 470         u64 addr;
 471
 472         addr = (u64)entry->src_data[0] << 12;
 473         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 474
 475         if (retry_fault) {
 476                 /* Returning 1 here also prevents sending the IV to the KFD */
 477
 478                 /* Process it onyl if it's the first fault for this address */
 479                 if (entry->ih != &adev->irq.ih_soft &&
 480                     amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 481                                              entry->timestamp))
 482                         return 1;
 483
 484                 /* Delegate it to a different ring if the hardware hasn't
 485                  * already done it.
 486                  */
 487                 if (in_interrupt()) {
 488                         amdgpu_irq_delegate(adev, entry, 8);
 489                         return 1;
 490                 }
 491
 492                 /* Try to handle the recoverable page faults by filling page
 493                  * tables
 494                  */
 495                 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr))
 496                         return 1;
 497         }
 498
 499         if (!printk_ratelimit())
 500                 return 0;
 501
 502         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 503                 hub_name = "mmhub0";
 504                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 505         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 506                 hub_name = "mmhub1";
 507                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 508         } else {
 509                 hub_name = "gfxhub0";
 510                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 511         }
 512
 513         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 514         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 515
 516         dev_err(adev->dev,
 517                 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 518                 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 519                 hub_name, retry_fault ? "retry" : "no-retry",
 520                 entry->src_id, entry->ring_id, entry->vmid,
 521                 entry->pasid, task_info.process_name, task_info.tgid,
 522                 task_info.task_name, task_info.pid);
 523         dev_err(adev->dev, "  in page starting at address 0x%012llx from client %d\n",
 524                 addr, entry->client_id);
 525
 526         if (amdgpu_sriov_vf(adev))
 527                 return 0;
 528
 529         /*
 530          * Issue a dummy read to wait for the status register to
 531          * be updated to avoid reading an incorrect value due to
 532          * the new fast GRBM interface.
 533          */
 534         if (entry->vmid_src == AMDGPU_GFXHUB_0)
 535                 RREG32(hub->vm_l2_pro_fault_status);
 536
 537         status = RREG32(hub->vm_l2_pro_fault_status);
 538         cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
 539         rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
 540         WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 541
 542
 543         dev_err(adev->dev,
 544                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 545                 status);
 546         if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
 547                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 548                         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
 549                         gfxhub_client_ids[cid],
 550                         cid);
 551         } else {
 552                 switch (adev->asic_type) {
 553                 case CHIP_VEGA10:
 554                         mmhub_cid = mmhub_client_ids_vega10[cid][rw];
 555                         break;
 556                 case CHIP_VEGA12:
 557                         mmhub_cid = mmhub_client_ids_vega12[cid][rw];
 558                         break;
 559                 case CHIP_VEGA20:
 560                         mmhub_cid = mmhub_client_ids_vega20[cid][rw];
 561                         break;
 562                 case CHIP_ARCTURUS:
 563                         mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
 564                         break;
 565                 case CHIP_RAVEN:
 566                         mmhub_cid = mmhub_client_ids_raven[cid][rw];
 567                         break;
 568                 case CHIP_RENOIR:
 569                         mmhub_cid = mmhub_client_ids_renoir[cid][rw];
 570                         break;
 571                 default:
 572                         mmhub_cid = NULL;
 573                         break;
 574                 }
 575                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 576                         mmhub_cid ? mmhub_cid : "unknown", cid);
 577         }
 578         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 579                 REG_GET_FIELD(status,
 580                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 581         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 582                 REG_GET_FIELD(status,
 583                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 584         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 585                 REG_GET_FIELD(status,
 586                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 587         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 588                 REG_GET_FIELD(status,
 589                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 590         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 591         return 0;
 592 }
 593
 594 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 595         .set = gmc_v9_0_vm_fault_interrupt_state,
 596         .process = gmc_v9_0_process_interrupt,
 597 };
 598
 599
 600 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 601         .set = gmc_v9_0_ecc_interrupt_state,
 602         .process = amdgpu_umc_process_ecc_irq,
 603 };
 604
 605 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 606 {
 607         adev->gmc.vm_fault.num_types = 1;
 608         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 609
 610         if (!amdgpu_sriov_vf(adev)) {
 611                 adev->gmc.ecc_irq.num_types = 1;
 612                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 613         }
 614 }
 615
 616 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 617                                         uint32_t flush_type)
 618 {
 619         u32 req = 0;
 620
 621         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 622                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 623         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 624         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 625         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 626         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 627         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 628         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 629         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 630                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 631
 632         return req;
 633 }
 634
 635 /**
 636  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 637  *
 638  * @adev: amdgpu_device pointer
 639  * @vmhub: vmhub type
 640  *
 641  */
 642 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 643                                        uint32_t vmhub)
 644 {
 645         return ((vmhub == AMDGPU_MMHUB_0 ||
 646                  vmhub == AMDGPU_MMHUB_1) &&
 647                 (!amdgpu_sriov_vf(adev)) &&
 648                 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 649                    (adev->apu_flags & AMD_APU_IS_PICASSO))));
 650 }
 651
 652 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 653                                         uint8_t vmid, uint16_t *p_pasid)
 654 {
 655         uint32_t value;
 656
 657         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 658                      + vmid);
 659         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 660
 661         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 662 }
 663
 664 /*
 665  * GART
 666  * VMID 0 is the physical GPU addresses as used by the kernel.
 667  * VMIDs 1-15 are used for userspace clients and are handled
 668  * by the amdgpu vm/hsa code.
 669  */
 670
 671 /**
 672  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 673  *
 674  * @adev: amdgpu_device pointer
 675  * @vmid: vm instance to flush
 676  * @vmhub: which hub to flush
 677  * @flush_type: the flush type
 678  *
 679  * Flush the TLB for the requested page table using certain type.
 680  */
 681 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 682                                         uint32_t vmhub, uint32_t flush_type)
 683 {
 684         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 685         const unsigned eng = 17;
 686         u32 j, inv_req, inv_req2, tmp;
 687         struct amdgpu_vmhub *hub;
 688
 689         BUG_ON(vmhub >= adev->num_vmhubs);
 690
 691         hub = &adev->vmhub[vmhub];
 692         if (adev->gmc.xgmi.num_physical_nodes &&
 693             adev->asic_type == CHIP_VEGA20) {
 694                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 695                  * heavy-weight TLB flush (type 2), which flushes
 696                  * both. Due to a race condition with concurrent
 697                  * memory accesses using the same TLB cache line, we
 698                  * still need a second TLB flush after this.
 699                  */
 700                 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
 701                 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 702         } else {
 703                 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 704                 inv_req2 = 0;
 705         }
 706
 707         /* This is necessary for a HW workaround under SRIOV as well
 708          * as GFXOFF under bare metal
 709          */
 710         if (adev->gfx.kiq.ring.sched.ready &&
 711             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 712             down_read_trylock(&adev->reset_sem)) {
 713                 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 714                 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 715
 716                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 717                                                    1 << vmid);
 718                 up_read(&adev->reset_sem);
 719                 return;
 720         }
 721
 722         spin_lock(&adev->gmc.invalidate_lock);
 723
 724         /*
 725          * It may lose gpuvm invalidate acknowldege state across power-gating
 726          * off cycle, add semaphore acquire before invalidation and semaphore
 727          * release after invalidation to avoid entering power gated state
 728          * to WA the Issue
 729          */
 730
 731         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 732         if (use_semaphore) {
 733                 for (j = 0; j < adev->usec_timeout; j++) {
 734                         /* a read return value of 1 means semaphore acuqire */
 735                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 736                                             hub->eng_distance * eng);
 737                         if (tmp & 0x1)
 738                                 break;
 739                         udelay(1);
 740                 }
 741
 742                 if (j >= adev->usec_timeout)
 743                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 744         }
 745
 746         do {
 747                 WREG32_NO_KIQ(hub->vm_inv_eng0_req +
 748                               hub->eng_distance * eng, inv_req);
 749
 750                 /*
 751                  * Issue a dummy read to wait for the ACK register to
 752                  * be cleared to avoid a false ACK due to the new fast
 753                  * GRBM interface.
 754                  */
 755                 if (vmhub == AMDGPU_GFXHUB_0)
 756                         RREG32_NO_KIQ(hub->vm_inv_eng0_req +
 757                                       hub->eng_distance * eng);
 758
 759                 for (j = 0; j < adev->usec_timeout; j++) {
 760                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
 761                                             hub->eng_distance * eng);
 762                         if (tmp & (1 << vmid))
 763                                 break;
 764                         udelay(1);
 765                 }
 766
 767                 inv_req = inv_req2;
 768                 inv_req2 = 0;
 769         } while (inv_req);
 770
 771         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 772         if (use_semaphore)
 773                 /*
 774                  * add semaphore release after invalidation,
 775                  * write with 0 means semaphore release
 776                  */
 777                 WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 778                               hub->eng_distance * eng, 0);
 779
 780         spin_unlock(&adev->gmc.invalidate_lock);
 781
 782         if (j < adev->usec_timeout)
 783                 return;
 784
 785         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 786 }
 787
 788 /**
 789  * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 790  *
 791  * @adev: amdgpu_device pointer
 792  * @pasid: pasid to be flush
 793  * @flush_type: the flush type
 794  * @all_hub: flush all hubs
 795  *
 796  * Flush the TLB for the requested pasid.
 797  */
 798 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 799                                         uint16_t pasid, uint32_t flush_type,
 800                                         bool all_hub)
 801 {
 802         int vmid, i;
 803         signed long r;
 804         uint32_t seq;
 805         uint16_t queried_pasid;
 806         bool ret;
 807         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 808         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 809
 810         if (amdgpu_in_reset(adev))
 811                 return -EIO;
 812
 813         if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) {
 814                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 815                  * heavy-weight TLB flush (type 2), which flushes
 816                  * both. Due to a race condition with concurrent
 817                  * memory accesses using the same TLB cache line, we
 818                  * still need a second TLB flush after this.
 819                  */
 820                 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
 821                                        adev->asic_type == CHIP_VEGA20);
 822                 /* 2 dwords flush + 8 dwords fence */
 823                 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
 824
 825                 if (vega20_xgmi_wa)
 826                         ndw += kiq->pmf->invalidate_tlbs_size;
 827
 828                 spin_lock(&adev->gfx.kiq.ring_lock);
 829                 /* 2 dwords flush + 8 dwords fence */
 830                 amdgpu_ring_alloc(ring, ndw);
 831                 if (vega20_xgmi_wa)
 832                         kiq->pmf->kiq_invalidate_tlbs(ring,
 833                                                       pasid, 2, all_hub);
 834                 kiq->pmf->kiq_invalidate_tlbs(ring,
 835                                         pasid, flush_type, all_hub);
 836                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 837                 if (r) {
 838                         amdgpu_ring_undo(ring);
 839                         spin_unlock(&adev->gfx.kiq.ring_lock);
 840                         up_read(&adev->reset_sem);
 841                         return -ETIME;
 842                 }
 843
 844                 amdgpu_ring_commit(ring);
 845                 spin_unlock(&adev->gfx.kiq.ring_lock);
 846                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 847                 if (r < 1) {
 848                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 849                         up_read(&adev->reset_sem);
 850                         return -ETIME;
 851                 }
 852                 up_read(&adev->reset_sem);
 853                 return 0;
 854         }
 855
 856         for (vmid = 1; vmid < 16; vmid++) {
 857
 858                 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 859                                 &queried_pasid);
 860                 if (ret && queried_pasid == pasid) {
 861                         if (all_hub) {
 862                                 for (i = 0; i < adev->num_vmhubs; i++)
 863                                         gmc_v9_0_flush_gpu_tlb(adev, vmid,
 864                                                         i, flush_type);
 865                         } else {
 866                                 gmc_v9_0_flush_gpu_tlb(adev, vmid,
 867                                                 AMDGPU_GFXHUB_0, flush_type);
 868                         }
 869                         break;
 870                 }
 871         }
 872
 873         return 0;
 874
 875 }
 876
 877 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 878                                             unsigned vmid, uint64_t pd_addr)
 879 {
 880         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 881         struct amdgpu_device *adev = ring->adev;
 882         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 883         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 884         unsigned eng = ring->vm_inv_eng;
 885
 886         /*
 887          * It may lose gpuvm invalidate acknowldege state across power-gating
 888          * off cycle, add semaphore acquire before invalidation and semaphore
 889          * release after invalidation to avoid entering power gated state
 890          * to WA the Issue
 891          */
 892
 893         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 894         if (use_semaphore)
 895                 /* a read return value of 1 means semaphore acuqire */
 896                 amdgpu_ring_emit_reg_wait(ring,
 897                                           hub->vm_inv_eng0_sem +
 898                                           hub->eng_distance * eng, 0x1, 0x1);
 899
 900         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 901                               (hub->ctx_addr_distance * vmid),
 902                               lower_32_bits(pd_addr));
 903
 904         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 905                               (hub->ctx_addr_distance * vmid),
 906                               upper_32_bits(pd_addr));
 907
 908         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 909                                             hub->eng_distance * eng,
 910                                             hub->vm_inv_eng0_ack +
 911                                             hub->eng_distance * eng,
 912                                             req, 1 << vmid);
 913
 914         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 915         if (use_semaphore)
 916                 /*
 917                  * add semaphore release after invalidation,
 918                  * write with 0 means semaphore release
 919                  */
 920                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 921                                       hub->eng_distance * eng, 0);
 922
 923         return pd_addr;
 924 }
 925
 926 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 927                                         unsigned pasid)
 928 {
 929         struct amdgpu_device *adev = ring->adev;
 930         uint32_t reg;
 931
 932         /* Do nothing because there's no lut register for mmhub1. */
 933         if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
 934                 return;
 935
 936         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 937                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 938         else
 939                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 940
 941         amdgpu_ring_emit_wreg(ring, reg, pasid);
 942 }
 943
 944 /*
 945  * PTE format on VEGA 10:
 946  * 63:59 reserved
 947  * 58:57 mtype
 948  * 56 F
 949  * 55 L
 950  * 54 P
 951  * 53 SW
 952  * 52 T
 953  * 50:48 reserved
 954  * 47:12 4k physical page base address
 955  * 11:7 fragment
 956  * 6 write
 957  * 5 read
 958  * 4 exe
 959  * 3 Z
 960  * 2 snooped
 961  * 1 system
 962  * 0 valid
 963  *
 964  * PDE format on VEGA 10:
 965  * 63:59 block fragment size
 966  * 58:55 reserved
 967  * 54 P
 968  * 53:48 reserved
 969  * 47:6 physical base address of PD or PTE
 970  * 5:3 reserved
 971  * 2 C
 972  * 1 system
 973  * 0 valid
 974  */
 975
 976 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 977
 978 {
 979         switch (flags) {
 980         case AMDGPU_VM_MTYPE_DEFAULT:
 981                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 982         case AMDGPU_VM_MTYPE_NC:
 983                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 984         case AMDGPU_VM_MTYPE_WC:
 985                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
 986         case AMDGPU_VM_MTYPE_RW:
 987                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
 988         case AMDGPU_VM_MTYPE_CC:
 989                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
 990         case AMDGPU_VM_MTYPE_UC:
 991                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
 992         default:
 993                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 994         }
 995 }
 996
 997 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 998                                 uint64_t *addr, uint64_t *flags)
 999 {
1000         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1001                 *addr = adev->vm_manager.vram_base_offset + *addr -
1002                         adev->gmc.vram_start;
1003         BUG_ON(*addr & 0xFFFF00000000003FULL);
1004
1005         if (!adev->gmc.translate_further)
1006                 return;
1007
1008         if (level == AMDGPU_VM_PDB1) {
1009                 /* Set the block fragment size */
1010                 if (!(*flags & AMDGPU_PDE_PTE))
1011                         *flags |= AMDGPU_PDE_BFS(0x9);
1012
1013         } else if (level == AMDGPU_VM_PDB0) {
1014                 if (*flags & AMDGPU_PDE_PTE)
1015                         *flags &= ~AMDGPU_PDE_PTE;
1016                 else
1017                         *flags |= AMDGPU_PTE_TF;
1018         }
1019 }
1020
1021 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1022                                 struct amdgpu_bo_va_mapping *mapping,
1023                                 uint64_t *flags)
1024 {
1025         *flags &= ~AMDGPU_PTE_EXECUTABLE;
1026         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1027
1028         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1029         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1030
1031         if (mapping->flags & AMDGPU_PTE_PRT) {
1032                 *flags |= AMDGPU_PTE_PRT;
1033                 *flags &= ~AMDGPU_PTE_VALID;
1034         }
1035
1036         if (adev->asic_type == CHIP_ARCTURUS &&
1037             !(*flags & AMDGPU_PTE_SYSTEM) &&
1038             mapping->bo_va->is_xgmi)
1039                 *flags |= AMDGPU_PTE_SNOOPED;
1040 }
1041
1042 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1043 {
1044         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1045         unsigned size;
1046
1047         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1048                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1049         } else {
1050                 u32 viewport;
1051
1052                 switch (adev->asic_type) {
1053                 case CHIP_RAVEN:
1054                 case CHIP_RENOIR:
1055                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1056                         size = (REG_GET_FIELD(viewport,
1057                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1058                                 REG_GET_FIELD(viewport,
1059                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1060                                 4);
1061                         break;
1062                 case CHIP_VEGA10:
1063                 case CHIP_VEGA12:
1064                 case CHIP_VEGA20:
1065                 default:
1066                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1067                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1068                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1069                                 4);
1070                         break;
1071                 }
1072         }
1073
1074         return size;
1075 }
1076
1077 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1078         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1079         .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1080         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1081         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1082         .map_mtype = gmc_v9_0_map_mtype,
1083         .get_vm_pde = gmc_v9_0_get_vm_pde,
1084         .get_vm_pte = gmc_v9_0_get_vm_pte,
1085         .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1086 };
1087
1088 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1089 {
1090         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1091 }
1092
1093 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1094 {
1095         switch (adev->asic_type) {
1096         case CHIP_VEGA10:
1097                 adev->umc.funcs = &umc_v6_0_funcs;
1098                 break;
1099         case CHIP_VEGA20:
1100                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1101                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1102                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1103                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1104                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1105                 adev->umc.funcs = &umc_v6_1_funcs;
1106                 break;
1107         case CHIP_ARCTURUS:
1108                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1109                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1110                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1111                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1112                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1113                 adev->umc.funcs = &umc_v6_1_funcs;
1114                 break;
1115         default:
1116                 break;
1117         }
1118 }
1119
1120 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1121 {
1122         switch (adev->asic_type) {
1123         case CHIP_ARCTURUS:
1124                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1125                 break;
1126         default:
1127                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1128                 break;
1129         }
1130 }
1131
1132 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1133 {
1134         adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1135 }
1136
1137 static int gmc_v9_0_early_init(void *handle)
1138 {
1139         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1140
1141         gmc_v9_0_set_gmc_funcs(adev);
1142         gmc_v9_0_set_irq_funcs(adev);
1143         gmc_v9_0_set_umc_funcs(adev);
1144         gmc_v9_0_set_mmhub_funcs(adev);
1145         gmc_v9_0_set_gfxhub_funcs(adev);
1146
1147         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1148         adev->gmc.shared_aperture_end =
1149                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1150         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1151         adev->gmc.private_aperture_end =
1152                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1153
1154         return 0;
1155 }
1156
1157 static int gmc_v9_0_late_init(void *handle)
1158 {
1159         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1160         int r;
1161
1162         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1163         if (r)
1164                 return r;
1165
1166         /*
1167          * Workaround performance drop issue with VBIOS enables partial
1168          * writes, while disables HBM ECC for vega10.
1169          */
1170         if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
1171                 if (!(adev->ras_features & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1172                         if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
1173                                 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1174                 }
1175         }
1176
1177         if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
1178                 adev->mmhub.funcs->reset_ras_error_count(adev);
1179
1180         r = amdgpu_gmc_ras_late_init(adev);
1181         if (r)
1182                 return r;
1183
1184         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1185 }
1186
1187 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1188                                         struct amdgpu_gmc *mc)
1189 {
1190         u64 base = 0;
1191
1192         if (!amdgpu_sriov_vf(adev))
1193                 base = adev->mmhub.funcs->get_fb_location(adev);
1194
1195         /* add the xgmi offset of the physical node */
1196         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1197         amdgpu_gmc_vram_location(adev, mc, base);
1198         amdgpu_gmc_gart_location(adev, mc);
1199         amdgpu_gmc_agp_location(adev, mc);
1200         /* base offset of vram pages */
1201         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1202
1203         /* XXX: add the xgmi offset of the physical node? */
1204         adev->vm_manager.vram_base_offset +=
1205                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1206 }
1207
1208 /**
1209  * gmc_v9_0_mc_init - initialize the memory controller driver params
1210  *
1211  * @adev: amdgpu_device pointer
1212  *
1213  * Look up the amount of vram, vram width, and decide how to place
1214  * vram and gart within the GPU's physical address space.
1215  * Returns 0 for success.
1216  */
1217 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1218 {
1219         int r;
1220
1221         /* size in MB on si */
1222         adev->gmc.mc_vram_size =
1223                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1224         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1225
1226         if (!(adev->flags & AMD_IS_APU)) {
1227                 r = amdgpu_device_resize_fb_bar(adev);
1228                 if (r)
1229                         return r;
1230         }
1231         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1232         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1233
1234 #ifdef CONFIG_X86_64
1235         if (adev->flags & AMD_IS_APU) {
1236                 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1237                 adev->gmc.aper_size = adev->gmc.real_vram_size;
1238         }
1239 #endif
1240         /* In case the PCI BAR is larger than the actual amount of vram */
1241         adev->gmc.visible_vram_size = adev->gmc.aper_size;
1242         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1243                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1244
1245         /* set the gart size */
1246         if (amdgpu_gart_size == -1) {
1247                 switch (adev->asic_type) {
1248                 case CHIP_VEGA10:  /* all engines support GPUVM */
1249                 case CHIP_VEGA12:  /* all engines support GPUVM */
1250                 case CHIP_VEGA20:
1251                 case CHIP_ARCTURUS:
1252                 default:
1253                         adev->gmc.gart_size = 512ULL << 20;
1254                         break;
1255                 case CHIP_RAVEN:   /* DCE SG support */
1256                 case CHIP_RENOIR:
1257                         adev->gmc.gart_size = 1024ULL << 20;
1258                         break;
1259                 }
1260         } else {
1261                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1262         }
1263
1264         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1265
1266         return 0;
1267 }
1268
1269 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1270 {
1271         int r;
1272
1273         if (adev->gart.bo) {
1274                 WARN(1, "VEGA10 PCIE GART already initialized\n");
1275                 return 0;
1276         }
1277         /* Initialize common gart structure */
1278         r = amdgpu_gart_init(adev);
1279         if (r)
1280                 return r;
1281         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1282         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1283                                  AMDGPU_PTE_EXECUTABLE;
1284         return amdgpu_gart_table_vram_alloc(adev);
1285 }
1286
1287 /**
1288  * gmc_v9_0_save_registers - saves regs
1289  *
1290  * @adev: amdgpu_device pointer
1291  *
1292  * This saves potential register values that should be
1293  * restored upon resume
1294  */
1295 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1296 {
1297         if (adev->asic_type == CHIP_RAVEN)
1298                 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1299 }
1300
1301 static int gmc_v9_0_sw_init(void *handle)
1302 {
1303         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305
1306         adev->gfxhub.funcs->init(adev);
1307
1308         adev->mmhub.funcs->init(adev);
1309
1310         spin_lock_init(&adev->gmc.invalidate_lock);
1311
1312         r = amdgpu_atomfirmware_get_vram_info(adev,
1313                 &vram_width, &vram_type, &vram_vendor);
1314         if (amdgpu_sriov_vf(adev))
1315                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1316                  * and DF related registers is not readable, seems hardcord is the
1317                  * only way to set the correct vram_width
1318                  */
1319                 adev->gmc.vram_width = 2048;
1320         else if (amdgpu_emu_mode != 1)
1321                 adev->gmc.vram_width = vram_width;
1322
1323         if (!adev->gmc.vram_width) {
1324                 int chansize, numchan;
1325
1326                 /* hbm memory channel size */
1327                 if (adev->flags & AMD_IS_APU)
1328                         chansize = 64;
1329                 else
1330                         chansize = 128;
1331
1332                 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1333                 adev->gmc.vram_width = numchan * chansize;
1334         }
1335
1336         adev->gmc.vram_type = vram_type;
1337         adev->gmc.vram_vendor = vram_vendor;
1338         switch (adev->asic_type) {
1339         case CHIP_RAVEN:
1340                 adev->num_vmhubs = 2;
1341
1342                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1343                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1344                 } else {
1345                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1346                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1347                         adev->gmc.translate_further =
1348                                 adev->vm_manager.num_level > 1;
1349                 }
1350                 break;
1351         case CHIP_VEGA10:
1352         case CHIP_VEGA12:
1353         case CHIP_VEGA20:
1354         case CHIP_RENOIR:
1355                 adev->num_vmhubs = 2;
1356
1357
1358                 /*
1359                  * To fulfill 4-level page support,
1360                  * vm size is 256TB (48bit), maximum size of Vega10,
1361                  * block size 512 (9bit)
1362                  */
1363                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1364                 if (amdgpu_sriov_vf(adev))
1365                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1366                 else
1367                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1368                 break;
1369         case CHIP_ARCTURUS:
1370                 adev->num_vmhubs = 3;
1371
1372                 /* Keep the vm size same with Vega20 */
1373                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1374                 break;
1375         default:
1376                 break;
1377         }
1378
1379         /* This interrupt is VMC page fault.*/
1380         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1381                                 &adev->gmc.vm_fault);
1382         if (r)
1383                 return r;
1384
1385         if (adev->asic_type == CHIP_ARCTURUS) {
1386                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1387                                         &adev->gmc.vm_fault);
1388                 if (r)
1389                         return r;
1390         }
1391
1392         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1393                                 &adev->gmc.vm_fault);
1394
1395         if (r)
1396                 return r;
1397
1398         if (!amdgpu_sriov_vf(adev)) {
1399                 /* interrupt sent to DF. */
1400                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1401                                       &adev->gmc.ecc_irq);
1402                 if (r)
1403                         return r;
1404         }
1405
1406         /* Set the internal MC address mask
1407          * This is the max address of the GPU's
1408          * internal address space.
1409          */
1410         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1411
1412         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1413         if (r) {
1414                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1415                 return r;
1416         }
1417         adev->need_swiotlb = drm_need_swiotlb(44);
1418
1419         if (adev->gmc.xgmi.supported) {
1420                 r = adev->gfxhub.funcs->get_xgmi_info(adev);
1421                 if (r)
1422                         return r;
1423         }
1424
1425         r = gmc_v9_0_mc_init(adev);
1426         if (r)
1427                 return r;
1428
1429         amdgpu_gmc_get_vbios_allocations(adev);
1430
1431         /* Memory manager */
1432         r = amdgpu_bo_init(adev);
1433         if (r)
1434                 return r;
1435
1436         r = gmc_v9_0_gart_init(adev);
1437         if (r)
1438                 return r;
1439
1440         /*
1441          * number of VMs
1442          * VMID 0 is reserved for System
1443          * amdgpu graphics/compute will use VMIDs 1..n-1
1444          * amdkfd will use VMIDs n..15
1445          *
1446          * The first KFD VMID is 8 for GPUs with graphics, 3 for
1447          * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1448          * for video processing.
1449          */
1450         adev->vm_manager.first_kfd_vmid =
1451                 adev->asic_type == CHIP_ARCTURUS ? 3 : 8;
1452
1453         amdgpu_vm_manager_init(adev);
1454
1455         gmc_v9_0_save_registers(adev);
1456
1457         return 0;
1458 }
1459
1460 static int gmc_v9_0_sw_fini(void *handle)
1461 {
1462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1463
1464         amdgpu_gmc_ras_fini(adev);
1465         amdgpu_gem_force_release(adev);
1466         amdgpu_vm_manager_fini(adev);
1467         amdgpu_gart_table_vram_free(adev);
1468         amdgpu_bo_fini(adev);
1469         amdgpu_gart_fini(adev);
1470
1471         return 0;
1472 }
1473
1474 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1475 {
1476
1477         switch (adev->asic_type) {
1478         case CHIP_VEGA10:
1479                 if (amdgpu_sriov_vf(adev))
1480                         break;
1481                 fallthrough;
1482         case CHIP_VEGA20:
1483                 soc15_program_register_sequence(adev,
1484                                                 golden_settings_mmhub_1_0_0,
1485                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1486                 soc15_program_register_sequence(adev,
1487                                                 golden_settings_athub_1_0_0,
1488                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1489                 break;
1490         case CHIP_VEGA12:
1491                 break;
1492         case CHIP_RAVEN:
1493                 /* TODO for renoir */
1494                 soc15_program_register_sequence(adev,
1495                                                 golden_settings_athub_1_0_0,
1496                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1497                 break;
1498         default:
1499                 break;
1500         }
1501 }
1502
1503 /**
1504  * gmc_v9_0_restore_registers - restores regs
1505  *
1506  * @adev: amdgpu_device pointer
1507  *
1508  * This restores register values, saved at suspend.
1509  */
1510 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1511 {
1512         if (adev->asic_type == CHIP_RAVEN) {
1513                 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1514                 WARN_ON(adev->gmc.sdpif_register !=
1515                         RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
1516         }
1517 }
1518
1519 /**
1520  * gmc_v9_0_gart_enable - gart enable
1521  *
1522  * @adev: amdgpu_device pointer
1523  */
1524 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1525 {
1526         int r;
1527
1528         if (adev->gart.bo == NULL) {
1529                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1530                 return -EINVAL;
1531         }
1532         r = amdgpu_gart_table_vram_pin(adev);
1533         if (r)
1534                 return r;
1535
1536         r = adev->gfxhub.funcs->gart_enable(adev);
1537         if (r)
1538                 return r;
1539
1540         r = adev->mmhub.funcs->gart_enable(adev);
1541         if (r)
1542                 return r;
1543
1544         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1545                  (unsigned)(adev->gmc.gart_size >> 20),
1546                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1547         adev->gart.ready = true;
1548         return 0;
1549 }
1550
1551 static int gmc_v9_0_hw_init(void *handle)
1552 {
1553         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1554         bool value;
1555         int r, i;
1556
1557         /* The sequence of these two function calls matters.*/
1558         gmc_v9_0_init_golden_registers(adev);
1559
1560         if (adev->mode_info.num_crtc) {
1561                 /* Lockout access through VGA aperture*/
1562                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1563                 /* disable VGA render */
1564                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1565         }
1566
1567         if (adev->mmhub.funcs->update_power_gating)
1568                 adev->mmhub.funcs->update_power_gating(adev, true);
1569
1570         adev->hdp.funcs->init_registers(adev);
1571
1572         /* After HDP is initialized, flush HDP.*/
1573         adev->hdp.funcs->flush_hdp(adev, NULL);
1574
1575         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1576                 value = false;
1577         else
1578                 value = true;
1579
1580         if (!amdgpu_sriov_vf(adev)) {
1581                 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1582                 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1583         }
1584         for (i = 0; i < adev->num_vmhubs; ++i)
1585                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1586
1587         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1588                 adev->umc.funcs->init_registers(adev);
1589
1590         r = gmc_v9_0_gart_enable(adev);
1591
1592         return r;
1593 }
1594
1595 /**
1596  * gmc_v9_0_gart_disable - gart disable
1597  *
1598  * @adev: amdgpu_device pointer
1599  *
1600  * This disables all VM page table.
1601  */
1602 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1603 {
1604         adev->gfxhub.funcs->gart_disable(adev);
1605         adev->mmhub.funcs->gart_disable(adev);
1606         amdgpu_gart_table_vram_unpin(adev);
1607 }
1608
1609 static int gmc_v9_0_hw_fini(void *handle)
1610 {
1611         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1612
1613         if (amdgpu_sriov_vf(adev)) {
1614                 /* full access mode, so don't touch any GMC register */
1615                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1616                 return 0;
1617         }
1618
1619         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1620         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1621         gmc_v9_0_gart_disable(adev);
1622
1623         return 0;
1624 }
1625
1626 static int gmc_v9_0_suspend(void *handle)
1627 {
1628         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1629
1630         return gmc_v9_0_hw_fini(adev);
1631 }
1632
1633 static int gmc_v9_0_resume(void *handle)
1634 {
1635         int r;
1636         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1637
1638         r = gmc_v9_0_hw_init(adev);
1639         if (r)
1640                 return r;
1641
1642         amdgpu_vmid_reset_all(adev);
1643
1644         return 0;
1645 }
1646
1647 static bool gmc_v9_0_is_idle(void *handle)
1648 {
1649         /* MC is always ready in GMC v9.*/
1650         return true;
1651 }
1652
1653 static int gmc_v9_0_wait_for_idle(void *handle)
1654 {
1655         /* There is no need to wait for MC idle in GMC v9.*/
1656         return 0;
1657 }
1658
1659 static int gmc_v9_0_soft_reset(void *handle)
1660 {
1661         /* XXX for emulation.*/
1662         return 0;
1663 }
1664
1665 static int gmc_v9_0_set_clockgating_state(void *handle,
1666                                         enum amd_clockgating_state state)
1667 {
1668         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1669
1670         adev->mmhub.funcs->set_clockgating(adev, state);
1671
1672         athub_v1_0_set_clockgating(adev, state);
1673
1674         return 0;
1675 }
1676
1677 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1678 {
1679         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1680
1681         adev->mmhub.funcs->get_clockgating(adev, flags);
1682
1683         athub_v1_0_get_clockgating(adev, flags);
1684 }
1685
1686 static int gmc_v9_0_set_powergating_state(void *handle,
1687                                         enum amd_powergating_state state)
1688 {
1689         return 0;
1690 }
1691
1692 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1693         .name = "gmc_v9_0",
1694         .early_init = gmc_v9_0_early_init,
1695         .late_init = gmc_v9_0_late_init,
1696         .sw_init = gmc_v9_0_sw_init,
1697         .sw_fini = gmc_v9_0_sw_fini,
1698         .hw_init = gmc_v9_0_hw_init,
1699         .hw_fini = gmc_v9_0_hw_fini,
1700         .suspend = gmc_v9_0_suspend,
1701         .resume = gmc_v9_0_resume,
1702         .is_idle = gmc_v9_0_is_idle,
1703         .wait_for_idle = gmc_v9_0_wait_for_idle,
1704         .soft_reset = gmc_v9_0_soft_reset,
1705         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1706         .set_powergating_state = gmc_v9_0_set_powergating_state,
1707         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1708 };
1709
1710 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1711 {
1712         .type = AMD_IP_BLOCK_TYPE_GMC,
1713         .major = 9,
1714         .minor = 0,
1715         .rev = 0,
1716         .funcs = &gmc_v9_0_ip_funcs,
1717 };