drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 104 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 106 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 108 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 110 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 112 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 114
 115 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 116 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 117 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 118 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 119 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 120 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 121
 122 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 123 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 124 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 125 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 126 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 127 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 128 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 129 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 130 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 131 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 132 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 133
 134 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 135 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 136 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 137 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 138 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 139 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 140
 141 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 142 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 143 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 144 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 145 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 146 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 147
 148 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 149 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 150 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 151 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 152 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 153 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 154
 155 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 156 {
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 197 };
 198
 199 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 200 {
 201         /* Pending on emulation bring up */
 202 };
 203
 204 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 205 {
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1258 };
1259
1260 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1261 {
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1300 };
1301
1302 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1303 {
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1344 };
1345
1346 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1347 {
1348         static void *scratch_reg0;
1349         static void *scratch_reg1;
1350         static void *scratch_reg2;
1351         static void *scratch_reg3;
1352         static void *spare_int;
1353         static uint32_t grbm_cntl;
1354         static uint32_t grbm_idx;
1355         uint32_t i = 0;
1356         uint32_t retries = 50000;
1357
1358         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1359         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1360         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1361         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1362         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1363
1364         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1365         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1366
1367         if (amdgpu_sriov_runtime(adev)) {
1368                 pr_err("shouldn't call rlcg write register during runtime\n");
1369                 return;
1370         }
1371
1372         writel(v, scratch_reg0);
1373         writel(offset | 0x80000000, scratch_reg1);
1374         writel(1, spare_int);
1375         for (i = 0; i < retries; i++) {
1376                 u32 tmp;
1377
1378                 tmp = readl(scratch_reg1);
1379                 if (!(tmp & 0x80000000))
1380                         break;
1381
1382                 udelay(10);
1383         }
1384
1385         if (i >= retries)
1386                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1387 }
1388
1389 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1390 {
1391         /* Pending on emulation bring up */
1392 };
1393
1394 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1395 {
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2016 };
2017
2018 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2019 {
2020         /* Pending on emulation bring up */
2021 };
2022
2023 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2024 {
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3077 };
3078
3079 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3080 {
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3117 };
3118
3119 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3120 {
3121         /* Pending on emulation bring up */
3122 };
3123
3124 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3125 {
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3164 };
3165
3166 #define DEFAULT_SH_MEM_CONFIG \
3167         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3168          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3169          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3170          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3171
3172
3173 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3174 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3175 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3176 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3177 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3178                                  struct amdgpu_cu_info *cu_info);
3179 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3180 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3181                                    u32 sh_num, u32 instance);
3182 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3183
3184 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3185 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3186 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3187 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3188 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3189 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3190 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3191
3192 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3193 {
3194         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3195         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3196                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3197         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3198         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3199         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3200         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3201         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3202         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3203 }
3204
3205 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3206                                  struct amdgpu_ring *ring)
3207 {
3208         struct amdgpu_device *adev = kiq_ring->adev;
3209         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3210         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3211         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3212
3213         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3214         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3215         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3216                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3217                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3218                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3219                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3220                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3221                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3222                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3223                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3224                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3225         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3226         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3227         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3228         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3229         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3230 }
3231
3232 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3233                                    struct amdgpu_ring *ring,
3234                                    enum amdgpu_unmap_queues_action action,
3235                                    u64 gpu_addr, u64 seq)
3236 {
3237         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3238
3239         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3240         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3241                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3242                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3243                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3244                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3245         amdgpu_ring_write(kiq_ring,
3246                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3247
3248         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3249                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3250                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3251                 amdgpu_ring_write(kiq_ring, seq);
3252         } else {
3253                 amdgpu_ring_write(kiq_ring, 0);
3254                 amdgpu_ring_write(kiq_ring, 0);
3255                 amdgpu_ring_write(kiq_ring, 0);
3256         }
3257 }
3258
3259 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3260                                    struct amdgpu_ring *ring,
3261                                    u64 addr,
3262                                    u64 seq)
3263 {
3264         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3265
3266         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3267         amdgpu_ring_write(kiq_ring,
3268                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3269                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3270                           PACKET3_QUERY_STATUS_COMMAND(2));
3271         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3272                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3273                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3274         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3275         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3276         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3277         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3278 }
3279
3280 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3281                                 uint16_t pasid, uint32_t flush_type,
3282                                 bool all_hub)
3283 {
3284         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3285         amdgpu_ring_write(kiq_ring,
3286                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3287                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3288                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3289                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3290 }
3291
3292 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3293         .kiq_set_resources = gfx10_kiq_set_resources,
3294         .kiq_map_queues = gfx10_kiq_map_queues,
3295         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3296         .kiq_query_status = gfx10_kiq_query_status,
3297         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3298         .set_resources_size = 8,
3299         .map_queues_size = 7,
3300         .unmap_queues_size = 6,
3301         .query_status_size = 7,
3302         .invalidate_tlbs_size = 2,
3303 };
3304
3305 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3306 {
3307         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3308 }
3309
3310 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3311 {
3312         switch (adev->asic_type) {
3313         case CHIP_NAVI10:
3314                 soc15_program_register_sequence(adev,
3315                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3316                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3317                 break;
3318         case CHIP_NAVI14:
3319                 soc15_program_register_sequence(adev,
3320                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3321                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3322                 break;
3323         case CHIP_NAVI12:
3324                 soc15_program_register_sequence(adev,
3325                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3326                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3327                 break;
3328         default:
3329                 break;
3330         }
3331 }
3332
3333 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3334 {
3335         switch (adev->asic_type) {
3336         case CHIP_NAVI10:
3337                 soc15_program_register_sequence(adev,
3338                                                 golden_settings_gc_10_1,
3339                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3340                 soc15_program_register_sequence(adev,
3341                                                 golden_settings_gc_10_0_nv10,
3342                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3343                 break;
3344         case CHIP_NAVI14:
3345                 soc15_program_register_sequence(adev,
3346                                                 golden_settings_gc_10_1_1,
3347                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3348                 soc15_program_register_sequence(adev,
3349                                                 golden_settings_gc_10_1_nv14,
3350                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3351                 break;
3352         case CHIP_NAVI12:
3353                 soc15_program_register_sequence(adev,
3354                                                 golden_settings_gc_10_1_2,
3355                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3356                 soc15_program_register_sequence(adev,
3357                                                 golden_settings_gc_10_1_2_nv12,
3358                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3359                 break;
3360         case CHIP_SIENNA_CICHLID:
3361                 soc15_program_register_sequence(adev,
3362                                                 golden_settings_gc_10_3,
3363                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3364                 soc15_program_register_sequence(adev,
3365                                                 golden_settings_gc_10_3_sienna_cichlid,
3366                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3367                 break;
3368         case CHIP_NAVY_FLOUNDER:
3369                 soc15_program_register_sequence(adev,
3370                                                 golden_settings_gc_10_3_2,
3371                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3372                 break;
3373
3374         default:
3375                 break;
3376         }
3377         gfx_v10_0_init_spm_golden_registers(adev);
3378 }
3379
3380 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3381 {
3382         adev->gfx.scratch.num_reg = 8;
3383         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3384         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3385 }
3386
3387 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3388                                        bool wc, uint32_t reg, uint32_t val)
3389 {
3390         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3391         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3392                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3393         amdgpu_ring_write(ring, reg);
3394         amdgpu_ring_write(ring, 0);
3395         amdgpu_ring_write(ring, val);
3396 }
3397
3398 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3399                                   int mem_space, int opt, uint32_t addr0,
3400                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3401                                   uint32_t inv)
3402 {
3403         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3404         amdgpu_ring_write(ring,
3405                           /* memory (1) or register (0) */
3406                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3407                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3408                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3409                            WAIT_REG_MEM_ENGINE(eng_sel)));
3410
3411         if (mem_space)
3412                 BUG_ON(addr0 & 0x3); /* Dword align */
3413         amdgpu_ring_write(ring, addr0);
3414         amdgpu_ring_write(ring, addr1);
3415         amdgpu_ring_write(ring, ref);
3416         amdgpu_ring_write(ring, mask);
3417         amdgpu_ring_write(ring, inv); /* poll interval */
3418 }
3419
3420 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3421 {
3422         struct amdgpu_device *adev = ring->adev;
3423         uint32_t scratch;
3424         uint32_t tmp = 0;
3425         unsigned i;
3426         int r;
3427
3428         r = amdgpu_gfx_scratch_get(adev, &scratch);
3429         if (r) {
3430                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3431                 return r;
3432         }
3433
3434         WREG32(scratch, 0xCAFEDEAD);
3435
3436         r = amdgpu_ring_alloc(ring, 3);
3437         if (r) {
3438                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3439                           ring->idx, r);
3440                 amdgpu_gfx_scratch_free(adev, scratch);
3441                 return r;
3442         }
3443
3444         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3445         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3446         amdgpu_ring_write(ring, 0xDEADBEEF);
3447         amdgpu_ring_commit(ring);
3448
3449         for (i = 0; i < adev->usec_timeout; i++) {
3450                 tmp = RREG32(scratch);
3451                 if (tmp == 0xDEADBEEF)
3452                         break;
3453                 if (amdgpu_emu_mode == 1)
3454                         msleep(1);
3455                 else
3456                         udelay(1);
3457         }
3458
3459         if (i >= adev->usec_timeout)
3460                 r = -ETIMEDOUT;
3461
3462         amdgpu_gfx_scratch_free(adev, scratch);
3463
3464         return r;
3465 }
3466
3467 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3468 {
3469         struct amdgpu_device *adev = ring->adev;
3470         struct amdgpu_ib ib;
3471         struct dma_fence *f = NULL;
3472         unsigned index;
3473         uint64_t gpu_addr;
3474         uint32_t tmp;
3475         long r;
3476
3477         r = amdgpu_device_wb_get(adev, &index);
3478         if (r)
3479                 return r;
3480
3481         gpu_addr = adev->wb.gpu_addr + (index * 4);
3482         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3483         memset(&ib, 0, sizeof(ib));
3484         r = amdgpu_ib_get(adev, NULL, 16,
3485                                         AMDGPU_IB_POOL_DIRECT, &ib);
3486         if (r)
3487                 goto err1;
3488
3489         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3490         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3491         ib.ptr[2] = lower_32_bits(gpu_addr);
3492         ib.ptr[3] = upper_32_bits(gpu_addr);
3493         ib.ptr[4] = 0xDEADBEEF;
3494         ib.length_dw = 5;
3495
3496         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3497         if (r)
3498                 goto err2;
3499
3500         r = dma_fence_wait_timeout(f, false, timeout);
3501         if (r == 0) {
3502                 r = -ETIMEDOUT;
3503                 goto err2;
3504         } else if (r < 0) {
3505                 goto err2;
3506         }
3507
3508         tmp = adev->wb.wb[index];
3509         if (tmp == 0xDEADBEEF)
3510                 r = 0;
3511         else
3512                 r = -EINVAL;
3513 err2:
3514         amdgpu_ib_free(adev, &ib, NULL);
3515         dma_fence_put(f);
3516 err1:
3517         amdgpu_device_wb_free(adev, index);
3518         return r;
3519 }
3520
3521 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3522 {
3523         release_firmware(adev->gfx.pfp_fw);
3524         adev->gfx.pfp_fw = NULL;
3525         release_firmware(adev->gfx.me_fw);
3526         adev->gfx.me_fw = NULL;
3527         release_firmware(adev->gfx.ce_fw);
3528         adev->gfx.ce_fw = NULL;
3529         release_firmware(adev->gfx.rlc_fw);
3530         adev->gfx.rlc_fw = NULL;
3531         release_firmware(adev->gfx.mec_fw);
3532         adev->gfx.mec_fw = NULL;
3533         release_firmware(adev->gfx.mec2_fw);
3534         adev->gfx.mec2_fw = NULL;
3535
3536         kfree(adev->gfx.rlc.register_list_format);
3537 }
3538
3539 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3540 {
3541         adev->gfx.cp_fw_write_wait = false;
3542
3543         switch (adev->asic_type) {
3544         case CHIP_NAVI10:
3545         case CHIP_NAVI12:
3546         case CHIP_NAVI14:
3547                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3548                     (adev->gfx.me_feature_version >= 27) &&
3549                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3550                     (adev->gfx.pfp_feature_version >= 27) &&
3551                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3552                     (adev->gfx.mec_feature_version >= 27))
3553                         adev->gfx.cp_fw_write_wait = true;
3554                 break;
3555         case CHIP_SIENNA_CICHLID:
3556         case CHIP_NAVY_FLOUNDER:
3557                 adev->gfx.cp_fw_write_wait = true;
3558                 break;
3559         default:
3560                 break;
3561         }
3562
3563         if (adev->gfx.cp_fw_write_wait == false)
3564                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3565 }
3566
3567
3568 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3569 {
3570         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3571
3572         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3573         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3574         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3575         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3576         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3577         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3578         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3579         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3580         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3581         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3582         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3583         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3584         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3585         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3586                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3587 }
3588
3589 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3590 {
3591         bool ret = false;
3592
3593         switch (adev->pdev->revision) {
3594         case 0xc2:
3595         case 0xc3:
3596                 ret = true;
3597                 break;
3598         default:
3599                 ret = false;
3600                 break;
3601         }
3602
3603         return ret ;
3604 }
3605
3606 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3607 {
3608         switch (adev->asic_type) {
3609         case CHIP_NAVI10:
3610                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3611                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3612                 break;
3613         default:
3614                 break;
3615         }
3616 }
3617
3618 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3619 {
3620         const char *chip_name;
3621         char fw_name[40];
3622         char wks[10];
3623         int err;
3624         struct amdgpu_firmware_info *info = NULL;
3625         const struct common_firmware_header *header = NULL;
3626         const struct gfx_firmware_header_v1_0 *cp_hdr;
3627         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3628         unsigned int *tmp = NULL;
3629         unsigned int i = 0;
3630         uint16_t version_major;
3631         uint16_t version_minor;
3632
3633         DRM_DEBUG("\n");
3634
3635         memset(wks, 0, sizeof(wks));
3636         switch (adev->asic_type) {
3637         case CHIP_NAVI10:
3638                 chip_name = "navi10";
3639                 break;
3640         case CHIP_NAVI14:
3641                 chip_name = "navi14";
3642                 if (!(adev->pdev->device == 0x7340 &&
3643                       adev->pdev->revision != 0x00))
3644                         snprintf(wks, sizeof(wks), "_wks");
3645                 break;
3646         case CHIP_NAVI12:
3647                 chip_name = "navi12";
3648                 break;
3649         case CHIP_SIENNA_CICHLID:
3650                 chip_name = "sienna_cichlid";
3651                 break;
3652         case CHIP_NAVY_FLOUNDER:
3653                 chip_name = "navy_flounder";
3654                 break;
3655         default:
3656                 BUG();
3657         }
3658
3659         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3660         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3661         if (err)
3662                 goto out;
3663         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3664         if (err)
3665                 goto out;
3666         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3667         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3668         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3669
3670         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3671         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3672         if (err)
3673                 goto out;
3674         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3675         if (err)
3676                 goto out;
3677         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3678         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3679         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3680
3681         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3682         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3683         if (err)
3684                 goto out;
3685         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3686         if (err)
3687                 goto out;
3688         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3689         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3690         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3691
3692         if (!amdgpu_sriov_vf(adev)) {
3693                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3694                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3695                 if (err)
3696                         goto out;
3697                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3698                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3699                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3700                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3701                 if (version_major == 2 && version_minor == 1)
3702                         adev->gfx.rlc.is_rlc_v2_1 = true;
3703
3704                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3705                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3706                 adev->gfx.rlc.save_and_restore_offset =
3707                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3708                 adev->gfx.rlc.clear_state_descriptor_offset =
3709                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3710                 adev->gfx.rlc.avail_scratch_ram_locations =
3711                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3712                 adev->gfx.rlc.reg_restore_list_size =
3713                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3714                 adev->gfx.rlc.reg_list_format_start =
3715                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3716                 adev->gfx.rlc.reg_list_format_separate_start =
3717                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3718                 adev->gfx.rlc.starting_offsets_start =
3719                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3720                 adev->gfx.rlc.reg_list_format_size_bytes =
3721                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3722                 adev->gfx.rlc.reg_list_size_bytes =
3723                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3724                 adev->gfx.rlc.register_list_format =
3725                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3726                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3727                 if (!adev->gfx.rlc.register_list_format) {
3728                         err = -ENOMEM;
3729                         goto out;
3730                 }
3731
3732                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3733                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3734                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3735                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3736
3737                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3738
3739                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3740                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3741                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3742                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3743
3744                 if (adev->gfx.rlc.is_rlc_v2_1)
3745                         gfx_v10_0_init_rlc_ext_microcode(adev);
3746         }
3747
3748         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3749         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3750         if (err)
3751                 goto out;
3752         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3753         if (err)
3754                 goto out;
3755         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3756         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3757         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3758
3759         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3760         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3761         if (!err) {
3762                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3763                 if (err)
3764                         goto out;
3765                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3766                 adev->gfx.mec2_fw->data;
3767                 adev->gfx.mec2_fw_version =
3768                 le32_to_cpu(cp_hdr->header.ucode_version);
3769                 adev->gfx.mec2_feature_version =
3770                 le32_to_cpu(cp_hdr->ucode_feature_version);
3771         } else {
3772                 err = 0;
3773                 adev->gfx.mec2_fw = NULL;
3774         }
3775
3776         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3777                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3778                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3779                 info->fw = adev->gfx.pfp_fw;
3780                 header = (const struct common_firmware_header *)info->fw->data;
3781                 adev->firmware.fw_size +=
3782                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3783
3784                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3785                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3786                 info->fw = adev->gfx.me_fw;
3787                 header = (const struct common_firmware_header *)info->fw->data;
3788                 adev->firmware.fw_size +=
3789                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3790
3791                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3792                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3793                 info->fw = adev->gfx.ce_fw;
3794                 header = (const struct common_firmware_header *)info->fw->data;
3795                 adev->firmware.fw_size +=
3796                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3797
3798                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3799                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3800                 info->fw = adev->gfx.rlc_fw;
3801                 if (info->fw) {
3802                         header = (const struct common_firmware_header *)info->fw->data;
3803                         adev->firmware.fw_size +=
3804                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3805                 }
3806                 if (adev->gfx.rlc.is_rlc_v2_1 &&
3807                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3808                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3809                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3810                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3811                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3812                         info->fw = adev->gfx.rlc_fw;
3813                         adev->firmware.fw_size +=
3814                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3815
3816                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3817                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3818                         info->fw = adev->gfx.rlc_fw;
3819                         adev->firmware.fw_size +=
3820                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3821
3822                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3823                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3824                         info->fw = adev->gfx.rlc_fw;
3825                         adev->firmware.fw_size +=
3826                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3827                 }
3828
3829                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3830                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3831                 info->fw = adev->gfx.mec_fw;
3832                 header = (const struct common_firmware_header *)info->fw->data;
3833                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3834                 adev->firmware.fw_size +=
3835                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3836                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3837
3838                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3839                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3840                 info->fw = adev->gfx.mec_fw;
3841                 adev->firmware.fw_size +=
3842                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3843
3844                 if (adev->gfx.mec2_fw) {
3845                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3846                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3847                         info->fw = adev->gfx.mec2_fw;
3848                         header = (const struct common_firmware_header *)info->fw->data;
3849                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3850                         adev->firmware.fw_size +=
3851                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3852                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3853                                       PAGE_SIZE);
3854                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3855                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3856                         info->fw = adev->gfx.mec2_fw;
3857                         adev->firmware.fw_size +=
3858                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3859                                       PAGE_SIZE);
3860                 }
3861         }
3862
3863         gfx_v10_0_check_fw_write_wait(adev);
3864 out:
3865         if (err) {
3866                 dev_err(adev->dev,
3867                         "gfx10: Failed to load firmware \"%s\"\n",
3868                         fw_name);
3869                 release_firmware(adev->gfx.pfp_fw);
3870                 adev->gfx.pfp_fw = NULL;
3871                 release_firmware(adev->gfx.me_fw);
3872                 adev->gfx.me_fw = NULL;
3873                 release_firmware(adev->gfx.ce_fw);
3874                 adev->gfx.ce_fw = NULL;
3875                 release_firmware(adev->gfx.rlc_fw);
3876                 adev->gfx.rlc_fw = NULL;
3877                 release_firmware(adev->gfx.mec_fw);
3878                 adev->gfx.mec_fw = NULL;
3879                 release_firmware(adev->gfx.mec2_fw);
3880                 adev->gfx.mec2_fw = NULL;
3881         }
3882
3883         gfx_v10_0_check_gfxoff_flag(adev);
3884
3885         return err;
3886 }
3887
3888 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3889 {
3890         u32 count = 0;
3891         const struct cs_section_def *sect = NULL;
3892         const struct cs_extent_def *ext = NULL;
3893
3894         /* begin clear state */
3895         count += 2;
3896         /* context control state */
3897         count += 3;
3898
3899         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3900                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3901                         if (sect->id == SECT_CONTEXT)
3902                                 count += 2 + ext->reg_count;
3903                         else
3904                                 return 0;
3905                 }
3906         }
3907
3908         /* set PA_SC_TILE_STEERING_OVERRIDE */
3909         count += 3;
3910         /* end clear state */
3911         count += 2;
3912         /* clear state */
3913         count += 2;
3914
3915         return count;
3916 }
3917
3918 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3919                                     volatile u32 *buffer)
3920 {
3921         u32 count = 0, i;
3922         const struct cs_section_def *sect = NULL;
3923         const struct cs_extent_def *ext = NULL;
3924         int ctx_reg_offset;
3925
3926         if (adev->gfx.rlc.cs_data == NULL)
3927                 return;
3928         if (buffer == NULL)
3929                 return;
3930
3931         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3932         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3933
3934         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3935         buffer[count++] = cpu_to_le32(0x80000000);
3936         buffer[count++] = cpu_to_le32(0x80000000);
3937
3938         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3939                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3940                         if (sect->id == SECT_CONTEXT) {
3941                                 buffer[count++] =
3942                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3943                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3944                                                 PACKET3_SET_CONTEXT_REG_START);
3945                                 for (i = 0; i < ext->reg_count; i++)
3946                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3947                         } else {
3948                                 return;
3949                         }
3950                 }
3951         }
3952
3953         ctx_reg_offset =
3954                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3955         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3956         buffer[count++] = cpu_to_le32(ctx_reg_offset);
3957         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
3958
3959         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3960         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3961
3962         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3963         buffer[count++] = cpu_to_le32(0);
3964 }
3965
3966 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
3967 {
3968         /* clear state block */
3969         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
3970                         &adev->gfx.rlc.clear_state_gpu_addr,
3971                         (void **)&adev->gfx.rlc.cs_ptr);
3972
3973         /* jump table block */
3974         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
3975                         &adev->gfx.rlc.cp_table_gpu_addr,
3976                         (void **)&adev->gfx.rlc.cp_table_ptr);
3977 }
3978
3979 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
3980 {
3981         const struct cs_section_def *cs_data;
3982         int r;
3983
3984         adev->gfx.rlc.cs_data = gfx10_cs_data;
3985
3986         cs_data = adev->gfx.rlc.cs_data;
3987
3988         if (cs_data) {
3989                 /* init clear state block */
3990                 r = amdgpu_gfx_rlc_init_csb(adev);
3991                 if (r)
3992                         return r;
3993         }
3994
3995         /* init spm vmid with 0xf */
3996         if (adev->gfx.rlc.funcs->update_spm_vmid)
3997                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
3998
3999         return 0;
4000 }
4001
4002 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4003 {
4004         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4005         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4006 }
4007
4008 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4009 {
4010         int r;
4011
4012         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4013
4014         amdgpu_gfx_graphics_queue_acquire(adev);
4015
4016         r = gfx_v10_0_init_microcode(adev);
4017         if (r)
4018                 DRM_ERROR("Failed to load gfx firmware!\n");
4019
4020         return r;
4021 }
4022
4023 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4024 {
4025         int r;
4026         u32 *hpd;
4027         const __le32 *fw_data = NULL;
4028         unsigned fw_size;
4029         u32 *fw = NULL;
4030         size_t mec_hpd_size;
4031
4032         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4033
4034         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4035
4036         /* take ownership of the relevant compute queues */
4037         amdgpu_gfx_compute_queue_acquire(adev);
4038         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4039
4040         if (mec_hpd_size) {
4041                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4042                                               AMDGPU_GEM_DOMAIN_GTT,
4043                                               &adev->gfx.mec.hpd_eop_obj,
4044                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4045                                               (void **)&hpd);
4046                 if (r) {
4047                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4048                         gfx_v10_0_mec_fini(adev);
4049                         return r;
4050                 }
4051
4052                 memset(hpd, 0, mec_hpd_size);
4053
4054                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4055                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4056         }
4057
4058         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4059                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4060
4061                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4062                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4063                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4064
4065                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4066                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4067                                               &adev->gfx.mec.mec_fw_obj,
4068                                               &adev->gfx.mec.mec_fw_gpu_addr,
4069                                               (void **)&fw);
4070                 if (r) {
4071                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4072                         gfx_v10_0_mec_fini(adev);
4073                         return r;
4074                 }
4075
4076                 memcpy(fw, fw_data, fw_size);
4077
4078                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4079                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4080         }
4081
4082         return 0;
4083 }
4084
4085 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4086 {
4087         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4088                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4089                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4090         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4091 }
4092
4093 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4094                            uint32_t thread, uint32_t regno,
4095                            uint32_t num, uint32_t *out)
4096 {
4097         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4098                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4099                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4100                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4101                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4102         while (num--)
4103                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4104 }
4105
4106 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4107 {
4108         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4109          * field when performing a select_se_sh so it should be
4110          * zero here */
4111         WARN_ON(simd != 0);
4112
4113         /* type 2 wave data */
4114         dst[(*no_fields)++] = 2;
4115         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4116         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4117         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4118         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4119         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4120         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4121         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4122         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4123         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4124         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4125         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4126         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4127         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4128         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4129         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4130 }
4131
4132 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4133                                      uint32_t wave, uint32_t start,
4134                                      uint32_t size, uint32_t *dst)
4135 {
4136         WARN_ON(simd != 0);
4137
4138         wave_read_regs(
4139                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4140                 dst);
4141 }
4142
4143 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4144                                       uint32_t wave, uint32_t thread,
4145                                       uint32_t start, uint32_t size,
4146                                       uint32_t *dst)
4147 {
4148         wave_read_regs(
4149                 adev, wave, thread,
4150                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4151 }
4152
4153 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4154                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4155  {
4156        nv_grbm_select(adev, me, pipe, q, vm);
4157  }
4158
4159
4160 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4161         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4162         .select_se_sh = &gfx_v10_0_select_se_sh,
4163         .read_wave_data = &gfx_v10_0_read_wave_data,
4164         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4165         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4166         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4167         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4168 };
4169
4170 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4171 {
4172         u32 gb_addr_config;
4173
4174         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4175
4176         switch (adev->asic_type) {
4177         case CHIP_NAVI10:
4178         case CHIP_NAVI14:
4179         case CHIP_NAVI12:
4180                 adev->gfx.config.max_hw_contexts = 8;
4181                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4182                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4183                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4184                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4185                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4186                 break;
4187         case CHIP_SIENNA_CICHLID:
4188         case CHIP_NAVY_FLOUNDER:
4189                 adev->gfx.config.max_hw_contexts = 8;
4190                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4191                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4192                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4193                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4194                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4195                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4196                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4197                 break;
4198         default:
4199                 BUG();
4200                 break;
4201         }
4202
4203         adev->gfx.config.gb_addr_config = gb_addr_config;
4204
4205         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4206                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4207                                       GB_ADDR_CONFIG, NUM_PIPES);
4208
4209         adev->gfx.config.max_tile_pipes =
4210                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4211
4212         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4213                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4214                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4215         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4216                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4217                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4218         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4219                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4220                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4221         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4222                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4223                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4224 }
4225
4226 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4227                                    int me, int pipe, int queue)
4228 {
4229         int r;
4230         struct amdgpu_ring *ring;
4231         unsigned int irq_type;
4232
4233         ring = &adev->gfx.gfx_ring[ring_id];
4234
4235         ring->me = me;
4236         ring->pipe = pipe;
4237         ring->queue = queue;
4238
4239         ring->ring_obj = NULL;
4240         ring->use_doorbell = true;
4241
4242         if (!ring_id)
4243                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4244         else
4245                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4246         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4247
4248         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4249         r = amdgpu_ring_init(adev, ring, 1024,
4250                              &adev->gfx.eop_irq, irq_type,
4251                              AMDGPU_RING_PRIO_DEFAULT);
4252         if (r)
4253                 return r;
4254         return 0;
4255 }
4256
4257 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4258                                        int mec, int pipe, int queue)
4259 {
4260         int r;
4261         unsigned irq_type;
4262         struct amdgpu_ring *ring;
4263         unsigned int hw_prio;
4264
4265         ring = &adev->gfx.compute_ring[ring_id];
4266
4267         /* mec0 is me1 */
4268         ring->me = mec + 1;
4269         ring->pipe = pipe;
4270         ring->queue = queue;
4271
4272         ring->ring_obj = NULL;
4273         ring->use_doorbell = true;
4274         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4275         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4276                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4277         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4278
4279         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4280                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4281                 + ring->pipe;
4282         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4283                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4284         /* type-2 packets are deprecated on MEC, use type-3 instead */
4285         r = amdgpu_ring_init(adev, ring, 1024,
4286                              &adev->gfx.eop_irq, irq_type, hw_prio);
4287         if (r)
4288                 return r;
4289
4290         return 0;
4291 }
4292
4293 static int gfx_v10_0_sw_init(void *handle)
4294 {
4295         int i, j, k, r, ring_id = 0;
4296         struct amdgpu_kiq *kiq;
4297         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4298
4299         switch (adev->asic_type) {
4300         case CHIP_NAVI10:
4301         case CHIP_NAVI14:
4302         case CHIP_NAVI12:
4303                 adev->gfx.me.num_me = 1;
4304                 adev->gfx.me.num_pipe_per_me = 1;
4305                 adev->gfx.me.num_queue_per_pipe = 1;
4306                 adev->gfx.mec.num_mec = 2;
4307                 adev->gfx.mec.num_pipe_per_mec = 4;
4308                 adev->gfx.mec.num_queue_per_pipe = 8;
4309                 break;
4310         case CHIP_SIENNA_CICHLID:
4311         case CHIP_NAVY_FLOUNDER:
4312                 adev->gfx.me.num_me = 1;
4313                 adev->gfx.me.num_pipe_per_me = 1;
4314                 adev->gfx.me.num_queue_per_pipe = 1;
4315                 adev->gfx.mec.num_mec = 2;
4316                 adev->gfx.mec.num_pipe_per_mec = 4;
4317                 adev->gfx.mec.num_queue_per_pipe = 4;
4318                 break;
4319         default:
4320                 adev->gfx.me.num_me = 1;
4321                 adev->gfx.me.num_pipe_per_me = 1;
4322                 adev->gfx.me.num_queue_per_pipe = 1;
4323                 adev->gfx.mec.num_mec = 1;
4324                 adev->gfx.mec.num_pipe_per_mec = 4;
4325                 adev->gfx.mec.num_queue_per_pipe = 8;
4326                 break;
4327         }
4328
4329         /* KIQ event */
4330         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4331                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4332                               &adev->gfx.kiq.irq);
4333         if (r)
4334                 return r;
4335
4336         /* EOP Event */
4337         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4338                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4339                               &adev->gfx.eop_irq);
4340         if (r)
4341                 return r;
4342
4343         /* Privileged reg */
4344         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4345                               &adev->gfx.priv_reg_irq);
4346         if (r)
4347                 return r;
4348
4349         /* Privileged inst */
4350         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4351                               &adev->gfx.priv_inst_irq);
4352         if (r)
4353                 return r;
4354
4355         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4356
4357         gfx_v10_0_scratch_init(adev);
4358
4359         r = gfx_v10_0_me_init(adev);
4360         if (r)
4361                 return r;
4362
4363         r = gfx_v10_0_rlc_init(adev);
4364         if (r) {
4365                 DRM_ERROR("Failed to init rlc BOs!\n");
4366                 return r;
4367         }
4368
4369         r = gfx_v10_0_mec_init(adev);
4370         if (r) {
4371                 DRM_ERROR("Failed to init MEC BOs!\n");
4372                 return r;
4373         }
4374
4375         /* set up the gfx ring */
4376         for (i = 0; i < adev->gfx.me.num_me; i++) {
4377                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4378                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4379                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4380                                         continue;
4381
4382                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4383                                                             i, k, j);
4384                                 if (r)
4385                                         return r;
4386                                 ring_id++;
4387                         }
4388                 }
4389         }
4390
4391         ring_id = 0;
4392         /* set up the compute queues - allocate horizontally across pipes */
4393         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4394                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4395                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4396                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4397                                                                      j))
4398                                         continue;
4399
4400                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4401                                                                 i, k, j);
4402                                 if (r)
4403                                         return r;
4404
4405                                 ring_id++;
4406                         }
4407                 }
4408         }
4409
4410         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4411         if (r) {
4412                 DRM_ERROR("Failed to init KIQ BOs!\n");
4413                 return r;
4414         }
4415
4416         kiq = &adev->gfx.kiq;
4417         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4418         if (r)
4419                 return r;
4420
4421         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4422         if (r)
4423                 return r;
4424
4425         /* allocate visible FB for rlc auto-loading fw */
4426         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4427                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4428                 if (r)
4429                         return r;
4430         }
4431
4432         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4433
4434         gfx_v10_0_gpu_early_init(adev);
4435
4436         return 0;
4437 }
4438
4439 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4440 {
4441         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4442                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4443                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4444 }
4445
4446 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4447 {
4448         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4449                               &adev->gfx.ce.ce_fw_gpu_addr,
4450                               (void **)&adev->gfx.ce.ce_fw_ptr);
4451 }
4452
4453 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4454 {
4455         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4456                               &adev->gfx.me.me_fw_gpu_addr,
4457                               (void **)&adev->gfx.me.me_fw_ptr);
4458 }
4459
4460 static int gfx_v10_0_sw_fini(void *handle)
4461 {
4462         int i;
4463         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4464
4465         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4466                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4467         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4468                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4469
4470         amdgpu_gfx_mqd_sw_fini(adev);
4471         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4472         amdgpu_gfx_kiq_fini(adev);
4473
4474         gfx_v10_0_pfp_fini(adev);
4475         gfx_v10_0_ce_fini(adev);
4476         gfx_v10_0_me_fini(adev);
4477         gfx_v10_0_rlc_fini(adev);
4478         gfx_v10_0_mec_fini(adev);
4479
4480         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4481                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4482
4483         gfx_v10_0_free_microcode(adev);
4484
4485         return 0;
4486 }
4487
4488 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4489                                    u32 sh_num, u32 instance)
4490 {
4491         u32 data;
4492
4493         if (instance == 0xffffffff)
4494                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4495                                      INSTANCE_BROADCAST_WRITES, 1);
4496         else
4497                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4498                                      instance);
4499
4500         if (se_num == 0xffffffff)
4501                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4502                                      1);
4503         else
4504                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4505
4506         if (sh_num == 0xffffffff)
4507                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4508                                      1);
4509         else
4510                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4511
4512         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4513 }
4514
4515 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4516 {
4517         u32 data, mask;
4518
4519         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4520         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4521
4522         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4523         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4524
4525         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4526                                          adev->gfx.config.max_sh_per_se);
4527
4528         return (~data) & mask;
4529 }
4530
4531 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4532 {
4533         int i, j;
4534         u32 data;
4535         u32 active_rbs = 0;
4536         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4537                                         adev->gfx.config.max_sh_per_se;
4538
4539         mutex_lock(&adev->grbm_idx_mutex);
4540         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4541                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4542                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4543                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4544                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4545                                                rb_bitmap_width_per_sh);
4546                 }
4547         }
4548         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4549         mutex_unlock(&adev->grbm_idx_mutex);
4550
4551         adev->gfx.config.backend_enable_mask = active_rbs;
4552         adev->gfx.config.num_rbs = hweight32(active_rbs);
4553 }
4554
4555 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4556 {
4557         uint32_t num_sc;
4558         uint32_t enabled_rb_per_sh;
4559         uint32_t active_rb_bitmap;
4560         uint32_t num_rb_per_sc;
4561         uint32_t num_packer_per_sc;
4562         uint32_t pa_sc_tile_steering_override;
4563
4564         /* for ASICs that integrates GFX v10.3
4565          * pa_sc_tile_steering_override should be set to 0 */
4566         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4567             adev->asic_type == CHIP_NAVY_FLOUNDER)
4568                 return 0;
4569
4570         /* init num_sc */
4571         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4572                         adev->gfx.config.num_sc_per_sh;
4573         /* init num_rb_per_sc */
4574         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4575         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4576         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4577         /* init num_packer_per_sc */
4578         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4579
4580         pa_sc_tile_steering_override = 0;
4581         pa_sc_tile_steering_override |=
4582                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4583                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4584         pa_sc_tile_steering_override |=
4585                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4586                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4587         pa_sc_tile_steering_override |=
4588                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4589                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4590
4591         return pa_sc_tile_steering_override;
4592 }
4593
4594 #define DEFAULT_SH_MEM_BASES    (0x6000)
4595
4596 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4597 {
4598         int i;
4599         uint32_t sh_mem_bases;
4600
4601         /*
4602          * Configure apertures:
4603          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4604          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4605          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4606          */
4607         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4608
4609         mutex_lock(&adev->srbm_mutex);
4610         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4611                 nv_grbm_select(adev, 0, 0, 0, i);
4612                 /* CP and shaders */
4613                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4614                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4615         }
4616         nv_grbm_select(adev, 0, 0, 0, 0);
4617         mutex_unlock(&adev->srbm_mutex);
4618
4619         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4620            acccess. These should be enabled by FW for target VMIDs. */
4621         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4622                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4623                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4624                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4625                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4626         }
4627 }
4628
4629 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4630 {
4631         int vmid;
4632
4633         /*
4634          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4635          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4636          * the driver can enable them for graphics. VMID0 should maintain
4637          * access so that HWS firmware can save/restore entries.
4638          */
4639         for (vmid = 1; vmid < 16; vmid++) {
4640                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4641                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4642                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4643                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4644         }
4645 }
4646
4647
4648 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4649 {
4650         int i, j, k;
4651         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4652         u32 tmp, wgp_active_bitmap = 0;
4653         u32 gcrd_targets_disable_tcp = 0;
4654         u32 utcl_invreq_disable = 0;
4655         /*
4656          * GCRD_TARGETS_DISABLE field contains
4657          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4658          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4659          */
4660         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4661                 2 * max_wgp_per_sh + /* TCP */
4662                 max_wgp_per_sh + /* SQC */
4663                 4); /* GL1C */
4664         /*
4665          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4666          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4667          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4668          */
4669         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4670                 2 * max_wgp_per_sh + /* TCP */
4671                 2 * max_wgp_per_sh + /* SQC */
4672                 4 + /* RMI */
4673                 1); /* SQG */
4674
4675         if (adev->asic_type == CHIP_NAVI10 ||
4676             adev->asic_type == CHIP_NAVI14 ||
4677             adev->asic_type == CHIP_NAVI12) {
4678                 mutex_lock(&adev->grbm_idx_mutex);
4679                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4680                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4681                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4682                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4683                                 /*
4684                                  * Set corresponding TCP bits for the inactive WGPs in
4685                                  * GCRD_SA_TARGETS_DISABLE
4686                                  */
4687                                 gcrd_targets_disable_tcp = 0;
4688                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4689                                 utcl_invreq_disable = 0;
4690
4691                                 for (k = 0; k < max_wgp_per_sh; k++) {
4692                                         if (!(wgp_active_bitmap & (1 << k))) {
4693                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4694                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4695                                                         (3 << (2 * (max_wgp_per_sh + k)));
4696                                         }
4697                                 }
4698
4699                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4700                                 /* only override TCP & SQC bits */
4701                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4702                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4703                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4704
4705                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4706                                 /* only override TCP bits */
4707                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4708                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4709                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4710                         }
4711                 }
4712
4713                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4714                 mutex_unlock(&adev->grbm_idx_mutex);
4715         }
4716 }
4717
4718 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4719 {
4720         /* TCCs are global (not instanced). */
4721         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4722                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4723
4724         adev->gfx.config.tcc_disabled_mask =
4725                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4726                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4727 }
4728
4729 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4730 {
4731         u32 tmp;
4732         int i;
4733
4734         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4735
4736         gfx_v10_0_setup_rb(adev);
4737         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4738         gfx_v10_0_get_tcc_info(adev);
4739         adev->gfx.config.pa_sc_tile_steering_override =
4740                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4741
4742         /* XXX SH_MEM regs */
4743         /* where to put LDS, scratch, GPUVM in FSA64 space */
4744         mutex_lock(&adev->srbm_mutex);
4745         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4746                 nv_grbm_select(adev, 0, 0, 0, i);
4747                 /* CP and shaders */
4748                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4749                 if (i != 0) {
4750                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4751                                 (adev->gmc.private_aperture_start >> 48));
4752                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4753                                 (adev->gmc.shared_aperture_start >> 48));
4754                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4755                 }
4756         }
4757         nv_grbm_select(adev, 0, 0, 0, 0);
4758
4759         mutex_unlock(&adev->srbm_mutex);
4760
4761         gfx_v10_0_init_compute_vmid(adev);
4762         gfx_v10_0_init_gds_vmid(adev);
4763
4764 }
4765
4766 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4767                                                bool enable)
4768 {
4769         u32 tmp;
4770
4771         if (amdgpu_sriov_vf(adev))
4772                 return;
4773
4774         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4775
4776         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4777                             enable ? 1 : 0);
4778         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4779                             enable ? 1 : 0);
4780         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4781                             enable ? 1 : 0);
4782         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4783                             enable ? 1 : 0);
4784
4785         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4786 }
4787
4788 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4789 {
4790         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4791
4792         /* csib */
4793         if (adev->asic_type == CHIP_NAVI12) {
4794                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4795                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4796                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4797                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4798                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4799         } else {
4800                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4801                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4802                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4803                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4804                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4805         }
4806         return 0;
4807 }
4808
4809 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4810 {
4811         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4812
4813         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4814         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4815 }
4816
4817 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4818 {
4819         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4820         udelay(50);
4821         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4822         udelay(50);
4823 }
4824
4825 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4826                                              bool enable)
4827 {
4828         uint32_t rlc_pg_cntl;
4829
4830         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4831
4832         if (!enable) {
4833                 /* RLC_PG_CNTL[23] = 0 (default)
4834                  * RLC will wait for handshake acks with SMU
4835                  * GFXOFF will be enabled
4836                  * RLC_PG_CNTL[23] = 1
4837                  * RLC will not issue any message to SMU
4838                  * hence no handshake between SMU & RLC
4839                  * GFXOFF will be disabled
4840                  */
4841                 rlc_pg_cntl |= 0x800000;
4842         } else
4843                 rlc_pg_cntl &= ~0x800000;
4844         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4845 }
4846
4847 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4848 {
4849         /* TODO: enable rlc & smu handshake until smu
4850          * and gfxoff feature works as expected */
4851         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4852                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4853
4854         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4855         udelay(50);
4856 }
4857
4858 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4859 {
4860         uint32_t tmp;
4861
4862         /* enable Save Restore Machine */
4863         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4864         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4865         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4866         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4867 }
4868
4869 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4870 {
4871         const struct rlc_firmware_header_v2_0 *hdr;
4872         const __le32 *fw_data;
4873         unsigned i, fw_size;
4874
4875         if (!adev->gfx.rlc_fw)
4876                 return -EINVAL;
4877
4878         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4879         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4880
4881         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4882                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4883         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4884
4885         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4886                      RLCG_UCODE_LOADING_START_ADDRESS);
4887
4888         for (i = 0; i < fw_size; i++)
4889                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4890                              le32_to_cpup(fw_data++));
4891
4892         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4893
4894         return 0;
4895 }
4896
4897 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4898 {
4899         int r;
4900
4901         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4902
4903                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4904                 if (r)
4905                         return r;
4906
4907                 gfx_v10_0_init_csb(adev);
4908
4909                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4910                         gfx_v10_0_rlc_enable_srm(adev);
4911         } else {
4912                 if (amdgpu_sriov_vf(adev)) {
4913                         gfx_v10_0_init_csb(adev);
4914                         return 0;
4915                 }
4916
4917                 adev->gfx.rlc.funcs->stop(adev);
4918
4919                 /* disable CG */
4920                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4921
4922                 /* disable PG */
4923                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4924
4925                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4926                         /* legacy rlc firmware loading */
4927                         r = gfx_v10_0_rlc_load_microcode(adev);
4928                         if (r)
4929                                 return r;
4930                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4931                         /* rlc backdoor autoload firmware */
4932                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4933                         if (r)
4934                                 return r;
4935                 }
4936
4937                 gfx_v10_0_init_csb(adev);
4938
4939                 adev->gfx.rlc.funcs->start(adev);
4940
4941                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4942                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4943                         if (r)
4944                                 return r;
4945                 }
4946         }
4947         return 0;
4948 }
4949
4950 static struct {
4951         FIRMWARE_ID     id;
4952         unsigned int    offset;
4953         unsigned int    size;
4954 } rlc_autoload_info[FIRMWARE_ID_MAX];
4955
4956 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
4957 {
4958         int ret;
4959         RLC_TABLE_OF_CONTENT *rlc_toc;
4960
4961         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
4962                                         AMDGPU_GEM_DOMAIN_GTT,
4963                                         &adev->gfx.rlc.rlc_toc_bo,
4964                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
4965                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
4966         if (ret) {
4967                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
4968                 return ret;
4969         }
4970
4971         /* Copy toc from psp sos fw to rlc toc buffer */
4972         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
4973
4974         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
4975         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
4976                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
4977                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
4978                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
4979                         /* Offset needs 4KB alignment */
4980                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
4981                 }
4982
4983                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
4984                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
4985                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
4986
4987                 rlc_toc++;
4988         }
4989
4990         return 0;
4991 }
4992
4993 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
4994 {
4995         uint32_t total_size = 0;
4996         FIRMWARE_ID id;
4997         int ret;
4998
4999         ret = gfx_v10_0_parse_rlc_toc(adev);
5000         if (ret) {
5001                 dev_err(adev->dev, "failed to parse rlc toc\n");
5002                 return 0;
5003         }
5004
5005         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5006                 total_size += rlc_autoload_info[id].size;
5007
5008         /* In case the offset in rlc toc ucode is aligned */
5009         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5010                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5011                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5012
5013         return total_size;
5014 }
5015
5016 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5017 {
5018         int r;
5019         uint32_t total_size;
5020
5021         total_size = gfx_v10_0_calc_toc_total_size(adev);
5022
5023         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5024                                       AMDGPU_GEM_DOMAIN_GTT,
5025                                       &adev->gfx.rlc.rlc_autoload_bo,
5026                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5027                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5028         if (r) {
5029                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5030                 return r;
5031         }
5032
5033         return 0;
5034 }
5035
5036 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5037 {
5038         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5039                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5040                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5041         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5042                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5043                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5044 }
5045
5046 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5047                                                        FIRMWARE_ID id,
5048                                                        const void *fw_data,
5049                                                        uint32_t fw_size)
5050 {
5051         uint32_t toc_offset;
5052         uint32_t toc_fw_size;
5053         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5054
5055         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5056                 return;
5057
5058         toc_offset = rlc_autoload_info[id].offset;
5059         toc_fw_size = rlc_autoload_info[id].size;
5060
5061         if (fw_size == 0)
5062                 fw_size = toc_fw_size;
5063
5064         if (fw_size > toc_fw_size)
5065                 fw_size = toc_fw_size;
5066
5067         memcpy(ptr + toc_offset, fw_data, fw_size);
5068
5069         if (fw_size < toc_fw_size)
5070                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5071 }
5072
5073 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5074 {
5075         void *data;
5076         uint32_t size;
5077
5078         data = adev->gfx.rlc.rlc_toc_buf;
5079         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5080
5081         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5082                                                    FIRMWARE_ID_RLC_TOC,
5083                                                    data, size);
5084 }
5085
5086 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5087 {
5088         const __le32 *fw_data;
5089         uint32_t fw_size;
5090         const struct gfx_firmware_header_v1_0 *cp_hdr;
5091         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5092
5093         /* pfp ucode */
5094         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5095                 adev->gfx.pfp_fw->data;
5096         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5097                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5098         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5099         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5100                                                    FIRMWARE_ID_CP_PFP,
5101                                                    fw_data, fw_size);
5102
5103         /* ce ucode */
5104         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5105                 adev->gfx.ce_fw->data;
5106         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5107                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5108         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5109         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5110                                                    FIRMWARE_ID_CP_CE,
5111                                                    fw_data, fw_size);
5112
5113         /* me ucode */
5114         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5115                 adev->gfx.me_fw->data;
5116         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5117                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5118         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5119         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5120                                                    FIRMWARE_ID_CP_ME,
5121                                                    fw_data, fw_size);
5122
5123         /* rlc ucode */
5124         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5125                 adev->gfx.rlc_fw->data;
5126         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5127                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5128         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5129         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5130                                                    FIRMWARE_ID_RLC_G_UCODE,
5131                                                    fw_data, fw_size);
5132
5133         /* mec1 ucode */
5134         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5135                 adev->gfx.mec_fw->data;
5136         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5137                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5138         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5139                 cp_hdr->jt_size * 4;
5140         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5141                                                    FIRMWARE_ID_CP_MEC,
5142                                                    fw_data, fw_size);
5143         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5144 }
5145
5146 /* Temporarily put sdma part here */
5147 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5148 {
5149         const __le32 *fw_data;
5150         uint32_t fw_size;
5151         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5152         int i;
5153
5154         for (i = 0; i < adev->sdma.num_instances; i++) {
5155                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5156                         adev->sdma.instance[i].fw->data;
5157                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5158                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5159                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5160
5161                 if (i == 0) {
5162                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5163                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5164                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5165                                 FIRMWARE_ID_SDMA0_JT,
5166                                 (uint32_t *)fw_data +
5167                                 sdma_hdr->jt_offset,
5168                                 sdma_hdr->jt_size * 4);
5169                 } else if (i == 1) {
5170                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5171                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5172                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5173                                 FIRMWARE_ID_SDMA1_JT,
5174                                 (uint32_t *)fw_data +
5175                                 sdma_hdr->jt_offset,
5176                                 sdma_hdr->jt_size * 4);
5177                 }
5178         }
5179 }
5180
5181 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5182 {
5183         uint32_t rlc_g_offset, rlc_g_size, tmp;
5184         uint64_t gpu_addr;
5185
5186         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5187         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5188         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5189
5190         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5191         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5192         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5193
5194         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5195         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5196         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5197
5198         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5199         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5200                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5201                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5202                 return -EINVAL;
5203         }
5204
5205         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5206         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5207                 DRM_ERROR("RLC ROM should halt itself\n");
5208                 return -EINVAL;
5209         }
5210
5211         return 0;
5212 }
5213
5214 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5215 {
5216         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5217         uint32_t tmp;
5218         int i;
5219         uint64_t addr;
5220
5221         /* Trigger an invalidation of the L1 instruction caches */
5222         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5223         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5224         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5225
5226         /* Wait for invalidation complete */
5227         for (i = 0; i < usec_timeout; i++) {
5228                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5229                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5230                         INVALIDATE_CACHE_COMPLETE))
5231                         break;
5232                 udelay(1);
5233         }
5234
5235         if (i >= usec_timeout) {
5236                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5237                 return -EINVAL;
5238         }
5239
5240         /* Program me ucode address into intruction cache address register */
5241         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5242                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5243         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5244                         lower_32_bits(addr) & 0xFFFFF000);
5245         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5246                         upper_32_bits(addr));
5247
5248         return 0;
5249 }
5250
5251 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5252 {
5253         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5254         uint32_t tmp;
5255         int i;
5256         uint64_t addr;
5257
5258         /* Trigger an invalidation of the L1 instruction caches */
5259         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5260         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5261         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5262
5263         /* Wait for invalidation complete */
5264         for (i = 0; i < usec_timeout; i++) {
5265                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5266                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5267                         INVALIDATE_CACHE_COMPLETE))
5268                         break;
5269                 udelay(1);
5270         }
5271
5272         if (i >= usec_timeout) {
5273                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5274                 return -EINVAL;
5275         }
5276
5277         /* Program ce ucode address into intruction cache address register */
5278         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5279                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5280         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5281                         lower_32_bits(addr) & 0xFFFFF000);
5282         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5283                         upper_32_bits(addr));
5284
5285         return 0;
5286 }
5287
5288 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5289 {
5290         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5291         uint32_t tmp;
5292         int i;
5293         uint64_t addr;
5294
5295         /* Trigger an invalidation of the L1 instruction caches */
5296         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5297         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5298         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5299
5300         /* Wait for invalidation complete */
5301         for (i = 0; i < usec_timeout; i++) {
5302                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5303                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5304                         INVALIDATE_CACHE_COMPLETE))
5305                         break;
5306                 udelay(1);
5307         }
5308
5309         if (i >= usec_timeout) {
5310                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5311                 return -EINVAL;
5312         }
5313
5314         /* Program pfp ucode address into intruction cache address register */
5315         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5316                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5317         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5318                         lower_32_bits(addr) & 0xFFFFF000);
5319         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5320                         upper_32_bits(addr));
5321
5322         return 0;
5323 }
5324
5325 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5326 {
5327         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5328         uint32_t tmp;
5329         int i;
5330         uint64_t addr;
5331
5332         /* Trigger an invalidation of the L1 instruction caches */
5333         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5334         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5335         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5336
5337         /* Wait for invalidation complete */
5338         for (i = 0; i < usec_timeout; i++) {
5339                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5340                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5341                         INVALIDATE_CACHE_COMPLETE))
5342                         break;
5343                 udelay(1);
5344         }
5345
5346         if (i >= usec_timeout) {
5347                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5348                 return -EINVAL;
5349         }
5350
5351         /* Program mec1 ucode address into intruction cache address register */
5352         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5353                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5354         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5355                         lower_32_bits(addr) & 0xFFFFF000);
5356         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5357                         upper_32_bits(addr));
5358
5359         return 0;
5360 }
5361
5362 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5363 {
5364         uint32_t cp_status;
5365         uint32_t bootload_status;
5366         int i, r;
5367
5368         for (i = 0; i < adev->usec_timeout; i++) {
5369                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5370                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5371                 if ((cp_status == 0) &&
5372                     (REG_GET_FIELD(bootload_status,
5373                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5374                         break;
5375                 }
5376                 udelay(1);
5377         }
5378
5379         if (i >= adev->usec_timeout) {
5380                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5381                 return -ETIMEDOUT;
5382         }
5383
5384         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5385                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5386                 if (r)
5387                         return r;
5388
5389                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5390                 if (r)
5391                         return r;
5392
5393                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5394                 if (r)
5395                         return r;
5396
5397                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5398                 if (r)
5399                         return r;
5400         }
5401
5402         return 0;
5403 }
5404
5405 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5406 {
5407         int i;
5408         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5409
5410         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5411         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5412         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5413
5414         if (adev->asic_type == CHIP_NAVI12) {
5415                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5416         } else {
5417                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5418         }
5419
5420         for (i = 0; i < adev->usec_timeout; i++) {
5421                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5422                         break;
5423                 udelay(1);
5424         }
5425
5426         if (i >= adev->usec_timeout)
5427                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5428
5429         return 0;
5430 }
5431
5432 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5433 {
5434         int r;
5435         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5436         const __le32 *fw_data;
5437         unsigned i, fw_size;
5438         uint32_t tmp;
5439         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5440
5441         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5442                 adev->gfx.pfp_fw->data;
5443
5444         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5445
5446         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5447                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5448         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5449
5450         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5451                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5452                                       &adev->gfx.pfp.pfp_fw_obj,
5453                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5454                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5455         if (r) {
5456                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5457                 gfx_v10_0_pfp_fini(adev);
5458                 return r;
5459         }
5460
5461         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5462
5463         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5464         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5465
5466         /* Trigger an invalidation of the L1 instruction caches */
5467         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5468         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5469         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5470
5471         /* Wait for invalidation complete */
5472         for (i = 0; i < usec_timeout; i++) {
5473                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5474                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5475                         INVALIDATE_CACHE_COMPLETE))
5476                         break;
5477                 udelay(1);
5478         }
5479
5480         if (i >= usec_timeout) {
5481                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5482                 return -EINVAL;
5483         }
5484
5485         if (amdgpu_emu_mode == 1)
5486                 adev->nbio.funcs->hdp_flush(adev, NULL);
5487
5488         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5489         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5490         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5491         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5492         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5493         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5494         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5495                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5496         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5497                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5498
5499         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5500
5501         for (i = 0; i < pfp_hdr->jt_size; i++)
5502                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5503                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5504
5505         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5506
5507         return 0;
5508 }
5509
5510 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5511 {
5512         int r;
5513         const struct gfx_firmware_header_v1_0 *ce_hdr;
5514         const __le32 *fw_data;
5515         unsigned i, fw_size;
5516         uint32_t tmp;
5517         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5518
5519         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5520                 adev->gfx.ce_fw->data;
5521
5522         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5523
5524         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5525                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5526         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5527
5528         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5529                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5530                                       &adev->gfx.ce.ce_fw_obj,
5531                                       &adev->gfx.ce.ce_fw_gpu_addr,
5532                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5533         if (r) {
5534                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5535                 gfx_v10_0_ce_fini(adev);
5536                 return r;
5537         }
5538
5539         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5540
5541         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5542         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5543
5544         /* Trigger an invalidation of the L1 instruction caches */
5545         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5546         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5547         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5548
5549         /* Wait for invalidation complete */
5550         for (i = 0; i < usec_timeout; i++) {
5551                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5552                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5553                         INVALIDATE_CACHE_COMPLETE))
5554                         break;
5555                 udelay(1);
5556         }
5557
5558         if (i >= usec_timeout) {
5559                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5560                 return -EINVAL;
5561         }
5562
5563         if (amdgpu_emu_mode == 1)
5564                 adev->nbio.funcs->hdp_flush(adev, NULL);
5565
5566         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5567         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5568         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5569         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5570         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5571         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5572                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5573         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5574                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5575
5576         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5577
5578         for (i = 0; i < ce_hdr->jt_size; i++)
5579                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5580                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5581
5582         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5583
5584         return 0;
5585 }
5586
5587 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5588 {
5589         int r;
5590         const struct gfx_firmware_header_v1_0 *me_hdr;
5591         const __le32 *fw_data;
5592         unsigned i, fw_size;
5593         uint32_t tmp;
5594         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5595
5596         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5597                 adev->gfx.me_fw->data;
5598
5599         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5600
5601         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5602                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5603         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5604
5605         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5606                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5607                                       &adev->gfx.me.me_fw_obj,
5608                                       &adev->gfx.me.me_fw_gpu_addr,
5609                                       (void **)&adev->gfx.me.me_fw_ptr);
5610         if (r) {
5611                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5612                 gfx_v10_0_me_fini(adev);
5613                 return r;
5614         }
5615
5616         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5617
5618         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5619         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5620
5621         /* Trigger an invalidation of the L1 instruction caches */
5622         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5623         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5624         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5625
5626         /* Wait for invalidation complete */
5627         for (i = 0; i < usec_timeout; i++) {
5628                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5629                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5630                         INVALIDATE_CACHE_COMPLETE))
5631                         break;
5632                 udelay(1);
5633         }
5634
5635         if (i >= usec_timeout) {
5636                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5637                 return -EINVAL;
5638         }
5639
5640         if (amdgpu_emu_mode == 1)
5641                 adev->nbio.funcs->hdp_flush(adev, NULL);
5642
5643         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5644         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5645         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5646         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5647         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5648         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5649                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5650         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5651                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5652
5653         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5654
5655         for (i = 0; i < me_hdr->jt_size; i++)
5656                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5657                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5658
5659         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5660
5661         return 0;
5662 }
5663
5664 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5665 {
5666         int r;
5667
5668         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5669                 return -EINVAL;
5670
5671         gfx_v10_0_cp_gfx_enable(adev, false);
5672
5673         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5674         if (r) {
5675                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5676                 return r;
5677         }
5678
5679         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5680         if (r) {
5681                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5682                 return r;
5683         }
5684
5685         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5686         if (r) {
5687                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5688                 return r;
5689         }
5690
5691         return 0;
5692 }
5693
5694 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5695 {
5696         struct amdgpu_ring *ring;
5697         const struct cs_section_def *sect = NULL;
5698         const struct cs_extent_def *ext = NULL;
5699         int r, i;
5700         int ctx_reg_offset;
5701
5702         /* init the CP */
5703         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5704                      adev->gfx.config.max_hw_contexts - 1);
5705         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5706
5707         gfx_v10_0_cp_gfx_enable(adev, true);
5708
5709         ring = &adev->gfx.gfx_ring[0];
5710         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5711         if (r) {
5712                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5713                 return r;
5714         }
5715
5716         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5717         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5718
5719         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5720         amdgpu_ring_write(ring, 0x80000000);
5721         amdgpu_ring_write(ring, 0x80000000);
5722
5723         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5724                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5725                         if (sect->id == SECT_CONTEXT) {
5726                                 amdgpu_ring_write(ring,
5727                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5728                                                           ext->reg_count));
5729                                 amdgpu_ring_write(ring, ext->reg_index -
5730                                                   PACKET3_SET_CONTEXT_REG_START);
5731                                 for (i = 0; i < ext->reg_count; i++)
5732                                         amdgpu_ring_write(ring, ext->extent[i]);
5733                         }
5734                 }
5735         }
5736
5737         ctx_reg_offset =
5738                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5739         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5740         amdgpu_ring_write(ring, ctx_reg_offset);
5741         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5742
5743         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5744         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5745
5746         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5747         amdgpu_ring_write(ring, 0);
5748
5749         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5750         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5751         amdgpu_ring_write(ring, 0x8000);
5752         amdgpu_ring_write(ring, 0x8000);
5753
5754         amdgpu_ring_commit(ring);
5755
5756         /* submit cs packet to copy state 0 to next available state */
5757         if (adev->gfx.num_gfx_rings > 1) {
5758                 /* maximum supported gfx ring is 2 */
5759                 ring = &adev->gfx.gfx_ring[1];
5760                 r = amdgpu_ring_alloc(ring, 2);
5761                 if (r) {
5762                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5763                         return r;
5764                 }
5765
5766                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5767                 amdgpu_ring_write(ring, 0);
5768
5769                 amdgpu_ring_commit(ring);
5770         }
5771         return 0;
5772 }
5773
5774 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5775                                          CP_PIPE_ID pipe)
5776 {
5777         u32 tmp;
5778
5779         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5780         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5781
5782         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5783 }
5784
5785 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5786                                           struct amdgpu_ring *ring)
5787 {
5788         u32 tmp;
5789
5790         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5791         if (ring->use_doorbell) {
5792                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5793                                     DOORBELL_OFFSET, ring->doorbell_index);
5794                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5795                                     DOORBELL_EN, 1);
5796         } else {
5797                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5798                                     DOORBELL_EN, 0);
5799         }
5800         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5801         switch (adev->asic_type) {
5802         case CHIP_SIENNA_CICHLID:
5803         case CHIP_NAVY_FLOUNDER:
5804                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5805                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5806                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5807
5808                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5809                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5810                 break;
5811         default:
5812                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5813                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5814                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5815
5816                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5817                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5818                 break;
5819         }
5820 }
5821
5822 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5823 {
5824         struct amdgpu_ring *ring;
5825         u32 tmp;
5826         u32 rb_bufsz;
5827         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5828         u32 i;
5829
5830         /* Set the write pointer delay */
5831         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5832
5833         /* set the RB to use vmid 0 */
5834         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5835
5836         /* Init gfx ring 0 for pipe 0 */
5837         mutex_lock(&adev->srbm_mutex);
5838         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5839
5840         /* Set ring buffer size */
5841         ring = &adev->gfx.gfx_ring[0];
5842         rb_bufsz = order_base_2(ring->ring_size / 8);
5843         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5844         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5845 #ifdef __BIG_ENDIAN
5846         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5847 #endif
5848         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5849
5850         /* Initialize the ring buffer's write pointers */
5851         ring->wptr = 0;
5852         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5853         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5854
5855         /* set the wb address wether it's enabled or not */
5856         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5857         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5858         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5859                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5860
5861         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5862         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5863                      lower_32_bits(wptr_gpu_addr));
5864         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5865                      upper_32_bits(wptr_gpu_addr));
5866
5867         mdelay(1);
5868         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5869
5870         rb_addr = ring->gpu_addr >> 8;
5871         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5872         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5873
5874         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5875
5876         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5877         mutex_unlock(&adev->srbm_mutex);
5878
5879         /* Init gfx ring 1 for pipe 1 */
5880         if (adev->gfx.num_gfx_rings > 1) {
5881                 mutex_lock(&adev->srbm_mutex);
5882                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5883                 /* maximum supported gfx ring is 2 */
5884                 ring = &adev->gfx.gfx_ring[1];
5885                 rb_bufsz = order_base_2(ring->ring_size / 8);
5886                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5887                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5888                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5889                 /* Initialize the ring buffer's write pointers */
5890                 ring->wptr = 0;
5891                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5892                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5893                 /* Set the wb address wether it's enabled or not */
5894                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5895                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5896                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5897                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5898                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5899                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5900                              lower_32_bits(wptr_gpu_addr));
5901                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5902                              upper_32_bits(wptr_gpu_addr));
5903
5904                 mdelay(1);
5905                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5906
5907                 rb_addr = ring->gpu_addr >> 8;
5908                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5909                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5910                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5911
5912                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5913                 mutex_unlock(&adev->srbm_mutex);
5914         }
5915         /* Switch to pipe 0 */
5916         mutex_lock(&adev->srbm_mutex);
5917         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5918         mutex_unlock(&adev->srbm_mutex);
5919
5920         /* start the ring */
5921         gfx_v10_0_cp_gfx_start(adev);
5922
5923         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5924                 ring = &adev->gfx.gfx_ring[i];
5925                 ring->sched.ready = true;
5926         }
5927
5928         return 0;
5929 }
5930
5931 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5932 {
5933         if (enable) {
5934                 switch (adev->asic_type) {
5935                 case CHIP_SIENNA_CICHLID:
5936                 case CHIP_NAVY_FLOUNDER:
5937                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
5938                         break;
5939                 default:
5940                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5941                         break;
5942                 }
5943         } else {
5944                 switch (adev->asic_type) {
5945                 case CHIP_SIENNA_CICHLID:
5946                 case CHIP_NAVY_FLOUNDER:
5947                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
5948                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5949                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5950                         break;
5951                 default:
5952                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
5953                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5954                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5955                         break;
5956                 }
5957                 adev->gfx.kiq.ring.sched.ready = false;
5958         }
5959         udelay(50);
5960 }
5961
5962 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
5963 {
5964         const struct gfx_firmware_header_v1_0 *mec_hdr;
5965         const __le32 *fw_data;
5966         unsigned i;
5967         u32 tmp;
5968         u32 usec_timeout = 50000; /* Wait for 50 ms */
5969
5970         if (!adev->gfx.mec_fw)
5971                 return -EINVAL;
5972
5973         gfx_v10_0_cp_compute_enable(adev, false);
5974
5975         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
5976         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
5977
5978         fw_data = (const __le32 *)
5979                 (adev->gfx.mec_fw->data +
5980                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
5981
5982         /* Trigger an invalidation of the L1 instruction caches */
5983         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5984         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5985         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5986
5987         /* Wait for invalidation complete */
5988         for (i = 0; i < usec_timeout; i++) {
5989                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5990                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5991                                        INVALIDATE_CACHE_COMPLETE))
5992                         break;
5993                 udelay(1);
5994         }
5995
5996         if (i >= usec_timeout) {
5997                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5998                 return -EINVAL;
5999         }
6000
6001         if (amdgpu_emu_mode == 1)
6002                 adev->nbio.funcs->hdp_flush(adev, NULL);
6003
6004         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6005         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6006         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6007         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6008         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6009
6010         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6011                      0xFFFFF000);
6012         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6013                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6014
6015         /* MEC1 */
6016         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6017
6018         for (i = 0; i < mec_hdr->jt_size; i++)
6019                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6020                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6021
6022         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6023
6024         /*
6025          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6026          * different microcode than MEC1.
6027          */
6028
6029         return 0;
6030 }
6031
6032 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6033 {
6034         uint32_t tmp;
6035         struct amdgpu_device *adev = ring->adev;
6036
6037         /* tell RLC which is KIQ queue */
6038         switch (adev->asic_type) {
6039         case CHIP_SIENNA_CICHLID:
6040         case CHIP_NAVY_FLOUNDER:
6041                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6042                 tmp &= 0xffffff00;
6043                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6044                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6045                 tmp |= 0x80;
6046                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6047                 break;
6048         default:
6049                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6050                 tmp &= 0xffffff00;
6051                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6052                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6053                 tmp |= 0x80;
6054                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6055                 break;
6056         }
6057 }
6058
6059 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6060 {
6061         struct amdgpu_device *adev = ring->adev;
6062         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6063         uint64_t hqd_gpu_addr, wb_gpu_addr;
6064         uint32_t tmp;
6065         uint32_t rb_bufsz;
6066
6067         /* set up gfx hqd wptr */
6068         mqd->cp_gfx_hqd_wptr = 0;
6069         mqd->cp_gfx_hqd_wptr_hi = 0;
6070
6071         /* set the pointer to the MQD */
6072         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6073         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6074
6075         /* set up mqd control */
6076         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6077         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6078         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6079         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6080         mqd->cp_gfx_mqd_control = tmp;
6081
6082         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6083         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6084         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6085         mqd->cp_gfx_hqd_vmid = 0;
6086
6087         /* set up default queue priority level
6088          * 0x0 = low priority, 0x1 = high priority */
6089         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6090         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6091         mqd->cp_gfx_hqd_queue_priority = tmp;
6092
6093         /* set up time quantum */
6094         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6095         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6096         mqd->cp_gfx_hqd_quantum = tmp;
6097
6098         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6099         hqd_gpu_addr = ring->gpu_addr >> 8;
6100         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6101         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6102
6103         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6104         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6105         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6106         mqd->cp_gfx_hqd_rptr_addr_hi =
6107                 upper_32_bits(wb_gpu_addr) & 0xffff;
6108
6109         /* set up rb_wptr_poll addr */
6110         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6111         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6112         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6113
6114         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6115         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6116         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6117         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6118         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6119 #ifdef __BIG_ENDIAN
6120         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6121 #endif
6122         mqd->cp_gfx_hqd_cntl = tmp;
6123
6124         /* set up cp_doorbell_control */
6125         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6126         if (ring->use_doorbell) {
6127                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6128                                     DOORBELL_OFFSET, ring->doorbell_index);
6129                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6130                                     DOORBELL_EN, 1);
6131         } else
6132                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6133                                     DOORBELL_EN, 0);
6134         mqd->cp_rb_doorbell_control = tmp;
6135
6136         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6137         ring->wptr = 0;
6138         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6139
6140         /* active the queue */
6141         mqd->cp_gfx_hqd_active = 1;
6142
6143         return 0;
6144 }
6145
6146 #ifdef BRING_UP_DEBUG
6147 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6148 {
6149         struct amdgpu_device *adev = ring->adev;
6150         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6151
6152         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6153         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6154         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6155
6156         /* set GFX_MQD_BASE */
6157         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6158         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6159
6160         /* set GFX_MQD_CONTROL */
6161         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6162
6163         /* set GFX_HQD_VMID to 0 */
6164         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6165
6166         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6167                         mqd->cp_gfx_hqd_queue_priority);
6168         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6169
6170         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6171         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6172         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6173
6174         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6175         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6176         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6177
6178         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6179         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6180
6181         /* set RB_WPTR_POLL_ADDR */
6182         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6183         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6184
6185         /* set RB_DOORBELL_CONTROL */
6186         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6187
6188         /* active the queue */
6189         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6190
6191         return 0;
6192 }
6193 #endif
6194
6195 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6196 {
6197         struct amdgpu_device *adev = ring->adev;
6198         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6199         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6200
6201         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6202                 memset((void *)mqd, 0, sizeof(*mqd));
6203                 mutex_lock(&adev->srbm_mutex);
6204                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6205                 gfx_v10_0_gfx_mqd_init(ring);
6206 #ifdef BRING_UP_DEBUG
6207                 gfx_v10_0_gfx_queue_init_register(ring);
6208 #endif
6209                 nv_grbm_select(adev, 0, 0, 0, 0);
6210                 mutex_unlock(&adev->srbm_mutex);
6211                 if (adev->gfx.me.mqd_backup[mqd_idx])
6212                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6213         } else if (amdgpu_in_reset(adev)) {
6214                 /* reset mqd with the backup copy */
6215                 if (adev->gfx.me.mqd_backup[mqd_idx])
6216                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6217                 /* reset the ring */
6218                 ring->wptr = 0;
6219                 adev->wb.wb[ring->wptr_offs] = 0;
6220                 amdgpu_ring_clear_ring(ring);
6221 #ifdef BRING_UP_DEBUG
6222                 mutex_lock(&adev->srbm_mutex);
6223                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6224                 gfx_v10_0_gfx_queue_init_register(ring);
6225                 nv_grbm_select(adev, 0, 0, 0, 0);
6226                 mutex_unlock(&adev->srbm_mutex);
6227 #endif
6228         } else {
6229                 amdgpu_ring_clear_ring(ring);
6230         }
6231
6232         return 0;
6233 }
6234
6235 #ifndef BRING_UP_DEBUG
6236 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6237 {
6238         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6239         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6240         int r, i;
6241
6242         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6243                 return -EINVAL;
6244
6245         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6246                                         adev->gfx.num_gfx_rings);
6247         if (r) {
6248                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6249                 return r;
6250         }
6251
6252         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6253                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6254
6255         return amdgpu_ring_test_helper(kiq_ring);
6256 }
6257 #endif
6258
6259 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6260 {
6261         int r, i;
6262         struct amdgpu_ring *ring;
6263
6264         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6265                 ring = &adev->gfx.gfx_ring[i];
6266
6267                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6268                 if (unlikely(r != 0))
6269                         goto done;
6270
6271                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6272                 if (!r) {
6273                         r = gfx_v10_0_gfx_init_queue(ring);
6274                         amdgpu_bo_kunmap(ring->mqd_obj);
6275                         ring->mqd_ptr = NULL;
6276                 }
6277                 amdgpu_bo_unreserve(ring->mqd_obj);
6278                 if (r)
6279                         goto done;
6280         }
6281 #ifndef BRING_UP_DEBUG
6282         r = gfx_v10_0_kiq_enable_kgq(adev);
6283         if (r)
6284                 goto done;
6285 #endif
6286         r = gfx_v10_0_cp_gfx_start(adev);
6287         if (r)
6288                 goto done;
6289
6290         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6291                 ring = &adev->gfx.gfx_ring[i];
6292                 ring->sched.ready = true;
6293         }
6294 done:
6295         return r;
6296 }
6297
6298 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6299 {
6300         struct amdgpu_device *adev = ring->adev;
6301
6302         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6303                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6304                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6305                         mqd->cp_hqd_queue_priority =
6306                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6307                 }
6308         }
6309 }
6310
6311 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6312 {
6313         struct amdgpu_device *adev = ring->adev;
6314         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6315         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6316         uint32_t tmp;
6317
6318         mqd->header = 0xC0310800;
6319         mqd->compute_pipelinestat_enable = 0x00000001;
6320         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6321         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6322         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6323         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6324         mqd->compute_misc_reserved = 0x00000003;
6325
6326         eop_base_addr = ring->eop_gpu_addr >> 8;
6327         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6328         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6329
6330         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6331         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6332         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6333                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6334
6335         mqd->cp_hqd_eop_control = tmp;
6336
6337         /* enable doorbell? */
6338         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6339
6340         if (ring->use_doorbell) {
6341                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6342                                     DOORBELL_OFFSET, ring->doorbell_index);
6343                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6344                                     DOORBELL_EN, 1);
6345                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6346                                     DOORBELL_SOURCE, 0);
6347                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6348                                     DOORBELL_HIT, 0);
6349         } else {
6350                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6351                                     DOORBELL_EN, 0);
6352         }
6353
6354         mqd->cp_hqd_pq_doorbell_control = tmp;
6355
6356         /* disable the queue if it's active */
6357         ring->wptr = 0;
6358         mqd->cp_hqd_dequeue_request = 0;
6359         mqd->cp_hqd_pq_rptr = 0;
6360         mqd->cp_hqd_pq_wptr_lo = 0;
6361         mqd->cp_hqd_pq_wptr_hi = 0;
6362
6363         /* set the pointer to the MQD */
6364         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6365         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6366
6367         /* set MQD vmid to 0 */
6368         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6369         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6370         mqd->cp_mqd_control = tmp;
6371
6372         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6373         hqd_gpu_addr = ring->gpu_addr >> 8;
6374         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6375         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6376
6377         /* set up the HQD, this is similar to CP_RB0_CNTL */
6378         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6379         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6380                             (order_base_2(ring->ring_size / 4) - 1));
6381         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6382                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6383 #ifdef __BIG_ENDIAN
6384         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6385 #endif
6386         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6387         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6388         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6389         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6390         mqd->cp_hqd_pq_control = tmp;
6391
6392         /* set the wb address whether it's enabled or not */
6393         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6394         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6395         mqd->cp_hqd_pq_rptr_report_addr_hi =
6396                 upper_32_bits(wb_gpu_addr) & 0xffff;
6397
6398         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6399         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6400         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6401         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6402
6403         tmp = 0;
6404         /* enable the doorbell if requested */
6405         if (ring->use_doorbell) {
6406                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6407                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6408                                 DOORBELL_OFFSET, ring->doorbell_index);
6409
6410                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6411                                     DOORBELL_EN, 1);
6412                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6413                                     DOORBELL_SOURCE, 0);
6414                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6415                                     DOORBELL_HIT, 0);
6416         }
6417
6418         mqd->cp_hqd_pq_doorbell_control = tmp;
6419
6420         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6421         ring->wptr = 0;
6422         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6423
6424         /* set the vmid for the queue */
6425         mqd->cp_hqd_vmid = 0;
6426
6427         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6428         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6429         mqd->cp_hqd_persistent_state = tmp;
6430
6431         /* set MIN_IB_AVAIL_SIZE */
6432         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6433         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6434         mqd->cp_hqd_ib_control = tmp;
6435
6436         /* set static priority for a compute queue/ring */
6437         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6438
6439         /* map_queues packet doesn't need activate the queue,
6440          * so only kiq need set this field.
6441          */
6442         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6443                 mqd->cp_hqd_active = 1;
6444
6445         return 0;
6446 }
6447
6448 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6449 {
6450         struct amdgpu_device *adev = ring->adev;
6451         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6452         int j;
6453
6454         /* inactivate the queue */
6455         if (amdgpu_sriov_vf(adev))
6456                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6457
6458         /* disable wptr polling */
6459         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6460
6461         /* write the EOP addr */
6462         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6463                mqd->cp_hqd_eop_base_addr_lo);
6464         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6465                mqd->cp_hqd_eop_base_addr_hi);
6466
6467         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6468         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6469                mqd->cp_hqd_eop_control);
6470
6471         /* enable doorbell? */
6472         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6473                mqd->cp_hqd_pq_doorbell_control);
6474
6475         /* disable the queue if it's active */
6476         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6477                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6478                 for (j = 0; j < adev->usec_timeout; j++) {
6479                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6480                                 break;
6481                         udelay(1);
6482                 }
6483                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6484                        mqd->cp_hqd_dequeue_request);
6485                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6486                        mqd->cp_hqd_pq_rptr);
6487                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6488                        mqd->cp_hqd_pq_wptr_lo);
6489                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6490                        mqd->cp_hqd_pq_wptr_hi);
6491         }
6492
6493         /* set the pointer to the MQD */
6494         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6495                mqd->cp_mqd_base_addr_lo);
6496         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6497                mqd->cp_mqd_base_addr_hi);
6498
6499         /* set MQD vmid to 0 */
6500         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6501                mqd->cp_mqd_control);
6502
6503         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6504         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6505                mqd->cp_hqd_pq_base_lo);
6506         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6507                mqd->cp_hqd_pq_base_hi);
6508
6509         /* set up the HQD, this is similar to CP_RB0_CNTL */
6510         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6511                mqd->cp_hqd_pq_control);
6512
6513         /* set the wb address whether it's enabled or not */
6514         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6515                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6516         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6517                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6518
6519         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6520         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6521                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6522         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6523                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6524
6525         /* enable the doorbell if requested */
6526         if (ring->use_doorbell) {
6527                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6528                         (adev->doorbell_index.kiq * 2) << 2);
6529                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6530                         (adev->doorbell_index.userqueue_end * 2) << 2);
6531         }
6532
6533         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6534                mqd->cp_hqd_pq_doorbell_control);
6535
6536         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6537         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6538                mqd->cp_hqd_pq_wptr_lo);
6539         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6540                mqd->cp_hqd_pq_wptr_hi);
6541
6542         /* set the vmid for the queue */
6543         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6544
6545         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6546                mqd->cp_hqd_persistent_state);
6547
6548         /* activate the queue */
6549         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6550                mqd->cp_hqd_active);
6551
6552         if (ring->use_doorbell)
6553                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6554
6555         return 0;
6556 }
6557
6558 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6559 {
6560         struct amdgpu_device *adev = ring->adev;
6561         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6562         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6563
6564         gfx_v10_0_kiq_setting(ring);
6565
6566         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6567                 /* reset MQD to a clean status */
6568                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6569                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6570
6571                 /* reset ring buffer */
6572                 ring->wptr = 0;
6573                 amdgpu_ring_clear_ring(ring);
6574
6575                 mutex_lock(&adev->srbm_mutex);
6576                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6577                 gfx_v10_0_kiq_init_register(ring);
6578                 nv_grbm_select(adev, 0, 0, 0, 0);
6579                 mutex_unlock(&adev->srbm_mutex);
6580         } else {
6581                 memset((void *)mqd, 0, sizeof(*mqd));
6582                 mutex_lock(&adev->srbm_mutex);
6583                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6584                 gfx_v10_0_compute_mqd_init(ring);
6585                 gfx_v10_0_kiq_init_register(ring);
6586                 nv_grbm_select(adev, 0, 0, 0, 0);
6587                 mutex_unlock(&adev->srbm_mutex);
6588
6589                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6590                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6591         }
6592
6593         return 0;
6594 }
6595
6596 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6597 {
6598         struct amdgpu_device *adev = ring->adev;
6599         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6600         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6601
6602         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6603                 memset((void *)mqd, 0, sizeof(*mqd));
6604                 mutex_lock(&adev->srbm_mutex);
6605                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6606                 gfx_v10_0_compute_mqd_init(ring);
6607                 nv_grbm_select(adev, 0, 0, 0, 0);
6608                 mutex_unlock(&adev->srbm_mutex);
6609
6610                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6611                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6612         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6613                 /* reset MQD to a clean status */
6614                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6615                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6616
6617                 /* reset ring buffer */
6618                 ring->wptr = 0;
6619                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6620                 amdgpu_ring_clear_ring(ring);
6621         } else {
6622                 amdgpu_ring_clear_ring(ring);
6623         }
6624
6625         return 0;
6626 }
6627
6628 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6629 {
6630         struct amdgpu_ring *ring;
6631         int r;
6632
6633         ring = &adev->gfx.kiq.ring;
6634
6635         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6636         if (unlikely(r != 0))
6637                 return r;
6638
6639         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6640         if (unlikely(r != 0))
6641                 return r;
6642
6643         gfx_v10_0_kiq_init_queue(ring);
6644         amdgpu_bo_kunmap(ring->mqd_obj);
6645         ring->mqd_ptr = NULL;
6646         amdgpu_bo_unreserve(ring->mqd_obj);
6647         ring->sched.ready = true;
6648         return 0;
6649 }
6650
6651 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6652 {
6653         struct amdgpu_ring *ring = NULL;
6654         int r = 0, i;
6655
6656         gfx_v10_0_cp_compute_enable(adev, true);
6657
6658         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6659                 ring = &adev->gfx.compute_ring[i];
6660
6661                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6662                 if (unlikely(r != 0))
6663                         goto done;
6664                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6665                 if (!r) {
6666                         r = gfx_v10_0_kcq_init_queue(ring);
6667                         amdgpu_bo_kunmap(ring->mqd_obj);
6668                         ring->mqd_ptr = NULL;
6669                 }
6670                 amdgpu_bo_unreserve(ring->mqd_obj);
6671                 if (r)
6672                         goto done;
6673         }
6674
6675         r = amdgpu_gfx_enable_kcq(adev);
6676 done:
6677         return r;
6678 }
6679
6680 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6681 {
6682         int r, i;
6683         struct amdgpu_ring *ring;
6684
6685         if (!(adev->flags & AMD_IS_APU))
6686                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6687
6688         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6689                 /* legacy firmware loading */
6690                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6691                 if (r)
6692                         return r;
6693
6694                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6695                 if (r)
6696                         return r;
6697         }
6698
6699         r = gfx_v10_0_kiq_resume(adev);
6700         if (r)
6701                 return r;
6702
6703         r = gfx_v10_0_kcq_resume(adev);
6704         if (r)
6705                 return r;
6706
6707         if (!amdgpu_async_gfx_ring) {
6708                 r = gfx_v10_0_cp_gfx_resume(adev);
6709                 if (r)
6710                         return r;
6711         } else {
6712                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6713                 if (r)
6714                         return r;
6715         }
6716
6717         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6718                 ring = &adev->gfx.gfx_ring[i];
6719                 r = amdgpu_ring_test_helper(ring);
6720                 if (r)
6721                         return r;
6722         }
6723
6724         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6725                 ring = &adev->gfx.compute_ring[i];
6726                 r = amdgpu_ring_test_helper(ring);
6727                 if (r)
6728                         return r;
6729         }
6730
6731         return 0;
6732 }
6733
6734 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6735 {
6736         gfx_v10_0_cp_gfx_enable(adev, enable);
6737         gfx_v10_0_cp_compute_enable(adev, enable);
6738 }
6739
6740 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6741 {
6742         uint32_t data, pattern = 0xDEADBEEF;
6743
6744         /* check if mmVGT_ESGS_RING_SIZE_UMD
6745          * has been remapped to mmVGT_ESGS_RING_SIZE */
6746         switch (adev->asic_type) {
6747         case CHIP_SIENNA_CICHLID:
6748         case CHIP_NAVY_FLOUNDER:
6749                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6750                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6751                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6752
6753                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6754                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6755                         return true;
6756                 } else {
6757                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6758                         return false;
6759                 }
6760                 break;
6761         default:
6762                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6763                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6764                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6765
6766                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6767                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6768                         return true;
6769                 } else {
6770                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6771                         return false;
6772                 }
6773                 break;
6774         }
6775 }
6776
6777 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6778 {
6779         uint32_t data;
6780
6781         /* initialize cam_index to 0
6782          * index will auto-inc after each data writting */
6783         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6784
6785         switch (adev->asic_type) {
6786         case CHIP_SIENNA_CICHLID:
6787         case CHIP_NAVY_FLOUNDER:
6788                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6789                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6790                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6791                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6792                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6793                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6794                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6795
6796                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6797                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6798                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6799                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6800                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6801                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6802                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6803
6804                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6805                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6806                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6807                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6808                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6809                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6810                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6811
6812                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6813                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6814                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6815                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6816                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6817                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6818                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6819
6820                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6821                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6822                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6823                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6824                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6825                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6826                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6827
6828                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6829                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6830                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6831                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6832                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6833                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6834                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6835
6836                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6837                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6838                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6839                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6840                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6841                 break;
6842         default:
6843                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6844                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6845                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6846                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6847                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6848                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6849                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6850
6851                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6852                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6853                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6854                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6855                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6856                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6857                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6858
6859                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6860                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6861                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6862                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6863                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6864                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6865                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6866
6867                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6868                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6869                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6870                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6871                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6872                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6873                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6874
6875                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6876                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6877                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6878                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6879                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6880                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6881                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6882
6883                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6884                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6885                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6886                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6887                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6888                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6889                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6890
6891                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6892                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6893                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6894                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6895                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6896                 break;
6897         }
6898
6899         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6900         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6901 }
6902
6903 static int gfx_v10_0_hw_init(void *handle)
6904 {
6905         int r;
6906         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6907
6908         if (!amdgpu_emu_mode)
6909                 gfx_v10_0_init_golden_registers(adev);
6910
6911         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6912                 /**
6913                  * For gfx 10, rlc firmware loading relies on smu firmware is
6914                  * loaded firstly, so in direct type, it has to load smc ucode
6915                  * here before rlc.
6916                  */
6917                 if (adev->smu.ppt_funcs != NULL) {
6918                         r = smu_load_microcode(&adev->smu);
6919                         if (r)
6920                                 return r;
6921
6922                         r = smu_check_fw_status(&adev->smu);
6923                         if (r) {
6924                                 pr_err("SMC firmware status is not correct\n");
6925                                 return r;
6926                         }
6927                 }
6928         }
6929
6930         /* if GRBM CAM not remapped, set up the remapping */
6931         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6932                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6933
6934         gfx_v10_0_constants_init(adev);
6935
6936         r = gfx_v10_0_rlc_resume(adev);
6937         if (r)
6938                 return r;
6939
6940         /*
6941          * init golden registers and rlc resume may override some registers,
6942          * reconfig them here
6943          */
6944         gfx_v10_0_tcp_harvest(adev);
6945
6946         r = gfx_v10_0_cp_resume(adev);
6947         if (r)
6948                 return r;
6949
6950         return r;
6951 }
6952
6953 #ifndef BRING_UP_DEBUG
6954 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
6955 {
6956         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6957         struct amdgpu_ring *kiq_ring = &kiq->ring;
6958         int i;
6959
6960         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
6961                 return -EINVAL;
6962
6963         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
6964                                         adev->gfx.num_gfx_rings))
6965                 return -ENOMEM;
6966
6967         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6968                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
6969                                            PREEMPT_QUEUES, 0, 0);
6970
6971         return amdgpu_ring_test_helper(kiq_ring);
6972 }
6973 #endif
6974
6975 static int gfx_v10_0_hw_fini(void *handle)
6976 {
6977         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6978         int r;
6979         uint32_t tmp;
6980
6981         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
6982         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
6983 #ifndef BRING_UP_DEBUG
6984         if (amdgpu_async_gfx_ring) {
6985                 r = gfx_v10_0_kiq_disable_kgq(adev);
6986                 if (r)
6987                         DRM_ERROR("KGQ disable failed\n");
6988         }
6989 #endif
6990         if (amdgpu_gfx_disable_kcq(adev))
6991                 DRM_ERROR("KCQ disable failed\n");
6992         if (amdgpu_sriov_vf(adev)) {
6993                 gfx_v10_0_cp_gfx_enable(adev, false);
6994                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
6995                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6996                 tmp &= 0xffffff00;
6997                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6998
6999                 return 0;
7000         }
7001         gfx_v10_0_cp_enable(adev, false);
7002         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7003
7004         return 0;
7005 }
7006
7007 static int gfx_v10_0_suspend(void *handle)
7008 {
7009         return gfx_v10_0_hw_fini(handle);
7010 }
7011
7012 static int gfx_v10_0_resume(void *handle)
7013 {
7014         return gfx_v10_0_hw_init(handle);
7015 }
7016
7017 static bool gfx_v10_0_is_idle(void *handle)
7018 {
7019         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7020
7021         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7022                                 GRBM_STATUS, GUI_ACTIVE))
7023                 return false;
7024         else
7025                 return true;
7026 }
7027
7028 static int gfx_v10_0_wait_for_idle(void *handle)
7029 {
7030         unsigned i;
7031         u32 tmp;
7032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7033
7034         for (i = 0; i < adev->usec_timeout; i++) {
7035                 /* read MC_STATUS */
7036                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7037                         GRBM_STATUS__GUI_ACTIVE_MASK;
7038
7039                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7040                         return 0;
7041                 udelay(1);
7042         }
7043         return -ETIMEDOUT;
7044 }
7045
7046 static int gfx_v10_0_soft_reset(void *handle)
7047 {
7048         u32 grbm_soft_reset = 0;
7049         u32 tmp;
7050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7051
7052         /* GRBM_STATUS */
7053         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7054         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7055                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7056                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7057                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7058                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7059                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7060                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7061                                                 1);
7062                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7063                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7064                                                 1);
7065         }
7066
7067         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7068                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7069                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7070                                                 1);
7071         }
7072
7073         /* GRBM_STATUS2 */
7074         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7075         switch (adev->asic_type) {
7076         case CHIP_SIENNA_CICHLID:
7077         case CHIP_NAVY_FLOUNDER:
7078                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7079                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7080                                                         GRBM_SOFT_RESET,
7081                                                         SOFT_RESET_RLC,
7082                                                         1);
7083                 break;
7084         default:
7085                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7086                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7087                                                         GRBM_SOFT_RESET,
7088                                                         SOFT_RESET_RLC,
7089                                                         1);
7090                 break;
7091         }
7092
7093         if (grbm_soft_reset) {
7094                 /* stop the rlc */
7095                 gfx_v10_0_rlc_stop(adev);
7096
7097                 /* Disable GFX parsing/prefetching */
7098                 gfx_v10_0_cp_gfx_enable(adev, false);
7099
7100                 /* Disable MEC parsing/prefetching */
7101                 gfx_v10_0_cp_compute_enable(adev, false);
7102
7103                 if (grbm_soft_reset) {
7104                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7105                         tmp |= grbm_soft_reset;
7106                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7107                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7108                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7109
7110                         udelay(50);
7111
7112                         tmp &= ~grbm_soft_reset;
7113                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7114                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7115                 }
7116
7117                 /* Wait a little for things to settle down */
7118                 udelay(50);
7119         }
7120         return 0;
7121 }
7122
7123 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7124 {
7125         uint64_t clock;
7126
7127         amdgpu_gfx_off_ctrl(adev, false);
7128         mutex_lock(&adev->gfx.gpu_clock_mutex);
7129         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7130                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7131         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7132         amdgpu_gfx_off_ctrl(adev, true);
7133         return clock;
7134 }
7135
7136 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7137                                            uint32_t vmid,
7138                                            uint32_t gds_base, uint32_t gds_size,
7139                                            uint32_t gws_base, uint32_t gws_size,
7140                                            uint32_t oa_base, uint32_t oa_size)
7141 {
7142         struct amdgpu_device *adev = ring->adev;
7143
7144         /* GDS Base */
7145         gfx_v10_0_write_data_to_reg(ring, 0, false,
7146                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7147                                     gds_base);
7148
7149         /* GDS Size */
7150         gfx_v10_0_write_data_to_reg(ring, 0, false,
7151                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7152                                     gds_size);
7153
7154         /* GWS */
7155         gfx_v10_0_write_data_to_reg(ring, 0, false,
7156                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7157                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7158
7159         /* OA */
7160         gfx_v10_0_write_data_to_reg(ring, 0, false,
7161                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7162                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7163 }
7164
7165 static int gfx_v10_0_early_init(void *handle)
7166 {
7167         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7168
7169         switch (adev->asic_type) {
7170         case CHIP_NAVI10:
7171         case CHIP_NAVI14:
7172         case CHIP_NAVI12:
7173                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7174                 break;
7175         case CHIP_SIENNA_CICHLID:
7176         case CHIP_NAVY_FLOUNDER:
7177                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7178                 break;
7179         default:
7180                 break;
7181         }
7182
7183         adev->gfx.num_compute_rings = amdgpu_num_kcq;
7184
7185         gfx_v10_0_set_kiq_pm4_funcs(adev);
7186         gfx_v10_0_set_ring_funcs(adev);
7187         gfx_v10_0_set_irq_funcs(adev);
7188         gfx_v10_0_set_gds_init(adev);
7189         gfx_v10_0_set_rlc_funcs(adev);
7190
7191         return 0;
7192 }
7193
7194 static int gfx_v10_0_late_init(void *handle)
7195 {
7196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7197         int r;
7198
7199         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7200         if (r)
7201                 return r;
7202
7203         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7204         if (r)
7205                 return r;
7206
7207         return 0;
7208 }
7209
7210 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7211 {
7212         uint32_t rlc_cntl;
7213
7214         /* if RLC is not enabled, do nothing */
7215         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7216         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7217 }
7218
7219 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7220 {
7221         uint32_t data;
7222         unsigned i;
7223
7224         data = RLC_SAFE_MODE__CMD_MASK;
7225         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7226
7227         switch (adev->asic_type) {
7228         case CHIP_SIENNA_CICHLID:
7229         case CHIP_NAVY_FLOUNDER:
7230                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7231
7232                 /* wait for RLC_SAFE_MODE */
7233                 for (i = 0; i < adev->usec_timeout; i++) {
7234                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7235                                            RLC_SAFE_MODE, CMD))
7236                                 break;
7237                         udelay(1);
7238                 }
7239                 break;
7240         default:
7241                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7242
7243                 /* wait for RLC_SAFE_MODE */
7244                 for (i = 0; i < adev->usec_timeout; i++) {
7245                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7246                                            RLC_SAFE_MODE, CMD))
7247                                 break;
7248                         udelay(1);
7249                 }
7250                 break;
7251         }
7252 }
7253
7254 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7255 {
7256         uint32_t data;
7257
7258         data = RLC_SAFE_MODE__CMD_MASK;
7259         switch (adev->asic_type) {
7260         case CHIP_SIENNA_CICHLID:
7261         case CHIP_NAVY_FLOUNDER:
7262                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7263                 break;
7264         default:
7265                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7266                 break;
7267         }
7268 }
7269
7270 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7271                                                       bool enable)
7272 {
7273         uint32_t data, def;
7274
7275         /* It is disabled by HW by default */
7276         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7277                 /* 0 - Disable some blocks' MGCG */
7278                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7279                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7280                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7281                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7282
7283                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7284                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7285                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7286                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7287                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7288                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7289
7290                 if (def != data)
7291                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7292
7293                 /* MGLS is a global flag to control all MGLS in GFX */
7294                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7295                         /* 2 - RLC memory Light sleep */
7296                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7297                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7298                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7299                                 if (def != data)
7300                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7301                         }
7302                         /* 3 - CP memory Light sleep */
7303                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7304                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7305                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7306                                 if (def != data)
7307                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7308                         }
7309                 }
7310         } else {
7311                 /* 1 - MGCG_OVERRIDE */
7312                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7313                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7314                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7315                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7316                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7317                 if (def != data)
7318                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7319
7320                 /* 2 - disable MGLS in CP */
7321                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7322                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7323                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7324                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7325                 }
7326
7327                 /* 3 - disable MGLS in RLC */
7328                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7329                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7330                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7331                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7332                 }
7333
7334         }
7335 }
7336
7337 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7338                                            bool enable)
7339 {
7340         uint32_t data, def;
7341
7342         /* Enable 3D CGCG/CGLS */
7343         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7344                 /* write cmd to clear cgcg/cgls ov */
7345                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7346                 /* unset CGCG override */
7347                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7348                 /* update CGCG and CGLS override bits */
7349                 if (def != data)
7350                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7351                 /* enable 3Dcgcg FSM(0x0000363f) */
7352                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7353                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7354                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7355                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7356                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7357                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7358                 if (def != data)
7359                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7360
7361                 /* set IDLE_POLL_COUNT(0x00900100) */
7362                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7363                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7364                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7365                 if (def != data)
7366                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7367         } else {
7368                 /* Disable CGCG/CGLS */
7369                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7370                 /* disable cgcg, cgls should be disabled */
7371                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7372                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7373                 /* disable cgcg and cgls in FSM */
7374                 if (def != data)
7375                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7376         }
7377 }
7378
7379 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7380                                                       bool enable)
7381 {
7382         uint32_t def, data;
7383
7384         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7385                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7386                 /* unset CGCG override */
7387                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7388                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7389                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7390                 else
7391                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7392                 /* update CGCG and CGLS override bits */
7393                 if (def != data)
7394                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7395
7396                 /* enable cgcg FSM(0x0000363F) */
7397                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7398                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7399                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7400                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7401                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7402                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7403                 if (def != data)
7404                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7405
7406                 /* set IDLE_POLL_COUNT(0x00900100) */
7407                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7408                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7409                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7410                 if (def != data)
7411                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7412         } else {
7413                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7414                 /* reset CGCG/CGLS bits */
7415                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7416                 /* disable cgcg and cgls in FSM */
7417                 if (def != data)
7418                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7419         }
7420 }
7421
7422 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7423                                             bool enable)
7424 {
7425         amdgpu_gfx_rlc_enter_safe_mode(adev);
7426
7427         if (enable) {
7428                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7429                  * ===  MGCG + MGLS ===
7430                  */
7431                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7432                 /* ===  CGCG /CGLS for GFX 3D Only === */
7433                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7434                 /* ===  CGCG + CGLS === */
7435                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7436         } else {
7437                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7438                  * ===  CGCG + CGLS ===
7439                  */
7440                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7441                 /* ===  CGCG /CGLS for GFX 3D Only === */
7442                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7443                 /* ===  MGCG + MGLS === */
7444                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7445         }
7446
7447         if (adev->cg_flags &
7448             (AMD_CG_SUPPORT_GFX_MGCG |
7449              AMD_CG_SUPPORT_GFX_CGLS |
7450              AMD_CG_SUPPORT_GFX_CGCG |
7451              AMD_CG_SUPPORT_GFX_3D_CGCG |
7452              AMD_CG_SUPPORT_GFX_3D_CGLS))
7453                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7454
7455         amdgpu_gfx_rlc_exit_safe_mode(adev);
7456
7457         return 0;
7458 }
7459
7460 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7461 {
7462         u32 reg, data;
7463
7464         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7465         if (amdgpu_sriov_is_pp_one_vf(adev))
7466                 data = RREG32_NO_KIQ(reg);
7467         else
7468                 data = RREG32(reg);
7469
7470         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7471         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7472
7473         if (amdgpu_sriov_is_pp_one_vf(adev))
7474                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7475         else
7476                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7477 }
7478
7479 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7480                                         uint32_t offset,
7481                                         struct soc15_reg_rlcg *entries, int arr_size)
7482 {
7483         int i;
7484         uint32_t reg;
7485
7486         if (!entries)
7487                 return false;
7488
7489         for (i = 0; i < arr_size; i++) {
7490                 const struct soc15_reg_rlcg *entry;
7491
7492                 entry = &entries[i];
7493                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7494                 if (offset == reg)
7495                         return true;
7496         }
7497
7498         return false;
7499 }
7500
7501 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7502 {
7503         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7504 }
7505
7506 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7507         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7508         .set_safe_mode = gfx_v10_0_set_safe_mode,
7509         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7510         .init = gfx_v10_0_rlc_init,
7511         .get_csb_size = gfx_v10_0_get_csb_size,
7512         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7513         .resume = gfx_v10_0_rlc_resume,
7514         .stop = gfx_v10_0_rlc_stop,
7515         .reset = gfx_v10_0_rlc_reset,
7516         .start = gfx_v10_0_rlc_start,
7517         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7518 };
7519
7520 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7521         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7522         .set_safe_mode = gfx_v10_0_set_safe_mode,
7523         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7524         .init = gfx_v10_0_rlc_init,
7525         .get_csb_size = gfx_v10_0_get_csb_size,
7526         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7527         .resume = gfx_v10_0_rlc_resume,
7528         .stop = gfx_v10_0_rlc_stop,
7529         .reset = gfx_v10_0_rlc_reset,
7530         .start = gfx_v10_0_rlc_start,
7531         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7532         .rlcg_wreg = gfx_v10_rlcg_wreg,
7533         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7534 };
7535
7536 static int gfx_v10_0_set_powergating_state(void *handle,
7537                                           enum amd_powergating_state state)
7538 {
7539         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7540         bool enable = (state == AMD_PG_STATE_GATE);
7541
7542         if (amdgpu_sriov_vf(adev))
7543                 return 0;
7544
7545         switch (adev->asic_type) {
7546         case CHIP_NAVI10:
7547         case CHIP_NAVI14:
7548         case CHIP_NAVI12:
7549         case CHIP_SIENNA_CICHLID:
7550         case CHIP_NAVY_FLOUNDER:
7551                 amdgpu_gfx_off_ctrl(adev, enable);
7552                 break;
7553         default:
7554                 break;
7555         }
7556         return 0;
7557 }
7558
7559 static int gfx_v10_0_set_clockgating_state(void *handle,
7560                                           enum amd_clockgating_state state)
7561 {
7562         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7563
7564         if (amdgpu_sriov_vf(adev))
7565                 return 0;
7566
7567         switch (adev->asic_type) {
7568         case CHIP_NAVI10:
7569         case CHIP_NAVI14:
7570         case CHIP_NAVI12:
7571         case CHIP_SIENNA_CICHLID:
7572         case CHIP_NAVY_FLOUNDER:
7573                 gfx_v10_0_update_gfx_clock_gating(adev,
7574                                                  state == AMD_CG_STATE_GATE);
7575                 break;
7576         default:
7577                 break;
7578         }
7579         return 0;
7580 }
7581
7582 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7583 {
7584         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7585         int data;
7586
7587         /* AMD_CG_SUPPORT_GFX_MGCG */
7588         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7589         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7590                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7591
7592         /* AMD_CG_SUPPORT_GFX_CGCG */
7593         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7594         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7595                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7596
7597         /* AMD_CG_SUPPORT_GFX_CGLS */
7598         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7599                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7600
7601         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7602         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7603         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7604                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7605
7606         /* AMD_CG_SUPPORT_GFX_CP_LS */
7607         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7608         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7609                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7610
7611         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7612         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7613         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7614                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7615
7616         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7617         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7618                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7619 }
7620
7621 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7622 {
7623         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7624 }
7625
7626 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7627 {
7628         struct amdgpu_device *adev = ring->adev;
7629         u64 wptr;
7630
7631         /* XXX check if swapping is necessary on BE */
7632         if (ring->use_doorbell) {
7633                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7634         } else {
7635                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7636                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7637         }
7638
7639         return wptr;
7640 }
7641
7642 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7643 {
7644         struct amdgpu_device *adev = ring->adev;
7645
7646         if (ring->use_doorbell) {
7647                 /* XXX check if swapping is necessary on BE */
7648                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7649                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7650         } else {
7651                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7652                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7653         }
7654 }
7655
7656 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7657 {
7658         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7659 }
7660
7661 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7662 {
7663         u64 wptr;
7664
7665         /* XXX check if swapping is necessary on BE */
7666         if (ring->use_doorbell)
7667                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7668         else
7669                 BUG();
7670         return wptr;
7671 }
7672
7673 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7674 {
7675         struct amdgpu_device *adev = ring->adev;
7676
7677         /* XXX check if swapping is necessary on BE */
7678         if (ring->use_doorbell) {
7679                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7680                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7681         } else {
7682                 BUG(); /* only DOORBELL method supported on gfx10 now */
7683         }
7684 }
7685
7686 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7687 {
7688         struct amdgpu_device *adev = ring->adev;
7689         u32 ref_and_mask, reg_mem_engine;
7690         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7691
7692         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7693                 switch (ring->me) {
7694                 case 1:
7695                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7696                         break;
7697                 case 2:
7698                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7699                         break;
7700                 default:
7701                         return;
7702                 }
7703                 reg_mem_engine = 0;
7704         } else {
7705                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7706                 reg_mem_engine = 1; /* pfp */
7707         }
7708
7709         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7710                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7711                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7712                                ref_and_mask, ref_and_mask, 0x20);
7713 }
7714
7715 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7716                                        struct amdgpu_job *job,
7717                                        struct amdgpu_ib *ib,
7718                                        uint32_t flags)
7719 {
7720         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7721         u32 header, control = 0;
7722
7723         if (ib->flags & AMDGPU_IB_FLAG_CE)
7724                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7725         else
7726                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7727
7728         control |= ib->length_dw | (vmid << 24);
7729
7730         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7731                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7732
7733                 if (flags & AMDGPU_IB_PREEMPTED)
7734                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7735
7736                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7737                         gfx_v10_0_ring_emit_de_meta(ring,
7738                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7739         }
7740
7741         amdgpu_ring_write(ring, header);
7742         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7743         amdgpu_ring_write(ring,
7744 #ifdef __BIG_ENDIAN
7745                 (2 << 0) |
7746 #endif
7747                 lower_32_bits(ib->gpu_addr));
7748         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7749         amdgpu_ring_write(ring, control);
7750 }
7751
7752 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7753                                            struct amdgpu_job *job,
7754                                            struct amdgpu_ib *ib,
7755                                            uint32_t flags)
7756 {
7757         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7758         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7759
7760         /* Currently, there is a high possibility to get wave ID mismatch
7761          * between ME and GDS, leading to a hw deadlock, because ME generates
7762          * different wave IDs than the GDS expects. This situation happens
7763          * randomly when at least 5 compute pipes use GDS ordered append.
7764          * The wave IDs generated by ME are also wrong after suspend/resume.
7765          * Those are probably bugs somewhere else in the kernel driver.
7766          *
7767          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7768          * GDS to 0 for this ring (me/pipe).
7769          */
7770         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7771                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7772                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7773                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7774         }
7775
7776         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7777         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7778         amdgpu_ring_write(ring,
7779 #ifdef __BIG_ENDIAN
7780                                 (2 << 0) |
7781 #endif
7782                                 lower_32_bits(ib->gpu_addr));
7783         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7784         amdgpu_ring_write(ring, control);
7785 }
7786
7787 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7788                                      u64 seq, unsigned flags)
7789 {
7790         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7791         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7792
7793         /* RELEASE_MEM - flush caches, send int */
7794         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7795         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7796                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7797                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7798                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7799                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7800                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7801                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7802         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7803                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7804
7805         /*
7806          * the address should be Qword aligned if 64bit write, Dword
7807          * aligned if only send 32bit data low (discard data high)
7808          */
7809         if (write64bit)
7810                 BUG_ON(addr & 0x7);
7811         else
7812                 BUG_ON(addr & 0x3);
7813         amdgpu_ring_write(ring, lower_32_bits(addr));
7814         amdgpu_ring_write(ring, upper_32_bits(addr));
7815         amdgpu_ring_write(ring, lower_32_bits(seq));
7816         amdgpu_ring_write(ring, upper_32_bits(seq));
7817         amdgpu_ring_write(ring, 0);
7818 }
7819
7820 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7821 {
7822         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7823         uint32_t seq = ring->fence_drv.sync_seq;
7824         uint64_t addr = ring->fence_drv.gpu_addr;
7825
7826         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7827                                upper_32_bits(addr), seq, 0xffffffff, 4);
7828 }
7829
7830 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7831                                          unsigned vmid, uint64_t pd_addr)
7832 {
7833         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7834
7835         /* compute doesn't have PFP */
7836         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7837                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7838                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7839                 amdgpu_ring_write(ring, 0x0);
7840         }
7841 }
7842
7843 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7844                                           u64 seq, unsigned int flags)
7845 {
7846         struct amdgpu_device *adev = ring->adev;
7847
7848         /* we only allocate 32bit for each seq wb address */
7849         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7850
7851         /* write fence seq to the "addr" */
7852         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7853         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7854                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7855         amdgpu_ring_write(ring, lower_32_bits(addr));
7856         amdgpu_ring_write(ring, upper_32_bits(addr));
7857         amdgpu_ring_write(ring, lower_32_bits(seq));
7858
7859         if (flags & AMDGPU_FENCE_FLAG_INT) {
7860                 /* set register to trigger INT */
7861                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7862                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7863                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7864                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7865                 amdgpu_ring_write(ring, 0);
7866                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7867         }
7868 }
7869
7870 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7871 {
7872         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7873         amdgpu_ring_write(ring, 0);
7874 }
7875
7876 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7877                                          uint32_t flags)
7878 {
7879         uint32_t dw2 = 0;
7880
7881         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7882                 gfx_v10_0_ring_emit_ce_meta(ring,
7883                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7884
7885         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7886         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7887                 /* set load_global_config & load_global_uconfig */
7888                 dw2 |= 0x8001;
7889                 /* set load_cs_sh_regs */
7890                 dw2 |= 0x01000000;
7891                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7892                 dw2 |= 0x10002;
7893
7894                 /* set load_ce_ram if preamble presented */
7895                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7896                         dw2 |= 0x10000000;
7897         } else {
7898                 /* still load_ce_ram if this is the first time preamble presented
7899                  * although there is no context switch happens.
7900                  */
7901                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7902                         dw2 |= 0x10000000;
7903         }
7904
7905         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7906         amdgpu_ring_write(ring, dw2);
7907         amdgpu_ring_write(ring, 0);
7908 }
7909
7910 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7911 {
7912         unsigned ret;
7913
7914         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7915         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7916         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7917         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7918         ret = ring->wptr & ring->buf_mask;
7919         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7920
7921         return ret;
7922 }
7923
7924 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7925 {
7926         unsigned cur;
7927         BUG_ON(offset > ring->buf_mask);
7928         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7929
7930         cur = (ring->wptr - 1) & ring->buf_mask;
7931         if (likely(cur > offset))
7932                 ring->ring[offset] = cur - offset;
7933         else
7934                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
7935 }
7936
7937 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
7938 {
7939         int i, r = 0;
7940         struct amdgpu_device *adev = ring->adev;
7941         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7942         struct amdgpu_ring *kiq_ring = &kiq->ring;
7943         unsigned long flags;
7944
7945         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7946                 return -EINVAL;
7947
7948         spin_lock_irqsave(&kiq->ring_lock, flags);
7949
7950         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
7951                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
7952                 return -ENOMEM;
7953         }
7954
7955         /* assert preemption condition */
7956         amdgpu_ring_set_preempt_cond_exec(ring, false);
7957
7958         /* assert IB preemption, emit the trailing fence */
7959         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
7960                                    ring->trail_fence_gpu_addr,
7961                                    ++ring->trail_seq);
7962         amdgpu_ring_commit(kiq_ring);
7963
7964         spin_unlock_irqrestore(&kiq->ring_lock, flags);
7965
7966         /* poll the trailing fence */
7967         for (i = 0; i < adev->usec_timeout; i++) {
7968                 if (ring->trail_seq ==
7969                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
7970                         break;
7971                 udelay(1);
7972         }
7973
7974         if (i >= adev->usec_timeout) {
7975                 r = -EINVAL;
7976                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
7977         }
7978
7979         /* deassert preemption condition */
7980         amdgpu_ring_set_preempt_cond_exec(ring, true);
7981         return r;
7982 }
7983
7984 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
7985 {
7986         struct amdgpu_device *adev = ring->adev;
7987         struct v10_ce_ib_state ce_payload = {0};
7988         uint64_t csa_addr;
7989         int cnt;
7990
7991         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
7992         csa_addr = amdgpu_csa_vaddr(ring->adev);
7993
7994         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7995         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7996                                  WRITE_DATA_DST_SEL(8) |
7997                                  WR_CONFIRM) |
7998                                  WRITE_DATA_CACHE_POLICY(0));
7999         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8000                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8001         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8002                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8003
8004         if (resume)
8005                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8006                                            offsetof(struct v10_gfx_meta_data,
8007                                                     ce_payload),
8008                                            sizeof(ce_payload) >> 2);
8009         else
8010                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8011                                            sizeof(ce_payload) >> 2);
8012 }
8013
8014 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8015 {
8016         struct amdgpu_device *adev = ring->adev;
8017         struct v10_de_ib_state de_payload = {0};
8018         uint64_t csa_addr, gds_addr;
8019         int cnt;
8020
8021         csa_addr = amdgpu_csa_vaddr(ring->adev);
8022         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8023                          PAGE_SIZE);
8024         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8025         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8026
8027         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8028         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8029         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8030                                  WRITE_DATA_DST_SEL(8) |
8031                                  WR_CONFIRM) |
8032                                  WRITE_DATA_CACHE_POLICY(0));
8033         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8034                               offsetof(struct v10_gfx_meta_data, de_payload)));
8035         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8036                               offsetof(struct v10_gfx_meta_data, de_payload)));
8037
8038         if (resume)
8039                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8040                                            offsetof(struct v10_gfx_meta_data,
8041                                                     de_payload),
8042                                            sizeof(de_payload) >> 2);
8043         else
8044                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8045                                            sizeof(de_payload) >> 2);
8046 }
8047
8048 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8049                                     bool secure)
8050 {
8051         uint32_t v = secure ? FRAME_TMZ : 0;
8052
8053         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8054         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8055 }
8056
8057 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8058                                      uint32_t reg_val_offs)
8059 {
8060         struct amdgpu_device *adev = ring->adev;
8061
8062         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8063         amdgpu_ring_write(ring, 0 |     /* src: register*/
8064                                 (5 << 8) |      /* dst: memory */
8065                                 (1 << 20));     /* write confirm */
8066         amdgpu_ring_write(ring, reg);
8067         amdgpu_ring_write(ring, 0);
8068         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8069                                 reg_val_offs * 4));
8070         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8071                                 reg_val_offs * 4));
8072 }
8073
8074 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8075                                    uint32_t val)
8076 {
8077         uint32_t cmd = 0;
8078
8079         switch (ring->funcs->type) {
8080         case AMDGPU_RING_TYPE_GFX:
8081                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8082                 break;
8083         case AMDGPU_RING_TYPE_KIQ:
8084                 cmd = (1 << 16); /* no inc addr */
8085                 break;
8086         default:
8087                 cmd = WR_CONFIRM;
8088                 break;
8089         }
8090         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8091         amdgpu_ring_write(ring, cmd);
8092         amdgpu_ring_write(ring, reg);
8093         amdgpu_ring_write(ring, 0);
8094         amdgpu_ring_write(ring, val);
8095 }
8096
8097 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8098                                         uint32_t val, uint32_t mask)
8099 {
8100         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8101 }
8102
8103 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8104                                                    uint32_t reg0, uint32_t reg1,
8105                                                    uint32_t ref, uint32_t mask)
8106 {
8107         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8108         struct amdgpu_device *adev = ring->adev;
8109         bool fw_version_ok = false;
8110
8111         fw_version_ok = adev->gfx.cp_fw_write_wait;
8112
8113         if (fw_version_ok)
8114                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8115                                        ref, mask, 0x20);
8116         else
8117                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8118                                                            ref, mask);
8119 }
8120
8121 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8122                                          unsigned vmid)
8123 {
8124         struct amdgpu_device *adev = ring->adev;
8125         uint32_t value = 0;
8126
8127         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8128         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8129         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8130         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8131         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8132 }
8133
8134 static void
8135 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8136                                       uint32_t me, uint32_t pipe,
8137                                       enum amdgpu_interrupt_state state)
8138 {
8139         uint32_t cp_int_cntl, cp_int_cntl_reg;
8140
8141         if (!me) {
8142                 switch (pipe) {
8143                 case 0:
8144                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8145                         break;
8146                 case 1:
8147                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8148                         break;
8149                 default:
8150                         DRM_DEBUG("invalid pipe %d\n", pipe);
8151                         return;
8152                 }
8153         } else {
8154                 DRM_DEBUG("invalid me %d\n", me);
8155                 return;
8156         }
8157
8158         switch (state) {
8159         case AMDGPU_IRQ_STATE_DISABLE:
8160                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8161                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8162                                             TIME_STAMP_INT_ENABLE, 0);
8163                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8164                 break;
8165         case AMDGPU_IRQ_STATE_ENABLE:
8166                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8167                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8168                                             TIME_STAMP_INT_ENABLE, 1);
8169                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8170                 break;
8171         default:
8172                 break;
8173         }
8174 }
8175
8176 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8177                                                      int me, int pipe,
8178                                                      enum amdgpu_interrupt_state state)
8179 {
8180         u32 mec_int_cntl, mec_int_cntl_reg;
8181
8182         /*
8183          * amdgpu controls only the first MEC. That's why this function only
8184          * handles the setting of interrupts for this specific MEC. All other
8185          * pipes' interrupts are set by amdkfd.
8186          */
8187
8188         if (me == 1) {
8189                 switch (pipe) {
8190                 case 0:
8191                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8192                         break;
8193                 case 1:
8194                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8195                         break;
8196                 case 2:
8197                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8198                         break;
8199                 case 3:
8200                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8201                         break;
8202                 default:
8203                         DRM_DEBUG("invalid pipe %d\n", pipe);
8204                         return;
8205                 }
8206         } else {
8207                 DRM_DEBUG("invalid me %d\n", me);
8208                 return;
8209         }
8210
8211         switch (state) {
8212         case AMDGPU_IRQ_STATE_DISABLE:
8213                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8214                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8215                                              TIME_STAMP_INT_ENABLE, 0);
8216                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8217                 break;
8218         case AMDGPU_IRQ_STATE_ENABLE:
8219                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8220                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8221                                              TIME_STAMP_INT_ENABLE, 1);
8222                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8223                 break;
8224         default:
8225                 break;
8226         }
8227 }
8228
8229 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8230                                             struct amdgpu_irq_src *src,
8231                                             unsigned type,
8232                                             enum amdgpu_interrupt_state state)
8233 {
8234         switch (type) {
8235         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8236                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8237                 break;
8238         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8239                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8240                 break;
8241         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8242                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8243                 break;
8244         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8245                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8246                 break;
8247         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8248                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8249                 break;
8250         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8251                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8252                 break;
8253         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8254                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8255                 break;
8256         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8257                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8258                 break;
8259         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8260                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8261                 break;
8262         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8263                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8264                 break;
8265         default:
8266                 break;
8267         }
8268         return 0;
8269 }
8270
8271 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8272                              struct amdgpu_irq_src *source,
8273                              struct amdgpu_iv_entry *entry)
8274 {
8275         int i;
8276         u8 me_id, pipe_id, queue_id;
8277         struct amdgpu_ring *ring;
8278
8279         DRM_DEBUG("IH: CP EOP\n");
8280         me_id = (entry->ring_id & 0x0c) >> 2;
8281         pipe_id = (entry->ring_id & 0x03) >> 0;
8282         queue_id = (entry->ring_id & 0x70) >> 4;
8283
8284         switch (me_id) {
8285         case 0:
8286                 if (pipe_id == 0)
8287                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8288                 else
8289                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8290                 break;
8291         case 1:
8292         case 2:
8293                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8294                         ring = &adev->gfx.compute_ring[i];
8295                         /* Per-queue interrupt is supported for MEC starting from VI.
8296                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8297                           */
8298                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8299                                 amdgpu_fence_process(ring);
8300                 }
8301                 break;
8302         }
8303         return 0;
8304 }
8305
8306 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8307                                               struct amdgpu_irq_src *source,
8308                                               unsigned type,
8309                                               enum amdgpu_interrupt_state state)
8310 {
8311         switch (state) {
8312         case AMDGPU_IRQ_STATE_DISABLE:
8313         case AMDGPU_IRQ_STATE_ENABLE:
8314                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8315                                PRIV_REG_INT_ENABLE,
8316                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8317                 break;
8318         default:
8319                 break;
8320         }
8321
8322         return 0;
8323 }
8324
8325 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8326                                                struct amdgpu_irq_src *source,
8327                                                unsigned type,
8328                                                enum amdgpu_interrupt_state state)
8329 {
8330         switch (state) {
8331         case AMDGPU_IRQ_STATE_DISABLE:
8332         case AMDGPU_IRQ_STATE_ENABLE:
8333                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8334                                PRIV_INSTR_INT_ENABLE,
8335                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8336         default:
8337                 break;
8338         }
8339
8340         return 0;
8341 }
8342
8343 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8344                                         struct amdgpu_iv_entry *entry)
8345 {
8346         u8 me_id, pipe_id, queue_id;
8347         struct amdgpu_ring *ring;
8348         int i;
8349
8350         me_id = (entry->ring_id & 0x0c) >> 2;
8351         pipe_id = (entry->ring_id & 0x03) >> 0;
8352         queue_id = (entry->ring_id & 0x70) >> 4;
8353
8354         switch (me_id) {
8355         case 0:
8356                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8357                         ring = &adev->gfx.gfx_ring[i];
8358                         /* we only enabled 1 gfx queue per pipe for now */
8359                         if (ring->me == me_id && ring->pipe == pipe_id)
8360                                 drm_sched_fault(&ring->sched);
8361                 }
8362                 break;
8363         case 1:
8364         case 2:
8365                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8366                         ring = &adev->gfx.compute_ring[i];
8367                         if (ring->me == me_id && ring->pipe == pipe_id &&
8368                             ring->queue == queue_id)
8369                                 drm_sched_fault(&ring->sched);
8370                 }
8371                 break;
8372         default:
8373                 BUG();
8374         }
8375 }
8376
8377 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8378                                   struct amdgpu_irq_src *source,
8379                                   struct amdgpu_iv_entry *entry)
8380 {
8381         DRM_ERROR("Illegal register access in command stream\n");
8382         gfx_v10_0_handle_priv_fault(adev, entry);
8383         return 0;
8384 }
8385
8386 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8387                                    struct amdgpu_irq_src *source,
8388                                    struct amdgpu_iv_entry *entry)
8389 {
8390         DRM_ERROR("Illegal instruction in command stream\n");
8391         gfx_v10_0_handle_priv_fault(adev, entry);
8392         return 0;
8393 }
8394
8395 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8396                                              struct amdgpu_irq_src *src,
8397                                              unsigned int type,
8398                                              enum amdgpu_interrupt_state state)
8399 {
8400         uint32_t tmp, target;
8401         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8402
8403         if (ring->me == 1)
8404                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8405         else
8406                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8407         target += ring->pipe;
8408
8409         switch (type) {
8410         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8411                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8412                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8413                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8414                                             GENERIC2_INT_ENABLE, 0);
8415                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8416
8417                         tmp = RREG32(target);
8418                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8419                                             GENERIC2_INT_ENABLE, 0);
8420                         WREG32(target, tmp);
8421                 } else {
8422                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8423                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8424                                             GENERIC2_INT_ENABLE, 1);
8425                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8426
8427                         tmp = RREG32(target);
8428                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8429                                             GENERIC2_INT_ENABLE, 1);
8430                         WREG32(target, tmp);
8431                 }
8432                 break;
8433         default:
8434                 BUG(); /* kiq only support GENERIC2_INT now */
8435                 break;
8436         }
8437         return 0;
8438 }
8439
8440 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8441                              struct amdgpu_irq_src *source,
8442                              struct amdgpu_iv_entry *entry)
8443 {
8444         u8 me_id, pipe_id, queue_id;
8445         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8446
8447         me_id = (entry->ring_id & 0x0c) >> 2;
8448         pipe_id = (entry->ring_id & 0x03) >> 0;
8449         queue_id = (entry->ring_id & 0x70) >> 4;
8450         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8451                    me_id, pipe_id, queue_id);
8452
8453         amdgpu_fence_process(ring);
8454         return 0;
8455 }
8456
8457 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8458 {
8459         const unsigned int gcr_cntl =
8460                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8461                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8462                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8463                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8464                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8465                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8466                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8467                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8468
8469         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8470         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8471         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8472         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8473         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8474         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8475         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8476         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8477         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8478 }
8479
8480 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8481         .name = "gfx_v10_0",
8482         .early_init = gfx_v10_0_early_init,
8483         .late_init = gfx_v10_0_late_init,
8484         .sw_init = gfx_v10_0_sw_init,
8485         .sw_fini = gfx_v10_0_sw_fini,
8486         .hw_init = gfx_v10_0_hw_init,
8487         .hw_fini = gfx_v10_0_hw_fini,
8488         .suspend = gfx_v10_0_suspend,
8489         .resume = gfx_v10_0_resume,
8490         .is_idle = gfx_v10_0_is_idle,
8491         .wait_for_idle = gfx_v10_0_wait_for_idle,
8492         .soft_reset = gfx_v10_0_soft_reset,
8493         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8494         .set_powergating_state = gfx_v10_0_set_powergating_state,
8495         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8496 };
8497
8498 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8499         .type = AMDGPU_RING_TYPE_GFX,
8500         .align_mask = 0xff,
8501         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8502         .support_64bit_ptrs = true,
8503         .vmhub = AMDGPU_GFXHUB_0,
8504         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8505         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8506         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8507         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8508                 5 + /* COND_EXEC */
8509                 7 + /* PIPELINE_SYNC */
8510                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8511                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8512                 2 + /* VM_FLUSH */
8513                 8 + /* FENCE for VM_FLUSH */
8514                 20 + /* GDS switch */
8515                 4 + /* double SWITCH_BUFFER,
8516                      * the first COND_EXEC jump to the place
8517                      * just prior to this double SWITCH_BUFFER
8518                      */
8519                 5 + /* COND_EXEC */
8520                 7 + /* HDP_flush */
8521                 4 + /* VGT_flush */
8522                 14 + /* CE_META */
8523                 31 + /* DE_META */
8524                 3 + /* CNTX_CTRL */
8525                 5 + /* HDP_INVL */
8526                 8 + 8 + /* FENCE x2 */
8527                 2 + /* SWITCH_BUFFER */
8528                 8, /* gfx_v10_0_emit_mem_sync */
8529         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8530         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8531         .emit_fence = gfx_v10_0_ring_emit_fence,
8532         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8533         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8534         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8535         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8536         .test_ring = gfx_v10_0_ring_test_ring,
8537         .test_ib = gfx_v10_0_ring_test_ib,
8538         .insert_nop = amdgpu_ring_insert_nop,
8539         .pad_ib = amdgpu_ring_generic_pad_ib,
8540         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8541         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8542         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8543         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8544         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8545         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8546         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8547         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8548         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8549         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8550         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8551 };
8552
8553 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8554         .type = AMDGPU_RING_TYPE_COMPUTE,
8555         .align_mask = 0xff,
8556         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8557         .support_64bit_ptrs = true,
8558         .vmhub = AMDGPU_GFXHUB_0,
8559         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8560         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8561         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8562         .emit_frame_size =
8563                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8564                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8565                 5 + /* hdp invalidate */
8566                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8567                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8568                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8569                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8570                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8571                 8, /* gfx_v10_0_emit_mem_sync */
8572         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8573         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8574         .emit_fence = gfx_v10_0_ring_emit_fence,
8575         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8576         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8577         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8578         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8579         .test_ring = gfx_v10_0_ring_test_ring,
8580         .test_ib = gfx_v10_0_ring_test_ib,
8581         .insert_nop = amdgpu_ring_insert_nop,
8582         .pad_ib = amdgpu_ring_generic_pad_ib,
8583         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8584         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8585         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8586         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8587 };
8588
8589 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8590         .type = AMDGPU_RING_TYPE_KIQ,
8591         .align_mask = 0xff,
8592         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8593         .support_64bit_ptrs = true,
8594         .vmhub = AMDGPU_GFXHUB_0,
8595         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8596         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8597         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8598         .emit_frame_size =
8599                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8600                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8601                 5 + /*hdp invalidate */
8602                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8603                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8604                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8605                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8606                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8607         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8608         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8609         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8610         .test_ring = gfx_v10_0_ring_test_ring,
8611         .test_ib = gfx_v10_0_ring_test_ib,
8612         .insert_nop = amdgpu_ring_insert_nop,
8613         .pad_ib = amdgpu_ring_generic_pad_ib,
8614         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8615         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8616         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8617         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8618 };
8619
8620 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8621 {
8622         int i;
8623
8624         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8625
8626         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8627                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8628
8629         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8630                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8631 }
8632
8633 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8634         .set = gfx_v10_0_set_eop_interrupt_state,
8635         .process = gfx_v10_0_eop_irq,
8636 };
8637
8638 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8639         .set = gfx_v10_0_set_priv_reg_fault_state,
8640         .process = gfx_v10_0_priv_reg_irq,
8641 };
8642
8643 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8644         .set = gfx_v10_0_set_priv_inst_fault_state,
8645         .process = gfx_v10_0_priv_inst_irq,
8646 };
8647
8648 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8649         .set = gfx_v10_0_kiq_set_interrupt_state,
8650         .process = gfx_v10_0_kiq_irq,
8651 };
8652
8653 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8654 {
8655         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8656         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8657
8658         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8659         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8660
8661         adev->gfx.priv_reg_irq.num_types = 1;
8662         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8663
8664         adev->gfx.priv_inst_irq.num_types = 1;
8665         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8666 }
8667
8668 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8669 {
8670         switch (adev->asic_type) {
8671         case CHIP_NAVI10:
8672         case CHIP_NAVI14:
8673         case CHIP_SIENNA_CICHLID:
8674         case CHIP_NAVY_FLOUNDER:
8675                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8676                 break;
8677         case CHIP_NAVI12:
8678                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8679                 break;
8680         default:
8681                 break;
8682         }
8683 }
8684
8685 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8686 {
8687         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8688                             adev->gfx.config.max_sh_per_se *
8689                             adev->gfx.config.max_shader_engines;
8690
8691         adev->gds.gds_size = 0x10000;
8692         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8693         adev->gds.gws_size = 64;
8694         adev->gds.oa_size = 16;
8695 }
8696
8697 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8698                                                           u32 bitmap)
8699 {
8700         u32 data;
8701
8702         if (!bitmap)
8703                 return;
8704
8705         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8706         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8707
8708         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8709 }
8710
8711 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8712 {
8713         u32 data, wgp_bitmask;
8714         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8715         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8716
8717         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8718         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8719
8720         wgp_bitmask =
8721                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8722
8723         return (~data) & wgp_bitmask;
8724 }
8725
8726 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8727 {
8728         u32 wgp_idx, wgp_active_bitmap;
8729         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8730
8731         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8732         cu_active_bitmap = 0;
8733
8734         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8735                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8736                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8737                 if (wgp_active_bitmap & (1 << wgp_idx))
8738                         cu_active_bitmap |= cu_bitmap_per_wgp;
8739         }
8740
8741         return cu_active_bitmap;
8742 }
8743
8744 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8745                                  struct amdgpu_cu_info *cu_info)
8746 {
8747         int i, j, k, counter, active_cu_number = 0;
8748         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8749         unsigned disable_masks[4 * 2];
8750
8751         if (!adev || !cu_info)
8752                 return -EINVAL;
8753
8754         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8755
8756         mutex_lock(&adev->grbm_idx_mutex);
8757         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8758                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8759                         mask = 1;
8760                         ao_bitmap = 0;
8761                         counter = 0;
8762                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8763                         if (i < 4 && j < 2)
8764                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8765                                         adev, disable_masks[i * 2 + j]);
8766                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8767                         cu_info->bitmap[i][j] = bitmap;
8768
8769                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8770                                 if (bitmap & mask) {
8771                                         if (counter < adev->gfx.config.max_cu_per_sh)
8772                                                 ao_bitmap |= mask;
8773                                         counter++;
8774                                 }
8775                                 mask <<= 1;
8776                         }
8777                         active_cu_number += counter;
8778                         if (i < 2 && j < 2)
8779                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8780                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8781                 }
8782         }
8783         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8784         mutex_unlock(&adev->grbm_idx_mutex);
8785
8786         cu_info->number = active_cu_number;
8787         cu_info->ao_cu_mask = ao_cu_mask;
8788         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8789
8790         return 0;
8791 }
8792
8793 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8794 {
8795         .type = AMD_IP_BLOCK_TYPE_GFX,
8796         .major = 10,
8797         .minor = 0,
8798         .rev = 0,
8799         .funcs = &gfx_v10_0_ip_funcs,
8800 };