drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *    Daniel Vetter <[email protected]>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_TRANSCODER_DSI_A:
  93                 return "TRANSCODER_DSI_A";
  94         case POWER_DOMAIN_TRANSCODER_DSI_C:
  95                 return "TRANSCODER_DSI_C";
  96         case POWER_DOMAIN_PORT_DDI_A_LANES:
  97                 return "PORT_DDI_A_LANES";
  98         case POWER_DOMAIN_PORT_DDI_B_LANES:
  99                 return "PORT_DDI_B_LANES";
 100         case POWER_DOMAIN_PORT_DDI_C_LANES:
 101                 return "PORT_DDI_C_LANES";
 102         case POWER_DOMAIN_PORT_DDI_D_LANES:
 103                 return "PORT_DDI_D_LANES";
 104         case POWER_DOMAIN_PORT_DDI_E_LANES:
 105                 return "PORT_DDI_E_LANES";
 106         case POWER_DOMAIN_PORT_DSI:
 107                 return "PORT_DSI";
 108         case POWER_DOMAIN_PORT_CRT:
 109                 return "PORT_CRT";
 110         case POWER_DOMAIN_PORT_OTHER:
 111                 return "PORT_OTHER";
 112         case POWER_DOMAIN_VGA:
 113                 return "VGA";
 114         case POWER_DOMAIN_AUDIO:
 115                 return "AUDIO";
 116         case POWER_DOMAIN_PLLS:
 117                 return "PLLS";
 118         case POWER_DOMAIN_AUX_A:
 119                 return "AUX_A";
 120         case POWER_DOMAIN_AUX_B:
 121                 return "AUX_B";
 122         case POWER_DOMAIN_AUX_C:
 123                 return "AUX_C";
 124         case POWER_DOMAIN_AUX_D:
 125                 return "AUX_D";
 126         case POWER_DOMAIN_GMBUS:
 127                 return "GMBUS";
 128         case POWER_DOMAIN_INIT:
 129                 return "INIT";
 130         case POWER_DOMAIN_MODESET:
 131                 return "MODESET";
 132         default:
 133                 MISSING_CASE(domain);
 134                 return "?";
 135         }
 136 }
 137
 138 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 139                                     struct i915_power_well *power_well)
 140 {
 141         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 142         power_well->ops->enable(dev_priv, power_well);
 143         power_well->hw_enabled = true;
 144 }
 145
 146 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 147                                      struct i915_power_well *power_well)
 148 {
 149         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 150         power_well->hw_enabled = false;
 151         power_well->ops->disable(dev_priv, power_well);
 152 }
 153
 154 /*
 155  * We should only use the power well if we explicitly asked the hardware to
 156  * enable it, so check if it's enabled and also check if we've requested it to
 157  * be enabled.
 158  */
 159 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 160                                    struct i915_power_well *power_well)
 161 {
 162         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 163                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 164 }
 165
 166 /**
 167  * __intel_display_power_is_enabled - unlocked check for a power domain
 168  * @dev_priv: i915 device instance
 169  * @domain: power domain to check
 170  *
 171  * This is the unlocked version of intel_display_power_is_enabled() and should
 172  * only be used from error capture and recovery code where deadlocks are
 173  * possible.
 174  *
 175  * Returns:
 176  * True when the power domain is enabled, false otherwise.
 177  */
 178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 179                                       enum intel_display_power_domain domain)
 180 {
 181         struct i915_power_domains *power_domains;
 182         struct i915_power_well *power_well;
 183         bool is_enabled;
 184         int i;
 185
 186         if (dev_priv->pm.suspended)
 187                 return false;
 188
 189         power_domains = &dev_priv->power_domains;
 190
 191         is_enabled = true;
 192
 193         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 194                 if (power_well->always_on)
 195                         continue;
 196
 197                 if (!power_well->hw_enabled) {
 198                         is_enabled = false;
 199                         break;
 200                 }
 201         }
 202
 203         return is_enabled;
 204 }
 205
 206 /**
 207  * intel_display_power_is_enabled - check for a power domain
 208  * @dev_priv: i915 device instance
 209  * @domain: power domain to check
 210  *
 211  * This function can be used to check the hw power domain state. It is mostly
 212  * used in hardware state readout functions. Everywhere else code should rely
 213  * upon explicit power domain reference counting to ensure that the hardware
 214  * block is powered up before accessing it.
 215  *
 216  * Callers must hold the relevant modesetting locks to ensure that concurrent
 217  * threads can't disable the power well while the caller tries to read a few
 218  * registers.
 219  *
 220  * Returns:
 221  * True when the power domain is enabled, false otherwise.
 222  */
 223 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 224                                     enum intel_display_power_domain domain)
 225 {
 226         struct i915_power_domains *power_domains;
 227         bool ret;
 228
 229         power_domains = &dev_priv->power_domains;
 230
 231         mutex_lock(&power_domains->lock);
 232         ret = __intel_display_power_is_enabled(dev_priv, domain);
 233         mutex_unlock(&power_domains->lock);
 234
 235         return ret;
 236 }
 237
 238 /**
 239  * intel_display_set_init_power - set the initial power domain state
 240  * @dev_priv: i915 device instance
 241  * @enable: whether to enable or disable the initial power domain state
 242  *
 243  * For simplicity our driver load/unload and system suspend/resume code assumes
 244  * that all power domains are always enabled. This functions controls the state
 245  * of this little hack. While the initial power domain state is enabled runtime
 246  * pm is effectively disabled.
 247  */
 248 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 249                                   bool enable)
 250 {
 251         if (dev_priv->power_domains.init_power_on == enable)
 252                 return;
 253
 254         if (enable)
 255                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 256         else
 257                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 258
 259         dev_priv->power_domains.init_power_on = enable;
 260 }
 261
 262 /*
 263  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 264  * when not needed anymore. We have 4 registers that can request the power well
 265  * to be enabled, and it will only be disabled if none of the registers is
 266  * requesting it to be enabled.
 267  */
 268 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 269 {
 270         struct drm_device *dev = dev_priv->dev;
 271
 272         /*
 273          * After we re-enable the power well, if we touch VGA register 0x3d5
 274          * we'll get unclaimed register interrupts. This stops after we write
 275          * anything to the VGA MSR register. The vgacon module uses this
 276          * register all the time, so if we unbind our driver and, as a
 277          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 278          * console_unlock(). So make here we touch the VGA MSR register, making
 279          * sure vgacon can keep working normally without triggering interrupts
 280          * and error messages.
 281          */
 282         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 283         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 284         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 285
 286         if (IS_BROADWELL(dev))
 287                 gen8_irq_power_well_post_enable(dev_priv,
 288                                                 1 << PIPE_C | 1 << PIPE_B);
 289 }
 290
 291 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 292 {
 293         if (IS_BROADWELL(dev_priv))
 294                 gen8_irq_power_well_pre_disable(dev_priv,
 295                                                 1 << PIPE_C | 1 << PIPE_B);
 296 }
 297
 298 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 299                                        struct i915_power_well *power_well)
 300 {
 301         struct drm_device *dev = dev_priv->dev;
 302
 303         /*
 304          * After we re-enable the power well, if we touch VGA register 0x3d5
 305          * we'll get unclaimed register interrupts. This stops after we write
 306          * anything to the VGA MSR register. The vgacon module uses this
 307          * register all the time, so if we unbind our driver and, as a
 308          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 309          * console_unlock(). So make here we touch the VGA MSR register, making
 310          * sure vgacon can keep working normally without triggering interrupts
 311          * and error messages.
 312          */
 313         if (power_well->data == SKL_DISP_PW_2) {
 314                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 315                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 316                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 317
 318                 gen8_irq_power_well_post_enable(dev_priv,
 319                                                 1 << PIPE_C | 1 << PIPE_B);
 320         }
 321 }
 322
 323 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 324                                        struct i915_power_well *power_well)
 325 {
 326         if (power_well->data == SKL_DISP_PW_2)
 327                 gen8_irq_power_well_pre_disable(dev_priv,
 328                                                 1 << PIPE_C | 1 << PIPE_B);
 329 }
 330
 331 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 332                                struct i915_power_well *power_well, bool enable)
 333 {
 334         bool is_enabled, enable_requested;
 335         uint32_t tmp;
 336
 337         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 338         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 339         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 340
 341         if (enable) {
 342                 if (!enable_requested)
 343                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 344                                    HSW_PWR_WELL_ENABLE_REQUEST);
 345
 346                 if (!is_enabled) {
 347                         DRM_DEBUG_KMS("Enabling power well\n");
 348                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 349                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 350                                 DRM_ERROR("Timeout enabling power well\n");
 351                         hsw_power_well_post_enable(dev_priv);
 352                 }
 353
 354         } else {
 355                 if (enable_requested) {
 356                         hsw_power_well_pre_disable(dev_priv);
 357                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 358                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 359                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 360                 }
 361         }
 362 }
 363
 364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 365         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 366         BIT(POWER_DOMAIN_PIPE_B) |                      \
 367         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 368         BIT(POWER_DOMAIN_PIPE_C) |                      \
 369         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 370         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 371         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 372         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 373         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 374         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 375         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 376         BIT(POWER_DOMAIN_AUX_B) |                       \
 377         BIT(POWER_DOMAIN_AUX_C) |                       \
 378         BIT(POWER_DOMAIN_AUX_D) |                       \
 379         BIT(POWER_DOMAIN_AUDIO) |                       \
 380         BIT(POWER_DOMAIN_VGA) |                         \
 381         BIT(POWER_DOMAIN_INIT))
 382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 383         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 384         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 385         BIT(POWER_DOMAIN_INIT))
 386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 387         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 388         BIT(POWER_DOMAIN_INIT))
 389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 390         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 391         BIT(POWER_DOMAIN_INIT))
 392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 393         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 394         BIT(POWER_DOMAIN_INIT))
 395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 396         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 397         BIT(POWER_DOMAIN_MODESET) |                     \
 398         BIT(POWER_DOMAIN_AUX_A) |                       \
 399         BIT(POWER_DOMAIN_INIT))
 400
 401 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 402         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 403         BIT(POWER_DOMAIN_PIPE_B) |                      \
 404         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 405         BIT(POWER_DOMAIN_PIPE_C) |                      \
 406         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 407         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 408         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 409         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 410         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 411         BIT(POWER_DOMAIN_AUX_B) |                       \
 412         BIT(POWER_DOMAIN_AUX_C) |                       \
 413         BIT(POWER_DOMAIN_AUDIO) |                       \
 414         BIT(POWER_DOMAIN_VGA) |                         \
 415         BIT(POWER_DOMAIN_GMBUS) |                       \
 416         BIT(POWER_DOMAIN_INIT))
 417 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 418         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 419         BIT(POWER_DOMAIN_MODESET) |                     \
 420         BIT(POWER_DOMAIN_AUX_A) |                       \
 421         BIT(POWER_DOMAIN_INIT))
 422
 423 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 424 {
 425         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 426                   "DC9 already programmed to be enabled.\n");
 427         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 428                   "DC5 still not disabled to enable DC9.\n");
 429         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 430         WARN_ONCE(intel_irqs_enabled(dev_priv),
 431                   "Interrupts not disabled yet.\n");
 432
 433          /*
 434           * TODO: check for the following to verify the conditions to enter DC9
 435           * state are satisfied:
 436           * 1] Check relevant display engine registers to verify if mode set
 437           * disable sequence was followed.
 438           * 2] Check if display uninitialize sequence is initialized.
 439           */
 440 }
 441
 442 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 443 {
 444         WARN_ONCE(intel_irqs_enabled(dev_priv),
 445                   "Interrupts not disabled yet.\n");
 446         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 447                   "DC5 still not disabled.\n");
 448
 449          /*
 450           * TODO: check for the following to verify DC9 state was indeed
 451           * entered before programming to disable it:
 452           * 1] Check relevant display engine registers to verify if mode
 453           *  set disable sequence was followed.
 454           * 2] Check if display uninitialize sequence is initialized.
 455           */
 456 }
 457
 458 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 459                                 u32 state)
 460 {
 461         int rewrites = 0;
 462         int rereads = 0;
 463         u32 v;
 464
 465         I915_WRITE(DC_STATE_EN, state);
 466
 467         /* It has been observed that disabling the dc6 state sometimes
 468          * doesn't stick and dmc keeps returning old value. Make sure
 469          * the write really sticks enough times and also force rewrite until
 470          * we are confident that state is exactly what we want.
 471          */
 472         do  {
 473                 v = I915_READ(DC_STATE_EN);
 474
 475                 if (v != state) {
 476                         I915_WRITE(DC_STATE_EN, state);
 477                         rewrites++;
 478                         rereads = 0;
 479                 } else if (rereads++ > 5) {
 480                         break;
 481                 }
 482
 483         } while (rewrites < 100);
 484
 485         if (v != state)
 486                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 487                           state, v);
 488
 489         /* Most of the times we need one retry, avoid spam */
 490         if (rewrites > 1)
 491                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 492                               state, rewrites);
 493 }
 494
 495 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 496 {
 497         uint32_t val;
 498         uint32_t mask;
 499
 500         mask = DC_STATE_EN_UPTO_DC5;
 501         if (IS_BROXTON(dev_priv))
 502                 mask |= DC_STATE_EN_DC9;
 503         else
 504                 mask |= DC_STATE_EN_UPTO_DC6;
 505
 506         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 507                 state &= dev_priv->csr.allowed_dc_mask;
 508
 509         val = I915_READ(DC_STATE_EN);
 510         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 511                       val & mask, state);
 512
 513         /* Check if DMC is ignoring our DC state requests */
 514         if ((val & mask) != dev_priv->csr.dc_state)
 515                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 516                           dev_priv->csr.dc_state, val & mask);
 517
 518         val &= ~mask;
 519         val |= state;
 520
 521         gen9_write_dc_state(dev_priv, val);
 522
 523         dev_priv->csr.dc_state = val & mask;
 524 }
 525
 526 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 527 {
 528         assert_can_enable_dc9(dev_priv);
 529
 530         DRM_DEBUG_KMS("Enabling DC9\n");
 531
 532         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 533 }
 534
 535 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 536 {
 537         assert_can_disable_dc9(dev_priv);
 538
 539         DRM_DEBUG_KMS("Disabling DC9\n");
 540
 541         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 542 }
 543
 544 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 545 {
 546         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 547                   "CSR program storage start is NULL\n");
 548         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 549         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 550 }
 551
 552 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 553 {
 554         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 555                                         SKL_DISP_PW_2);
 556
 557         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 558
 559         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 560                   "DC5 already programmed to be enabled.\n");
 561         assert_rpm_wakelock_held(dev_priv);
 562
 563         assert_csr_loaded(dev_priv);
 564 }
 565
 566 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 567 {
 568         assert_can_enable_dc5(dev_priv);
 569
 570         DRM_DEBUG_KMS("Enabling DC5\n");
 571
 572         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 573 }
 574
 575 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 576 {
 577         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 578                   "Backlight is not disabled.\n");
 579         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 580                   "DC6 already programmed to be enabled.\n");
 581
 582         assert_csr_loaded(dev_priv);
 583 }
 584
 585 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 586 {
 587         assert_can_enable_dc6(dev_priv);
 588
 589         DRM_DEBUG_KMS("Enabling DC6\n");
 590
 591         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 592
 593 }
 594
 595 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 596 {
 597         DRM_DEBUG_KMS("Disabling DC6\n");
 598
 599         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 600 }
 601
 602 static void
 603 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 604                                   struct i915_power_well *power_well)
 605 {
 606         enum skl_disp_power_wells power_well_id = power_well->data;
 607         u32 val;
 608         u32 mask;
 609
 610         mask = SKL_POWER_WELL_REQ(power_well_id);
 611
 612         val = I915_READ(HSW_PWR_WELL_KVMR);
 613         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 614                       power_well->name))
 615                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 616
 617         val = I915_READ(HSW_PWR_WELL_BIOS);
 618         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 619
 620         if (!(val & mask))
 621                 return;
 622
 623         /*
 624          * DMC is known to force on the request bits for power well 1 on SKL
 625          * and BXT and the misc IO power well on SKL but we don't expect any
 626          * other request bits to be set, so WARN for those.
 627          */
 628         if (power_well_id == SKL_DISP_PW_1 ||
 629             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 630              power_well_id == SKL_DISP_PW_MISC_IO))
 631                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 632                                  "by DMC\n", power_well->name);
 633         else
 634                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 635                           power_well->name);
 636
 637         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 638         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 639 }
 640
 641 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 642                         struct i915_power_well *power_well, bool enable)
 643 {
 644         uint32_t tmp, fuse_status;
 645         uint32_t req_mask, state_mask;
 646         bool is_enabled, enable_requested, check_fuse_status = false;
 647
 648         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 649         fuse_status = I915_READ(SKL_FUSE_STATUS);
 650
 651         switch (power_well->data) {
 652         case SKL_DISP_PW_1:
 653                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 654                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 655                         DRM_ERROR("PG0 not enabled\n");
 656                         return;
 657                 }
 658                 break;
 659         case SKL_DISP_PW_2:
 660                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 661                         DRM_ERROR("PG1 in disabled state\n");
 662                         return;
 663                 }
 664                 break;
 665         case SKL_DISP_PW_DDI_A_E:
 666         case SKL_DISP_PW_DDI_B:
 667         case SKL_DISP_PW_DDI_C:
 668         case SKL_DISP_PW_DDI_D:
 669         case SKL_DISP_PW_MISC_IO:
 670                 break;
 671         default:
 672                 WARN(1, "Unknown power well %lu\n", power_well->data);
 673                 return;
 674         }
 675
 676         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 677         enable_requested = tmp & req_mask;
 678         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 679         is_enabled = tmp & state_mask;
 680
 681         if (!enable && enable_requested)
 682                 skl_power_well_pre_disable(dev_priv, power_well);
 683
 684         if (enable) {
 685                 if (!enable_requested) {
 686                         WARN((tmp & state_mask) &&
 687                                 !I915_READ(HSW_PWR_WELL_BIOS),
 688                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 689                                 when request is to disable!\n");
 690                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 691                 }
 692
 693                 if (!is_enabled) {
 694                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 695                         check_fuse_status = true;
 696                 }
 697         } else {
 698                 if (enable_requested) {
 699                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 700                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 701                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 702                 }
 703
 704                 if (IS_GEN9(dev_priv))
 705                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 706         }
 707
 708         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 709                      1))
 710                 DRM_ERROR("%s %s timeout\n",
 711                           power_well->name, enable ? "enable" : "disable");
 712
 713         if (check_fuse_status) {
 714                 if (power_well->data == SKL_DISP_PW_1) {
 715                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 716                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 717                                 DRM_ERROR("PG1 distributing status timeout\n");
 718                 } else if (power_well->data == SKL_DISP_PW_2) {
 719                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 720                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 721                                 DRM_ERROR("PG2 distributing status timeout\n");
 722                 }
 723         }
 724
 725         if (enable && !is_enabled)
 726                 skl_power_well_post_enable(dev_priv, power_well);
 727 }
 728
 729 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 730                                    struct i915_power_well *power_well)
 731 {
 732         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 733
 734         /*
 735          * We're taking over the BIOS, so clear any requests made by it since
 736          * the driver is in charge now.
 737          */
 738         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 739                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 740 }
 741
 742 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 743                                   struct i915_power_well *power_well)
 744 {
 745         hsw_set_power_well(dev_priv, power_well, true);
 746 }
 747
 748 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 749                                    struct i915_power_well *power_well)
 750 {
 751         hsw_set_power_well(dev_priv, power_well, false);
 752 }
 753
 754 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 755                                         struct i915_power_well *power_well)
 756 {
 757         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 758                 SKL_POWER_WELL_STATE(power_well->data);
 759
 760         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 761 }
 762
 763 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 764                                 struct i915_power_well *power_well)
 765 {
 766         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 767
 768         /* Clear any request made by BIOS as driver is taking over */
 769         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 770 }
 771
 772 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 773                                 struct i915_power_well *power_well)
 774 {
 775         skl_set_power_well(dev_priv, power_well, true);
 776 }
 777
 778 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 779                                 struct i915_power_well *power_well)
 780 {
 781         skl_set_power_well(dev_priv, power_well, false);
 782 }
 783
 784 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 785                                            struct i915_power_well *power_well)
 786 {
 787         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 788 }
 789
 790 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 791                                           struct i915_power_well *power_well)
 792 {
 793         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 794
 795         if (IS_BROXTON(dev_priv)) {
 796                 broxton_cdclk_verify_state(dev_priv);
 797                 broxton_ddi_phy_verify_state(dev_priv);
 798         }
 799 }
 800
 801 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 802                                            struct i915_power_well *power_well)
 803 {
 804         if (!dev_priv->csr.dmc_payload)
 805                 return;
 806
 807         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 808                 skl_enable_dc6(dev_priv);
 809         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 810                 gen9_enable_dc5(dev_priv);
 811 }
 812
 813 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 814                                            struct i915_power_well *power_well)
 815 {
 816         if (power_well->count > 0)
 817                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 818         else
 819                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 820 }
 821
 822 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 823                                            struct i915_power_well *power_well)
 824 {
 825 }
 826
 827 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 828                                              struct i915_power_well *power_well)
 829 {
 830         return true;
 831 }
 832
 833 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 834                                struct i915_power_well *power_well, bool enable)
 835 {
 836         enum punit_power_well power_well_id = power_well->data;
 837         u32 mask;
 838         u32 state;
 839         u32 ctrl;
 840
 841         mask = PUNIT_PWRGT_MASK(power_well_id);
 842         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 843                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 844
 845         mutex_lock(&dev_priv->rps.hw_lock);
 846
 847 #define COND \
 848         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 849
 850         if (COND)
 851                 goto out;
 852
 853         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 854         ctrl &= ~mask;
 855         ctrl |= state;
 856         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 857
 858         if (wait_for(COND, 100))
 859                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 860                           state,
 861                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 862
 863 #undef COND
 864
 865 out:
 866         mutex_unlock(&dev_priv->rps.hw_lock);
 867 }
 868
 869 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 870                                    struct i915_power_well *power_well)
 871 {
 872         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 873 }
 874
 875 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 876                                   struct i915_power_well *power_well)
 877 {
 878         vlv_set_power_well(dev_priv, power_well, true);
 879 }
 880
 881 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 882                                    struct i915_power_well *power_well)
 883 {
 884         vlv_set_power_well(dev_priv, power_well, false);
 885 }
 886
 887 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 888                                    struct i915_power_well *power_well)
 889 {
 890         int power_well_id = power_well->data;
 891         bool enabled = false;
 892         u32 mask;
 893         u32 state;
 894         u32 ctrl;
 895
 896         mask = PUNIT_PWRGT_MASK(power_well_id);
 897         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 898
 899         mutex_lock(&dev_priv->rps.hw_lock);
 900
 901         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 902         /*
 903          * We only ever set the power-on and power-gate states, anything
 904          * else is unexpected.
 905          */
 906         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 907                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 908         if (state == ctrl)
 909                 enabled = true;
 910
 911         /*
 912          * A transient state at this point would mean some unexpected party
 913          * is poking at the power controls too.
 914          */
 915         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 916         WARN_ON(ctrl != state);
 917
 918         mutex_unlock(&dev_priv->rps.hw_lock);
 919
 920         return enabled;
 921 }
 922
 923 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 924 {
 925         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 926
 927         /*
 928          * Disable trickle feed and enable pnd deadline calculation
 929          */
 930         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 931         I915_WRITE(CBR1_VLV, 0);
 932 }
 933
 934 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 935 {
 936         enum pipe pipe;
 937
 938         /*
 939          * Enable the CRI clock source so we can get at the
 940          * display and the reference clock for VGA
 941          * hotplug / manual detection. Supposedly DSI also
 942          * needs the ref clock up and running.
 943          *
 944          * CHV DPLL B/C have some issues if VGA mode is enabled.
 945          */
 946         for_each_pipe(dev_priv->dev, pipe) {
 947                 u32 val = I915_READ(DPLL(pipe));
 948
 949                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 950                 if (pipe != PIPE_A)
 951                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 952
 953                 I915_WRITE(DPLL(pipe), val);
 954         }
 955
 956         vlv_init_display_clock_gating(dev_priv);
 957
 958         spin_lock_irq(&dev_priv->irq_lock);
 959         valleyview_enable_display_irqs(dev_priv);
 960         spin_unlock_irq(&dev_priv->irq_lock);
 961
 962         /*
 963          * During driver initialization/resume we can avoid restoring the
 964          * part of the HW/SW state that will be inited anyway explicitly.
 965          */
 966         if (dev_priv->power_domains.initializing)
 967                 return;
 968
 969         intel_hpd_init(dev_priv);
 970
 971         i915_redisable_vga_power_on(dev_priv->dev);
 972 }
 973
 974 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 975 {
 976         spin_lock_irq(&dev_priv->irq_lock);
 977         valleyview_disable_display_irqs(dev_priv);
 978         spin_unlock_irq(&dev_priv->irq_lock);
 979
 980         /* make sure we're done processing display irqs */
 981         synchronize_irq(dev_priv->dev->irq);
 982
 983         vlv_power_sequencer_reset(dev_priv);
 984 }
 985
 986 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 987                                           struct i915_power_well *power_well)
 988 {
 989         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 990
 991         vlv_set_power_well(dev_priv, power_well, true);
 992
 993         vlv_display_power_well_init(dev_priv);
 994 }
 995
 996 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 997                                            struct i915_power_well *power_well)
 998 {
 999         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1000
1001         vlv_display_power_well_deinit(dev_priv);
1002
1003         vlv_set_power_well(dev_priv, power_well, false);
1004 }
1005
1006 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1007                                            struct i915_power_well *power_well)
1008 {
1009         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1010
1011         /* since ref/cri clock was enabled */
1012         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1013
1014         vlv_set_power_well(dev_priv, power_well, true);
1015
1016         /*
1017          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1018          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1019          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1020          *   b. The other bits such as sfr settings / modesel may all
1021          *      be set to 0.
1022          *
1023          * This should only be done on init and resume from S3 with
1024          * both PLLs disabled, or we risk losing DPIO and PLL
1025          * synchronization.
1026          */
1027         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1028 }
1029
1030 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1031                                             struct i915_power_well *power_well)
1032 {
1033         enum pipe pipe;
1034
1035         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1036
1037         for_each_pipe(dev_priv, pipe)
1038                 assert_pll_disabled(dev_priv, pipe);
1039
1040         /* Assert common reset */
1041         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1042
1043         vlv_set_power_well(dev_priv, power_well, false);
1044 }
1045
1046 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1047
1048 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1049                                                  int power_well_id)
1050 {
1051         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1052         int i;
1053
1054         for (i = 0; i < power_domains->power_well_count; i++) {
1055                 struct i915_power_well *power_well;
1056
1057                 power_well = &power_domains->power_wells[i];
1058                 if (power_well->data == power_well_id)
1059                         return power_well;
1060         }
1061
1062         return NULL;
1063 }
1064
1065 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1066
1067 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1068 {
1069         struct i915_power_well *cmn_bc =
1070                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1071         struct i915_power_well *cmn_d =
1072                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1073         u32 phy_control = dev_priv->chv_phy_control;
1074         u32 phy_status = 0;
1075         u32 phy_status_mask = 0xffffffff;
1076         u32 tmp;
1077
1078         /*
1079          * The BIOS can leave the PHY is some weird state
1080          * where it doesn't fully power down some parts.
1081          * Disable the asserts until the PHY has been fully
1082          * reset (ie. the power well has been disabled at
1083          * least once).
1084          */
1085         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1086                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1087                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1088                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1089                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1090                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1091                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1092
1093         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1094                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1095                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1096                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1097
1098         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1099                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1100
1101                 /* this assumes override is only used to enable lanes */
1102                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1103                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1104
1105                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1106                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1107
1108                 /* CL1 is on whenever anything is on in either channel */
1109                 if (BITS_SET(phy_control,
1110                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1111                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1112                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1113
1114                 /*
1115                  * The DPLLB check accounts for the pipe B + port A usage
1116                  * with CL2 powered up but all the lanes in the second channel
1117                  * powered down.
1118                  */
1119                 if (BITS_SET(phy_control,
1120                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1121                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1122                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1123
1124                 if (BITS_SET(phy_control,
1125                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1126                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1127                 if (BITS_SET(phy_control,
1128                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1129                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1130
1131                 if (BITS_SET(phy_control,
1132                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1133                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1134                 if (BITS_SET(phy_control,
1135                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1136                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1137         }
1138
1139         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1140                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1141
1142                 /* this assumes override is only used to enable lanes */
1143                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1144                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1145
1146                 if (BITS_SET(phy_control,
1147                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1148                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1149
1150                 if (BITS_SET(phy_control,
1151                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1152                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1153                 if (BITS_SET(phy_control,
1154                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1155                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1156         }
1157
1158         phy_status &= phy_status_mask;
1159
1160         /*
1161          * The PHY may be busy with some initial calibration and whatnot,
1162          * so the power state can take a while to actually change.
1163          */
1164         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1165                 WARN(phy_status != tmp,
1166                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1167                      tmp, phy_status, dev_priv->chv_phy_control);
1168 }
1169
1170 #undef BITS_SET
1171
1172 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1173                                            struct i915_power_well *power_well)
1174 {
1175         enum dpio_phy phy;
1176         enum pipe pipe;
1177         uint32_t tmp;
1178
1179         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1180                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1181
1182         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1183                 pipe = PIPE_A;
1184                 phy = DPIO_PHY0;
1185         } else {
1186                 pipe = PIPE_C;
1187                 phy = DPIO_PHY1;
1188         }
1189
1190         /* since ref/cri clock was enabled */
1191         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1192         vlv_set_power_well(dev_priv, power_well, true);
1193
1194         /* Poll for phypwrgood signal */
1195         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1196                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1197
1198         mutex_lock(&dev_priv->sb_lock);
1199
1200         /* Enable dynamic power down */
1201         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1202         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1203                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1204         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1205
1206         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1207                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1208                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1209                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1210         } else {
1211                 /*
1212                  * Force the non-existing CL2 off. BXT does this
1213                  * too, so maybe it saves some power even though
1214                  * CL2 doesn't exist?
1215                  */
1216                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1217                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1218                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1219         }
1220
1221         mutex_unlock(&dev_priv->sb_lock);
1222
1223         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1224         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1225
1226         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1227                       phy, dev_priv->chv_phy_control);
1228
1229         assert_chv_phy_status(dev_priv);
1230 }
1231
1232 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1233                                             struct i915_power_well *power_well)
1234 {
1235         enum dpio_phy phy;
1236
1237         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1238                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1239
1240         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1241                 phy = DPIO_PHY0;
1242                 assert_pll_disabled(dev_priv, PIPE_A);
1243                 assert_pll_disabled(dev_priv, PIPE_B);
1244         } else {
1245                 phy = DPIO_PHY1;
1246                 assert_pll_disabled(dev_priv, PIPE_C);
1247         }
1248
1249         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1250         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1251
1252         vlv_set_power_well(dev_priv, power_well, false);
1253
1254         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1255                       phy, dev_priv->chv_phy_control);
1256
1257         /* PHY is fully reset now, so we can enable the PHY state asserts */
1258         dev_priv->chv_phy_assert[phy] = true;
1259
1260         assert_chv_phy_status(dev_priv);
1261 }
1262
1263 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1264                                      enum dpio_channel ch, bool override, unsigned int mask)
1265 {
1266         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1267         u32 reg, val, expected, actual;
1268
1269         /*
1270          * The BIOS can leave the PHY is some weird state
1271          * where it doesn't fully power down some parts.
1272          * Disable the asserts until the PHY has been fully
1273          * reset (ie. the power well has been disabled at
1274          * least once).
1275          */
1276         if (!dev_priv->chv_phy_assert[phy])
1277                 return;
1278
1279         if (ch == DPIO_CH0)
1280                 reg = _CHV_CMN_DW0_CH0;
1281         else
1282                 reg = _CHV_CMN_DW6_CH1;
1283
1284         mutex_lock(&dev_priv->sb_lock);
1285         val = vlv_dpio_read(dev_priv, pipe, reg);
1286         mutex_unlock(&dev_priv->sb_lock);
1287
1288         /*
1289          * This assumes !override is only used when the port is disabled.
1290          * All lanes should power down even without the override when
1291          * the port is disabled.
1292          */
1293         if (!override || mask == 0xf) {
1294                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1295                 /*
1296                  * If CH1 common lane is not active anymore
1297                  * (eg. for pipe B DPLL) the entire channel will
1298                  * shut down, which causes the common lane registers
1299                  * to read as 0. That means we can't actually check
1300                  * the lane power down status bits, but as the entire
1301                  * register reads as 0 it's a good indication that the
1302                  * channel is indeed entirely powered down.
1303                  */
1304                 if (ch == DPIO_CH1 && val == 0)
1305                         expected = 0;
1306         } else if (mask != 0x0) {
1307                 expected = DPIO_ANYDL_POWERDOWN;
1308         } else {
1309                 expected = 0;
1310         }
1311
1312         if (ch == DPIO_CH0)
1313                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1314         else
1315                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1316         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1317
1318         WARN(actual != expected,
1319              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1320              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1321              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1322              reg, val);
1323 }
1324
1325 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1326                           enum dpio_channel ch, bool override)
1327 {
1328         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1329         bool was_override;
1330
1331         mutex_lock(&power_domains->lock);
1332
1333         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1334
1335         if (override == was_override)
1336                 goto out;
1337
1338         if (override)
1339                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1340         else
1341                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1342
1343         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1344
1345         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1346                       phy, ch, dev_priv->chv_phy_control);
1347
1348         assert_chv_phy_status(dev_priv);
1349
1350 out:
1351         mutex_unlock(&power_domains->lock);
1352
1353         return was_override;
1354 }
1355
1356 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1357                              bool override, unsigned int mask)
1358 {
1359         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1360         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1361         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1362         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1363
1364         mutex_lock(&power_domains->lock);
1365
1366         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1367         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1368
1369         if (override)
1370                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1371         else
1372                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1373
1374         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1375
1376         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1377                       phy, ch, mask, dev_priv->chv_phy_control);
1378
1379         assert_chv_phy_status(dev_priv);
1380
1381         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1382
1383         mutex_unlock(&power_domains->lock);
1384 }
1385
1386 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1387                                         struct i915_power_well *power_well)
1388 {
1389         enum pipe pipe = power_well->data;
1390         bool enabled;
1391         u32 state, ctrl;
1392
1393         mutex_lock(&dev_priv->rps.hw_lock);
1394
1395         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1396         /*
1397          * We only ever set the power-on and power-gate states, anything
1398          * else is unexpected.
1399          */
1400         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1401         enabled = state == DP_SSS_PWR_ON(pipe);
1402
1403         /*
1404          * A transient state at this point would mean some unexpected party
1405          * is poking at the power controls too.
1406          */
1407         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1408         WARN_ON(ctrl << 16 != state);
1409
1410         mutex_unlock(&dev_priv->rps.hw_lock);
1411
1412         return enabled;
1413 }
1414
1415 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1416                                     struct i915_power_well *power_well,
1417                                     bool enable)
1418 {
1419         enum pipe pipe = power_well->data;
1420         u32 state;
1421         u32 ctrl;
1422
1423         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1424
1425         mutex_lock(&dev_priv->rps.hw_lock);
1426
1427 #define COND \
1428         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1429
1430         if (COND)
1431                 goto out;
1432
1433         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1434         ctrl &= ~DP_SSC_MASK(pipe);
1435         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1436         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1437
1438         if (wait_for(COND, 100))
1439                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1440                           state,
1441                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1442
1443 #undef COND
1444
1445 out:
1446         mutex_unlock(&dev_priv->rps.hw_lock);
1447 }
1448
1449 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1450                                         struct i915_power_well *power_well)
1451 {
1452         WARN_ON_ONCE(power_well->data != PIPE_A);
1453
1454         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1455 }
1456
1457 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1458                                        struct i915_power_well *power_well)
1459 {
1460         WARN_ON_ONCE(power_well->data != PIPE_A);
1461
1462         chv_set_pipe_power_well(dev_priv, power_well, true);
1463
1464         vlv_display_power_well_init(dev_priv);
1465 }
1466
1467 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1468                                         struct i915_power_well *power_well)
1469 {
1470         WARN_ON_ONCE(power_well->data != PIPE_A);
1471
1472         vlv_display_power_well_deinit(dev_priv);
1473
1474         chv_set_pipe_power_well(dev_priv, power_well, false);
1475 }
1476
1477 static void
1478 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1479                                  enum intel_display_power_domain domain)
1480 {
1481         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1482         struct i915_power_well *power_well;
1483         int i;
1484
1485         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1486                 if (!power_well->count++)
1487                         intel_power_well_enable(dev_priv, power_well);
1488         }
1489
1490         power_domains->domain_use_count[domain]++;
1491 }
1492
1493 /**
1494  * intel_display_power_get - grab a power domain reference
1495  * @dev_priv: i915 device instance
1496  * @domain: power domain to reference
1497  *
1498  * This function grabs a power domain reference for @domain and ensures that the
1499  * power domain and all its parents are powered up. Therefore users should only
1500  * grab a reference to the innermost power domain they need.
1501  *
1502  * Any power domain reference obtained by this function must have a symmetric
1503  * call to intel_display_power_put() to release the reference again.
1504  */
1505 void intel_display_power_get(struct drm_i915_private *dev_priv,
1506                              enum intel_display_power_domain domain)
1507 {
1508         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1509
1510         intel_runtime_pm_get(dev_priv);
1511
1512         mutex_lock(&power_domains->lock);
1513
1514         __intel_display_power_get_domain(dev_priv, domain);
1515
1516         mutex_unlock(&power_domains->lock);
1517 }
1518
1519 /**
1520  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1521  * @dev_priv: i915 device instance
1522  * @domain: power domain to reference
1523  *
1524  * This function grabs a power domain reference for @domain and ensures that the
1525  * power domain and all its parents are powered up. Therefore users should only
1526  * grab a reference to the innermost power domain they need.
1527  *
1528  * Any power domain reference obtained by this function must have a symmetric
1529  * call to intel_display_power_put() to release the reference again.
1530  */
1531 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1532                                         enum intel_display_power_domain domain)
1533 {
1534         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1535         bool is_enabled;
1536
1537         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1538                 return false;
1539
1540         mutex_lock(&power_domains->lock);
1541
1542         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1543                 __intel_display_power_get_domain(dev_priv, domain);
1544                 is_enabled = true;
1545         } else {
1546                 is_enabled = false;
1547         }
1548
1549         mutex_unlock(&power_domains->lock);
1550
1551         if (!is_enabled)
1552                 intel_runtime_pm_put(dev_priv);
1553
1554         return is_enabled;
1555 }
1556
1557 /**
1558  * intel_display_power_put - release a power domain reference
1559  * @dev_priv: i915 device instance
1560  * @domain: power domain to reference
1561  *
1562  * This function drops the power domain reference obtained by
1563  * intel_display_power_get() and might power down the corresponding hardware
1564  * block right away if this is the last reference.
1565  */
1566 void intel_display_power_put(struct drm_i915_private *dev_priv,
1567                              enum intel_display_power_domain domain)
1568 {
1569         struct i915_power_domains *power_domains;
1570         struct i915_power_well *power_well;
1571         int i;
1572
1573         power_domains = &dev_priv->power_domains;
1574
1575         mutex_lock(&power_domains->lock);
1576
1577         WARN(!power_domains->domain_use_count[domain],
1578              "Use count on domain %s is already zero\n",
1579              intel_display_power_domain_str(domain));
1580         power_domains->domain_use_count[domain]--;
1581
1582         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1583                 WARN(!power_well->count,
1584                      "Use count on power well %s is already zero",
1585                      power_well->name);
1586
1587                 if (!--power_well->count)
1588                         intel_power_well_disable(dev_priv, power_well);
1589         }
1590
1591         mutex_unlock(&power_domains->lock);
1592
1593         intel_runtime_pm_put(dev_priv);
1594 }
1595
1596 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1597         BIT(POWER_DOMAIN_PIPE_B) |                      \
1598         BIT(POWER_DOMAIN_PIPE_C) |                      \
1599         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1600         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1601         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1602         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1603         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1604         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1605         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1606         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1607         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1608         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1609         BIT(POWER_DOMAIN_VGA) |                         \
1610         BIT(POWER_DOMAIN_AUDIO) |                       \
1611         BIT(POWER_DOMAIN_INIT))
1612
1613 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1614         BIT(POWER_DOMAIN_PIPE_B) |                      \
1615         BIT(POWER_DOMAIN_PIPE_C) |                      \
1616         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1617         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1618         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1619         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1620         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1621         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1622         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1623         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1624         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1625         BIT(POWER_DOMAIN_VGA) |                         \
1626         BIT(POWER_DOMAIN_AUDIO) |                       \
1627         BIT(POWER_DOMAIN_INIT))
1628
1629 #define VLV_DISPLAY_POWER_DOMAINS (             \
1630         BIT(POWER_DOMAIN_PIPE_A) |              \
1631         BIT(POWER_DOMAIN_PIPE_B) |              \
1632         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1633         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1634         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1635         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1636         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1637         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1638         BIT(POWER_DOMAIN_PORT_DSI) |            \
1639         BIT(POWER_DOMAIN_PORT_CRT) |            \
1640         BIT(POWER_DOMAIN_VGA) |                 \
1641         BIT(POWER_DOMAIN_AUDIO) |               \
1642         BIT(POWER_DOMAIN_AUX_B) |               \
1643         BIT(POWER_DOMAIN_AUX_C) |               \
1644         BIT(POWER_DOMAIN_GMBUS) |               \
1645         BIT(POWER_DOMAIN_INIT))
1646
1647 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1648         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1649         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1650         BIT(POWER_DOMAIN_PORT_CRT) |            \
1651         BIT(POWER_DOMAIN_AUX_B) |               \
1652         BIT(POWER_DOMAIN_AUX_C) |               \
1653         BIT(POWER_DOMAIN_INIT))
1654
1655 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1656         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1657         BIT(POWER_DOMAIN_AUX_B) |               \
1658         BIT(POWER_DOMAIN_INIT))
1659
1660 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1661         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1662         BIT(POWER_DOMAIN_AUX_B) |               \
1663         BIT(POWER_DOMAIN_INIT))
1664
1665 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1666         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1667         BIT(POWER_DOMAIN_AUX_C) |               \
1668         BIT(POWER_DOMAIN_INIT))
1669
1670 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1671         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1672         BIT(POWER_DOMAIN_AUX_C) |               \
1673         BIT(POWER_DOMAIN_INIT))
1674
1675 #define CHV_DISPLAY_POWER_DOMAINS (             \
1676         BIT(POWER_DOMAIN_PIPE_A) |              \
1677         BIT(POWER_DOMAIN_PIPE_B) |              \
1678         BIT(POWER_DOMAIN_PIPE_C) |              \
1679         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1680         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1681         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1682         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1683         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1684         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1685         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1686         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1687         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1688         BIT(POWER_DOMAIN_PORT_DSI) |            \
1689         BIT(POWER_DOMAIN_VGA) |                 \
1690         BIT(POWER_DOMAIN_AUDIO) |               \
1691         BIT(POWER_DOMAIN_AUX_B) |               \
1692         BIT(POWER_DOMAIN_AUX_C) |               \
1693         BIT(POWER_DOMAIN_AUX_D) |               \
1694         BIT(POWER_DOMAIN_GMBUS) |               \
1695         BIT(POWER_DOMAIN_INIT))
1696
1697 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1698         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1699         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1700         BIT(POWER_DOMAIN_AUX_B) |               \
1701         BIT(POWER_DOMAIN_AUX_C) |               \
1702         BIT(POWER_DOMAIN_INIT))
1703
1704 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1705         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1706         BIT(POWER_DOMAIN_AUX_D) |               \
1707         BIT(POWER_DOMAIN_INIT))
1708
1709 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1710         .sync_hw = i9xx_always_on_power_well_noop,
1711         .enable = i9xx_always_on_power_well_noop,
1712         .disable = i9xx_always_on_power_well_noop,
1713         .is_enabled = i9xx_always_on_power_well_enabled,
1714 };
1715
1716 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1717         .sync_hw = chv_pipe_power_well_sync_hw,
1718         .enable = chv_pipe_power_well_enable,
1719         .disable = chv_pipe_power_well_disable,
1720         .is_enabled = chv_pipe_power_well_enabled,
1721 };
1722
1723 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1724         .sync_hw = vlv_power_well_sync_hw,
1725         .enable = chv_dpio_cmn_power_well_enable,
1726         .disable = chv_dpio_cmn_power_well_disable,
1727         .is_enabled = vlv_power_well_enabled,
1728 };
1729
1730 static struct i915_power_well i9xx_always_on_power_well[] = {
1731         {
1732                 .name = "always-on",
1733                 .always_on = 1,
1734                 .domains = POWER_DOMAIN_MASK,
1735                 .ops = &i9xx_always_on_power_well_ops,
1736         },
1737 };
1738
1739 static const struct i915_power_well_ops hsw_power_well_ops = {
1740         .sync_hw = hsw_power_well_sync_hw,
1741         .enable = hsw_power_well_enable,
1742         .disable = hsw_power_well_disable,
1743         .is_enabled = hsw_power_well_enabled,
1744 };
1745
1746 static const struct i915_power_well_ops skl_power_well_ops = {
1747         .sync_hw = skl_power_well_sync_hw,
1748         .enable = skl_power_well_enable,
1749         .disable = skl_power_well_disable,
1750         .is_enabled = skl_power_well_enabled,
1751 };
1752
1753 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1754         .sync_hw = gen9_dc_off_power_well_sync_hw,
1755         .enable = gen9_dc_off_power_well_enable,
1756         .disable = gen9_dc_off_power_well_disable,
1757         .is_enabled = gen9_dc_off_power_well_enabled,
1758 };
1759
1760 static struct i915_power_well hsw_power_wells[] = {
1761         {
1762                 .name = "always-on",
1763                 .always_on = 1,
1764                 .domains = POWER_DOMAIN_MASK,
1765                 .ops = &i9xx_always_on_power_well_ops,
1766         },
1767         {
1768                 .name = "display",
1769                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1770                 .ops = &hsw_power_well_ops,
1771         },
1772 };
1773
1774 static struct i915_power_well bdw_power_wells[] = {
1775         {
1776                 .name = "always-on",
1777                 .always_on = 1,
1778                 .domains = POWER_DOMAIN_MASK,
1779                 .ops = &i9xx_always_on_power_well_ops,
1780         },
1781         {
1782                 .name = "display",
1783                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1784                 .ops = &hsw_power_well_ops,
1785         },
1786 };
1787
1788 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1789         .sync_hw = vlv_power_well_sync_hw,
1790         .enable = vlv_display_power_well_enable,
1791         .disable = vlv_display_power_well_disable,
1792         .is_enabled = vlv_power_well_enabled,
1793 };
1794
1795 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1796         .sync_hw = vlv_power_well_sync_hw,
1797         .enable = vlv_dpio_cmn_power_well_enable,
1798         .disable = vlv_dpio_cmn_power_well_disable,
1799         .is_enabled = vlv_power_well_enabled,
1800 };
1801
1802 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1803         .sync_hw = vlv_power_well_sync_hw,
1804         .enable = vlv_power_well_enable,
1805         .disable = vlv_power_well_disable,
1806         .is_enabled = vlv_power_well_enabled,
1807 };
1808
1809 static struct i915_power_well vlv_power_wells[] = {
1810         {
1811                 .name = "always-on",
1812                 .always_on = 1,
1813                 .domains = POWER_DOMAIN_MASK,
1814                 .ops = &i9xx_always_on_power_well_ops,
1815                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1816         },
1817         {
1818                 .name = "display",
1819                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1820                 .data = PUNIT_POWER_WELL_DISP2D,
1821                 .ops = &vlv_display_power_well_ops,
1822         },
1823         {
1824                 .name = "dpio-tx-b-01",
1825                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1826                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1827                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1828                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1829                 .ops = &vlv_dpio_power_well_ops,
1830                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1831         },
1832         {
1833                 .name = "dpio-tx-b-23",
1834                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1835                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1836                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1837                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1838                 .ops = &vlv_dpio_power_well_ops,
1839                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1840         },
1841         {
1842                 .name = "dpio-tx-c-01",
1843                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1844                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1845                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1846                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1847                 .ops = &vlv_dpio_power_well_ops,
1848                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1849         },
1850         {
1851                 .name = "dpio-tx-c-23",
1852                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1853                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1854                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1855                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1856                 .ops = &vlv_dpio_power_well_ops,
1857                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1858         },
1859         {
1860                 .name = "dpio-common",
1861                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1862                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1863                 .ops = &vlv_dpio_cmn_power_well_ops,
1864         },
1865 };
1866
1867 static struct i915_power_well chv_power_wells[] = {
1868         {
1869                 .name = "always-on",
1870                 .always_on = 1,
1871                 .domains = POWER_DOMAIN_MASK,
1872                 .ops = &i9xx_always_on_power_well_ops,
1873         },
1874         {
1875                 .name = "display",
1876                 /*
1877                  * Pipe A power well is the new disp2d well. Pipe B and C
1878                  * power wells don't actually exist. Pipe A power well is
1879                  * required for any pipe to work.
1880                  */
1881                 .domains = CHV_DISPLAY_POWER_DOMAINS,
1882                 .data = PIPE_A,
1883                 .ops = &chv_pipe_power_well_ops,
1884         },
1885         {
1886                 .name = "dpio-common-bc",
1887                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1888                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1889                 .ops = &chv_dpio_cmn_power_well_ops,
1890         },
1891         {
1892                 .name = "dpio-common-d",
1893                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1894                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1895                 .ops = &chv_dpio_cmn_power_well_ops,
1896         },
1897 };
1898
1899 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1900                                     int power_well_id)
1901 {
1902         struct i915_power_well *power_well;
1903         bool ret;
1904
1905         power_well = lookup_power_well(dev_priv, power_well_id);
1906         ret = power_well->ops->is_enabled(dev_priv, power_well);
1907
1908         return ret;
1909 }
1910
1911 static struct i915_power_well skl_power_wells[] = {
1912         {
1913                 .name = "always-on",
1914                 .always_on = 1,
1915                 .domains = POWER_DOMAIN_MASK,
1916                 .ops = &i9xx_always_on_power_well_ops,
1917                 .data = SKL_DISP_PW_ALWAYS_ON,
1918         },
1919         {
1920                 .name = "power well 1",
1921                 /* Handled by the DMC firmware */
1922                 .domains = 0,
1923                 .ops = &skl_power_well_ops,
1924                 .data = SKL_DISP_PW_1,
1925         },
1926         {
1927                 .name = "MISC IO power well",
1928                 /* Handled by the DMC firmware */
1929                 .domains = 0,
1930                 .ops = &skl_power_well_ops,
1931                 .data = SKL_DISP_PW_MISC_IO,
1932         },
1933         {
1934                 .name = "DC off",
1935                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1936                 .ops = &gen9_dc_off_power_well_ops,
1937                 .data = SKL_DISP_PW_DC_OFF,
1938         },
1939         {
1940                 .name = "power well 2",
1941                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1942                 .ops = &skl_power_well_ops,
1943                 .data = SKL_DISP_PW_2,
1944         },
1945         {
1946                 .name = "DDI A/E power well",
1947                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1948                 .ops = &skl_power_well_ops,
1949                 .data = SKL_DISP_PW_DDI_A_E,
1950         },
1951         {
1952                 .name = "DDI B power well",
1953                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1954                 .ops = &skl_power_well_ops,
1955                 .data = SKL_DISP_PW_DDI_B,
1956         },
1957         {
1958                 .name = "DDI C power well",
1959                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1960                 .ops = &skl_power_well_ops,
1961                 .data = SKL_DISP_PW_DDI_C,
1962         },
1963         {
1964                 .name = "DDI D power well",
1965                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1966                 .ops = &skl_power_well_ops,
1967                 .data = SKL_DISP_PW_DDI_D,
1968         },
1969 };
1970
1971 static struct i915_power_well bxt_power_wells[] = {
1972         {
1973                 .name = "always-on",
1974                 .always_on = 1,
1975                 .domains = POWER_DOMAIN_MASK,
1976                 .ops = &i9xx_always_on_power_well_ops,
1977         },
1978         {
1979                 .name = "power well 1",
1980                 .domains = 0,
1981                 .ops = &skl_power_well_ops,
1982                 .data = SKL_DISP_PW_1,
1983         },
1984         {
1985                 .name = "DC off",
1986                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1987                 .ops = &gen9_dc_off_power_well_ops,
1988                 .data = SKL_DISP_PW_DC_OFF,
1989         },
1990         {
1991                 .name = "power well 2",
1992                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1993                 .ops = &skl_power_well_ops,
1994                 .data = SKL_DISP_PW_2,
1995         },
1996 };
1997
1998 static int
1999 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2000                                    int disable_power_well)
2001 {
2002         if (disable_power_well >= 0)
2003                 return !!disable_power_well;
2004
2005         return 1;
2006 }
2007
2008 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2009                                     int enable_dc)
2010 {
2011         uint32_t mask;
2012         int requested_dc;
2013         int max_dc;
2014
2015         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2016                 max_dc = 2;
2017                 mask = 0;
2018         } else if (IS_BROXTON(dev_priv)) {
2019                 max_dc = 1;
2020                 /*
2021                  * DC9 has a separate HW flow from the rest of the DC states,
2022                  * not depending on the DMC firmware. It's needed by system
2023                  * suspend/resume, so allow it unconditionally.
2024                  */
2025                 mask = DC_STATE_EN_DC9;
2026         } else {
2027                 max_dc = 0;
2028                 mask = 0;
2029         }
2030
2031         if (!i915.disable_power_well)
2032                 max_dc = 0;
2033
2034         if (enable_dc >= 0 && enable_dc <= max_dc) {
2035                 requested_dc = enable_dc;
2036         } else if (enable_dc == -1) {
2037                 requested_dc = max_dc;
2038         } else if (enable_dc > max_dc && enable_dc <= 2) {
2039                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2040                               enable_dc, max_dc);
2041                 requested_dc = max_dc;
2042         } else {
2043                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2044                 requested_dc = max_dc;
2045         }
2046
2047         if (requested_dc > 1)
2048                 mask |= DC_STATE_EN_UPTO_DC6;
2049         if (requested_dc > 0)
2050                 mask |= DC_STATE_EN_UPTO_DC5;
2051
2052         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2053
2054         return mask;
2055 }
2056
2057 #define set_power_wells(power_domains, __power_wells) ({                \
2058         (power_domains)->power_wells = (__power_wells);                 \
2059         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2060 })
2061
2062 /**
2063  * intel_power_domains_init - initializes the power domain structures
2064  * @dev_priv: i915 device instance
2065  *
2066  * Initializes the power domain structures for @dev_priv depending upon the
2067  * supported platform.
2068  */
2069 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2070 {
2071         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2072
2073         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2074                                                      i915.disable_power_well);
2075         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2076                                                             i915.enable_dc);
2077
2078         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2079
2080         mutex_init(&power_domains->lock);
2081
2082         /*
2083          * The enabling order will be from lower to higher indexed wells,
2084          * the disabling order is reversed.
2085          */
2086         if (IS_HASWELL(dev_priv)) {
2087                 set_power_wells(power_domains, hsw_power_wells);
2088         } else if (IS_BROADWELL(dev_priv)) {
2089                 set_power_wells(power_domains, bdw_power_wells);
2090         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2091                 set_power_wells(power_domains, skl_power_wells);
2092         } else if (IS_BROXTON(dev_priv)) {
2093                 set_power_wells(power_domains, bxt_power_wells);
2094         } else if (IS_CHERRYVIEW(dev_priv)) {
2095                 set_power_wells(power_domains, chv_power_wells);
2096         } else if (IS_VALLEYVIEW(dev_priv)) {
2097                 set_power_wells(power_domains, vlv_power_wells);
2098         } else {
2099                 set_power_wells(power_domains, i9xx_always_on_power_well);
2100         }
2101
2102         return 0;
2103 }
2104
2105 /**
2106  * intel_power_domains_fini - finalizes the power domain structures
2107  * @dev_priv: i915 device instance
2108  *
2109  * Finalizes the power domain structures for @dev_priv depending upon the
2110  * supported platform. This function also disables runtime pm and ensures that
2111  * the device stays powered up so that the driver can be reloaded.
2112  */
2113 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2114 {
2115         struct device *device = &dev_priv->dev->pdev->dev;
2116
2117         /*
2118          * The i915.ko module is still not prepared to be loaded when
2119          * the power well is not enabled, so just enable it in case
2120          * we're going to unload/reload.
2121          * The following also reacquires the RPM reference the core passed
2122          * to the driver during loading, which is dropped in
2123          * intel_runtime_pm_enable(). We have to hand back the control of the
2124          * device to the core with this reference held.
2125          */
2126         intel_display_set_init_power(dev_priv, true);
2127
2128         /* Remove the refcount we took to keep power well support disabled. */
2129         if (!i915.disable_power_well)
2130                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2131
2132         /*
2133          * Remove the refcount we took in intel_runtime_pm_enable() in case
2134          * the platform doesn't support runtime PM.
2135          */
2136         if (!HAS_RUNTIME_PM(dev_priv))
2137                 pm_runtime_put(device);
2138 }
2139
2140 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2141 {
2142         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2143         struct i915_power_well *power_well;
2144         int i;
2145
2146         mutex_lock(&power_domains->lock);
2147         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2148                 power_well->ops->sync_hw(dev_priv, power_well);
2149                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2150                                                                      power_well);
2151         }
2152         mutex_unlock(&power_domains->lock);
2153 }
2154
2155 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2156                                    bool resume)
2157 {
2158         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2159         struct i915_power_well *well;
2160         uint32_t val;
2161
2162         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2163
2164         /* enable PCH reset handshake */
2165         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2166         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2167
2168         /* enable PG1 and Misc I/O */
2169         mutex_lock(&power_domains->lock);
2170
2171         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2172         intel_power_well_enable(dev_priv, well);
2173
2174         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2175         intel_power_well_enable(dev_priv, well);
2176
2177         mutex_unlock(&power_domains->lock);
2178
2179         if (!resume)
2180                 return;
2181
2182         skl_init_cdclk(dev_priv);
2183
2184         if (dev_priv->csr.dmc_payload)
2185                 intel_csr_load_program(dev_priv);
2186 }
2187
2188 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2189 {
2190         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2191         struct i915_power_well *well;
2192
2193         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2194
2195         skl_uninit_cdclk(dev_priv);
2196
2197         /* The spec doesn't call for removing the reset handshake flag */
2198         /* disable PG1 and Misc I/O */
2199
2200         mutex_lock(&power_domains->lock);
2201
2202         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2203         intel_power_well_disable(dev_priv, well);
2204
2205         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2206         intel_power_well_disable(dev_priv, well);
2207
2208         mutex_unlock(&power_domains->lock);
2209 }
2210
2211 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2212                            bool resume)
2213 {
2214         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2215         struct i915_power_well *well;
2216         uint32_t val;
2217
2218         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2219
2220         /*
2221          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2222          * or else the reset will hang because there is no PCH to respond.
2223          * Move the handshake programming to initialization sequence.
2224          * Previously was left up to BIOS.
2225          */
2226         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2227         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2228         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2229
2230         /* Enable PG1 */
2231         mutex_lock(&power_domains->lock);
2232
2233         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2234         intel_power_well_enable(dev_priv, well);
2235
2236         mutex_unlock(&power_domains->lock);
2237
2238         broxton_init_cdclk(dev_priv);
2239         broxton_ddi_phy_init(dev_priv);
2240
2241         broxton_cdclk_verify_state(dev_priv);
2242         broxton_ddi_phy_verify_state(dev_priv);
2243
2244         if (resume && dev_priv->csr.dmc_payload)
2245                 intel_csr_load_program(dev_priv);
2246 }
2247
2248 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2249 {
2250         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2251         struct i915_power_well *well;
2252
2253         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2254
2255         broxton_ddi_phy_uninit(dev_priv);
2256         broxton_uninit_cdclk(dev_priv);
2257
2258         /* The spec doesn't call for removing the reset handshake flag */
2259
2260         /* Disable PG1 */
2261         mutex_lock(&power_domains->lock);
2262
2263         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2264         intel_power_well_disable(dev_priv, well);
2265
2266         mutex_unlock(&power_domains->lock);
2267 }
2268
2269 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2270 {
2271         struct i915_power_well *cmn_bc =
2272                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2273         struct i915_power_well *cmn_d =
2274                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2275
2276         /*
2277          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2278          * workaround never ever read DISPLAY_PHY_CONTROL, and
2279          * instead maintain a shadow copy ourselves. Use the actual
2280          * power well state and lane status to reconstruct the
2281          * expected initial value.
2282          */
2283         dev_priv->chv_phy_control =
2284                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2285                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2286                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2287                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2288                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2289
2290         /*
2291          * If all lanes are disabled we leave the override disabled
2292          * with all power down bits cleared to match the state we
2293          * would use after disabling the port. Otherwise enable the
2294          * override and set the lane powerdown bits accding to the
2295          * current lane status.
2296          */
2297         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2298                 uint32_t status = I915_READ(DPLL(PIPE_A));
2299                 unsigned int mask;
2300
2301                 mask = status & DPLL_PORTB_READY_MASK;
2302                 if (mask == 0xf)
2303                         mask = 0x0;
2304                 else
2305                         dev_priv->chv_phy_control |=
2306                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2307
2308                 dev_priv->chv_phy_control |=
2309                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2310
2311                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2312                 if (mask == 0xf)
2313                         mask = 0x0;
2314                 else
2315                         dev_priv->chv_phy_control |=
2316                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2317
2318                 dev_priv->chv_phy_control |=
2319                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2320
2321                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2322
2323                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2324         } else {
2325                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2326         }
2327
2328         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2329                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2330                 unsigned int mask;
2331
2332                 mask = status & DPLL_PORTD_READY_MASK;
2333
2334                 if (mask == 0xf)
2335                         mask = 0x0;
2336                 else
2337                         dev_priv->chv_phy_control |=
2338                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2339
2340                 dev_priv->chv_phy_control |=
2341                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2342
2343                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2344
2345                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2346         } else {
2347                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2348         }
2349
2350         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2351
2352         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2353                       dev_priv->chv_phy_control);
2354 }
2355
2356 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2357 {
2358         struct i915_power_well *cmn =
2359                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2360         struct i915_power_well *disp2d =
2361                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2362
2363         /* If the display might be already active skip this */
2364         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2365             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2366             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2367                 return;
2368
2369         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2370
2371         /* cmnlane needs DPLL registers */
2372         disp2d->ops->enable(dev_priv, disp2d);
2373
2374         /*
2375          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2376          * Need to assert and de-assert PHY SB reset by gating the
2377          * common lane power, then un-gating it.
2378          * Simply ungating isn't enough to reset the PHY enough to get
2379          * ports and lanes running.
2380          */
2381         cmn->ops->disable(dev_priv, cmn);
2382 }
2383
2384 /**
2385  * intel_power_domains_init_hw - initialize hardware power domain state
2386  * @dev_priv: i915 device instance
2387  *
2388  * This function initializes the hardware power domain state and enables all
2389  * power domains using intel_display_set_init_power().
2390  */
2391 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2392 {
2393         struct drm_device *dev = dev_priv->dev;
2394         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2395
2396         power_domains->initializing = true;
2397
2398         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2399                 skl_display_core_init(dev_priv, resume);
2400         } else if (IS_BROXTON(dev)) {
2401                 bxt_display_core_init(dev_priv, resume);
2402         } else if (IS_CHERRYVIEW(dev)) {
2403                 mutex_lock(&power_domains->lock);
2404                 chv_phy_control_init(dev_priv);
2405                 mutex_unlock(&power_domains->lock);
2406         } else if (IS_VALLEYVIEW(dev)) {
2407                 mutex_lock(&power_domains->lock);
2408                 vlv_cmnlane_wa(dev_priv);
2409                 mutex_unlock(&power_domains->lock);
2410         }
2411
2412         /* For now, we need the power well to be always enabled. */
2413         intel_display_set_init_power(dev_priv, true);
2414         /* Disable power support if the user asked so. */
2415         if (!i915.disable_power_well)
2416                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2417         intel_power_domains_sync_hw(dev_priv);
2418         power_domains->initializing = false;
2419 }
2420
2421 /**
2422  * intel_power_domains_suspend - suspend power domain state
2423  * @dev_priv: i915 device instance
2424  *
2425  * This function prepares the hardware power domain state before entering
2426  * system suspend. It must be paired with intel_power_domains_init_hw().
2427  */
2428 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2429 {
2430         /*
2431          * Even if power well support was disabled we still want to disable
2432          * power wells while we are system suspended.
2433          */
2434         if (!i915.disable_power_well)
2435                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2436
2437         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2438                 skl_display_core_uninit(dev_priv);
2439         else if (IS_BROXTON(dev_priv))
2440                 bxt_display_core_uninit(dev_priv);
2441 }
2442
2443 /**
2444  * intel_runtime_pm_get - grab a runtime pm reference
2445  * @dev_priv: i915 device instance
2446  *
2447  * This function grabs a device-level runtime pm reference (mostly used for GEM
2448  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2449  *
2450  * Any runtime pm reference obtained by this function must have a symmetric
2451  * call to intel_runtime_pm_put() to release the reference again.
2452  */
2453 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2454 {
2455         struct drm_device *dev = dev_priv->dev;
2456         struct device *device = &dev->pdev->dev;
2457
2458         pm_runtime_get_sync(device);
2459
2460         atomic_inc(&dev_priv->pm.wakeref_count);
2461         assert_rpm_wakelock_held(dev_priv);
2462 }
2463
2464 /**
2465  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2466  * @dev_priv: i915 device instance
2467  *
2468  * This function grabs a device-level runtime pm reference if the device is
2469  * already in use and ensures that it is powered up.
2470  *
2471  * Any runtime pm reference obtained by this function must have a symmetric
2472  * call to intel_runtime_pm_put() to release the reference again.
2473  */
2474 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2475 {
2476         struct drm_device *dev = dev_priv->dev;
2477         struct device *device = &dev->pdev->dev;
2478
2479         if (IS_ENABLED(CONFIG_PM)) {
2480                 int ret = pm_runtime_get_if_in_use(device);
2481
2482                 /*
2483                  * In cases runtime PM is disabled by the RPM core and we get
2484                  * an -EINVAL return value we are not supposed to call this
2485                  * function, since the power state is undefined. This applies
2486                  * atm to the late/early system suspend/resume handlers.
2487                  */
2488                 WARN_ON_ONCE(ret < 0);
2489                 if (ret <= 0)
2490                         return false;
2491         }
2492
2493         atomic_inc(&dev_priv->pm.wakeref_count);
2494         assert_rpm_wakelock_held(dev_priv);
2495
2496         return true;
2497 }
2498
2499 /**
2500  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2501  * @dev_priv: i915 device instance
2502  *
2503  * This function grabs a device-level runtime pm reference (mostly used for GEM
2504  * code to ensure the GTT or GT is on).
2505  *
2506  * It will _not_ power up the device but instead only check that it's powered
2507  * on.  Therefore it is only valid to call this functions from contexts where
2508  * the device is known to be powered up and where trying to power it up would
2509  * result in hilarity and deadlocks. That pretty much means only the system
2510  * suspend/resume code where this is used to grab runtime pm references for
2511  * delayed setup down in work items.
2512  *
2513  * Any runtime pm reference obtained by this function must have a symmetric
2514  * call to intel_runtime_pm_put() to release the reference again.
2515  */
2516 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2517 {
2518         struct drm_device *dev = dev_priv->dev;
2519         struct device *device = &dev->pdev->dev;
2520
2521         assert_rpm_wakelock_held(dev_priv);
2522         pm_runtime_get_noresume(device);
2523
2524         atomic_inc(&dev_priv->pm.wakeref_count);
2525 }
2526
2527 /**
2528  * intel_runtime_pm_put - release a runtime pm reference
2529  * @dev_priv: i915 device instance
2530  *
2531  * This function drops the device-level runtime pm reference obtained by
2532  * intel_runtime_pm_get() and might power down the corresponding
2533  * hardware block right away if this is the last reference.
2534  */
2535 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2536 {
2537         struct drm_device *dev = dev_priv->dev;
2538         struct device *device = &dev->pdev->dev;
2539
2540         assert_rpm_wakelock_held(dev_priv);
2541         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2542                 atomic_inc(&dev_priv->pm.atomic_seq);
2543
2544         pm_runtime_mark_last_busy(device);
2545         pm_runtime_put_autosuspend(device);
2546 }
2547
2548 /**
2549  * intel_runtime_pm_enable - enable runtime pm
2550  * @dev_priv: i915 device instance
2551  *
2552  * This function enables runtime pm at the end of the driver load sequence.
2553  *
2554  * Note that this function does currently not enable runtime pm for the
2555  * subordinate display power domains. That is only done on the first modeset
2556  * using intel_display_set_init_power().
2557  */
2558 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2559 {
2560         struct drm_device *dev = dev_priv->dev;
2561         struct device *device = &dev->pdev->dev;
2562
2563         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2564         pm_runtime_mark_last_busy(device);
2565
2566         /*
2567          * Take a permanent reference to disable the RPM functionality and drop
2568          * it only when unloading the driver. Use the low level get/put helpers,
2569          * so the driver's own RPM reference tracking asserts also work on
2570          * platforms without RPM support.
2571          */
2572         if (!HAS_RUNTIME_PM(dev)) {
2573                 pm_runtime_dont_use_autosuspend(device);
2574                 pm_runtime_get_sync(device);
2575         } else {
2576                 pm_runtime_use_autosuspend(device);
2577         }
2578
2579         /*
2580          * The core calls the driver load handler with an RPM reference held.
2581          * We drop that here and will reacquire it during unloading in
2582          * intel_power_domains_fini().
2583          */
2584         pm_runtime_put_autosuspend(device);
2585 }
2586