drivers/gpu/drm/bridge/fsl-ldb.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2022 Marek Vasut <[email protected]>
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/media-bus-format.h>
   8 #include <linux/mfd/syscon.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/of_graph.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_bridge.h>
  18 #include <drm/drm_of.h>
  19 #include <drm/drm_panel.h>
  20
  21 #define LDB_CTRL_CH0_ENABLE                     BIT(0)
  22 #define LDB_CTRL_CH0_DI_SELECT                  BIT(1)
  23 #define LDB_CTRL_CH1_ENABLE                     BIT(2)
  24 #define LDB_CTRL_CH1_DI_SELECT                  BIT(3)
  25 #define LDB_CTRL_SPLIT_MODE                     BIT(4)
  26 #define LDB_CTRL_CH0_DATA_WIDTH                 BIT(5)
  27 #define LDB_CTRL_CH0_BIT_MAPPING                BIT(6)
  28 #define LDB_CTRL_CH1_DATA_WIDTH                 BIT(7)
  29 #define LDB_CTRL_CH1_BIT_MAPPING                BIT(8)
  30 #define LDB_CTRL_DI0_VSYNC_POLARITY             BIT(9)
  31 #define LDB_CTRL_DI1_VSYNC_POLARITY             BIT(10)
  32 #define LDB_CTRL_REG_CH0_FIFO_RESET             BIT(11)
  33 #define LDB_CTRL_REG_CH1_FIFO_RESET             BIT(12)
  34 #define LDB_CTRL_ASYNC_FIFO_ENABLE              BIT(24)
  35 #define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK      GENMASK(27, 25)
  36
  37 #define LVDS_CTRL_CH0_EN                        BIT(0)
  38 #define LVDS_CTRL_CH1_EN                        BIT(1)
  39 /*
  40  * LVDS_CTRL_LVDS_EN bit is poorly named in i.MX93 reference manual.
  41  * Clear it to enable LVDS and set it to disable LVDS.
  42  */
  43 #define LVDS_CTRL_LVDS_EN                       BIT(1)
  44 #define LVDS_CTRL_VBG_EN                        BIT(2)
  45 #define LVDS_CTRL_HS_EN                         BIT(3)
  46 #define LVDS_CTRL_PRE_EMPH_EN                   BIT(4)
  47 #define LVDS_CTRL_PRE_EMPH_ADJ(n)               (((n) & 0x7) << 5)
  48 #define LVDS_CTRL_PRE_EMPH_ADJ_MASK             GENMASK(7, 5)
  49 #define LVDS_CTRL_CM_ADJ(n)                     (((n) & 0x7) << 8)
  50 #define LVDS_CTRL_CM_ADJ_MASK                   GENMASK(10, 8)
  51 #define LVDS_CTRL_CC_ADJ(n)                     (((n) & 0x7) << 11)
  52 #define LVDS_CTRL_CC_ADJ_MASK                   GENMASK(13, 11)
  53 #define LVDS_CTRL_SLEW_ADJ(n)                   (((n) & 0x7) << 14)
  54 #define LVDS_CTRL_SLEW_ADJ_MASK                 GENMASK(16, 14)
  55 #define LVDS_CTRL_VBG_ADJ(n)                    (((n) & 0x7) << 17)
  56 #define LVDS_CTRL_VBG_ADJ_MASK                  GENMASK(19, 17)
  57
  58 enum fsl_ldb_devtype {
  59         IMX8MP_LDB,
  60         IMX93_LDB,
  61 };
  62
  63 struct fsl_ldb_devdata {
  64         u32 ldb_ctrl;
  65         u32 lvds_ctrl;
  66         bool lvds_en_bit;
  67 };
  68
  69 static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
  70         [IMX8MP_LDB] = {
  71                 .ldb_ctrl = 0x5c,
  72                 .lvds_ctrl = 0x128,
  73         },
  74         [IMX93_LDB] = {
  75                 .ldb_ctrl = 0x20,
  76                 .lvds_ctrl = 0x24,
  77                 .lvds_en_bit = true,
  78         },
  79 };
  80
  81 struct fsl_ldb {
  82         struct device *dev;
  83         struct drm_bridge bridge;
  84         struct drm_bridge *panel_bridge;
  85         struct clk *clk;
  86         struct regmap *regmap;
  87         bool lvds_dual_link;
  88         const struct fsl_ldb_devdata *devdata;
  89 };
  90
  91 static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge)
  92 {
  93         return container_of(bridge, struct fsl_ldb, bridge);
  94 }
  95
  96 static unsigned long fsl_ldb_link_frequency(struct fsl_ldb *fsl_ldb, int clock)
  97 {
  98         if (fsl_ldb->lvds_dual_link)
  99                 return clock * 3500;
 100         else
 101                 return clock * 7000;
 102 }
 103
 104 static int fsl_ldb_attach(struct drm_bridge *bridge,
 105                           enum drm_bridge_attach_flags flags)
 106 {
 107         struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
 108
 109         return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge,
 110                                  bridge, flags);
 111 }
 112
 113 static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
 114                                   struct drm_bridge_state *old_bridge_state)
 115 {
 116         struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
 117         struct drm_atomic_state *state = old_bridge_state->base.state;
 118         const struct drm_bridge_state *bridge_state;
 119         const struct drm_crtc_state *crtc_state;
 120         const struct drm_display_mode *mode;
 121         struct drm_connector *connector;
 122         struct drm_crtc *crtc;
 123         unsigned long configured_link_freq;
 124         unsigned long requested_link_freq;
 125         bool lvds_format_24bpp;
 126         bool lvds_format_jeida;
 127         u32 reg;
 128
 129         /* Get the LVDS format from the bridge state. */
 130         bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
 131
 132         switch (bridge_state->output_bus_cfg.format) {
 133         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 134                 lvds_format_24bpp = false;
 135                 lvds_format_jeida = true;
 136                 break;
 137         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 138                 lvds_format_24bpp = true;
 139                 lvds_format_jeida = true;
 140                 break;
 141         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 142                 lvds_format_24bpp = true;
 143                 lvds_format_jeida = false;
 144                 break;
 145         default:
 146                 /*
 147                  * Some bridges still don't set the correct LVDS bus pixel
 148                  * format, use SPWG24 default format until those are fixed.
 149                  */
 150                 lvds_format_24bpp = true;
 151                 lvds_format_jeida = false;
 152                 dev_warn(fsl_ldb->dev,
 153                          "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
 154                          bridge_state->output_bus_cfg.format);
 155                 break;
 156         }
 157
 158         /*
 159          * Retrieve the CRTC adjusted mode. This requires a little dance to go
 160          * from the bridge to the encoder, to the connector and to the CRTC.
 161          */
 162         connector = drm_atomic_get_new_connector_for_encoder(state,
 163                                                              bridge->encoder);
 164         crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
 165         crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
 166         mode = &crtc_state->adjusted_mode;
 167
 168         requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock);
 169         clk_set_rate(fsl_ldb->clk, requested_link_freq);
 170
 171         configured_link_freq = clk_get_rate(fsl_ldb->clk);
 172         if (configured_link_freq != requested_link_freq)
 173                 dev_warn(fsl_ldb->dev, "Configured LDB clock (%lu Hz) does not match requested LVDS clock: %lu Hz",
 174                          configured_link_freq,
 175                          requested_link_freq);
 176
 177         clk_prepare_enable(fsl_ldb->clk);
 178
 179         /* Program LDB_CTRL */
 180         reg = LDB_CTRL_CH0_ENABLE;
 181
 182         if (fsl_ldb->lvds_dual_link)
 183                 reg |= LDB_CTRL_CH1_ENABLE | LDB_CTRL_SPLIT_MODE;
 184
 185         if (lvds_format_24bpp) {
 186                 reg |= LDB_CTRL_CH0_DATA_WIDTH;
 187                 if (fsl_ldb->lvds_dual_link)
 188                         reg |= LDB_CTRL_CH1_DATA_WIDTH;
 189         }
 190
 191         if (lvds_format_jeida) {
 192                 reg |= LDB_CTRL_CH0_BIT_MAPPING;
 193                 if (fsl_ldb->lvds_dual_link)
 194                         reg |= LDB_CTRL_CH1_BIT_MAPPING;
 195         }
 196
 197         if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
 198                 reg |= LDB_CTRL_DI0_VSYNC_POLARITY;
 199                 if (fsl_ldb->lvds_dual_link)
 200                         reg |= LDB_CTRL_DI1_VSYNC_POLARITY;
 201         }
 202
 203         regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
 204
 205         /* Program LVDS_CTRL */
 206         reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
 207               LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
 208         regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg);
 209
 210         /* Wait for VBG to stabilize. */
 211         usleep_range(15, 20);
 212
 213         reg |= LVDS_CTRL_CH0_EN;
 214         if (fsl_ldb->lvds_dual_link)
 215                 reg |= LVDS_CTRL_CH1_EN;
 216
 217         regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg);
 218 }
 219
 220 static void fsl_ldb_atomic_disable(struct drm_bridge *bridge,
 221                                    struct drm_bridge_state *old_bridge_state)
 222 {
 223         struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
 224
 225         /* Stop channel(s). */
 226         if (fsl_ldb->devdata->lvds_en_bit)
 227                 /* Set LVDS_CTRL_LVDS_EN bit to disable. */
 228                 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
 229                              LVDS_CTRL_LVDS_EN);
 230         else
 231                 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
 232         regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
 233
 234         clk_disable_unprepare(fsl_ldb->clk);
 235 }
 236
 237 #define MAX_INPUT_SEL_FORMATS 1
 238 static u32 *
 239 fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 240                                   struct drm_bridge_state *bridge_state,
 241                                   struct drm_crtc_state *crtc_state,
 242                                   struct drm_connector_state *conn_state,
 243                                   u32 output_fmt,
 244                                   unsigned int *num_input_fmts)
 245 {
 246         u32 *input_fmts;
 247
 248         *num_input_fmts = 0;
 249
 250         input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
 251                              GFP_KERNEL);
 252         if (!input_fmts)
 253                 return NULL;
 254
 255         input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
 256         *num_input_fmts = MAX_INPUT_SEL_FORMATS;
 257
 258         return input_fmts;
 259 }
 260
 261 static enum drm_mode_status
 262 fsl_ldb_mode_valid(struct drm_bridge *bridge,
 263                    const struct drm_display_info *info,
 264                    const struct drm_display_mode *mode)
 265 {
 266         struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
 267
 268         if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000))
 269                 return MODE_CLOCK_HIGH;
 270
 271         return MODE_OK;
 272 }
 273
 274 static const struct drm_bridge_funcs funcs = {
 275         .attach = fsl_ldb_attach,
 276         .atomic_enable = fsl_ldb_atomic_enable,
 277         .atomic_disable = fsl_ldb_atomic_disable,
 278         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 279         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 280         .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts,
 281         .atomic_reset = drm_atomic_helper_bridge_reset,
 282         .mode_valid = fsl_ldb_mode_valid,
 283 };
 284
 285 static int fsl_ldb_probe(struct platform_device *pdev)
 286 {
 287         struct device *dev = &pdev->dev;
 288         struct device_node *panel_node;
 289         struct device_node *port1, *port2;
 290         struct drm_panel *panel;
 291         struct fsl_ldb *fsl_ldb;
 292         int dual_link;
 293
 294         fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL);
 295         if (!fsl_ldb)
 296                 return -ENOMEM;
 297
 298         fsl_ldb->devdata = of_device_get_match_data(dev);
 299         if (!fsl_ldb->devdata)
 300                 return -EINVAL;
 301
 302         fsl_ldb->dev = &pdev->dev;
 303         fsl_ldb->bridge.funcs = &funcs;
 304         fsl_ldb->bridge.of_node = dev->of_node;
 305
 306         fsl_ldb->clk = devm_clk_get(dev, "ldb");
 307         if (IS_ERR(fsl_ldb->clk))
 308                 return PTR_ERR(fsl_ldb->clk);
 309
 310         fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent);
 311         if (IS_ERR(fsl_ldb->regmap))
 312                 return PTR_ERR(fsl_ldb->regmap);
 313
 314         /* Locate the panel DT node. */
 315         panel_node = of_graph_get_remote_node(dev->of_node, 1, 0);
 316         if (!panel_node)
 317                 return -ENXIO;
 318
 319         panel = of_drm_find_panel(panel_node);
 320         of_node_put(panel_node);
 321         if (IS_ERR(panel))
 322                 return PTR_ERR(panel);
 323
 324         fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
 325         if (IS_ERR(fsl_ldb->panel_bridge))
 326                 return PTR_ERR(fsl_ldb->panel_bridge);
 327
 328         /* Determine whether this is dual-link configuration */
 329         port1 = of_graph_get_port_by_id(dev->of_node, 1);
 330         port2 = of_graph_get_port_by_id(dev->of_node, 2);
 331         dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
 332         of_node_put(port1);
 333         of_node_put(port2);
 334
 335         if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
 336                 dev_err(dev, "LVDS channel pixel swap not supported.\n");
 337                 return -EINVAL;
 338         }
 339
 340         if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
 341                 fsl_ldb->lvds_dual_link = true;
 342
 343         platform_set_drvdata(pdev, fsl_ldb);
 344
 345         drm_bridge_add(&fsl_ldb->bridge);
 346
 347         return 0;
 348 }
 349
 350 static int fsl_ldb_remove(struct platform_device *pdev)
 351 {
 352         struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev);
 353
 354         drm_bridge_remove(&fsl_ldb->bridge);
 355
 356         return 0;
 357 }
 358
 359 static const struct of_device_id fsl_ldb_match[] = {
 360         { .compatible = "fsl,imx8mp-ldb",
 361           .data = &fsl_ldb_devdata[IMX8MP_LDB], },
 362         { .compatible = "fsl,imx93-ldb",
 363           .data = &fsl_ldb_devdata[IMX93_LDB], },
 364         { /* sentinel */ },
 365 };
 366 MODULE_DEVICE_TABLE(of, fsl_ldb_match);
 367
 368 static struct platform_driver fsl_ldb_driver = {
 369         .probe  = fsl_ldb_probe,
 370         .remove = fsl_ldb_remove,
 371         .driver         = {
 372                 .name           = "fsl-ldb",
 373                 .of_match_table = fsl_ldb_match,
 374         },
 375 };
 376 module_platform_driver(fsl_ldb_driver);
 377
 378 MODULE_AUTHOR("Marek Vasut <[email protected]>");
 379 MODULE_DESCRIPTION("Freescale i.MX8MP LDB");
 380 MODULE_LICENSE("GPL");