drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/drm_cache.h>
  29 #include "amdgpu.h"
  30 #include "cikd.h"
  31 #include "cik.h"
  32 #include "gmc_v7_0.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_amdkfd.h"
  35 #include "amdgpu_gem.h"
  36
  37 #include "bif/bif_4_1_d.h"
  38 #include "bif/bif_4_1_sh_mask.h"
  39
  40 #include "gmc/gmc_7_1_d.h"
  41 #include "gmc/gmc_7_1_sh_mask.h"
  42
  43 #include "oss/oss_2_0_d.h"
  44 #include "oss/oss_2_0_sh_mask.h"
  45
  46 #include "dce/dce_8_0_d.h"
  47 #include "dce/dce_8_0_sh_mask.h"
  48
  49 #include "amdgpu_atombios.h"
  50
  51 #include "ivsrcid/ivsrcid_vislands30.h"
  52
  53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
  54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static int gmc_v7_0_wait_for_idle(void *handle);
  56
  57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
  58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
  59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  60
  61 static const u32 golden_settings_iceland_a11[] =
  62 {
  63         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  66         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  67 };
  68
  69 static const u32 iceland_mgcg_cgcg_init[] =
  70 {
  71         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  72 };
  73
  74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  75 {
  76         switch (adev->asic_type) {
  77         case CHIP_TOPAZ:
  78                 amdgpu_device_program_register_sequence(adev,
  79                                                         iceland_mgcg_cgcg_init,
  80                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
  81                 amdgpu_device_program_register_sequence(adev,
  82                                                         golden_settings_iceland_a11,
  83                                                         ARRAY_SIZE(golden_settings_iceland_a11));
  84                 break;
  85         default:
  86                 break;
  87         }
  88 }
  89
  90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
  91 {
  92         u32 blackout;
  93
  94         gmc_v7_0_wait_for_idle((void *)adev);
  95
  96         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  97         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  98                 /* Block CPU access */
  99                 WREG32(mmBIF_FB_EN, 0);
 100                 /* blackout the MC */
 101                 blackout = REG_SET_FIELD(blackout,
 102                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 103                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 104         }
 105         /* wait for the MC to settle */
 106         udelay(100);
 107 }
 108
 109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
 110 {
 111         u32 tmp;
 112
 113         /* unblackout the MC */
 114         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 115         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 116         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 117         /* allow CPU access */
 118         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 119         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 120         WREG32(mmBIF_FB_EN, tmp);
 121 }
 122
 123 /**
 124  * gmc_v7_0_init_microcode - load ucode images from disk
 125  *
 126  * @adev: amdgpu_device pointer
 127  *
 128  * Use the firmware interface to load the ucode images into
 129  * the driver (not loaded into hw).
 130  * Returns 0 on success, error on failure.
 131  */
 132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 133 {
 134         const char *chip_name;
 135         char fw_name[30];
 136         int err;
 137
 138         DRM_DEBUG("\n");
 139
 140         switch (adev->asic_type) {
 141         case CHIP_BONAIRE:
 142                 chip_name = "bonaire";
 143                 break;
 144         case CHIP_HAWAII:
 145                 chip_name = "hawaii";
 146                 break;
 147         case CHIP_TOPAZ:
 148                 chip_name = "topaz";
 149                 break;
 150         case CHIP_KAVERI:
 151         case CHIP_KABINI:
 152         case CHIP_MULLINS:
 153                 return 0;
 154         default: BUG();
 155         }
 156
 157         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 158
 159         err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name);
 160         if (err) {
 161                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 162                 amdgpu_ucode_release(&adev->gmc.fw);
 163         }
 164         return err;
 165 }
 166
 167 /**
 168  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 169  *
 170  * @adev: amdgpu_device pointer
 171  *
 172  * Load the GDDR MC ucode into the hw (CIK).
 173  * Returns 0 on success, error on failure.
 174  */
 175 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 176 {
 177         const struct mc_firmware_header_v1_0 *hdr;
 178         const __le32 *fw_data = NULL;
 179         const __le32 *io_mc_regs = NULL;
 180         u32 running;
 181         int i, ucode_size, regs_size;
 182
 183         if (!adev->gmc.fw)
 184                 return -EINVAL;
 185
 186         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 187         amdgpu_ucode_print_mc_hdr(&hdr->header);
 188
 189         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 190         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 191         io_mc_regs = (const __le32 *)
 192                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 193         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 194         fw_data = (const __le32 *)
 195                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 196
 197         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 198
 199         if (running == 0) {
 200                 /* reset the engine and set to writable */
 201                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 202                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 203
 204                 /* load mc io regs */
 205                 for (i = 0; i < regs_size; i++) {
 206                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 207                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 208                 }
 209                 /* load the MC ucode */
 210                 for (i = 0; i < ucode_size; i++)
 211                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 212
 213                 /* put the engine back into the active state */
 214                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 215                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 216                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 217
 218                 /* wait for training to complete */
 219                 for (i = 0; i < adev->usec_timeout; i++) {
 220                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 221                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 222                                 break;
 223                         udelay(1);
 224                 }
 225                 for (i = 0; i < adev->usec_timeout; i++) {
 226                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 227                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 228                                 break;
 229                         udelay(1);
 230                 }
 231         }
 232
 233         return 0;
 234 }
 235
 236 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 237                                        struct amdgpu_gmc *mc)
 238 {
 239         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 240         base <<= 24;
 241
 242         amdgpu_gmc_vram_location(adev, mc, base);
 243         amdgpu_gmc_gart_location(adev, mc);
 244 }
 245
 246 /**
 247  * gmc_v7_0_mc_program - program the GPU memory controller
 248  *
 249  * @adev: amdgpu_device pointer
 250  *
 251  * Set the location of vram, gart, and AGP in the GPU's
 252  * physical address space (CIK).
 253  */
 254 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 255 {
 256         u32 tmp;
 257         int i, j;
 258
 259         /* Initialize HDP */
 260         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 261                 WREG32((0xb05 + j), 0x00000000);
 262                 WREG32((0xb06 + j), 0x00000000);
 263                 WREG32((0xb07 + j), 0x00000000);
 264                 WREG32((0xb08 + j), 0x00000000);
 265                 WREG32((0xb09 + j), 0x00000000);
 266         }
 267         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 268
 269         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 270                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 271         }
 272         if (adev->mode_info.num_crtc) {
 273                 /* Lockout access through VGA aperture*/
 274                 tmp = RREG32(mmVGA_HDP_CONTROL);
 275                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 276                 WREG32(mmVGA_HDP_CONTROL, tmp);
 277
 278                 /* disable VGA render */
 279                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 280                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 281                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 282         }
 283         /* Update configuration */
 284         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 285                adev->gmc.vram_start >> 12);
 286         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 287                adev->gmc.vram_end >> 12);
 288         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 289                adev->mem_scratch.gpu_addr >> 12);
 290         WREG32(mmMC_VM_AGP_BASE, 0);
 291         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 292         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 293         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 294                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 295         }
 296
 297         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 298
 299         tmp = RREG32(mmHDP_MISC_CNTL);
 300         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 301         WREG32(mmHDP_MISC_CNTL, tmp);
 302
 303         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 304         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 305 }
 306
 307 /**
 308  * gmc_v7_0_mc_init - initialize the memory controller driver params
 309  *
 310  * @adev: amdgpu_device pointer
 311  *
 312  * Look up the amount of vram, vram width, and decide how to place
 313  * vram and gart within the GPU's physical address space (CIK).
 314  * Returns 0 for success.
 315  */
 316 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 317 {
 318         int r;
 319
 320         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 321         if (!adev->gmc.vram_width) {
 322                 u32 tmp;
 323                 int chansize, numchan;
 324
 325                 /* Get VRAM informations */
 326                 tmp = RREG32(mmMC_ARB_RAMCFG);
 327                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 328                         chansize = 64;
 329                 } else {
 330                         chansize = 32;
 331                 }
 332                 tmp = RREG32(mmMC_SHARED_CHMAP);
 333                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 334                 case 0:
 335                 default:
 336                         numchan = 1;
 337                         break;
 338                 case 1:
 339                         numchan = 2;
 340                         break;
 341                 case 2:
 342                         numchan = 4;
 343                         break;
 344                 case 3:
 345                         numchan = 8;
 346                         break;
 347                 case 4:
 348                         numchan = 3;
 349                         break;
 350                 case 5:
 351                         numchan = 6;
 352                         break;
 353                 case 6:
 354                         numchan = 10;
 355                         break;
 356                 case 7:
 357                         numchan = 12;
 358                         break;
 359                 case 8:
 360                         numchan = 16;
 361                         break;
 362                 }
 363                 adev->gmc.vram_width = numchan * chansize;
 364         }
 365         /* size in MB on si */
 366         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 367         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 368
 369         if (!(adev->flags & AMD_IS_APU)) {
 370                 r = amdgpu_device_resize_fb_bar(adev);
 371                 if (r)
 372                         return r;
 373         }
 374         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 375         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 376
 377 #ifdef CONFIG_X86_64
 378         if ((adev->flags & AMD_IS_APU) &&
 379             adev->gmc.real_vram_size > adev->gmc.aper_size &&
 380             !amdgpu_passthrough(adev)) {
 381                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 382                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 383         }
 384 #endif
 385
 386         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 387
 388         /* set the gart size */
 389         if (amdgpu_gart_size == -1) {
 390                 switch (adev->asic_type) {
 391                 case CHIP_TOPAZ:     /* no MM engines */
 392                 default:
 393                         adev->gmc.gart_size = 256ULL << 20;
 394                         break;
 395 #ifdef CONFIG_DRM_AMDGPU_CIK
 396                 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
 397                 case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
 398                 case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
 399                 case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
 400                 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
 401                         adev->gmc.gart_size = 1024ULL << 20;
 402                         break;
 403 #endif
 404                 }
 405         } else {
 406                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 407         }
 408
 409         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
 410         gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
 411
 412         return 0;
 413 }
 414
 415 /**
 416  * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
 417  *
 418  * @adev: amdgpu_device pointer
 419  * @pasid: pasid to be flush
 420  * @flush_type: type of flush
 421  * @all_hub: flush all hubs
 422  *
 423  * Flush the TLB for the requested pasid.
 424  */
 425 static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 426                                         uint16_t pasid, uint32_t flush_type,
 427                                         bool all_hub)
 428 {
 429         int vmid;
 430         unsigned int tmp;
 431
 432         if (amdgpu_in_reset(adev))
 433                 return -EIO;
 434
 435         for (vmid = 1; vmid < 16; vmid++) {
 436
 437                 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 438                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 439                         (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
 440                         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 441                         RREG32(mmVM_INVALIDATE_RESPONSE);
 442                         break;
 443                 }
 444         }
 445
 446         return 0;
 447 }
 448
 449 /*
 450  * GART
 451  * VMID 0 is the physical GPU addresses as used by the kernel.
 452  * VMIDs 1-15 are used for userspace clients and are handled
 453  * by the amdgpu vm/hsa code.
 454  */
 455
 456 /**
 457  * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
 458  *
 459  * @adev: amdgpu_device pointer
 460  * @vmid: vm instance to flush
 461  * @vmhub: which hub to flush
 462  * @flush_type: type of flush
 463  * *
 464  * Flush the TLB for the requested page table (CIK).
 465  */
 466 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 467                                         uint32_t vmhub, uint32_t flush_type)
 468 {
 469         /* bits 0-15 are the VM contexts0-15 */
 470         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 471 }
 472
 473 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 474                                             unsigned vmid, uint64_t pd_addr)
 475 {
 476         uint32_t reg;
 477
 478         if (vmid < 8)
 479                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 480         else
 481                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 482         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 483
 484         /* bits 0-15 are the VM contexts0-15 */
 485         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 486
 487         return pd_addr;
 488 }
 489
 490 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 491                                         unsigned pasid)
 492 {
 493         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 494 }
 495
 496 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
 497                                 uint64_t *addr, uint64_t *flags)
 498 {
 499         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 500 }
 501
 502 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
 503                                 struct amdgpu_bo_va_mapping *mapping,
 504                                 uint64_t *flags)
 505 {
 506         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 507         *flags &= ~AMDGPU_PTE_PRT;
 508 }
 509
 510 /**
 511  * gmc_v7_0_set_fault_enable_default - update VM fault handling
 512  *
 513  * @adev: amdgpu_device pointer
 514  * @value: true redirects VM faults to the default page
 515  */
 516 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 517                                               bool value)
 518 {
 519         u32 tmp;
 520
 521         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 522         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 523                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 524         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 525                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 526         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 527                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 528         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 529                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 530         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 531                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 532         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 533                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 534         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 535 }
 536
 537 /**
 538  * gmc_v7_0_set_prt - set PRT VM fault
 539  *
 540  * @adev: amdgpu_device pointer
 541  * @enable: enable/disable VM fault handling for PRT
 542  */
 543 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 544 {
 545         uint32_t tmp;
 546
 547         if (enable && !adev->gmc.prt_warning) {
 548                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 549                 adev->gmc.prt_warning = true;
 550         }
 551
 552         tmp = RREG32(mmVM_PRT_CNTL);
 553         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 554                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 555         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 556                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 557         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 558                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 559         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 560                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 561         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 562                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 563         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 564                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 565         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 566                             MASK_PDE0_FAULT, enable);
 567         WREG32(mmVM_PRT_CNTL, tmp);
 568
 569         if (enable) {
 570                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 571                 uint32_t high = adev->vm_manager.max_pfn -
 572                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 573
 574                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 575                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 576                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 577                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 578                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 579                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 580                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 581                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 582         } else {
 583                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 584                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 585                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 586                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 587                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 588                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 589                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 590                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 591         }
 592 }
 593
 594 /**
 595  * gmc_v7_0_gart_enable - gart enable
 596  *
 597  * @adev: amdgpu_device pointer
 598  *
 599  * This sets up the TLBs, programs the page tables for VMID0,
 600  * sets up the hw for VMIDs 1-15 which are allocated on
 601  * demand, and sets up the global locations for the LDS, GDS,
 602  * and GPUVM for FSA64 clients (CIK).
 603  * Returns 0 for success, errors for failure.
 604  */
 605 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 606 {
 607         uint64_t table_addr;
 608         u32 tmp, field;
 609         int i;
 610
 611         if (adev->gart.bo == NULL) {
 612                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 613                 return -EINVAL;
 614         }
 615         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 616         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 617
 618         /* Setup TLB control */
 619         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 620         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 621         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 622         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 623         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 624         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 625         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 626         /* Setup L2 cache */
 627         tmp = RREG32(mmVM_L2_CNTL);
 628         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 629         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 630         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 631         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 632         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 633         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 634         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 635         WREG32(mmVM_L2_CNTL, tmp);
 636         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 637         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 638         WREG32(mmVM_L2_CNTL2, tmp);
 639
 640         field = adev->vm_manager.fragment_size;
 641         tmp = RREG32(mmVM_L2_CNTL3);
 642         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 643         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 644         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 645         WREG32(mmVM_L2_CNTL3, tmp);
 646         /* setup context0 */
 647         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 648         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 649         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 650         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 651                         (u32)(adev->dummy_page_addr >> 12));
 652         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 653         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 654         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 655         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 656         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 657         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 658
 659         WREG32(0x575, 0);
 660         WREG32(0x576, 0);
 661         WREG32(0x577, 0);
 662
 663         /* empty context1-15 */
 664         /* FIXME start with 4G, once using 2 level pt switch to full
 665          * vm size space
 666          */
 667         /* set vm size, must be a multiple of 4 */
 668         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 669         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 670         for (i = 1; i < AMDGPU_NUM_VMID; i++) {
 671                 if (i < 8)
 672                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 673                                table_addr >> 12);
 674                 else
 675                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 676                                table_addr >> 12);
 677         }
 678
 679         /* enable context1-15 */
 680         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 681                (u32)(adev->dummy_page_addr >> 12));
 682         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 683         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 684         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 685         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 686         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 687                             adev->vm_manager.block_size - 9);
 688         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 689         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 690                 gmc_v7_0_set_fault_enable_default(adev, false);
 691         else
 692                 gmc_v7_0_set_fault_enable_default(adev, true);
 693
 694         if (adev->asic_type == CHIP_KAVERI) {
 695                 tmp = RREG32(mmCHUB_CONTROL);
 696                 tmp &= ~BYPASS_VM;
 697                 WREG32(mmCHUB_CONTROL, tmp);
 698         }
 699
 700         gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
 701         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 702                  (unsigned)(adev->gmc.gart_size >> 20),
 703                  (unsigned long long)table_addr);
 704         return 0;
 705 }
 706
 707 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 708 {
 709         int r;
 710
 711         if (adev->gart.bo) {
 712                 WARN(1, "R600 PCIE GART already initialized\n");
 713                 return 0;
 714         }
 715         /* Initialize common gart structure */
 716         r = amdgpu_gart_init(adev);
 717         if (r)
 718                 return r;
 719         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 720         adev->gart.gart_pte_flags = 0;
 721         return amdgpu_gart_table_vram_alloc(adev);
 722 }
 723
 724 /**
 725  * gmc_v7_0_gart_disable - gart disable
 726  *
 727  * @adev: amdgpu_device pointer
 728  *
 729  * This disables all VM page table (CIK).
 730  */
 731 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 732 {
 733         u32 tmp;
 734
 735         /* Disable all tables */
 736         WREG32(mmVM_CONTEXT0_CNTL, 0);
 737         WREG32(mmVM_CONTEXT1_CNTL, 0);
 738         /* Setup TLB control */
 739         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 740         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 741         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 742         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 743         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 744         /* Setup L2 cache */
 745         tmp = RREG32(mmVM_L2_CNTL);
 746         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 747         WREG32(mmVM_L2_CNTL, tmp);
 748         WREG32(mmVM_L2_CNTL2, 0);
 749 }
 750
 751 /**
 752  * gmc_v7_0_vm_decode_fault - print human readable fault info
 753  *
 754  * @adev: amdgpu_device pointer
 755  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 756  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 757  * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
 758  * @pasid: debug logging only - no functional use
 759  *
 760  * Print human readable fault information (CIK).
 761  */
 762 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
 763                                      u32 addr, u32 mc_client, unsigned pasid)
 764 {
 765         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 766         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 767                                         PROTECTIONS);
 768         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 769                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 770         u32 mc_id;
 771
 772         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 773                               MEMORY_CLIENT_ID);
 774
 775         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 776                protections, vmid, pasid, addr,
 777                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 778                              MEMORY_CLIENT_RW) ?
 779                "write" : "read", block, mc_client, mc_id);
 780 }
 781
 782
 783 static const u32 mc_cg_registers[] = {
 784         mmMC_HUB_MISC_HUB_CG,
 785         mmMC_HUB_MISC_SIP_CG,
 786         mmMC_HUB_MISC_VM_CG,
 787         mmMC_XPB_CLK_GAT,
 788         mmATC_MISC_CG,
 789         mmMC_CITF_MISC_WR_CG,
 790         mmMC_CITF_MISC_RD_CG,
 791         mmMC_CITF_MISC_VM_CG,
 792         mmVM_L2_CG,
 793 };
 794
 795 static const u32 mc_cg_ls_en[] = {
 796         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 797         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 798         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 799         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 800         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 801         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 802         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 803         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 804         VM_L2_CG__MEM_LS_ENABLE_MASK,
 805 };
 806
 807 static const u32 mc_cg_en[] = {
 808         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 809         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 810         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 811         MC_XPB_CLK_GAT__ENABLE_MASK,
 812         ATC_MISC_CG__ENABLE_MASK,
 813         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 814         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 815         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 816         VM_L2_CG__ENABLE_MASK,
 817 };
 818
 819 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 820                                   bool enable)
 821 {
 822         int i;
 823         u32 orig, data;
 824
 825         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 826                 orig = data = RREG32(mc_cg_registers[i]);
 827                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 828                         data |= mc_cg_ls_en[i];
 829                 else
 830                         data &= ~mc_cg_ls_en[i];
 831                 if (data != orig)
 832                         WREG32(mc_cg_registers[i], data);
 833         }
 834 }
 835
 836 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 837                                     bool enable)
 838 {
 839         int i;
 840         u32 orig, data;
 841
 842         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 843                 orig = data = RREG32(mc_cg_registers[i]);
 844                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 845                         data |= mc_cg_en[i];
 846                 else
 847                         data &= ~mc_cg_en[i];
 848                 if (data != orig)
 849                         WREG32(mc_cg_registers[i], data);
 850         }
 851 }
 852
 853 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 854                                      bool enable)
 855 {
 856         u32 orig, data;
 857
 858         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 859
 860         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 861                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 862                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 863                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 864                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 865         } else {
 866                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 867                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 868                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 869                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 870         }
 871
 872         if (orig != data)
 873                 WREG32_PCIE(ixPCIE_CNTL2, data);
 874 }
 875
 876 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 877                                      bool enable)
 878 {
 879         u32 orig, data;
 880
 881         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 882
 883         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 884                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 885         else
 886                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 887
 888         if (orig != data)
 889                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 890 }
 891
 892 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 893                                    bool enable)
 894 {
 895         u32 orig, data;
 896
 897         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 898
 899         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 900                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 901         else
 902                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 903
 904         if (orig != data)
 905                 WREG32(mmHDP_MEM_POWER_LS, data);
 906 }
 907
 908 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 909 {
 910         switch (mc_seq_vram_type) {
 911         case MC_SEQ_MISC0__MT__GDDR1:
 912                 return AMDGPU_VRAM_TYPE_GDDR1;
 913         case MC_SEQ_MISC0__MT__DDR2:
 914                 return AMDGPU_VRAM_TYPE_DDR2;
 915         case MC_SEQ_MISC0__MT__GDDR3:
 916                 return AMDGPU_VRAM_TYPE_GDDR3;
 917         case MC_SEQ_MISC0__MT__GDDR4:
 918                 return AMDGPU_VRAM_TYPE_GDDR4;
 919         case MC_SEQ_MISC0__MT__GDDR5:
 920                 return AMDGPU_VRAM_TYPE_GDDR5;
 921         case MC_SEQ_MISC0__MT__HBM:
 922                 return AMDGPU_VRAM_TYPE_HBM;
 923         case MC_SEQ_MISC0__MT__DDR3:
 924                 return AMDGPU_VRAM_TYPE_DDR3;
 925         default:
 926                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 927         }
 928 }
 929
 930 static int gmc_v7_0_early_init(void *handle)
 931 {
 932         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 933
 934         gmc_v7_0_set_gmc_funcs(adev);
 935         gmc_v7_0_set_irq_funcs(adev);
 936
 937         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 938         adev->gmc.shared_aperture_end =
 939                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 940         adev->gmc.private_aperture_start =
 941                 adev->gmc.shared_aperture_end + 1;
 942         adev->gmc.private_aperture_end =
 943                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 944
 945         return 0;
 946 }
 947
 948 static int gmc_v7_0_late_init(void *handle)
 949 {
 950         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 951
 952         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 953                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 954         else
 955                 return 0;
 956 }
 957
 958 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
 959 {
 960         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
 961         unsigned size;
 962
 963         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 964                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
 965         } else {
 966                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
 967                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 968                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 969                         4);
 970         }
 971
 972         return size;
 973 }
 974
 975 static int gmc_v7_0_sw_init(void *handle)
 976 {
 977         int r;
 978         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 979
 980         adev->num_vmhubs = 1;
 981
 982         if (adev->flags & AMD_IS_APU) {
 983                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 984         } else {
 985                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 986                 tmp &= MC_SEQ_MISC0__MT__MASK;
 987                 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 988         }
 989
 990         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
 991         if (r)
 992                 return r;
 993
 994         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
 995         if (r)
 996                 return r;
 997
 998         /* Adjust VM size here.
 999          * Currently set to 4GB ((1 << 20) 4k pages).
1000          * Max GPUVM size for cayman and SI is 40 bits.
1001          */
1002         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1003
1004         /* Set the internal MC address mask
1005          * This is the max address of the GPU's
1006          * internal address space.
1007          */
1008         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1009
1010         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1011         if (r) {
1012                 pr_warn("No suitable DMA available\n");
1013                 return r;
1014         }
1015         adev->need_swiotlb = drm_need_swiotlb(40);
1016
1017         r = gmc_v7_0_init_microcode(adev);
1018         if (r) {
1019                 DRM_ERROR("Failed to load mc firmware!\n");
1020                 return r;
1021         }
1022
1023         r = gmc_v7_0_mc_init(adev);
1024         if (r)
1025                 return r;
1026
1027         amdgpu_gmc_get_vbios_allocations(adev);
1028
1029         /* Memory manager */
1030         r = amdgpu_bo_init(adev);
1031         if (r)
1032                 return r;
1033
1034         r = gmc_v7_0_gart_init(adev);
1035         if (r)
1036                 return r;
1037
1038         /*
1039          * number of VMs
1040          * VMID 0 is reserved for System
1041          * amdgpu graphics/compute will use VMIDs 1-7
1042          * amdkfd will use VMIDs 8-15
1043          */
1044         adev->vm_manager.first_kfd_vmid = 8;
1045         amdgpu_vm_manager_init(adev);
1046
1047         /* base offset of vram pages */
1048         if (adev->flags & AMD_IS_APU) {
1049                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1050
1051                 tmp <<= 22;
1052                 adev->vm_manager.vram_base_offset = tmp;
1053         } else {
1054                 adev->vm_manager.vram_base_offset = 0;
1055         }
1056
1057         adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1058                                         GFP_KERNEL);
1059         if (!adev->gmc.vm_fault_info)
1060                 return -ENOMEM;
1061         atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1062
1063         return 0;
1064 }
1065
1066 static int gmc_v7_0_sw_fini(void *handle)
1067 {
1068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069
1070         amdgpu_gem_force_release(adev);
1071         amdgpu_vm_manager_fini(adev);
1072         kfree(adev->gmc.vm_fault_info);
1073         amdgpu_gart_table_vram_free(adev);
1074         amdgpu_bo_fini(adev);
1075         amdgpu_ucode_release(&adev->gmc.fw);
1076
1077         return 0;
1078 }
1079
1080 static int gmc_v7_0_hw_init(void *handle)
1081 {
1082         int r;
1083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084
1085         gmc_v7_0_init_golden_registers(adev);
1086
1087         gmc_v7_0_mc_program(adev);
1088
1089         if (!(adev->flags & AMD_IS_APU)) {
1090                 r = gmc_v7_0_mc_load_microcode(adev);
1091                 if (r) {
1092                         DRM_ERROR("Failed to load MC firmware!\n");
1093                         return r;
1094                 }
1095         }
1096
1097         r = gmc_v7_0_gart_enable(adev);
1098         if (r)
1099                 return r;
1100
1101         if (amdgpu_emu_mode == 1)
1102                 return amdgpu_gmc_vram_checking(adev);
1103         else
1104                 return r;
1105 }
1106
1107 static int gmc_v7_0_hw_fini(void *handle)
1108 {
1109         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1110
1111         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1112         gmc_v7_0_gart_disable(adev);
1113
1114         return 0;
1115 }
1116
1117 static int gmc_v7_0_suspend(void *handle)
1118 {
1119         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120
1121         gmc_v7_0_hw_fini(adev);
1122
1123         return 0;
1124 }
1125
1126 static int gmc_v7_0_resume(void *handle)
1127 {
1128         int r;
1129         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1130
1131         r = gmc_v7_0_hw_init(adev);
1132         if (r)
1133                 return r;
1134
1135         amdgpu_vmid_reset_all(adev);
1136
1137         return 0;
1138 }
1139
1140 static bool gmc_v7_0_is_idle(void *handle)
1141 {
1142         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1143         u32 tmp = RREG32(mmSRBM_STATUS);
1144
1145         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1146                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1147                 return false;
1148
1149         return true;
1150 }
1151
1152 static int gmc_v7_0_wait_for_idle(void *handle)
1153 {
1154         unsigned i;
1155         u32 tmp;
1156         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1157
1158         for (i = 0; i < adev->usec_timeout; i++) {
1159                 /* read MC_STATUS */
1160                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1161                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1162                                                SRBM_STATUS__MCC_BUSY_MASK |
1163                                                SRBM_STATUS__MCD_BUSY_MASK |
1164                                                SRBM_STATUS__VMC_BUSY_MASK);
1165                 if (!tmp)
1166                         return 0;
1167                 udelay(1);
1168         }
1169         return -ETIMEDOUT;
1170
1171 }
1172
1173 static int gmc_v7_0_soft_reset(void *handle)
1174 {
1175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1176         u32 srbm_soft_reset = 0;
1177         u32 tmp = RREG32(mmSRBM_STATUS);
1178
1179         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1180                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1181                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1182
1183         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1184                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1185                 if (!(adev->flags & AMD_IS_APU))
1186                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1187                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1188         }
1189
1190         if (srbm_soft_reset) {
1191                 gmc_v7_0_mc_stop(adev);
1192                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1193                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1194                 }
1195
1196
1197                 tmp = RREG32(mmSRBM_SOFT_RESET);
1198                 tmp |= srbm_soft_reset;
1199                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1200                 WREG32(mmSRBM_SOFT_RESET, tmp);
1201                 tmp = RREG32(mmSRBM_SOFT_RESET);
1202
1203                 udelay(50);
1204
1205                 tmp &= ~srbm_soft_reset;
1206                 WREG32(mmSRBM_SOFT_RESET, tmp);
1207                 tmp = RREG32(mmSRBM_SOFT_RESET);
1208
1209                 /* Wait a little for things to settle down */
1210                 udelay(50);
1211
1212                 gmc_v7_0_mc_resume(adev);
1213                 udelay(50);
1214         }
1215
1216         return 0;
1217 }
1218
1219 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1220                                              struct amdgpu_irq_src *src,
1221                                              unsigned type,
1222                                              enum amdgpu_interrupt_state state)
1223 {
1224         u32 tmp;
1225         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1226                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1227                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1228                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1229                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1230                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1231
1232         switch (state) {
1233         case AMDGPU_IRQ_STATE_DISABLE:
1234                 /* system context */
1235                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1236                 tmp &= ~bits;
1237                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1238                 /* VMs */
1239                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1240                 tmp &= ~bits;
1241                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1242                 break;
1243         case AMDGPU_IRQ_STATE_ENABLE:
1244                 /* system context */
1245                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1246                 tmp |= bits;
1247                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1248                 /* VMs */
1249                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1250                 tmp |= bits;
1251                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1252                 break;
1253         default:
1254                 break;
1255         }
1256
1257         return 0;
1258 }
1259
1260 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1261                                       struct amdgpu_irq_src *source,
1262                                       struct amdgpu_iv_entry *entry)
1263 {
1264         u32 addr, status, mc_client, vmid;
1265
1266         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1267         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1268         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1269         /* reset addr and status */
1270         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1271
1272         if (!addr && !status)
1273                 return 0;
1274
1275         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1276                 gmc_v7_0_set_fault_enable_default(adev, false);
1277
1278         if (printk_ratelimit()) {
1279                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1280                         entry->src_id, entry->src_data[0]);
1281                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1282                         addr);
1283                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1284                         status);
1285                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1286                                          entry->pasid);
1287         }
1288
1289         vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1290                              VMID);
1291         if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1292                 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1293                 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1294                 u32 protections = REG_GET_FIELD(status,
1295                                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1296                                         PROTECTIONS);
1297
1298                 info->vmid = vmid;
1299                 info->mc_id = REG_GET_FIELD(status,
1300                                             VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1301                                             MEMORY_CLIENT_ID);
1302                 info->status = status;
1303                 info->page_addr = addr;
1304                 info->prot_valid = protections & 0x7 ? true : false;
1305                 info->prot_read = protections & 0x8 ? true : false;
1306                 info->prot_write = protections & 0x10 ? true : false;
1307                 info->prot_exec = protections & 0x20 ? true : false;
1308                 mb();
1309                 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1310         }
1311
1312         return 0;
1313 }
1314
1315 static int gmc_v7_0_set_clockgating_state(void *handle,
1316                                           enum amd_clockgating_state state)
1317 {
1318         bool gate = false;
1319         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320
1321         if (state == AMD_CG_STATE_GATE)
1322                 gate = true;
1323
1324         if (!(adev->flags & AMD_IS_APU)) {
1325                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1326                 gmc_v7_0_enable_mc_ls(adev, gate);
1327         }
1328         gmc_v7_0_enable_bif_mgls(adev, gate);
1329         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1330         gmc_v7_0_enable_hdp_ls(adev, gate);
1331
1332         return 0;
1333 }
1334
1335 static int gmc_v7_0_set_powergating_state(void *handle,
1336                                           enum amd_powergating_state state)
1337 {
1338         return 0;
1339 }
1340
1341 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1342         .name = "gmc_v7_0",
1343         .early_init = gmc_v7_0_early_init,
1344         .late_init = gmc_v7_0_late_init,
1345         .sw_init = gmc_v7_0_sw_init,
1346         .sw_fini = gmc_v7_0_sw_fini,
1347         .hw_init = gmc_v7_0_hw_init,
1348         .hw_fini = gmc_v7_0_hw_fini,
1349         .suspend = gmc_v7_0_suspend,
1350         .resume = gmc_v7_0_resume,
1351         .is_idle = gmc_v7_0_is_idle,
1352         .wait_for_idle = gmc_v7_0_wait_for_idle,
1353         .soft_reset = gmc_v7_0_soft_reset,
1354         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1355         .set_powergating_state = gmc_v7_0_set_powergating_state,
1356 };
1357
1358 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1359         .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1360         .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
1361         .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1362         .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1363         .set_prt = gmc_v7_0_set_prt,
1364         .get_vm_pde = gmc_v7_0_get_vm_pde,
1365         .get_vm_pte = gmc_v7_0_get_vm_pte,
1366         .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size,
1367 };
1368
1369 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1370         .set = gmc_v7_0_vm_fault_interrupt_state,
1371         .process = gmc_v7_0_process_interrupt,
1372 };
1373
1374 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1375 {
1376         adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1377 }
1378
1379 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1380 {
1381         adev->gmc.vm_fault.num_types = 1;
1382         adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1383 }
1384
1385 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1386 {
1387         .type = AMD_IP_BLOCK_TYPE_GMC,
1388         .major = 7,
1389         .minor = 0,
1390         .rev = 0,
1391         .funcs = &gmc_v7_0_ip_funcs,
1392 };
1393
1394 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1395 {
1396         .type = AMD_IP_BLOCK_TYPE_GMC,
1397         .major = 7,
1398         .minor = 4,
1399         .rev = 0,
1400         .funcs = &gmc_v7_0_ip_funcs,
1401 };