drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_sysfs_init(struct amdgpu_device *adev);
  49 static void psp_sysfs_fini(struct amdgpu_device *adev);
  50
  51 static int psp_load_smu_fw(struct psp_context *psp);
  52 static int psp_rap_terminate(struct psp_context *psp);
  53 static int psp_securedisplay_terminate(struct psp_context *psp);
  54
  55 static int psp_ring_init(struct psp_context *psp,
  56                          enum psp_ring_type ring_type)
  57 {
  58         int ret = 0;
  59         struct psp_ring *ring;
  60         struct amdgpu_device *adev = psp->adev;
  61
  62         ring = &psp->km_ring;
  63
  64         ring->ring_type = ring_type;
  65
  66         /* allocate 4k Page of Local Frame Buffer memory for ring */
  67         ring->ring_size = 0x1000;
  68         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  69                                       AMDGPU_GEM_DOMAIN_VRAM |
  70                                       AMDGPU_GEM_DOMAIN_GTT,
  71                                       &adev->firmware.rbuf,
  72                                       &ring->ring_mem_mc_addr,
  73                                       (void **)&ring->ring_mem);
  74         if (ret) {
  75                 ring->ring_size = 0;
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 /*
  83  * Due to DF Cstate management centralized to PMFW, the firmware
  84  * loading sequence will be updated as below:
  85  *   - Load KDB
  86  *   - Load SYS_DRV
  87  *   - Load tOS
  88  *   - Load PMFW
  89  *   - Setup TMR
  90  *   - Load other non-psp fw
  91  *   - Load ASD
  92  *   - Load XGMI/RAS/HDCP/DTM TA if any
  93  *
  94  * This new sequence is required for
  95  *   - Arcturus and onwards
  96  */
  97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  98 {
  99         struct amdgpu_device *adev = psp->adev;
 100
 101         if (amdgpu_sriov_vf(adev)) {
 102                 psp->pmfw_centralized_cstate_management = false;
 103                 return;
 104         }
 105
 106         switch (adev->ip_versions[MP0_HWIP][0]) {
 107         case IP_VERSION(11, 0, 0):
 108         case IP_VERSION(11, 0, 4):
 109         case IP_VERSION(11, 0, 5):
 110         case IP_VERSION(11, 0, 7):
 111         case IP_VERSION(11, 0, 9):
 112         case IP_VERSION(11, 0, 11):
 113         case IP_VERSION(11, 0, 12):
 114         case IP_VERSION(11, 0, 13):
 115         case IP_VERSION(13, 0, 0):
 116         case IP_VERSION(13, 0, 2):
 117         case IP_VERSION(13, 0, 7):
 118                 psp->pmfw_centralized_cstate_management = true;
 119                 break;
 120         default:
 121                 psp->pmfw_centralized_cstate_management = false;
 122                 break;
 123         }
 124 }
 125
 126 static int psp_init_sriov_microcode(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         char ucode_prefix[30];
 130         int ret = 0;
 131
 132         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 133
 134         switch (adev->ip_versions[MP0_HWIP][0]) {
 135         case IP_VERSION(9, 0, 0):
 136         case IP_VERSION(11, 0, 7):
 137         case IP_VERSION(11, 0, 9):
 138                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 139                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 140                 break;
 141         case IP_VERSION(13, 0, 2):
 142                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 143                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 144                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 145                 break;
 146         case IP_VERSION(13, 0, 0):
 147                 adev->virt.autoload_ucode_id = 0;
 148                 break;
 149         case IP_VERSION(13, 0, 10):
 150                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 151                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 152                 break;
 153         default:
 154                 return -EINVAL;
 155         }
 156         return ret;
 157 }
 158
 159 static int psp_early_init(void *handle)
 160 {
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162         struct psp_context *psp = &adev->psp;
 163
 164         switch (adev->ip_versions[MP0_HWIP][0]) {
 165         case IP_VERSION(9, 0, 0):
 166                 psp_v3_1_set_psp_funcs(psp);
 167                 psp->autoload_supported = false;
 168                 break;
 169         case IP_VERSION(10, 0, 0):
 170         case IP_VERSION(10, 0, 1):
 171                 psp_v10_0_set_psp_funcs(psp);
 172                 psp->autoload_supported = false;
 173                 break;
 174         case IP_VERSION(11, 0, 2):
 175         case IP_VERSION(11, 0, 4):
 176                 psp_v11_0_set_psp_funcs(psp);
 177                 psp->autoload_supported = false;
 178                 break;
 179         case IP_VERSION(11, 0, 0):
 180         case IP_VERSION(11, 0, 5):
 181         case IP_VERSION(11, 0, 9):
 182         case IP_VERSION(11, 0, 7):
 183         case IP_VERSION(11, 0, 11):
 184         case IP_VERSION(11, 5, 0):
 185         case IP_VERSION(11, 0, 12):
 186         case IP_VERSION(11, 0, 13):
 187                 psp_v11_0_set_psp_funcs(psp);
 188                 psp->autoload_supported = true;
 189                 break;
 190         case IP_VERSION(11, 0, 3):
 191         case IP_VERSION(12, 0, 1):
 192                 psp_v12_0_set_psp_funcs(psp);
 193                 break;
 194         case IP_VERSION(13, 0, 2):
 195         case IP_VERSION(13, 0, 6):
 196                 psp_v13_0_set_psp_funcs(psp);
 197                 break;
 198         case IP_VERSION(13, 0, 1):
 199         case IP_VERSION(13, 0, 3):
 200         case IP_VERSION(13, 0, 5):
 201         case IP_VERSION(13, 0, 8):
 202         case IP_VERSION(13, 0, 10):
 203         case IP_VERSION(13, 0, 11):
 204                 psp_v13_0_set_psp_funcs(psp);
 205                 psp->autoload_supported = true;
 206                 break;
 207         case IP_VERSION(11, 0, 8):
 208                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 209                         psp_v11_0_8_set_psp_funcs(psp);
 210                         psp->autoload_supported = false;
 211                 }
 212                 break;
 213         case IP_VERSION(13, 0, 0):
 214         case IP_VERSION(13, 0, 7):
 215                 psp_v13_0_set_psp_funcs(psp);
 216                 psp->autoload_supported = true;
 217                 break;
 218         case IP_VERSION(13, 0, 4):
 219                 psp_v13_0_4_set_psp_funcs(psp);
 220                 psp->autoload_supported = true;
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225
 226         psp->adev = adev;
 227
 228         psp_check_pmfw_centralized_cstate_management(psp);
 229
 230         if (amdgpu_sriov_vf(adev))
 231                 return psp_init_sriov_microcode(psp);
 232         else
 233                 return psp_init_microcode(psp);
 234 }
 235
 236 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 237 {
 238         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 239                               &mem_ctx->shared_buf);
 240         mem_ctx->shared_bo = NULL;
 241 }
 242
 243 static void psp_free_shared_bufs(struct psp_context *psp)
 244 {
 245         void *tmr_buf;
 246         void **pptr;
 247
 248         /* free TMR memory buffer */
 249         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 250         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 251         psp->tmr_bo = NULL;
 252
 253         /* free xgmi shared memory */
 254         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 255
 256         /* free ras shared memory */
 257         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 258
 259         /* free hdcp shared memory */
 260         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 261
 262         /* free dtm shared memory */
 263         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 264
 265         /* free rap shared memory */
 266         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 267
 268         /* free securedisplay shared memory */
 269         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 270
 271
 272 }
 273
 274 static void psp_memory_training_fini(struct psp_context *psp)
 275 {
 276         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 277
 278         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 279         kfree(ctx->sys_cache);
 280         ctx->sys_cache = NULL;
 281 }
 282
 283 static int psp_memory_training_init(struct psp_context *psp)
 284 {
 285         int ret;
 286         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 287
 288         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 289                 DRM_DEBUG("memory training is not supported!\n");
 290                 return 0;
 291         }
 292
 293         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 294         if (ctx->sys_cache == NULL) {
 295                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 296                 ret = -ENOMEM;
 297                 goto Err_out;
 298         }
 299
 300         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 301                   ctx->train_data_size,
 302                   ctx->p2c_train_data_offset,
 303                   ctx->c2p_train_data_offset);
 304         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 305         return 0;
 306
 307 Err_out:
 308         psp_memory_training_fini(psp);
 309         return ret;
 310 }
 311
 312 /*
 313  * Helper funciton to query psp runtime database entry
 314  *
 315  * @adev: amdgpu_device pointer
 316  * @entry_type: the type of psp runtime database entry
 317  * @db_entry: runtime database entry pointer
 318  *
 319  * Return false if runtime database doesn't exit or entry is invalid
 320  * or true if the specific database entry is found, and copy to @db_entry
 321  */
 322 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 323                                      enum psp_runtime_entry_type entry_type,
 324                                      void *db_entry)
 325 {
 326         uint64_t db_header_pos, db_dir_pos;
 327         struct psp_runtime_data_header db_header = {0};
 328         struct psp_runtime_data_directory db_dir = {0};
 329         bool ret = false;
 330         int i;
 331
 332         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 333         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 334
 335         /* read runtime db header from vram */
 336         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 337                         sizeof(struct psp_runtime_data_header), false);
 338
 339         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 340                 /* runtime db doesn't exist, exit */
 341                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 342                 return false;
 343         }
 344
 345         /* read runtime database entry from vram */
 346         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 347                         sizeof(struct psp_runtime_data_directory), false);
 348
 349         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 350                 /* invalid db entry count, exit */
 351                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 352                 return false;
 353         }
 354
 355         /* look up for requested entry type */
 356         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 357                 if (db_dir.entry_list[i].entry_type == entry_type) {
 358                         switch (entry_type) {
 359                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 360                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 361                                         /* invalid db entry size */
 362                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 363                                         return false;
 364                                 }
 365                                 /* read runtime database entry */
 366                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 367                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 368                                 ret = true;
 369                                 break;
 370                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 371                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 372                                         /* invalid db entry size */
 373                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 374                                         return false;
 375                                 }
 376                                 /* read runtime database entry */
 377                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 378                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 379                                 ret = true;
 380                                 break;
 381                         default:
 382                                 ret = false;
 383                                 break;
 384                         }
 385                 }
 386         }
 387
 388         return ret;
 389 }
 390
 391 static int psp_sw_init(void *handle)
 392 {
 393         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 394         struct psp_context *psp = &adev->psp;
 395         int ret;
 396         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 397         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 398         struct psp_runtime_scpm_entry scpm_entry;
 399
 400         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 401         if (!psp->cmd) {
 402                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 403                 ret = -ENOMEM;
 404         }
 405
 406         adev->psp.xgmi_context.supports_extended_data =
 407                 !adev->gmc.xgmi.connected_to_cpu &&
 408                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 409
 410         memset(&scpm_entry, 0, sizeof(scpm_entry));
 411         if ((psp_get_runtime_db_entry(adev,
 412                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 413                                 &scpm_entry)) &&
 414             (SCPM_DISABLE != scpm_entry.scpm_status)) {
 415                 adev->scpm_enabled = true;
 416                 adev->scpm_status = scpm_entry.scpm_status;
 417         } else {
 418                 adev->scpm_enabled = false;
 419                 adev->scpm_status = SCPM_DISABLE;
 420         }
 421
 422         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 423
 424         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 425         if (psp_get_runtime_db_entry(adev,
 426                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 427                                 &boot_cfg_entry)) {
 428                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 429                 if ((psp->boot_cfg_bitmask) &
 430                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 431                         /* If psp runtime database exists, then
 432                          * only enable two stage memory training
 433                          * when TWO_STAGE_DRAM_TRAINING bit is set
 434                          * in runtime database */
 435                         mem_training_ctx->enable_mem_training = true;
 436                 }
 437
 438         } else {
 439                 /* If psp runtime database doesn't exist or
 440                  * is invalid, force enable two stage memory
 441                  * training */
 442                 mem_training_ctx->enable_mem_training = true;
 443         }
 444
 445         if (mem_training_ctx->enable_mem_training) {
 446                 ret = psp_memory_training_init(psp);
 447                 if (ret) {
 448                         DRM_ERROR("Failed to initialize memory training!\n");
 449                         return ret;
 450                 }
 451
 452                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 453                 if (ret) {
 454                         DRM_ERROR("Failed to process memory training!\n");
 455                         return ret;
 456                 }
 457         }
 458
 459         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 460             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 461                 ret= psp_sysfs_init(adev);
 462                 if (ret) {
 463                         return ret;
 464                 }
 465         }
 466
 467         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 468                                       amdgpu_sriov_vf(adev) ?
 469                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 470                                       &psp->fw_pri_bo,
 471                                       &psp->fw_pri_mc_addr,
 472                                       &psp->fw_pri_buf);
 473         if (ret)
 474                 return ret;
 475
 476         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 477                                       AMDGPU_GEM_DOMAIN_VRAM,
 478                                       &psp->fence_buf_bo,
 479                                       &psp->fence_buf_mc_addr,
 480                                       &psp->fence_buf);
 481         if (ret)
 482                 goto failed1;
 483
 484         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 485                                       AMDGPU_GEM_DOMAIN_VRAM,
 486                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 487                                       (void **)&psp->cmd_buf_mem);
 488         if (ret)
 489                 goto failed2;
 490
 491         return 0;
 492
 493 failed2:
 494         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 495                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 496 failed1:
 497         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 498                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 499         return ret;
 500 }
 501
 502 static int psp_sw_fini(void *handle)
 503 {
 504         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 505         struct psp_context *psp = &adev->psp;
 506         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 507
 508         psp_memory_training_fini(psp);
 509
 510         amdgpu_ucode_release(&psp->sos_fw);
 511         amdgpu_ucode_release(&psp->asd_fw);
 512         amdgpu_ucode_release(&psp->ta_fw);
 513         amdgpu_ucode_release(&psp->cap_fw);
 514         amdgpu_ucode_release(&psp->toc_fw);
 515
 516         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 517             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 518                 psp_sysfs_fini(adev);
 519
 520         kfree(cmd);
 521         cmd = NULL;
 522
 523         if (psp->km_ring.ring_mem)
 524                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 525                                       &psp->km_ring.ring_mem_mc_addr,
 526                                       (void **)&psp->km_ring.ring_mem);
 527
 528         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 529                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 530         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 531                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 532         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 533                               (void **)&psp->cmd_buf_mem);
 534
 535         return 0;
 536 }
 537
 538 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 539                  uint32_t reg_val, uint32_t mask, bool check_changed)
 540 {
 541         uint32_t val;
 542         int i;
 543         struct amdgpu_device *adev = psp->adev;
 544
 545         if (psp->adev->no_hw_access)
 546                 return 0;
 547
 548         for (i = 0; i < adev->usec_timeout; i++) {
 549                 val = RREG32(reg_index);
 550                 if (check_changed) {
 551                         if (val != reg_val)
 552                                 return 0;
 553                 } else {
 554                         if ((val & mask) == reg_val)
 555                                 return 0;
 556                 }
 557                 udelay(1);
 558         }
 559
 560         return -ETIME;
 561 }
 562
 563 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 564 {
 565         switch (cmd_id) {
 566         case GFX_CMD_ID_LOAD_TA:
 567                 return "LOAD_TA";
 568         case GFX_CMD_ID_UNLOAD_TA:
 569                 return "UNLOAD_TA";
 570         case GFX_CMD_ID_INVOKE_CMD:
 571                 return "INVOKE_CMD";
 572         case GFX_CMD_ID_LOAD_ASD:
 573                 return "LOAD_ASD";
 574         case GFX_CMD_ID_SETUP_TMR:
 575                 return "SETUP_TMR";
 576         case GFX_CMD_ID_LOAD_IP_FW:
 577                 return "LOAD_IP_FW";
 578         case GFX_CMD_ID_DESTROY_TMR:
 579                 return "DESTROY_TMR";
 580         case GFX_CMD_ID_SAVE_RESTORE:
 581                 return "SAVE_RESTORE_IP_FW";
 582         case GFX_CMD_ID_SETUP_VMR:
 583                 return "SETUP_VMR";
 584         case GFX_CMD_ID_DESTROY_VMR:
 585                 return "DESTROY_VMR";
 586         case GFX_CMD_ID_PROG_REG:
 587                 return "PROG_REG";
 588         case GFX_CMD_ID_GET_FW_ATTESTATION:
 589                 return "GET_FW_ATTESTATION";
 590         case GFX_CMD_ID_LOAD_TOC:
 591                 return "ID_LOAD_TOC";
 592         case GFX_CMD_ID_AUTOLOAD_RLC:
 593                 return "AUTOLOAD_RLC";
 594         case GFX_CMD_ID_BOOT_CFG:
 595                 return "BOOT_CFG";
 596         default:
 597                 return "UNKNOWN CMD";
 598         }
 599 }
 600
 601 static int
 602 psp_cmd_submit_buf(struct psp_context *psp,
 603                    struct amdgpu_firmware_info *ucode,
 604                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 605 {
 606         int ret;
 607         int index;
 608         int timeout = 20000;
 609         bool ras_intr = false;
 610         bool skip_unsupport = false;
 611
 612         if (psp->adev->no_hw_access)
 613                 return 0;
 614
 615         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 616
 617         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 618
 619         index = atomic_inc_return(&psp->fence_value);
 620         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 621         if (ret) {
 622                 atomic_dec(&psp->fence_value);
 623                 goto exit;
 624         }
 625
 626         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 627         while (*((unsigned int *)psp->fence_buf) != index) {
 628                 if (--timeout == 0)
 629                         break;
 630                 /*
 631                  * Shouldn't wait for timeout when err_event_athub occurs,
 632                  * because gpu reset thread triggered and lock resource should
 633                  * be released for psp resume sequence.
 634                  */
 635                 ras_intr = amdgpu_ras_intr_triggered();
 636                 if (ras_intr)
 637                         break;
 638                 usleep_range(10, 100);
 639                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 640         }
 641
 642         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 643         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 644                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 645
 646         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 647
 648         /* In some cases, psp response status is not 0 even there is no
 649          * problem while the command is submitted. Some version of PSP FW
 650          * doesn't write 0 to that field.
 651          * So here we would like to only print a warning instead of an error
 652          * during psp initialization to avoid breaking hw_init and it doesn't
 653          * return -EINVAL.
 654          */
 655         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 656                 if (ucode)
 657                         DRM_WARN("failed to load ucode %s(0x%X) ",
 658                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 659                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 660                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 661                          psp->cmd_buf_mem->resp.status);
 662                 /* If any firmware (including CAP) load fails under SRIOV, it should
 663                  * return failure to stop the VF from initializing.
 664                  * Also return failure in case of timeout
 665                  */
 666                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 667                         ret = -EINVAL;
 668                         goto exit;
 669                 }
 670         }
 671
 672         if (ucode) {
 673                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 674                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 675         }
 676
 677 exit:
 678         return ret;
 679 }
 680
 681 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 682 {
 683         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 684
 685         mutex_lock(&psp->mutex);
 686
 687         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 688
 689         return cmd;
 690 }
 691
 692 static void release_psp_cmd_buf(struct psp_context *psp)
 693 {
 694         mutex_unlock(&psp->mutex);
 695 }
 696
 697 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 698                                  struct psp_gfx_cmd_resp *cmd,
 699                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 700 {
 701         struct amdgpu_device *adev = psp->adev;
 702         uint32_t size = amdgpu_bo_size(tmr_bo);
 703         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 704
 705         if (amdgpu_sriov_vf(psp->adev))
 706                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 707         else
 708                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 709         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 710         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 711         cmd->cmd.cmd_setup_tmr.buf_size = size;
 712         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 713         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 714         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 715 }
 716
 717 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 718                                       uint64_t pri_buf_mc, uint32_t size)
 719 {
 720         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 721         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 722         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 723         cmd->cmd.cmd_load_toc.toc_size = size;
 724 }
 725
 726 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 727 static int psp_load_toc(struct psp_context *psp,
 728                         uint32_t *tmr_size)
 729 {
 730         int ret;
 731         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 732
 733         /* Copy toc to psp firmware private buffer */
 734         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 735
 736         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 737
 738         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 739                                  psp->fence_buf_mc_addr);
 740         if (!ret)
 741                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 742
 743         release_psp_cmd_buf(psp);
 744
 745         return ret;
 746 }
 747
 748 /* Set up Trusted Memory Region */
 749 static int psp_tmr_init(struct psp_context *psp)
 750 {
 751         int ret = 0;
 752         int tmr_size;
 753         void *tmr_buf;
 754         void **pptr;
 755
 756         /*
 757          * According to HW engineer, they prefer the TMR address be "naturally
 758          * aligned" , e.g. the start address be an integer divide of TMR size.
 759          *
 760          * Note: this memory need be reserved till the driver
 761          * uninitializes.
 762          */
 763         tmr_size = PSP_TMR_SIZE(psp->adev);
 764
 765         /* For ASICs support RLC autoload, psp will parse the toc
 766          * and calculate the total size of TMR needed */
 767         if (!amdgpu_sriov_vf(psp->adev) &&
 768             psp->toc.start_addr &&
 769             psp->toc.size_bytes &&
 770             psp->fw_pri_buf) {
 771                 ret = psp_load_toc(psp, &tmr_size);
 772                 if (ret) {
 773                         DRM_ERROR("Failed to load toc\n");
 774                         return ret;
 775                 }
 776         }
 777
 778         if (!psp->tmr_bo) {
 779                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 780                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 781                                               PSP_TMR_ALIGNMENT,
 782                                               AMDGPU_HAS_VRAM(psp->adev) ?
 783                                               AMDGPU_GEM_DOMAIN_VRAM :
 784                                               AMDGPU_GEM_DOMAIN_GTT,
 785                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 786                                               pptr);
 787         }
 788
 789         return ret;
 790 }
 791
 792 static bool psp_skip_tmr(struct psp_context *psp)
 793 {
 794         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 795         case IP_VERSION(11, 0, 9):
 796         case IP_VERSION(11, 0, 7):
 797         case IP_VERSION(13, 0, 2):
 798         case IP_VERSION(13, 0, 10):
 799                 return true;
 800         default:
 801                 return false;
 802         }
 803 }
 804
 805 static int psp_tmr_load(struct psp_context *psp)
 806 {
 807         int ret;
 808         struct psp_gfx_cmd_resp *cmd;
 809
 810         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 811          * Already set up by host driver.
 812          */
 813         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 814                 return 0;
 815
 816         cmd = acquire_psp_cmd_buf(psp);
 817
 818         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 819         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 820                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 821
 822         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 823                                  psp->fence_buf_mc_addr);
 824
 825         release_psp_cmd_buf(psp);
 826
 827         return ret;
 828 }
 829
 830 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 831                                         struct psp_gfx_cmd_resp *cmd)
 832 {
 833         if (amdgpu_sriov_vf(psp->adev))
 834                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 835         else
 836                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 837 }
 838
 839 static int psp_tmr_unload(struct psp_context *psp)
 840 {
 841         int ret;
 842         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 843
 844         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 845         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 846
 847         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 848                                  psp->fence_buf_mc_addr);
 849
 850         release_psp_cmd_buf(psp);
 851
 852         return ret;
 853 }
 854
 855 static int psp_tmr_terminate(struct psp_context *psp)
 856 {
 857         return psp_tmr_unload(psp);
 858 }
 859
 860 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 861                                         uint64_t *output_ptr)
 862 {
 863         int ret;
 864         struct psp_gfx_cmd_resp *cmd;
 865
 866         if (!output_ptr)
 867                 return -EINVAL;
 868
 869         if (amdgpu_sriov_vf(psp->adev))
 870                 return 0;
 871
 872         cmd = acquire_psp_cmd_buf(psp);
 873
 874         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 875
 876         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 877                                  psp->fence_buf_mc_addr);
 878
 879         if (!ret) {
 880                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 881                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 882         }
 883
 884         release_psp_cmd_buf(psp);
 885
 886         return ret;
 887 }
 888
 889 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 890 {
 891         struct psp_context *psp = &adev->psp;
 892         struct psp_gfx_cmd_resp *cmd;
 893         int ret;
 894
 895         if (amdgpu_sriov_vf(adev))
 896                 return 0;
 897
 898         cmd = acquire_psp_cmd_buf(psp);
 899
 900         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 901         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 902
 903         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 904         if (!ret) {
 905                 *boot_cfg =
 906                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 907         }
 908
 909         release_psp_cmd_buf(psp);
 910
 911         return ret;
 912 }
 913
 914 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 915 {
 916         int ret;
 917         struct psp_context *psp = &adev->psp;
 918         struct psp_gfx_cmd_resp *cmd;
 919
 920         if (amdgpu_sriov_vf(adev))
 921                 return 0;
 922
 923         cmd = acquire_psp_cmd_buf(psp);
 924
 925         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 926         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 927         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 928         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 929
 930         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 931
 932         release_psp_cmd_buf(psp);
 933
 934         return ret;
 935 }
 936
 937 static int psp_rl_load(struct amdgpu_device *adev)
 938 {
 939         int ret;
 940         struct psp_context *psp = &adev->psp;
 941         struct psp_gfx_cmd_resp *cmd;
 942
 943         if (!is_psp_fw_valid(psp->rl))
 944                 return 0;
 945
 946         cmd = acquire_psp_cmd_buf(psp);
 947
 948         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 949         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 950
 951         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 952         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 953         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 954         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 955         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 956
 957         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 958
 959         release_psp_cmd_buf(psp);
 960
 961         return ret;
 962 }
 963
 964 static int psp_asd_initialize(struct psp_context *psp)
 965 {
 966         int ret;
 967
 968         /* If PSP version doesn't match ASD version, asd loading will be failed.
 969          * add workaround to bypass it for sriov now.
 970          * TODO: add version check to make it common
 971          */
 972         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
 973                 return 0;
 974
 975         psp->asd_context.mem_context.shared_mc_addr  = 0;
 976         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
 977         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
 978
 979         ret = psp_ta_load(psp, &psp->asd_context);
 980         if (!ret)
 981                 psp->asd_context.initialized = true;
 982
 983         return ret;
 984 }
 985
 986 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 987                                        uint32_t session_id)
 988 {
 989         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 990         cmd->cmd.cmd_unload_ta.session_id = session_id;
 991 }
 992
 993 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
 994 {
 995         int ret;
 996         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 997
 998         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
 999
1000         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1001
1002         context->resp_status = cmd->resp.status;
1003
1004         release_psp_cmd_buf(psp);
1005
1006         return ret;
1007 }
1008
1009 static int psp_asd_terminate(struct psp_context *psp)
1010 {
1011         int ret;
1012
1013         if (amdgpu_sriov_vf(psp->adev))
1014                 return 0;
1015
1016         if (!psp->asd_context.initialized)
1017                 return 0;
1018
1019         ret = psp_ta_unload(psp, &psp->asd_context);
1020         if (!ret)
1021                 psp->asd_context.initialized = false;
1022
1023         return ret;
1024 }
1025
1026 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1027                 uint32_t id, uint32_t value)
1028 {
1029         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1030         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1031         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1032 }
1033
1034 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1035                 uint32_t value)
1036 {
1037         struct psp_gfx_cmd_resp *cmd;
1038         int ret = 0;
1039
1040         if (reg >= PSP_REG_LAST)
1041                 return -EINVAL;
1042
1043         cmd = acquire_psp_cmd_buf(psp);
1044
1045         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1046         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1047         if (ret)
1048                 DRM_ERROR("PSP failed to program reg id %d", reg);
1049
1050         release_psp_cmd_buf(psp);
1051
1052         return ret;
1053 }
1054
1055 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1056                                      uint64_t ta_bin_mc,
1057                                      struct ta_context *context)
1058 {
1059         cmd->cmd_id                             = context->ta_load_type;
1060         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1061         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1062         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1063
1064         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1065                 lower_32_bits(context->mem_context.shared_mc_addr);
1066         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1067                 upper_32_bits(context->mem_context.shared_mc_addr);
1068         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1069 }
1070
1071 int psp_ta_init_shared_buf(struct psp_context *psp,
1072                                   struct ta_mem_context *mem_ctx)
1073 {
1074         /*
1075         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1076         * physical) for ta to host memory
1077         */
1078         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1079                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1080                                       AMDGPU_GEM_DOMAIN_GTT,
1081                                       &mem_ctx->shared_bo,
1082                                       &mem_ctx->shared_mc_addr,
1083                                       &mem_ctx->shared_buf);
1084 }
1085
1086 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1087                                        uint32_t ta_cmd_id,
1088                                        uint32_t session_id)
1089 {
1090         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1091         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1092         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1093 }
1094
1095 int psp_ta_invoke(struct psp_context *psp,
1096                   uint32_t ta_cmd_id,
1097                   struct ta_context *context)
1098 {
1099         int ret;
1100         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1101
1102         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1103
1104         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1105                                  psp->fence_buf_mc_addr);
1106
1107         context->resp_status = cmd->resp.status;
1108
1109         release_psp_cmd_buf(psp);
1110
1111         return ret;
1112 }
1113
1114 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1115 {
1116         int ret;
1117         struct psp_gfx_cmd_resp *cmd;
1118
1119         cmd = acquire_psp_cmd_buf(psp);
1120
1121         psp_copy_fw(psp, context->bin_desc.start_addr,
1122                     context->bin_desc.size_bytes);
1123
1124         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1125
1126         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1127                                  psp->fence_buf_mc_addr);
1128
1129         context->resp_status = cmd->resp.status;
1130
1131         if (!ret) {
1132                 context->session_id = cmd->resp.session_id;
1133         }
1134
1135         release_psp_cmd_buf(psp);
1136
1137         return ret;
1138 }
1139
1140 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1141 {
1142         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1143 }
1144
1145 int psp_xgmi_terminate(struct psp_context *psp)
1146 {
1147         int ret;
1148         struct amdgpu_device *adev = psp->adev;
1149
1150         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1151         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1152             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1153              adev->gmc.xgmi.connected_to_cpu))
1154                 return 0;
1155
1156         if (!psp->xgmi_context.context.initialized)
1157                 return 0;
1158
1159         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1160
1161         psp->xgmi_context.context.initialized = false;
1162
1163         return ret;
1164 }
1165
1166 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1167 {
1168         struct ta_xgmi_shared_memory *xgmi_cmd;
1169         int ret;
1170
1171         if (!psp->ta_fw ||
1172             !psp->xgmi_context.context.bin_desc.size_bytes ||
1173             !psp->xgmi_context.context.bin_desc.start_addr)
1174                 return -ENOENT;
1175
1176         if (!load_ta)
1177                 goto invoke;
1178
1179         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1180         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1181
1182         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1183                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1184                 if (ret)
1185                         return ret;
1186         }
1187
1188         /* Load XGMI TA */
1189         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1190         if (!ret)
1191                 psp->xgmi_context.context.initialized = true;
1192         else
1193                 return ret;
1194
1195 invoke:
1196         /* Initialize XGMI session */
1197         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1198         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1199         xgmi_cmd->flag_extend_link_record = set_extended_data;
1200         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1201
1202         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1203
1204         return ret;
1205 }
1206
1207 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1208 {
1209         struct ta_xgmi_shared_memory *xgmi_cmd;
1210         int ret;
1211
1212         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1213         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1214
1215         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1216
1217         /* Invoke xgmi ta to get hive id */
1218         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1219         if (ret)
1220                 return ret;
1221
1222         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1223
1224         return 0;
1225 }
1226
1227 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1228 {
1229         struct ta_xgmi_shared_memory *xgmi_cmd;
1230         int ret;
1231
1232         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1233         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1234
1235         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1236
1237         /* Invoke xgmi ta to get the node id */
1238         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1239         if (ret)
1240                 return ret;
1241
1242         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1243
1244         return 0;
1245 }
1246
1247 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1248 {
1249         return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1250                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1251 }
1252
1253 /*
1254  * Chips that support extended topology information require the driver to
1255  * reflect topology information in the opposite direction.  This is
1256  * because the TA has already exceeded its link record limit and if the
1257  * TA holds bi-directional information, the driver would have to do
1258  * multiple fetches instead of just two.
1259  */
1260 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1261                                         struct psp_xgmi_node_info node_info)
1262 {
1263         struct amdgpu_device *mirror_adev;
1264         struct amdgpu_hive_info *hive;
1265         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1266         uint64_t dst_node_id = node_info.node_id;
1267         uint8_t dst_num_hops = node_info.num_hops;
1268         uint8_t dst_num_links = node_info.num_links;
1269
1270         hive = amdgpu_get_xgmi_hive(psp->adev);
1271         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1272                 struct psp_xgmi_topology_info *mirror_top_info;
1273                 int j;
1274
1275                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1276                         continue;
1277
1278                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1279                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1280                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1281                                 continue;
1282
1283                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1284                         /*
1285                          * prevent 0 num_links value re-reflection since reflection
1286                          * criteria is based on num_hops (direct or indirect).
1287                          *
1288                          */
1289                         if (dst_num_links)
1290                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1291
1292                         break;
1293                 }
1294
1295                 break;
1296         }
1297
1298         amdgpu_put_xgmi_hive(hive);
1299 }
1300
1301 int psp_xgmi_get_topology_info(struct psp_context *psp,
1302                                int number_devices,
1303                                struct psp_xgmi_topology_info *topology,
1304                                bool get_extended_data)
1305 {
1306         struct ta_xgmi_shared_memory *xgmi_cmd;
1307         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1308         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1309         int i;
1310         int ret;
1311
1312         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1313                 return -EINVAL;
1314
1315         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1316         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1317         xgmi_cmd->flag_extend_link_record = get_extended_data;
1318
1319         /* Fill in the shared memory with topology information as input */
1320         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1321         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1322         topology_info_input->num_nodes = number_devices;
1323
1324         for (i = 0; i < topology_info_input->num_nodes; i++) {
1325                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1326                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1327                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1328                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1329         }
1330
1331         /* Invoke xgmi ta to get the topology information */
1332         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1333         if (ret)
1334                 return ret;
1335
1336         /* Read the output topology information from the shared memory */
1337         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1338         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1339         for (i = 0; i < topology->num_nodes; i++) {
1340                 /* extended data will either be 0 or equal to non-extended data */
1341                 if (topology_info_output->nodes[i].num_hops)
1342                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1343
1344                 /* non-extended data gets everything here so no need to update */
1345                 if (!get_extended_data) {
1346                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1347                         topology->nodes[i].is_sharing_enabled =
1348                                         topology_info_output->nodes[i].is_sharing_enabled;
1349                         topology->nodes[i].sdma_engine =
1350                                         topology_info_output->nodes[i].sdma_engine;
1351                 }
1352
1353         }
1354
1355         /* Invoke xgmi ta again to get the link information */
1356         if (psp_xgmi_peer_link_info_supported(psp)) {
1357                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1358
1359                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1360
1361                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1362
1363                 if (ret)
1364                         return ret;
1365
1366                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1367                 for (i = 0; i < topology->num_nodes; i++) {
1368                         /* accumulate num_links on extended data */
1369                         topology->nodes[i].num_links = get_extended_data ?
1370                                         topology->nodes[i].num_links +
1371                                                         link_info_output->nodes[i].num_links :
1372                                         link_info_output->nodes[i].num_links;
1373
1374                         /* reflect the topology information for bi-directionality */
1375                         if (psp->xgmi_context.supports_extended_data &&
1376                                         get_extended_data && topology->nodes[i].num_hops)
1377                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1378                 }
1379         }
1380
1381         return 0;
1382 }
1383
1384 int psp_xgmi_set_topology_info(struct psp_context *psp,
1385                                int number_devices,
1386                                struct psp_xgmi_topology_info *topology)
1387 {
1388         struct ta_xgmi_shared_memory *xgmi_cmd;
1389         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1390         int i;
1391
1392         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1393                 return -EINVAL;
1394
1395         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1396         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1397
1398         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1399         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1400         topology_info_input->num_nodes = number_devices;
1401
1402         for (i = 0; i < topology_info_input->num_nodes; i++) {
1403                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1404                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1405                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1406                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1407         }
1408
1409         /* Invoke xgmi ta to set topology information */
1410         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1411 }
1412
1413 // ras begin
1414 static void psp_ras_ta_check_status(struct psp_context *psp)
1415 {
1416         struct ta_ras_shared_memory *ras_cmd =
1417                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1418
1419         switch (ras_cmd->ras_status) {
1420         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1421                 dev_warn(psp->adev->dev,
1422                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1423                 break;
1424         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1425                 dev_warn(psp->adev->dev,
1426                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1427                 break;
1428         case TA_RAS_STATUS__SUCCESS:
1429                 break;
1430         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1431                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1432                         dev_warn(psp->adev->dev,
1433                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1434                 break;
1435         default:
1436                 dev_warn(psp->adev->dev,
1437                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1438                 break;
1439         }
1440 }
1441
1442 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1443 {
1444         struct ta_ras_shared_memory *ras_cmd;
1445         int ret;
1446
1447         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1448
1449         /*
1450          * TODO: bypass the loading in sriov for now
1451          */
1452         if (amdgpu_sriov_vf(psp->adev))
1453                 return 0;
1454
1455         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1456
1457         if (amdgpu_ras_intr_triggered())
1458                 return ret;
1459
1460         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1461         {
1462                 DRM_WARN("RAS: Unsupported Interface");
1463                 return -EINVAL;
1464         }
1465
1466         if (!ret) {
1467                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1468                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1469
1470                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1471                 }
1472                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1473                         dev_warn(psp->adev->dev,
1474                                  "RAS internal register access blocked\n");
1475
1476                 psp_ras_ta_check_status(psp);
1477         }
1478
1479         return ret;
1480 }
1481
1482 int psp_ras_enable_features(struct psp_context *psp,
1483                 union ta_ras_cmd_input *info, bool enable)
1484 {
1485         struct ta_ras_shared_memory *ras_cmd;
1486         int ret;
1487
1488         if (!psp->ras_context.context.initialized)
1489                 return -EINVAL;
1490
1491         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1492         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1493
1494         if (enable)
1495                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1496         else
1497                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1498
1499         ras_cmd->ras_in_message = *info;
1500
1501         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1502         if (ret)
1503                 return -EINVAL;
1504
1505         return 0;
1506 }
1507
1508 int psp_ras_terminate(struct psp_context *psp)
1509 {
1510         int ret;
1511
1512         /*
1513          * TODO: bypass the terminate in sriov for now
1514          */
1515         if (amdgpu_sriov_vf(psp->adev))
1516                 return 0;
1517
1518         if (!psp->ras_context.context.initialized)
1519                 return 0;
1520
1521         ret = psp_ta_unload(psp, &psp->ras_context.context);
1522
1523         psp->ras_context.context.initialized = false;
1524
1525         return ret;
1526 }
1527
1528 int psp_ras_initialize(struct psp_context *psp)
1529 {
1530         int ret;
1531         uint32_t boot_cfg = 0xFF;
1532         struct amdgpu_device *adev = psp->adev;
1533         struct ta_ras_shared_memory *ras_cmd;
1534
1535         /*
1536          * TODO: bypass the initialize in sriov for now
1537          */
1538         if (amdgpu_sriov_vf(adev))
1539                 return 0;
1540
1541         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1542             !adev->psp.ras_context.context.bin_desc.start_addr) {
1543                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1544                 return 0;
1545         }
1546
1547         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1548                 /* query GECC enablement status from boot config
1549                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1550                  */
1551                 ret = psp_boot_config_get(adev, &boot_cfg);
1552                 if (ret)
1553                         dev_warn(adev->dev, "PSP get boot config failed\n");
1554
1555                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1556                         if (!boot_cfg) {
1557                                 dev_info(adev->dev, "GECC is disabled\n");
1558                         } else {
1559                                 /* disable GECC in next boot cycle if ras is
1560                                  * disabled by module parameter amdgpu_ras_enable
1561                                  * and/or amdgpu_ras_mask, or boot_config_get call
1562                                  * is failed
1563                                  */
1564                                 ret = psp_boot_config_set(adev, 0);
1565                                 if (ret)
1566                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1567                                 else
1568                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1569                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1570                         }
1571                 } else {
1572                         if (1 == boot_cfg) {
1573                                 dev_info(adev->dev, "GECC is enabled\n");
1574                         } else {
1575                                 /* enable GECC in next boot cycle if it is disabled
1576                                  * in boot config, or force enable GECC if failed to
1577                                  * get boot configuration
1578                                  */
1579                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1580                                 if (ret)
1581                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1582                                 else
1583                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1584                         }
1585                 }
1586         }
1587
1588         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1589         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1590
1591         if (!psp->ras_context.context.mem_context.shared_buf) {
1592                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1593                 if (ret)
1594                         return ret;
1595         }
1596
1597         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1598         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1599
1600         if (amdgpu_ras_is_poison_mode_supported(adev))
1601                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1602         if (!adev->gmc.xgmi.connected_to_cpu)
1603                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1604
1605         ret = psp_ta_load(psp, &psp->ras_context.context);
1606
1607         if (!ret && !ras_cmd->ras_status)
1608                 psp->ras_context.context.initialized = true;
1609         else {
1610                 if (ras_cmd->ras_status)
1611                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1612
1613                 /* fail to load RAS TA */
1614                 psp->ras_context.context.initialized = false;
1615         }
1616
1617         return ret;
1618 }
1619
1620 int psp_ras_trigger_error(struct psp_context *psp,
1621                           struct ta_ras_trigger_error_input *info)
1622 {
1623         struct ta_ras_shared_memory *ras_cmd;
1624         int ret;
1625
1626         if (!psp->ras_context.context.initialized)
1627                 return -EINVAL;
1628
1629         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1630         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1631
1632         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1633         ras_cmd->ras_in_message.trigger_error = *info;
1634
1635         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1636         if (ret)
1637                 return -EINVAL;
1638
1639         /* If err_event_athub occurs error inject was successful, however
1640            return status from TA is no long reliable */
1641         if (amdgpu_ras_intr_triggered())
1642                 return 0;
1643
1644         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1645                 return -EACCES;
1646         else if (ras_cmd->ras_status)
1647                 return -EINVAL;
1648
1649         return 0;
1650 }
1651 // ras end
1652
1653 // HDCP start
1654 static int psp_hdcp_initialize(struct psp_context *psp)
1655 {
1656         int ret;
1657
1658         /*
1659          * TODO: bypass the initialize in sriov for now
1660          */
1661         if (amdgpu_sriov_vf(psp->adev))
1662                 return 0;
1663
1664         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1665             !psp->hdcp_context.context.bin_desc.start_addr) {
1666                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1667                 return 0;
1668         }
1669
1670         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1671         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1672
1673         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1674                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1675                 if (ret)
1676                         return ret;
1677         }
1678
1679         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1680         if (!ret) {
1681                 psp->hdcp_context.context.initialized = true;
1682                 mutex_init(&psp->hdcp_context.mutex);
1683         }
1684
1685         return ret;
1686 }
1687
1688 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1689 {
1690         /*
1691          * TODO: bypass the loading in sriov for now
1692          */
1693         if (amdgpu_sriov_vf(psp->adev))
1694                 return 0;
1695
1696         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1697 }
1698
1699 static int psp_hdcp_terminate(struct psp_context *psp)
1700 {
1701         int ret;
1702
1703         /*
1704          * TODO: bypass the terminate in sriov for now
1705          */
1706         if (amdgpu_sriov_vf(psp->adev))
1707                 return 0;
1708
1709         if (!psp->hdcp_context.context.initialized)
1710                 return 0;
1711
1712         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1713
1714         psp->hdcp_context.context.initialized = false;
1715
1716         return ret;
1717 }
1718 // HDCP end
1719
1720 // DTM start
1721 static int psp_dtm_initialize(struct psp_context *psp)
1722 {
1723         int ret;
1724
1725         /*
1726          * TODO: bypass the initialize in sriov for now
1727          */
1728         if (amdgpu_sriov_vf(psp->adev))
1729                 return 0;
1730
1731         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1732             !psp->dtm_context.context.bin_desc.start_addr) {
1733                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1734                 return 0;
1735         }
1736
1737         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1738         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1739
1740         if (!psp->dtm_context.context.mem_context.shared_buf) {
1741                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1742                 if (ret)
1743                         return ret;
1744         }
1745
1746         ret = psp_ta_load(psp, &psp->dtm_context.context);
1747         if (!ret) {
1748                 psp->dtm_context.context.initialized = true;
1749                 mutex_init(&psp->dtm_context.mutex);
1750         }
1751
1752         return ret;
1753 }
1754
1755 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1756 {
1757         /*
1758          * TODO: bypass the loading in sriov for now
1759          */
1760         if (amdgpu_sriov_vf(psp->adev))
1761                 return 0;
1762
1763         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1764 }
1765
1766 static int psp_dtm_terminate(struct psp_context *psp)
1767 {
1768         int ret;
1769
1770         /*
1771          * TODO: bypass the terminate in sriov for now
1772          */
1773         if (amdgpu_sriov_vf(psp->adev))
1774                 return 0;
1775
1776         if (!psp->dtm_context.context.initialized)
1777                 return 0;
1778
1779         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1780
1781         psp->dtm_context.context.initialized = false;
1782
1783         return ret;
1784 }
1785 // DTM end
1786
1787 // RAP start
1788 static int psp_rap_initialize(struct psp_context *psp)
1789 {
1790         int ret;
1791         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1792
1793         /*
1794          * TODO: bypass the initialize in sriov for now
1795          */
1796         if (amdgpu_sriov_vf(psp->adev))
1797                 return 0;
1798
1799         if (!psp->rap_context.context.bin_desc.size_bytes ||
1800             !psp->rap_context.context.bin_desc.start_addr) {
1801                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1802                 return 0;
1803         }
1804
1805         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1806         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1807
1808         if (!psp->rap_context.context.mem_context.shared_buf) {
1809                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1810                 if (ret)
1811                         return ret;
1812         }
1813
1814         ret = psp_ta_load(psp, &psp->rap_context.context);
1815         if (!ret) {
1816                 psp->rap_context.context.initialized = true;
1817                 mutex_init(&psp->rap_context.mutex);
1818         } else
1819                 return ret;
1820
1821         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1822         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1823                 psp_rap_terminate(psp);
1824                 /* free rap shared memory */
1825                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1826
1827                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1828                          ret, status);
1829
1830                 return ret;
1831         }
1832
1833         return 0;
1834 }
1835
1836 static int psp_rap_terminate(struct psp_context *psp)
1837 {
1838         int ret;
1839
1840         if (!psp->rap_context.context.initialized)
1841                 return 0;
1842
1843         ret = psp_ta_unload(psp, &psp->rap_context.context);
1844
1845         psp->rap_context.context.initialized = false;
1846
1847         return ret;
1848 }
1849
1850 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1851 {
1852         struct ta_rap_shared_memory *rap_cmd;
1853         int ret = 0;
1854
1855         if (!psp->rap_context.context.initialized)
1856                 return 0;
1857
1858         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1859             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1860                 return -EINVAL;
1861
1862         mutex_lock(&psp->rap_context.mutex);
1863
1864         rap_cmd = (struct ta_rap_shared_memory *)
1865                   psp->rap_context.context.mem_context.shared_buf;
1866         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1867
1868         rap_cmd->cmd_id = ta_cmd_id;
1869         rap_cmd->validation_method_id = METHOD_A;
1870
1871         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1872         if (ret)
1873                 goto out_unlock;
1874
1875         if (status)
1876                 *status = rap_cmd->rap_status;
1877
1878 out_unlock:
1879         mutex_unlock(&psp->rap_context.mutex);
1880
1881         return ret;
1882 }
1883 // RAP end
1884
1885 /* securedisplay start */
1886 static int psp_securedisplay_initialize(struct psp_context *psp)
1887 {
1888         int ret;
1889         struct ta_securedisplay_cmd *securedisplay_cmd;
1890
1891         /*
1892          * TODO: bypass the initialize in sriov for now
1893          */
1894         if (amdgpu_sriov_vf(psp->adev))
1895                 return 0;
1896
1897         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1898             !psp->securedisplay_context.context.bin_desc.start_addr) {
1899                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1900                 return 0;
1901         }
1902
1903         psp->securedisplay_context.context.mem_context.shared_mem_size =
1904                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1905         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1906
1907         if (!psp->securedisplay_context.context.initialized) {
1908                 ret = psp_ta_init_shared_buf(psp,
1909                                              &psp->securedisplay_context.context.mem_context);
1910                 if (ret)
1911                         return ret;
1912         }
1913
1914         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1915         if (!ret) {
1916                 psp->securedisplay_context.context.initialized = true;
1917                 mutex_init(&psp->securedisplay_context.mutex);
1918         } else
1919                 return ret;
1920
1921         mutex_lock(&psp->securedisplay_context.mutex);
1922
1923         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1924                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1925
1926         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1927
1928         mutex_unlock(&psp->securedisplay_context.mutex);
1929
1930         if (ret) {
1931                 psp_securedisplay_terminate(psp);
1932                 /* free securedisplay shared memory */
1933                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1934                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1935                 return -EINVAL;
1936         }
1937
1938         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1939                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1940                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1941                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1942         }
1943
1944         return 0;
1945 }
1946
1947 static int psp_securedisplay_terminate(struct psp_context *psp)
1948 {
1949         int ret;
1950
1951         /*
1952          * TODO:bypass the terminate in sriov for now
1953          */
1954         if (amdgpu_sriov_vf(psp->adev))
1955                 return 0;
1956
1957         if (!psp->securedisplay_context.context.initialized)
1958                 return 0;
1959
1960         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1961
1962         psp->securedisplay_context.context.initialized = false;
1963
1964         return ret;
1965 }
1966
1967 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1968 {
1969         int ret;
1970
1971         if (!psp->securedisplay_context.context.initialized)
1972                 return -EINVAL;
1973
1974         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1975             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1976                 return -EINVAL;
1977
1978         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1979
1980         return ret;
1981 }
1982 /* SECUREDISPLAY end */
1983
1984 static int psp_hw_start(struct psp_context *psp)
1985 {
1986         struct amdgpu_device *adev = psp->adev;
1987         int ret;
1988
1989         if (!amdgpu_sriov_vf(adev)) {
1990                 if ((is_psp_fw_valid(psp->kdb)) &&
1991                     (psp->funcs->bootloader_load_kdb != NULL)) {
1992                         ret = psp_bootloader_load_kdb(psp);
1993                         if (ret) {
1994                                 DRM_ERROR("PSP load kdb failed!\n");
1995                                 return ret;
1996                         }
1997                 }
1998
1999                 if ((is_psp_fw_valid(psp->spl)) &&
2000                     (psp->funcs->bootloader_load_spl != NULL)) {
2001                         ret = psp_bootloader_load_spl(psp);
2002                         if (ret) {
2003                                 DRM_ERROR("PSP load spl failed!\n");
2004                                 return ret;
2005                         }
2006                 }
2007
2008                 if ((is_psp_fw_valid(psp->sys)) &&
2009                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2010                         ret = psp_bootloader_load_sysdrv(psp);
2011                         if (ret) {
2012                                 DRM_ERROR("PSP load sys drv failed!\n");
2013                                 return ret;
2014                         }
2015                 }
2016
2017                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2018                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2019                         ret = psp_bootloader_load_soc_drv(psp);
2020                         if (ret) {
2021                                 DRM_ERROR("PSP load soc drv failed!\n");
2022                                 return ret;
2023                         }
2024                 }
2025
2026                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2027                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2028                         ret = psp_bootloader_load_intf_drv(psp);
2029                         if (ret) {
2030                                 DRM_ERROR("PSP load intf drv failed!\n");
2031                                 return ret;
2032                         }
2033                 }
2034
2035                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2036                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2037                         ret = psp_bootloader_load_dbg_drv(psp);
2038                         if (ret) {
2039                                 DRM_ERROR("PSP load dbg drv failed!\n");
2040                                 return ret;
2041                         }
2042                 }
2043
2044                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2045                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2046                         ret = psp_bootloader_load_ras_drv(psp);
2047                         if (ret) {
2048                                 DRM_ERROR("PSP load ras_drv failed!\n");
2049                                 return ret;
2050                         }
2051                 }
2052
2053                 if ((is_psp_fw_valid(psp->sos)) &&
2054                     (psp->funcs->bootloader_load_sos != NULL)) {
2055                         ret = psp_bootloader_load_sos(psp);
2056                         if (ret) {
2057                                 DRM_ERROR("PSP load sos failed!\n");
2058                                 return ret;
2059                         }
2060                 }
2061         }
2062
2063         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2064         if (ret) {
2065                 DRM_ERROR("PSP create ring failed!\n");
2066                 return ret;
2067         }
2068
2069         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2070                 goto skip_pin_bo;
2071
2072         ret = psp_tmr_init(psp);
2073         if (ret) {
2074                 DRM_ERROR("PSP tmr init failed!\n");
2075                 return ret;
2076         }
2077
2078 skip_pin_bo:
2079         /*
2080          * For ASICs with DF Cstate management centralized
2081          * to PMFW, TMR setup should be performed after PMFW
2082          * loaded and before other non-psp firmware loaded.
2083          */
2084         if (psp->pmfw_centralized_cstate_management) {
2085                 ret = psp_load_smu_fw(psp);
2086                 if (ret)
2087                         return ret;
2088         }
2089
2090         ret = psp_tmr_load(psp);
2091         if (ret) {
2092                 DRM_ERROR("PSP load tmr failed!\n");
2093                 return ret;
2094         }
2095
2096         return 0;
2097 }
2098
2099 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2100                            enum psp_gfx_fw_type *type)
2101 {
2102         switch (ucode->ucode_id) {
2103         case AMDGPU_UCODE_ID_CAP:
2104                 *type = GFX_FW_TYPE_CAP;
2105                 break;
2106         case AMDGPU_UCODE_ID_SDMA0:
2107                 *type = GFX_FW_TYPE_SDMA0;
2108                 break;
2109         case AMDGPU_UCODE_ID_SDMA1:
2110                 *type = GFX_FW_TYPE_SDMA1;
2111                 break;
2112         case AMDGPU_UCODE_ID_SDMA2:
2113                 *type = GFX_FW_TYPE_SDMA2;
2114                 break;
2115         case AMDGPU_UCODE_ID_SDMA3:
2116                 *type = GFX_FW_TYPE_SDMA3;
2117                 break;
2118         case AMDGPU_UCODE_ID_SDMA4:
2119                 *type = GFX_FW_TYPE_SDMA4;
2120                 break;
2121         case AMDGPU_UCODE_ID_SDMA5:
2122                 *type = GFX_FW_TYPE_SDMA5;
2123                 break;
2124         case AMDGPU_UCODE_ID_SDMA6:
2125                 *type = GFX_FW_TYPE_SDMA6;
2126                 break;
2127         case AMDGPU_UCODE_ID_SDMA7:
2128                 *type = GFX_FW_TYPE_SDMA7;
2129                 break;
2130         case AMDGPU_UCODE_ID_CP_MES:
2131                 *type = GFX_FW_TYPE_CP_MES;
2132                 break;
2133         case AMDGPU_UCODE_ID_CP_MES_DATA:
2134                 *type = GFX_FW_TYPE_MES_STACK;
2135                 break;
2136         case AMDGPU_UCODE_ID_CP_MES1:
2137                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2138                 break;
2139         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2140                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2141                 break;
2142         case AMDGPU_UCODE_ID_CP_CE:
2143                 *type = GFX_FW_TYPE_CP_CE;
2144                 break;
2145         case AMDGPU_UCODE_ID_CP_PFP:
2146                 *type = GFX_FW_TYPE_CP_PFP;
2147                 break;
2148         case AMDGPU_UCODE_ID_CP_ME:
2149                 *type = GFX_FW_TYPE_CP_ME;
2150                 break;
2151         case AMDGPU_UCODE_ID_CP_MEC1:
2152                 *type = GFX_FW_TYPE_CP_MEC;
2153                 break;
2154         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2155                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2156                 break;
2157         case AMDGPU_UCODE_ID_CP_MEC2:
2158                 *type = GFX_FW_TYPE_CP_MEC;
2159                 break;
2160         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2161                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2162                 break;
2163         case AMDGPU_UCODE_ID_RLC_P:
2164                 *type = GFX_FW_TYPE_RLC_P;
2165                 break;
2166         case AMDGPU_UCODE_ID_RLC_V:
2167                 *type = GFX_FW_TYPE_RLC_V;
2168                 break;
2169         case AMDGPU_UCODE_ID_RLC_G:
2170                 *type = GFX_FW_TYPE_RLC_G;
2171                 break;
2172         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2173                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2174                 break;
2175         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2176                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2177                 break;
2178         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2179                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2180                 break;
2181         case AMDGPU_UCODE_ID_RLC_IRAM:
2182                 *type = GFX_FW_TYPE_RLC_IRAM;
2183                 break;
2184         case AMDGPU_UCODE_ID_RLC_DRAM:
2185                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2186                 break;
2187         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2188                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2189                 break;
2190         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2191                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2192                 break;
2193         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2194                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2195                 break;
2196         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2197                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2198                 break;
2199         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2200                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2201                 break;
2202         case AMDGPU_UCODE_ID_SMC:
2203                 *type = GFX_FW_TYPE_SMU;
2204                 break;
2205         case AMDGPU_UCODE_ID_PPTABLE:
2206                 *type = GFX_FW_TYPE_PPTABLE;
2207                 break;
2208         case AMDGPU_UCODE_ID_UVD:
2209                 *type = GFX_FW_TYPE_UVD;
2210                 break;
2211         case AMDGPU_UCODE_ID_UVD1:
2212                 *type = GFX_FW_TYPE_UVD1;
2213                 break;
2214         case AMDGPU_UCODE_ID_VCE:
2215                 *type = GFX_FW_TYPE_VCE;
2216                 break;
2217         case AMDGPU_UCODE_ID_VCN:
2218                 *type = GFX_FW_TYPE_VCN;
2219                 break;
2220         case AMDGPU_UCODE_ID_VCN1:
2221                 *type = GFX_FW_TYPE_VCN1;
2222                 break;
2223         case AMDGPU_UCODE_ID_DMCU_ERAM:
2224                 *type = GFX_FW_TYPE_DMCU_ERAM;
2225                 break;
2226         case AMDGPU_UCODE_ID_DMCU_INTV:
2227                 *type = GFX_FW_TYPE_DMCU_ISR;
2228                 break;
2229         case AMDGPU_UCODE_ID_VCN0_RAM:
2230                 *type = GFX_FW_TYPE_VCN0_RAM;
2231                 break;
2232         case AMDGPU_UCODE_ID_VCN1_RAM:
2233                 *type = GFX_FW_TYPE_VCN1_RAM;
2234                 break;
2235         case AMDGPU_UCODE_ID_DMCUB:
2236                 *type = GFX_FW_TYPE_DMUB;
2237                 break;
2238         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2239                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2240                 break;
2241         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2242                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2243                 break;
2244         case AMDGPU_UCODE_ID_IMU_I:
2245                 *type = GFX_FW_TYPE_IMU_I;
2246                 break;
2247         case AMDGPU_UCODE_ID_IMU_D:
2248                 *type = GFX_FW_TYPE_IMU_D;
2249                 break;
2250         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2251                 *type = GFX_FW_TYPE_RS64_PFP;
2252                 break;
2253         case AMDGPU_UCODE_ID_CP_RS64_ME:
2254                 *type = GFX_FW_TYPE_RS64_ME;
2255                 break;
2256         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2257                 *type = GFX_FW_TYPE_RS64_MEC;
2258                 break;
2259         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2260                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2261                 break;
2262         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2263                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2264                 break;
2265         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2266                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2267                 break;
2268         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2269                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2270                 break;
2271         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2272                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2273                 break;
2274         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2275                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2276                 break;
2277         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2278                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2279                 break;
2280         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2281                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2282                 break;
2283         case AMDGPU_UCODE_ID_MAXIMUM:
2284         default:
2285                 return -EINVAL;
2286         }
2287
2288         return 0;
2289 }
2290
2291 static void psp_print_fw_hdr(struct psp_context *psp,
2292                              struct amdgpu_firmware_info *ucode)
2293 {
2294         struct amdgpu_device *adev = psp->adev;
2295         struct common_firmware_header *hdr;
2296
2297         switch (ucode->ucode_id) {
2298         case AMDGPU_UCODE_ID_SDMA0:
2299         case AMDGPU_UCODE_ID_SDMA1:
2300         case AMDGPU_UCODE_ID_SDMA2:
2301         case AMDGPU_UCODE_ID_SDMA3:
2302         case AMDGPU_UCODE_ID_SDMA4:
2303         case AMDGPU_UCODE_ID_SDMA5:
2304         case AMDGPU_UCODE_ID_SDMA6:
2305         case AMDGPU_UCODE_ID_SDMA7:
2306                 hdr = (struct common_firmware_header *)
2307                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2308                 amdgpu_ucode_print_sdma_hdr(hdr);
2309                 break;
2310         case AMDGPU_UCODE_ID_CP_CE:
2311                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2312                 amdgpu_ucode_print_gfx_hdr(hdr);
2313                 break;
2314         case AMDGPU_UCODE_ID_CP_PFP:
2315                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2316                 amdgpu_ucode_print_gfx_hdr(hdr);
2317                 break;
2318         case AMDGPU_UCODE_ID_CP_ME:
2319                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2320                 amdgpu_ucode_print_gfx_hdr(hdr);
2321                 break;
2322         case AMDGPU_UCODE_ID_CP_MEC1:
2323                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2324                 amdgpu_ucode_print_gfx_hdr(hdr);
2325                 break;
2326         case AMDGPU_UCODE_ID_RLC_G:
2327                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2328                 amdgpu_ucode_print_rlc_hdr(hdr);
2329                 break;
2330         case AMDGPU_UCODE_ID_SMC:
2331                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2332                 amdgpu_ucode_print_smc_hdr(hdr);
2333                 break;
2334         default:
2335                 break;
2336         }
2337 }
2338
2339 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2340                                        struct psp_gfx_cmd_resp *cmd)
2341 {
2342         int ret;
2343         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2344
2345         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2346         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2347         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2348         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2349
2350         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2351         if (ret)
2352                 DRM_ERROR("Unknown firmware type\n");
2353
2354         return ret;
2355 }
2356
2357 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2358                                   struct amdgpu_firmware_info *ucode)
2359 {
2360         int ret = 0;
2361         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2362
2363         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2364         if (!ret) {
2365                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2366                                          psp->fence_buf_mc_addr);
2367         }
2368
2369         release_psp_cmd_buf(psp);
2370
2371         return ret;
2372 }
2373
2374 static int psp_load_smu_fw(struct psp_context *psp)
2375 {
2376         int ret;
2377         struct amdgpu_device *adev = psp->adev;
2378         struct amdgpu_firmware_info *ucode =
2379                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2380         struct amdgpu_ras *ras = psp->ras_context.ras;
2381
2382         /*
2383          * Skip SMU FW reloading in case of using BACO for runpm only,
2384          * as SMU is always alive.
2385          */
2386         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2387                 return 0;
2388
2389         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2390                 return 0;
2391
2392         if ((amdgpu_in_reset(adev) &&
2393              ras && adev->ras_enabled &&
2394              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2395               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2396                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2397                 if (ret) {
2398                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2399                 }
2400         }
2401
2402         ret = psp_execute_non_psp_fw_load(psp, ucode);
2403
2404         if (ret)
2405                 DRM_ERROR("PSP load smu failed!\n");
2406
2407         return ret;
2408 }
2409
2410 static bool fw_load_skip_check(struct psp_context *psp,
2411                                struct amdgpu_firmware_info *ucode)
2412 {
2413         if (!ucode->fw || !ucode->ucode_size)
2414                 return true;
2415
2416         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2417             (psp_smu_reload_quirk(psp) ||
2418              psp->autoload_supported ||
2419              psp->pmfw_centralized_cstate_management))
2420                 return true;
2421
2422         if (amdgpu_sriov_vf(psp->adev) &&
2423             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2424                 return true;
2425
2426         if (psp->autoload_supported &&
2427             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2428              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2429                 /* skip mec JT when autoload is enabled */
2430                 return true;
2431
2432         return false;
2433 }
2434
2435 int psp_load_fw_list(struct psp_context *psp,
2436                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2437 {
2438         int ret = 0, i;
2439         struct amdgpu_firmware_info *ucode;
2440
2441         for (i = 0; i < ucode_count; ++i) {
2442                 ucode = ucode_list[i];
2443                 psp_print_fw_hdr(psp, ucode);
2444                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2445                 if (ret)
2446                         return ret;
2447         }
2448         return ret;
2449 }
2450
2451 static int psp_load_non_psp_fw(struct psp_context *psp)
2452 {
2453         int i, ret;
2454         struct amdgpu_firmware_info *ucode;
2455         struct amdgpu_device *adev = psp->adev;
2456
2457         if (psp->autoload_supported &&
2458             !psp->pmfw_centralized_cstate_management) {
2459                 ret = psp_load_smu_fw(psp);
2460                 if (ret)
2461                         return ret;
2462         }
2463
2464         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2465                 ucode = &adev->firmware.ucode[i];
2466
2467                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2468                     !fw_load_skip_check(psp, ucode)) {
2469                         ret = psp_load_smu_fw(psp);
2470                         if (ret)
2471                                 return ret;
2472                         continue;
2473                 }
2474
2475                 if (fw_load_skip_check(psp, ucode))
2476                         continue;
2477
2478                 if (psp->autoload_supported &&
2479                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2480                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2481                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2482                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2483                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2484                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2485                         /* PSP only receive one SDMA fw for sienna_cichlid,
2486                          * as all four sdma fw are same */
2487                         continue;
2488
2489                 psp_print_fw_hdr(psp, ucode);
2490
2491                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2492                 if (ret)
2493                         return ret;
2494
2495                 /* Start rlc autoload after psp recieved all the gfx firmware */
2496                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2497                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2498                         ret = psp_rlc_autoload_start(psp);
2499                         if (ret) {
2500                                 DRM_ERROR("Failed to start rlc autoload\n");
2501                                 return ret;
2502                         }
2503                 }
2504         }
2505
2506         return 0;
2507 }
2508
2509 static int psp_load_fw(struct amdgpu_device *adev)
2510 {
2511         int ret;
2512         struct psp_context *psp = &adev->psp;
2513
2514         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2515                 /* should not destroy ring, only stop */
2516                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2517         } else {
2518                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2519
2520                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2521                 if (ret) {
2522                         DRM_ERROR("PSP ring init failed!\n");
2523                         goto failed;
2524                 }
2525         }
2526
2527         ret = psp_hw_start(psp);
2528         if (ret)
2529                 goto failed;
2530
2531         ret = psp_load_non_psp_fw(psp);
2532         if (ret)
2533                 goto failed1;
2534
2535         ret = psp_asd_initialize(psp);
2536         if (ret) {
2537                 DRM_ERROR("PSP load asd failed!\n");
2538                 goto failed1;
2539         }
2540
2541         ret = psp_rl_load(adev);
2542         if (ret) {
2543                 DRM_ERROR("PSP load RL failed!\n");
2544                 goto failed1;
2545         }
2546
2547         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2548                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2549                         ret = psp_xgmi_initialize(psp, false, true);
2550                         /* Warning the XGMI seesion initialize failure
2551                         * Instead of stop driver initialization
2552                         */
2553                         if (ret)
2554                                 dev_err(psp->adev->dev,
2555                                         "XGMI: Failed to initialize XGMI session\n");
2556                 }
2557         }
2558
2559         if (psp->ta_fw) {
2560                 ret = psp_ras_initialize(psp);
2561                 if (ret)
2562                         dev_err(psp->adev->dev,
2563                                         "RAS: Failed to initialize RAS\n");
2564
2565                 ret = psp_hdcp_initialize(psp);
2566                 if (ret)
2567                         dev_err(psp->adev->dev,
2568                                 "HDCP: Failed to initialize HDCP\n");
2569
2570                 ret = psp_dtm_initialize(psp);
2571                 if (ret)
2572                         dev_err(psp->adev->dev,
2573                                 "DTM: Failed to initialize DTM\n");
2574
2575                 ret = psp_rap_initialize(psp);
2576                 if (ret)
2577                         dev_err(psp->adev->dev,
2578                                 "RAP: Failed to initialize RAP\n");
2579
2580                 ret = psp_securedisplay_initialize(psp);
2581                 if (ret)
2582                         dev_err(psp->adev->dev,
2583                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2584         }
2585
2586         return 0;
2587
2588 failed1:
2589         psp_free_shared_bufs(psp);
2590 failed:
2591         /*
2592          * all cleanup jobs (xgmi terminate, ras terminate,
2593          * ring destroy, cmd/fence/fw buffers destory,
2594          * psp->cmd destory) are delayed to psp_hw_fini
2595          */
2596         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2597         return ret;
2598 }
2599
2600 static int psp_hw_init(void *handle)
2601 {
2602         int ret;
2603         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2604
2605         mutex_lock(&adev->firmware.mutex);
2606         /*
2607          * This sequence is just used on hw_init only once, no need on
2608          * resume.
2609          */
2610         ret = amdgpu_ucode_init_bo(adev);
2611         if (ret)
2612                 goto failed;
2613
2614         ret = psp_load_fw(adev);
2615         if (ret) {
2616                 DRM_ERROR("PSP firmware loading failed\n");
2617                 goto failed;
2618         }
2619
2620         mutex_unlock(&adev->firmware.mutex);
2621         return 0;
2622
2623 failed:
2624         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2625         mutex_unlock(&adev->firmware.mutex);
2626         return -EINVAL;
2627 }
2628
2629 static int psp_hw_fini(void *handle)
2630 {
2631         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2632         struct psp_context *psp = &adev->psp;
2633
2634         if (psp->ta_fw) {
2635                 psp_ras_terminate(psp);
2636                 psp_securedisplay_terminate(psp);
2637                 psp_rap_terminate(psp);
2638                 psp_dtm_terminate(psp);
2639                 psp_hdcp_terminate(psp);
2640
2641                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2642                         psp_xgmi_terminate(psp);
2643         }
2644
2645         psp_asd_terminate(psp);
2646         psp_tmr_terminate(psp);
2647
2648         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2649
2650         psp_free_shared_bufs(psp);
2651
2652         return 0;
2653 }
2654
2655 static int psp_suspend(void *handle)
2656 {
2657         int ret = 0;
2658         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2659         struct psp_context *psp = &adev->psp;
2660
2661         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2662             psp->xgmi_context.context.initialized) {
2663                 ret = psp_xgmi_terminate(psp);
2664                 if (ret) {
2665                         DRM_ERROR("Failed to terminate xgmi ta\n");
2666                         goto out;
2667                 }
2668         }
2669
2670         if (psp->ta_fw) {
2671                 ret = psp_ras_terminate(psp);
2672                 if (ret) {
2673                         DRM_ERROR("Failed to terminate ras ta\n");
2674                         goto out;
2675                 }
2676                 ret = psp_hdcp_terminate(psp);
2677                 if (ret) {
2678                         DRM_ERROR("Failed to terminate hdcp ta\n");
2679                         goto out;
2680                 }
2681                 ret = psp_dtm_terminate(psp);
2682                 if (ret) {
2683                         DRM_ERROR("Failed to terminate dtm ta\n");
2684                         goto out;
2685                 }
2686                 ret = psp_rap_terminate(psp);
2687                 if (ret) {
2688                         DRM_ERROR("Failed to terminate rap ta\n");
2689                         goto out;
2690                 }
2691                 ret = psp_securedisplay_terminate(psp);
2692                 if (ret) {
2693                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2694                         goto out;
2695                 }
2696         }
2697
2698         ret = psp_asd_terminate(psp);
2699         if (ret) {
2700                 DRM_ERROR("Failed to terminate asd\n");
2701                 goto out;
2702         }
2703
2704         ret = psp_tmr_terminate(psp);
2705         if (ret) {
2706                 DRM_ERROR("Failed to terminate tmr\n");
2707                 goto out;
2708         }
2709
2710         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2711         if (ret) {
2712                 DRM_ERROR("PSP ring stop failed\n");
2713         }
2714
2715 out:
2716         return ret;
2717 }
2718
2719 static int psp_resume(void *handle)
2720 {
2721         int ret;
2722         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2723         struct psp_context *psp = &adev->psp;
2724
2725         DRM_INFO("PSP is resuming...\n");
2726
2727         if (psp->mem_train_ctx.enable_mem_training) {
2728                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2729                 if (ret) {
2730                         DRM_ERROR("Failed to process memory training!\n");
2731                         return ret;
2732                 }
2733         }
2734
2735         mutex_lock(&adev->firmware.mutex);
2736
2737         ret = psp_hw_start(psp);
2738         if (ret)
2739                 goto failed;
2740
2741         ret = psp_load_non_psp_fw(psp);
2742         if (ret)
2743                 goto failed;
2744
2745         ret = psp_asd_initialize(psp);
2746         if (ret) {
2747                 DRM_ERROR("PSP load asd failed!\n");
2748                 goto failed;
2749         }
2750
2751         ret = psp_rl_load(adev);
2752         if (ret) {
2753                 dev_err(adev->dev, "PSP load RL failed!\n");
2754                 goto failed;
2755         }
2756
2757         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2758                 ret = psp_xgmi_initialize(psp, false, true);
2759                 /* Warning the XGMI seesion initialize failure
2760                  * Instead of stop driver initialization
2761                  */
2762                 if (ret)
2763                         dev_err(psp->adev->dev,
2764                                 "XGMI: Failed to initialize XGMI session\n");
2765         }
2766
2767         if (psp->ta_fw) {
2768                 ret = psp_ras_initialize(psp);
2769                 if (ret)
2770                         dev_err(psp->adev->dev,
2771                                         "RAS: Failed to initialize RAS\n");
2772
2773                 ret = psp_hdcp_initialize(psp);
2774                 if (ret)
2775                         dev_err(psp->adev->dev,
2776                                 "HDCP: Failed to initialize HDCP\n");
2777
2778                 ret = psp_dtm_initialize(psp);
2779                 if (ret)
2780                         dev_err(psp->adev->dev,
2781                                 "DTM: Failed to initialize DTM\n");
2782
2783                 ret = psp_rap_initialize(psp);
2784                 if (ret)
2785                         dev_err(psp->adev->dev,
2786                                 "RAP: Failed to initialize RAP\n");
2787
2788                 ret = psp_securedisplay_initialize(psp);
2789                 if (ret)
2790                         dev_err(psp->adev->dev,
2791                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2792         }
2793
2794         mutex_unlock(&adev->firmware.mutex);
2795
2796         return 0;
2797
2798 failed:
2799         DRM_ERROR("PSP resume failed\n");
2800         mutex_unlock(&adev->firmware.mutex);
2801         return ret;
2802 }
2803
2804 int psp_gpu_reset(struct amdgpu_device *adev)
2805 {
2806         int ret;
2807
2808         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2809                 return 0;
2810
2811         mutex_lock(&adev->psp.mutex);
2812         ret = psp_mode1_reset(&adev->psp);
2813         mutex_unlock(&adev->psp.mutex);
2814
2815         return ret;
2816 }
2817
2818 int psp_rlc_autoload_start(struct psp_context *psp)
2819 {
2820         int ret;
2821         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2822
2823         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2824
2825         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2826                                  psp->fence_buf_mc_addr);
2827
2828         release_psp_cmd_buf(psp);
2829
2830         return ret;
2831 }
2832
2833 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2834                         uint64_t cmd_gpu_addr, int cmd_size)
2835 {
2836         struct amdgpu_firmware_info ucode = {0};
2837
2838         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2839                 AMDGPU_UCODE_ID_VCN0_RAM;
2840         ucode.mc_addr = cmd_gpu_addr;
2841         ucode.ucode_size = cmd_size;
2842
2843         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2844 }
2845
2846 int psp_ring_cmd_submit(struct psp_context *psp,
2847                         uint64_t cmd_buf_mc_addr,
2848                         uint64_t fence_mc_addr,
2849                         int index)
2850 {
2851         unsigned int psp_write_ptr_reg = 0;
2852         struct psp_gfx_rb_frame *write_frame;
2853         struct psp_ring *ring = &psp->km_ring;
2854         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2855         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2856                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2857         struct amdgpu_device *adev = psp->adev;
2858         uint32_t ring_size_dw = ring->ring_size / 4;
2859         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2860
2861         /* KM (GPCOM) prepare write pointer */
2862         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2863
2864         /* Update KM RB frame pointer to new frame */
2865         /* write_frame ptr increments by size of rb_frame in bytes */
2866         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2867         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2868                 write_frame = ring_buffer_start;
2869         else
2870                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2871         /* Check invalid write_frame ptr address */
2872         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2873                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2874                           ring_buffer_start, ring_buffer_end, write_frame);
2875                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2876                 return -EINVAL;
2877         }
2878
2879         /* Initialize KM RB frame */
2880         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2881
2882         /* Update KM RB frame */
2883         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2884         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2885         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2886         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2887         write_frame->fence_value = index;
2888         amdgpu_device_flush_hdp(adev, NULL);
2889
2890         /* Update the write Pointer in DWORDs */
2891         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2892         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2893         return 0;
2894 }
2895
2896 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2897 {
2898         struct amdgpu_device *adev = psp->adev;
2899         char fw_name[PSP_FW_NAME_LEN];
2900         const struct psp_firmware_header_v1_0 *asd_hdr;
2901         int err = 0;
2902
2903         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2904         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
2905         if (err)
2906                 goto out;
2907
2908         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2909         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2910         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2911         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2912         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2913                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2914         return 0;
2915 out:
2916         amdgpu_ucode_release(&adev->psp.asd_fw);
2917         return err;
2918 }
2919
2920 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
2921 {
2922         struct amdgpu_device *adev = psp->adev;
2923         char fw_name[PSP_FW_NAME_LEN];
2924         const struct psp_firmware_header_v1_0 *toc_hdr;
2925         int err = 0;
2926
2927         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2928         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
2929         if (err)
2930                 goto out;
2931
2932         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2933         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2934         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2935         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2936         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2937                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2938         return 0;
2939 out:
2940         amdgpu_ucode_release(&adev->psp.toc_fw);
2941         return err;
2942 }
2943
2944 static int parse_sos_bin_descriptor(struct psp_context *psp,
2945                                    const struct psp_fw_bin_desc *desc,
2946                                    const struct psp_firmware_header_v2_0 *sos_hdr)
2947 {
2948         uint8_t *ucode_start_addr  = NULL;
2949
2950         if (!psp || !desc || !sos_hdr)
2951                 return -EINVAL;
2952
2953         ucode_start_addr  = (uint8_t *)sos_hdr +
2954                             le32_to_cpu(desc->offset_bytes) +
2955                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2956
2957         switch (desc->fw_type) {
2958         case PSP_FW_TYPE_PSP_SOS:
2959                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
2960                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
2961                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
2962                 psp->sos.start_addr        = ucode_start_addr;
2963                 break;
2964         case PSP_FW_TYPE_PSP_SYS_DRV:
2965                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
2966                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
2967                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
2968                 psp->sys.start_addr        = ucode_start_addr;
2969                 break;
2970         case PSP_FW_TYPE_PSP_KDB:
2971                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
2972                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
2973                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
2974                 psp->kdb.start_addr        = ucode_start_addr;
2975                 break;
2976         case PSP_FW_TYPE_PSP_TOC:
2977                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
2978                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
2979                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
2980                 psp->toc.start_addr        = ucode_start_addr;
2981                 break;
2982         case PSP_FW_TYPE_PSP_SPL:
2983                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
2984                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
2985                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
2986                 psp->spl.start_addr        = ucode_start_addr;
2987                 break;
2988         case PSP_FW_TYPE_PSP_RL:
2989                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
2990                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
2991                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
2992                 psp->rl.start_addr         = ucode_start_addr;
2993                 break;
2994         case PSP_FW_TYPE_PSP_SOC_DRV:
2995                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
2996                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
2997                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
2998                 psp->soc_drv.start_addr         = ucode_start_addr;
2999                 break;
3000         case PSP_FW_TYPE_PSP_INTF_DRV:
3001                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3002                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3003                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3004                 psp->intf_drv.start_addr        = ucode_start_addr;
3005                 break;
3006         case PSP_FW_TYPE_PSP_DBG_DRV:
3007                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3008                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3009                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3010                 psp->dbg_drv.start_addr         = ucode_start_addr;
3011                 break;
3012         case PSP_FW_TYPE_PSP_RAS_DRV:
3013                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3014                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3015                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3016                 psp->ras_drv.start_addr         = ucode_start_addr;
3017                 break;
3018         default:
3019                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3020                 break;
3021         }
3022
3023         return 0;
3024 }
3025
3026 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3027 {
3028         const struct psp_firmware_header_v1_0 *sos_hdr;
3029         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3030         uint8_t *ucode_array_start_addr;
3031
3032         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3033         ucode_array_start_addr = (uint8_t *)sos_hdr +
3034                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3035
3036         if (adev->gmc.xgmi.connected_to_cpu ||
3037             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3038                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3039                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3040
3041                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3042                 adev->psp.sys.start_addr = ucode_array_start_addr;
3043
3044                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3045                 adev->psp.sos.start_addr = ucode_array_start_addr +
3046                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3047         } else {
3048                 /* Load alternate PSP SOS FW */
3049                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3050
3051                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3052                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3053
3054                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3055                 adev->psp.sys.start_addr = ucode_array_start_addr +
3056                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3057
3058                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3059                 adev->psp.sos.start_addr = ucode_array_start_addr +
3060                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3061         }
3062
3063         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3064                 dev_warn(adev->dev, "PSP SOS FW not available");
3065                 return -EINVAL;
3066         }
3067
3068         return 0;
3069 }
3070
3071 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3072 {
3073         struct amdgpu_device *adev = psp->adev;
3074         char fw_name[PSP_FW_NAME_LEN];
3075         const struct psp_firmware_header_v1_0 *sos_hdr;
3076         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3077         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3078         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3079         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3080         int err = 0;
3081         uint8_t *ucode_array_start_addr;
3082         int fw_index = 0;
3083
3084         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3085         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3086         if (err)
3087                 goto out;
3088
3089         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3090         ucode_array_start_addr = (uint8_t *)sos_hdr +
3091                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3092         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3093
3094         switch (sos_hdr->header.header_version_major) {
3095         case 1:
3096                 err = psp_init_sos_base_fw(adev);
3097                 if (err)
3098                         goto out;
3099
3100                 if (sos_hdr->header.header_version_minor == 1) {
3101                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3102                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3103                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3104                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3105                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3106                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3107                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3108                 }
3109                 if (sos_hdr->header.header_version_minor == 2) {
3110                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3111                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3112                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3113                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3114                 }
3115                 if (sos_hdr->header.header_version_minor == 3) {
3116                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3117                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3118                         adev->psp.toc.start_addr = ucode_array_start_addr +
3119                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3120                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3121                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3122                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3123                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3124                         adev->psp.spl.start_addr = ucode_array_start_addr +
3125                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3126                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3127                         adev->psp.rl.start_addr = ucode_array_start_addr +
3128                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3129                 }
3130                 break;
3131         case 2:
3132                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3133
3134                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3135                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3136                         err = -EINVAL;
3137                         goto out;
3138                 }
3139
3140                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3141                         err = parse_sos_bin_descriptor(psp,
3142                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3143                                                        sos_hdr_v2_0);
3144                         if (err)
3145                                 goto out;
3146                 }
3147                 break;
3148         default:
3149                 dev_err(adev->dev,
3150                         "unsupported psp sos firmware\n");
3151                 err = -EINVAL;
3152                 goto out;
3153         }
3154
3155         return 0;
3156 out:
3157         amdgpu_ucode_release(&adev->psp.sos_fw);
3158
3159         return err;
3160 }
3161
3162 static int parse_ta_bin_descriptor(struct psp_context *psp,
3163                                    const struct psp_fw_bin_desc *desc,
3164                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3165 {
3166         uint8_t *ucode_start_addr  = NULL;
3167
3168         if (!psp || !desc || !ta_hdr)
3169                 return -EINVAL;
3170
3171         ucode_start_addr  = (uint8_t *)ta_hdr +
3172                             le32_to_cpu(desc->offset_bytes) +
3173                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3174
3175         switch (desc->fw_type) {
3176         case TA_FW_TYPE_PSP_ASD:
3177                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3178                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3179                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3180                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3181                 break;
3182         case TA_FW_TYPE_PSP_XGMI:
3183                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3184                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3185                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3186                 break;
3187         case TA_FW_TYPE_PSP_RAS:
3188                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3189                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3190                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3191                 break;
3192         case TA_FW_TYPE_PSP_HDCP:
3193                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3194                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3195                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3196                 break;
3197         case TA_FW_TYPE_PSP_DTM:
3198                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3199                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3200                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3201                 break;
3202         case TA_FW_TYPE_PSP_RAP:
3203                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3204                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3205                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3206                 break;
3207         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3208                 psp->securedisplay_context.context.bin_desc.fw_version =
3209                         le32_to_cpu(desc->fw_version);
3210                 psp->securedisplay_context.context.bin_desc.size_bytes =
3211                         le32_to_cpu(desc->size_bytes);
3212                 psp->securedisplay_context.context.bin_desc.start_addr =
3213                         ucode_start_addr;
3214                 break;
3215         default:
3216                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3217                 break;
3218         }
3219
3220         return 0;
3221 }
3222
3223 static int parse_ta_v1_microcode(struct psp_context *psp)
3224 {
3225         const struct ta_firmware_header_v1_0 *ta_hdr;
3226         struct amdgpu_device *adev = psp->adev;
3227
3228         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3229
3230         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3231                 return -EINVAL;
3232
3233         adev->psp.xgmi_context.context.bin_desc.fw_version =
3234                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3235         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3236                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3237         adev->psp.xgmi_context.context.bin_desc.start_addr =
3238                 (uint8_t *)ta_hdr +
3239                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3240
3241         adev->psp.ras_context.context.bin_desc.fw_version =
3242                 le32_to_cpu(ta_hdr->ras.fw_version);
3243         adev->psp.ras_context.context.bin_desc.size_bytes =
3244                 le32_to_cpu(ta_hdr->ras.size_bytes);
3245         adev->psp.ras_context.context.bin_desc.start_addr =
3246                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3247                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3248
3249         adev->psp.hdcp_context.context.bin_desc.fw_version =
3250                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3251         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3252                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3253         adev->psp.hdcp_context.context.bin_desc.start_addr =
3254                 (uint8_t *)ta_hdr +
3255                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3256
3257         adev->psp.dtm_context.context.bin_desc.fw_version =
3258                 le32_to_cpu(ta_hdr->dtm.fw_version);
3259         adev->psp.dtm_context.context.bin_desc.size_bytes =
3260                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3261         adev->psp.dtm_context.context.bin_desc.start_addr =
3262                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3263                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3264
3265         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3266                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3267         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3268                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3269         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3270                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3271                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3272
3273         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3274
3275         return 0;
3276 }
3277
3278 static int parse_ta_v2_microcode(struct psp_context *psp)
3279 {
3280         const struct ta_firmware_header_v2_0 *ta_hdr;
3281         struct amdgpu_device *adev = psp->adev;
3282         int err = 0;
3283         int ta_index = 0;
3284
3285         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3286
3287         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3288                 return -EINVAL;
3289
3290         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3291                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3292                 return -EINVAL;
3293         }
3294
3295         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3296                 err = parse_ta_bin_descriptor(psp,
3297                                               &ta_hdr->ta_fw_bin[ta_index],
3298                                               ta_hdr);
3299                 if (err)
3300                         return err;
3301         }
3302
3303         return 0;
3304 }
3305
3306 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3307 {
3308         const struct common_firmware_header *hdr;
3309         struct amdgpu_device *adev = psp->adev;
3310         char fw_name[PSP_FW_NAME_LEN];
3311         int err;
3312
3313         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3314         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3315         if (err)
3316                 return err;
3317
3318         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3319         switch (le16_to_cpu(hdr->header_version_major)) {
3320         case 1:
3321                 err = parse_ta_v1_microcode(psp);
3322                 break;
3323         case 2:
3324                 err = parse_ta_v2_microcode(psp);
3325                 break;
3326         default:
3327                 dev_err(adev->dev, "unsupported TA header version\n");
3328                 err = -EINVAL;
3329         }
3330
3331         if (err)
3332                 amdgpu_ucode_release(&adev->psp.ta_fw);
3333
3334         return err;
3335 }
3336
3337 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3338 {
3339         struct amdgpu_device *adev = psp->adev;
3340         char fw_name[PSP_FW_NAME_LEN];
3341         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3342         struct amdgpu_firmware_info *info = NULL;
3343         int err = 0;
3344
3345         if (!amdgpu_sriov_vf(adev)) {
3346                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3347                 return -EINVAL;
3348         }
3349
3350         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3351         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3352         if (err) {
3353                 if (err == -ENODEV) {
3354                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3355                         err = 0;
3356                         goto out;
3357                 }
3358                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3359         }
3360
3361         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3362         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3363         info->fw = adev->psp.cap_fw;
3364         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3365                 adev->psp.cap_fw->data;
3366         adev->firmware.fw_size += ALIGN(
3367                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3368         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3369         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3370         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3371
3372         return 0;
3373
3374 out:
3375         amdgpu_ucode_release(&adev->psp.cap_fw);
3376         return err;
3377 }
3378
3379 static int psp_set_clockgating_state(void *handle,
3380                                      enum amd_clockgating_state state)
3381 {
3382         return 0;
3383 }
3384
3385 static int psp_set_powergating_state(void *handle,
3386                                      enum amd_powergating_state state)
3387 {
3388         return 0;
3389 }
3390
3391 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3392                                          struct device_attribute *attr,
3393                                          char *buf)
3394 {
3395         struct drm_device *ddev = dev_get_drvdata(dev);
3396         struct amdgpu_device *adev = drm_to_adev(ddev);
3397         uint32_t fw_ver;
3398         int ret;
3399
3400         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3401                 DRM_INFO("PSP block is not ready yet.");
3402                 return -EBUSY;
3403         }
3404
3405         mutex_lock(&adev->psp.mutex);
3406         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3407         mutex_unlock(&adev->psp.mutex);
3408
3409         if (ret) {
3410                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3411                 return ret;
3412         }
3413
3414         return sysfs_emit(buf, "%x\n", fw_ver);
3415 }
3416
3417 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3418                                                        struct device_attribute *attr,
3419                                                        const char *buf,
3420                                                        size_t count)
3421 {
3422         struct drm_device *ddev = dev_get_drvdata(dev);
3423         struct amdgpu_device *adev = drm_to_adev(ddev);
3424         int ret, idx;
3425         char fw_name[100];
3426         const struct firmware *usbc_pd_fw;
3427         struct amdgpu_bo *fw_buf_bo = NULL;
3428         uint64_t fw_pri_mc_addr;
3429         void *fw_pri_cpu_addr;
3430
3431         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3432                 DRM_INFO("PSP block is not ready yet.");
3433                 return -EBUSY;
3434         }
3435
3436         if (!drm_dev_enter(ddev, &idx))
3437                 return -ENODEV;
3438
3439         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3440         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3441         if (ret)
3442                 goto fail;
3443
3444         /* LFB address which is aligned to 1MB boundary per PSP request */
3445         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3446                                       AMDGPU_GEM_DOMAIN_VRAM |
3447                                       AMDGPU_GEM_DOMAIN_GTT,
3448                                       &fw_buf_bo, &fw_pri_mc_addr,
3449                                       &fw_pri_cpu_addr);
3450         if (ret)
3451                 goto rel_buf;
3452
3453         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3454
3455         mutex_lock(&adev->psp.mutex);
3456         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3457         mutex_unlock(&adev->psp.mutex);
3458
3459         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3460
3461 rel_buf:
3462         release_firmware(usbc_pd_fw);
3463 fail:
3464         if (ret) {
3465                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3466                 count = ret;
3467         }
3468
3469         drm_dev_exit(idx);
3470         return count;
3471 }
3472
3473 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3474 {
3475         int idx;
3476
3477         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3478                 return;
3479
3480         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3481         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3482
3483         drm_dev_exit(idx);
3484 }
3485
3486 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3487                    psp_usbc_pd_fw_sysfs_read,
3488                    psp_usbc_pd_fw_sysfs_write);
3489
3490 int is_psp_fw_valid(struct psp_bin_desc bin)
3491 {
3492         return bin.size_bytes;
3493 }
3494
3495 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3496                                         struct bin_attribute *bin_attr,
3497                                         char *buffer, loff_t pos, size_t count)
3498 {
3499         struct device *dev = kobj_to_dev(kobj);
3500         struct drm_device *ddev = dev_get_drvdata(dev);
3501         struct amdgpu_device *adev = drm_to_adev(ddev);
3502
3503         adev->psp.vbflash_done = false;
3504
3505         /* Safeguard against memory drain */
3506         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3507                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3508                 kvfree(adev->psp.vbflash_tmp_buf);
3509                 adev->psp.vbflash_tmp_buf = NULL;
3510                 adev->psp.vbflash_image_size = 0;
3511                 return -ENOMEM;
3512         }
3513
3514         /* TODO Just allocate max for now and optimize to realloc later if needed */
3515         if (!adev->psp.vbflash_tmp_buf) {
3516                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3517                 if (!adev->psp.vbflash_tmp_buf)
3518                         return -ENOMEM;
3519         }
3520
3521         mutex_lock(&adev->psp.mutex);
3522         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3523         adev->psp.vbflash_image_size += count;
3524         mutex_unlock(&adev->psp.mutex);
3525
3526         dev_info(adev->dev, "VBIOS flash write PSP done");
3527
3528         return count;
3529 }
3530
3531 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3532                                        struct bin_attribute *bin_attr, char *buffer,
3533                                        loff_t pos, size_t count)
3534 {
3535         struct device *dev = kobj_to_dev(kobj);
3536         struct drm_device *ddev = dev_get_drvdata(dev);
3537         struct amdgpu_device *adev = drm_to_adev(ddev);
3538         struct amdgpu_bo *fw_buf_bo = NULL;
3539         uint64_t fw_pri_mc_addr;
3540         void *fw_pri_cpu_addr;
3541         int ret;
3542
3543         dev_info(adev->dev, "VBIOS flash to PSP started");
3544
3545         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3546                                         AMDGPU_GPU_PAGE_SIZE,
3547                                         AMDGPU_GEM_DOMAIN_VRAM,
3548                                         &fw_buf_bo,
3549                                         &fw_pri_mc_addr,
3550                                         &fw_pri_cpu_addr);
3551         if (ret)
3552                 goto rel_buf;
3553
3554         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3555
3556         mutex_lock(&adev->psp.mutex);
3557         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3558         mutex_unlock(&adev->psp.mutex);
3559
3560         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3561
3562 rel_buf:
3563         kvfree(adev->psp.vbflash_tmp_buf);
3564         adev->psp.vbflash_tmp_buf = NULL;
3565         adev->psp.vbflash_image_size = 0;
3566
3567         if (ret) {
3568                 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3569                 return ret;
3570         }
3571
3572         dev_info(adev->dev, "VBIOS flash to PSP done");
3573         return 0;
3574 }
3575
3576 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3577                                          struct device_attribute *attr,
3578                                          char *buf)
3579 {
3580         struct drm_device *ddev = dev_get_drvdata(dev);
3581         struct amdgpu_device *adev = drm_to_adev(ddev);
3582         uint32_t vbflash_status;
3583
3584         vbflash_status = psp_vbflash_status(&adev->psp);
3585         if (!adev->psp.vbflash_done)
3586                 vbflash_status = 0;
3587         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3588                 vbflash_status = 1;
3589
3590         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3591 }
3592
3593 static const struct bin_attribute psp_vbflash_bin_attr = {
3594         .attr = {.name = "psp_vbflash", .mode = 0664},
3595         .size = 0,
3596         .write = amdgpu_psp_vbflash_write,
3597         .read = amdgpu_psp_vbflash_read,
3598 };
3599
3600 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3601
3602 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3603 {
3604         int ret = 0;
3605         struct psp_context *psp = &adev->psp;
3606
3607         if (amdgpu_sriov_vf(adev))
3608                 return -EINVAL;
3609
3610         switch (adev->ip_versions[MP0_HWIP][0]) {
3611         case IP_VERSION(13, 0, 0):
3612         case IP_VERSION(13, 0, 7):
3613                 if (!psp->adev) {
3614                         psp->adev = adev;
3615                         psp_v13_0_set_psp_funcs(psp);
3616                 }
3617                 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3618                 if (ret)
3619                         dev_err(adev->dev, "Failed to create device file psp_vbflash");
3620                 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3621                 if (ret)
3622                         dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3623                 return ret;
3624         default:
3625                 return 0;
3626         }
3627 }
3628
3629 const struct amd_ip_funcs psp_ip_funcs = {
3630         .name = "psp",
3631         .early_init = psp_early_init,
3632         .late_init = NULL,
3633         .sw_init = psp_sw_init,
3634         .sw_fini = psp_sw_fini,
3635         .hw_init = psp_hw_init,
3636         .hw_fini = psp_hw_fini,
3637         .suspend = psp_suspend,
3638         .resume = psp_resume,
3639         .is_idle = NULL,
3640         .check_soft_reset = NULL,
3641         .wait_for_idle = NULL,
3642         .soft_reset = NULL,
3643         .set_clockgating_state = psp_set_clockgating_state,
3644         .set_powergating_state = psp_set_powergating_state,
3645 };
3646
3647 static int psp_sysfs_init(struct amdgpu_device *adev)
3648 {
3649         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3650
3651         if (ret)
3652                 DRM_ERROR("Failed to create USBC PD FW control file!");
3653
3654         return ret;
3655 }
3656
3657 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3658 {
3659         sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3660         device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3661 }
3662
3663 static void psp_sysfs_fini(struct amdgpu_device *adev)
3664 {
3665         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3666 }
3667
3668 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3669 {
3670         .type = AMD_IP_BLOCK_TYPE_PSP,
3671         .major = 3,
3672         .minor = 1,
3673         .rev = 0,
3674         .funcs = &psp_ip_funcs,
3675 };
3676
3677 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3678 {
3679         .type = AMD_IP_BLOCK_TYPE_PSP,
3680         .major = 10,
3681         .minor = 0,
3682         .rev = 0,
3683         .funcs = &psp_ip_funcs,
3684 };
3685
3686 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3687 {
3688         .type = AMD_IP_BLOCK_TYPE_PSP,
3689         .major = 11,
3690         .minor = 0,
3691         .rev = 0,
3692         .funcs = &psp_ip_funcs,
3693 };
3694
3695 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3696         .type = AMD_IP_BLOCK_TYPE_PSP,
3697         .major = 11,
3698         .minor = 0,
3699         .rev = 8,
3700         .funcs = &psp_ip_funcs,
3701 };
3702
3703 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3704 {
3705         .type = AMD_IP_BLOCK_TYPE_PSP,
3706         .major = 12,
3707         .minor = 0,
3708         .rev = 0,
3709         .funcs = &psp_ip_funcs,
3710 };
3711
3712 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3713         .type = AMD_IP_BLOCK_TYPE_PSP,
3714         .major = 13,
3715         .minor = 0,
3716         .rev = 0,
3717         .funcs = &psp_ip_funcs,
3718 };
3719
3720 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3721         .type = AMD_IP_BLOCK_TYPE_PSP,
3722         .major = 13,
3723         .minor = 0,
3724         .rev = 4,
3725         .funcs = &psp_ip_funcs,
3726 };