drivers/gpu/drm/tegra/hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Avionic Design GmbH
   4  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/delay.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/math64.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19
  20 #include <soc/tegra/common.h>
  21 #include <sound/hdmi-codec.h>
  22
  23 #include <drm/drm_bridge_connector.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_debugfs.h>
  27 #include <drm/drm_eld.h>
  28 #include <drm/drm_file.h>
  29 #include <drm/drm_fourcc.h>
  30 #include <drm/drm_probe_helper.h>
  31 #include <drm/drm_simple_kms_helper.h>
  32
  33 #include "hda.h"
  34 #include "hdmi.h"
  35 #include "drm.h"
  36 #include "dc.h"
  37 #include "trace.h"
  38
  39 #define HDMI_ELD_BUFFER_SIZE 96
  40
  41 struct tmds_config {
  42         unsigned int pclk;
  43         u32 pll0;
  44         u32 pll1;
  45         u32 pe_current;
  46         u32 drive_current;
  47         u32 peak_current;
  48 };
  49
  50 struct tegra_hdmi_config {
  51         const struct tmds_config *tmds;
  52         unsigned int num_tmds;
  53
  54         unsigned long fuse_override_offset;
  55         u32 fuse_override_value;
  56
  57         bool has_sor_io_peak_current;
  58         bool has_hda;
  59         bool has_hbr;
  60 };
  61
  62 struct tegra_hdmi {
  63         struct host1x_client client;
  64         struct tegra_output output;
  65         struct device *dev;
  66
  67         struct regulator *hdmi;
  68         struct regulator *pll;
  69         struct regulator *vdd;
  70
  71         void __iomem *regs;
  72         unsigned int irq;
  73
  74         struct clk *clk_parent;
  75         struct clk *clk;
  76         struct reset_control *rst;
  77
  78         const struct tegra_hdmi_config *config;
  79
  80         unsigned int audio_source;
  81         struct tegra_hda_format format;
  82
  83         unsigned int pixel_clock;
  84         bool stereo;
  85         bool dvi;
  86
  87         struct drm_info_list *debugfs_files;
  88
  89         struct platform_device *audio_pdev;
  90         struct mutex audio_lock;
  91 };
  92
  93 static inline struct tegra_hdmi *
  94 host1x_client_to_hdmi(struct host1x_client *client)
  95 {
  96         return container_of(client, struct tegra_hdmi, client);
  97 }
  98
  99 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
 100 {
 101         return container_of(output, struct tegra_hdmi, output);
 102 }
 103
 104 #define HDMI_AUDIOCLK_FREQ 216000000
 105 #define HDMI_REKEY_DEFAULT 56
 106
 107 enum {
 108         AUTO = 0,
 109         SPDIF,
 110         HDA,
 111 };
 112
 113 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
 114                                    unsigned int offset)
 115 {
 116         u32 value = readl(hdmi->regs + (offset << 2));
 117
 118         trace_hdmi_readl(hdmi->dev, offset, value);
 119
 120         return value;
 121 }
 122
 123 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
 124                                      unsigned int offset)
 125 {
 126         trace_hdmi_writel(hdmi->dev, offset, value);
 127         writel(value, hdmi->regs + (offset << 2));
 128 }
 129
 130 struct tegra_hdmi_audio_config {
 131         unsigned int n;
 132         unsigned int cts;
 133         unsigned int aval;
 134 };
 135
 136 static const struct tmds_config tegra20_tmds_config[] = {
 137         { /* slow pixel clock modes */
 138                 .pclk = 27000000,
 139                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 140                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 141                         SOR_PLL_TX_REG_LOAD(3),
 142                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 143                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 144                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 145                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 146                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 147                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 148                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 149                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 150                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 151         },
 152         { /* high pixel clock modes */
 153                 .pclk = UINT_MAX,
 154                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 155                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 156                         SOR_PLL_TX_REG_LOAD(3),
 157                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 158                 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
 159                         PE_CURRENT1(PE_CURRENT_6_0_mA) |
 160                         PE_CURRENT2(PE_CURRENT_6_0_mA) |
 161                         PE_CURRENT3(PE_CURRENT_6_0_mA),
 162                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 163                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 164                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 165                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 166         },
 167 };
 168
 169 static const struct tmds_config tegra30_tmds_config[] = {
 170         { /* 480p modes */
 171                 .pclk = 27000000,
 172                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 173                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 174                         SOR_PLL_TX_REG_LOAD(0),
 175                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 176                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 177                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 178                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 179                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 180                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 181                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 182                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 183                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 184         }, { /* 720p modes */
 185                 .pclk = 74250000,
 186                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 187                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 188                         SOR_PLL_TX_REG_LOAD(0),
 189                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 190                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 191                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 192                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 193                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 194                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 195                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 196                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 197                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 198         }, { /* 1080p modes */
 199                 .pclk = UINT_MAX,
 200                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 201                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
 202                         SOR_PLL_TX_REG_LOAD(0),
 203                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 204                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 205                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 206                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 207                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 208                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 209                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 210                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 211                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 212         },
 213 };
 214
 215 static const struct tmds_config tegra114_tmds_config[] = {
 216         { /* 480p/576p / 25.2MHz/27MHz modes */
 217                 .pclk = 27000000,
 218                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 219                         SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
 220                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 221                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 222                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 223                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 224                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 225                 .drive_current =
 226                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 227                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 228                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 229                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 230                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 231                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 232                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 233                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 234         }, { /* 720p / 74.25MHz modes */
 235                 .pclk = 74250000,
 236                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 237                         SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
 238                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 239                         SOR_PLL_TMDS_TERMADJ(0),
 240                 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
 241                         PE_CURRENT1(PE_CURRENT_15_mA_T114) |
 242                         PE_CURRENT2(PE_CURRENT_15_mA_T114) |
 243                         PE_CURRENT3(PE_CURRENT_15_mA_T114),
 244                 .drive_current =
 245                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 246                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 247                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 248                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 249                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 250                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 251                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 252                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 253         }, { /* 1080p / 148.5MHz modes */
 254                 .pclk = 148500000,
 255                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 256                         SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
 257                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 258                         SOR_PLL_TMDS_TERMADJ(0),
 259                 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
 260                         PE_CURRENT1(PE_CURRENT_10_mA_T114) |
 261                         PE_CURRENT2(PE_CURRENT_10_mA_T114) |
 262                         PE_CURRENT3(PE_CURRENT_10_mA_T114),
 263                 .drive_current =
 264                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
 265                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
 266                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
 267                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
 268                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 269                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 270                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 271                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 272         }, { /* 225/297MHz modes */
 273                 .pclk = UINT_MAX,
 274                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 275                         SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
 276                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 277                         | SOR_PLL_TMDS_TERM_ENABLE,
 278                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 279                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 280                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 281                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 282                 .drive_current =
 283                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
 284                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
 285                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
 286                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
 287                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
 288                         PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
 289                         PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
 290                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
 291         },
 292 };
 293
 294 static const struct tmds_config tegra124_tmds_config[] = {
 295         { /* 480p/576p / 25.2MHz/27MHz modes */
 296                 .pclk = 27000000,
 297                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 298                         SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
 299                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 300                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 301                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 302                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 303                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 304                 .drive_current =
 305                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 306                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 307                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 308                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 309                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 310                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 311                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 312                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 313         }, { /* 720p / 74.25MHz modes */
 314                 .pclk = 74250000,
 315                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 316                         SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
 317                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 318                         SOR_PLL_TMDS_TERMADJ(0),
 319                 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
 320                         PE_CURRENT1(PE_CURRENT_15_mA_T114) |
 321                         PE_CURRENT2(PE_CURRENT_15_mA_T114) |
 322                         PE_CURRENT3(PE_CURRENT_15_mA_T114),
 323                 .drive_current =
 324                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 325                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 326                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 327                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 328                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 329                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 330                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 331                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 332         }, { /* 1080p / 148.5MHz modes */
 333                 .pclk = 148500000,
 334                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 335                         SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
 336                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 337                         SOR_PLL_TMDS_TERMADJ(0),
 338                 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
 339                         PE_CURRENT1(PE_CURRENT_10_mA_T114) |
 340                         PE_CURRENT2(PE_CURRENT_10_mA_T114) |
 341                         PE_CURRENT3(PE_CURRENT_10_mA_T114),
 342                 .drive_current =
 343                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
 344                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
 345                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
 346                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
 347                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 348                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 349                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 350                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 351         }, { /* 225/297MHz modes */
 352                 .pclk = UINT_MAX,
 353                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 354                         SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
 355                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 356                         | SOR_PLL_TMDS_TERM_ENABLE,
 357                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 358                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 359                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 360                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 361                 .drive_current =
 362                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
 363                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
 364                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
 365                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
 366                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
 367                         PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
 368                         PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
 369                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
 370         },
 371 };
 372
 373 static void tegra_hdmi_audio_lock(struct tegra_hdmi *hdmi)
 374 {
 375         mutex_lock(&hdmi->audio_lock);
 376         disable_irq(hdmi->irq);
 377 }
 378
 379 static void tegra_hdmi_audio_unlock(struct tegra_hdmi *hdmi)
 380 {
 381         enable_irq(hdmi->irq);
 382         mutex_unlock(&hdmi->audio_lock);
 383 }
 384
 385 static int
 386 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
 387                             struct tegra_hdmi_audio_config *config)
 388 {
 389         const unsigned int afreq = 128 * audio_freq;
 390         const unsigned int min_n = afreq / 1500;
 391         const unsigned int max_n = afreq / 300;
 392         const unsigned int ideal_n = afreq / 1000;
 393         int64_t min_err = (uint64_t)-1 >> 1;
 394         unsigned int min_delta = -1;
 395         int n;
 396
 397         memset(config, 0, sizeof(*config));
 398         config->n = -1;
 399
 400         for (n = min_n; n <= max_n; n++) {
 401                 uint64_t cts_f, aval_f;
 402                 unsigned int delta;
 403                 int64_t cts, err;
 404
 405                 /* compute aval in 48.16 fixed point */
 406                 aval_f = ((int64_t)24000000 << 16) * n;
 407                 do_div(aval_f, afreq);
 408                 /* It should round without any rest */
 409                 if (aval_f & 0xFFFF)
 410                         continue;
 411
 412                 /* Compute cts in 48.16 fixed point */
 413                 cts_f = ((int64_t)pix_clock << 16) * n;
 414                 do_div(cts_f, afreq);
 415                 /* Round it to the nearest integer */
 416                 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
 417
 418                 delta = abs(n - ideal_n);
 419
 420                 /* Compute the absolute error */
 421                 err = abs((int64_t)cts_f - cts);
 422                 if (err < min_err || (err == min_err && delta < min_delta)) {
 423                         config->n = n;
 424                         config->cts = cts >> 16;
 425                         config->aval = aval_f >> 16;
 426                         min_delta = delta;
 427                         min_err = err;
 428                 }
 429         }
 430
 431         return config->n != -1 ? 0 : -EINVAL;
 432 }
 433
 434 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
 435 {
 436         const unsigned int freqs[] = {
 437                 32000, 44100, 48000, 88200, 96000, 176400, 192000
 438         };
 439         unsigned int i;
 440
 441         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 442                 unsigned int f = freqs[i];
 443                 unsigned int eight_half;
 444                 unsigned int delta;
 445                 u32 value;
 446
 447                 if (f > 96000)
 448                         delta = 2;
 449                 else if (f > 48000)
 450                         delta = 6;
 451                 else
 452                         delta = 9;
 453
 454                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 455                 value = AUDIO_FS_LOW(eight_half - delta) |
 456                         AUDIO_FS_HIGH(eight_half + delta);
 457                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
 458         }
 459 }
 460
 461 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
 462 {
 463         static const struct {
 464                 unsigned int sample_rate;
 465                 unsigned int offset;
 466         } regs[] = {
 467                 {  32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
 468                 {  44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
 469                 {  48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
 470                 {  88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
 471                 {  96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
 472                 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
 473                 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
 474         };
 475         unsigned int i;
 476
 477         for (i = 0; i < ARRAY_SIZE(regs); i++) {
 478                 if (regs[i].sample_rate == hdmi->format.sample_rate) {
 479                         tegra_hdmi_writel(hdmi, value, regs[i].offset);
 480                         break;
 481                 }
 482         }
 483 }
 484
 485 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
 486 {
 487         struct tegra_hdmi_audio_config config;
 488         u32 source, value;
 489         int err;
 490
 491         switch (hdmi->audio_source) {
 492         case HDA:
 493                 if (hdmi->config->has_hda)
 494                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
 495                 else
 496                         return -EINVAL;
 497
 498                 break;
 499
 500         case SPDIF:
 501                 if (hdmi->config->has_hda)
 502                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 503                 else
 504                         source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 505                 break;
 506
 507         default:
 508                 if (hdmi->config->has_hda)
 509                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 510                 else
 511                         source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 512                 break;
 513         }
 514
 515         /*
 516          * Tegra30 and later use a slightly modified version of the register
 517          * layout to accomodate for changes related to supporting HDA as the
 518          * audio input source for HDMI. The source select field has moved to
 519          * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
 520          * per block fields remain in the AUDIO_CNTRL0 register.
 521          */
 522         if (hdmi->config->has_hda) {
 523                 /*
 524                  * Inject null samples into the audio FIFO for every frame in
 525                  * which the codec did not receive any samples. This applies
 526                  * to stereo LPCM only.
 527                  *
 528                  * XXX: This seems to be a remnant of MCP days when this was
 529                  * used to work around issues with monitors not being able to
 530                  * play back system startup sounds early. It is possibly not
 531                  * needed on Linux at all.
 532                  */
 533                 if (hdmi->format.channels == 2)
 534                         value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
 535                 else
 536                         value = 0;
 537
 538                 value |= source;
 539
 540                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
 541         }
 542
 543         /*
 544          * On Tegra20, HDA is not a supported audio source and the source
 545          * select field is part of the AUDIO_CNTRL0 register.
 546          */
 547         value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
 548                 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
 549
 550         if (!hdmi->config->has_hda)
 551                 value |= source;
 552
 553         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
 554
 555         /*
 556          * Advertise support for High Bit-Rate on Tegra114 and later.
 557          */
 558         if (hdmi->config->has_hbr) {
 559                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
 560                 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
 561                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
 562         }
 563
 564         err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
 565                                           hdmi->pixel_clock, &config);
 566         if (err < 0) {
 567                 dev_err(hdmi->dev,
 568                         "cannot set audio to %u Hz at %u Hz pixel clock\n",
 569                         hdmi->format.sample_rate, hdmi->pixel_clock);
 570                 return err;
 571         }
 572
 573         dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
 574                 hdmi->pixel_clock, config.n, config.cts, config.aval);
 575
 576         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 577
 578         value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
 579                 AUDIO_N_VALUE(config.n - 1);
 580         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 581
 582         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
 583                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 584
 585         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
 586                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 587
 588         value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
 589         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
 590
 591         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
 592         value &= ~AUDIO_N_RESETF;
 593         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 594
 595         if (hdmi->config->has_hda)
 596                 tegra_hdmi_write_aval(hdmi, config.aval);
 597
 598         tegra_hdmi_setup_audio_fs_tables(hdmi);
 599
 600         return 0;
 601 }
 602
 603 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
 604 {
 605         u32 value;
 606
 607         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 608         value &= ~GENERIC_CTRL_AUDIO;
 609         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 610 }
 611
 612 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
 613 {
 614         u32 value;
 615
 616         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 617         value |= GENERIC_CTRL_AUDIO;
 618         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 619 }
 620
 621 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
 622 {
 623         size_t length = drm_eld_size(hdmi->output.connector.eld), i;
 624         u32 value;
 625
 626         for (i = 0; i < length; i++)
 627                 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
 628                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
 629
 630         /*
 631          * The HDA codec will always report an ELD buffer size of 96 bytes and
 632          * the HDA codec driver will check that each byte read from the buffer
 633          * is valid. Therefore every byte must be written, even if no 96 bytes
 634          * were parsed from EDID.
 635          */
 636         for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
 637                 tegra_hdmi_writel(hdmi, i << 8 | 0,
 638                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
 639
 640         value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
 641         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
 642 }
 643
 644 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
 645 {
 646         u32 value = 0;
 647         size_t i;
 648
 649         for (i = size; i > 0; i--)
 650                 value = (value << 8) | ptr[i - 1];
 651
 652         return value;
 653 }
 654
 655 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
 656                                       size_t size)
 657 {
 658         const u8 *ptr = data;
 659         unsigned long offset;
 660         size_t i, j;
 661         u32 value;
 662
 663         switch (ptr[0]) {
 664         case HDMI_INFOFRAME_TYPE_AVI:
 665                 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
 666                 break;
 667
 668         case HDMI_INFOFRAME_TYPE_AUDIO:
 669                 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
 670                 break;
 671
 672         case HDMI_INFOFRAME_TYPE_VENDOR:
 673                 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
 674                 break;
 675
 676         default:
 677                 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
 678                         ptr[0]);
 679                 return;
 680         }
 681
 682         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
 683                 INFOFRAME_HEADER_VERSION(ptr[1]) |
 684                 INFOFRAME_HEADER_LEN(ptr[2]);
 685         tegra_hdmi_writel(hdmi, value, offset);
 686         offset++;
 687
 688         /*
 689          * Each subpack contains 7 bytes, divided into:
 690          * - subpack_low: bytes 0 - 3
 691          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
 692          */
 693         for (i = 3, j = 0; i < size; i += 7, j += 8) {
 694                 size_t rem = size - i, num = min_t(size_t, rem, 4);
 695
 696                 value = tegra_hdmi_subpack(&ptr[i], num);
 697                 tegra_hdmi_writel(hdmi, value, offset++);
 698
 699                 num = min_t(size_t, rem - num, 3);
 700
 701                 value = tegra_hdmi_subpack(&ptr[i + 4], num);
 702                 tegra_hdmi_writel(hdmi, value, offset++);
 703         }
 704 }
 705
 706 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
 707                                            struct drm_display_mode *mode)
 708 {
 709         struct hdmi_avi_infoframe frame;
 710         u8 buffer[17];
 711         ssize_t err;
 712
 713         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 714                                                        &hdmi->output.connector, mode);
 715         if (err < 0) {
 716                 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
 717                 return;
 718         }
 719
 720         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 721         if (err < 0) {
 722                 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
 723                 return;
 724         }
 725
 726         tegra_hdmi_write_infopack(hdmi, buffer, err);
 727 }
 728
 729 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
 730 {
 731         u32 value;
 732
 733         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 734         value &= ~INFOFRAME_CTRL_ENABLE;
 735         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 736 }
 737
 738 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
 739 {
 740         u32 value;
 741
 742         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 743         value |= INFOFRAME_CTRL_ENABLE;
 744         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 745 }
 746
 747 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
 748 {
 749         struct hdmi_audio_infoframe frame;
 750         u8 buffer[14];
 751         ssize_t err;
 752
 753         err = hdmi_audio_infoframe_init(&frame);
 754         if (err < 0) {
 755                 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
 756                         err);
 757                 return;
 758         }
 759
 760         frame.channels = hdmi->format.channels;
 761
 762         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
 763         if (err < 0) {
 764                 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
 765                         err);
 766                 return;
 767         }
 768
 769         /*
 770          * The audio infoframe has only one set of subpack registers, so the
 771          * infoframe needs to be truncated. One set of subpack registers can
 772          * contain 7 bytes. Including the 3 byte header only the first 10
 773          * bytes can be programmed.
 774          */
 775         tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
 776 }
 777
 778 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
 779 {
 780         u32 value;
 781
 782         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 783         value &= ~INFOFRAME_CTRL_ENABLE;
 784         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 785 }
 786
 787 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
 788 {
 789         u32 value;
 790
 791         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 792         value |= INFOFRAME_CTRL_ENABLE;
 793         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 794 }
 795
 796 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
 797 {
 798         struct hdmi_vendor_infoframe frame;
 799         u8 buffer[10];
 800         ssize_t err;
 801
 802         hdmi_vendor_infoframe_init(&frame);
 803         frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
 804
 805         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
 806         if (err < 0) {
 807                 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
 808                         err);
 809                 return;
 810         }
 811
 812         tegra_hdmi_write_infopack(hdmi, buffer, err);
 813 }
 814
 815 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
 816 {
 817         u32 value;
 818
 819         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 820         value &= ~GENERIC_CTRL_ENABLE;
 821         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 822 }
 823
 824 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
 825 {
 826         u32 value;
 827
 828         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 829         value |= GENERIC_CTRL_ENABLE;
 830         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 831 }
 832
 833 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
 834                                   const struct tmds_config *tmds)
 835 {
 836         u32 value;
 837
 838         tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
 839         tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
 840         tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
 841
 842         tegra_hdmi_writel(hdmi, tmds->drive_current,
 843                           HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 844
 845         value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
 846         value |= hdmi->config->fuse_override_value;
 847         tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
 848
 849         if (hdmi->config->has_sor_io_peak_current)
 850                 tegra_hdmi_writel(hdmi, tmds->peak_current,
 851                                   HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
 852 }
 853
 854 static int tegra_hdmi_reconfigure_audio(struct tegra_hdmi *hdmi)
 855 {
 856         int err;
 857
 858         err = tegra_hdmi_setup_audio(hdmi);
 859         if (err < 0) {
 860                 tegra_hdmi_disable_audio_infoframe(hdmi);
 861                 tegra_hdmi_disable_audio(hdmi);
 862         } else {
 863                 tegra_hdmi_setup_audio_infoframe(hdmi);
 864                 tegra_hdmi_enable_audio_infoframe(hdmi);
 865                 tegra_hdmi_enable_audio(hdmi);
 866         }
 867
 868         return err;
 869 }
 870
 871 static bool tegra_output_is_hdmi(struct tegra_output *output)
 872 {
 873         return output->connector.display_info.is_hdmi;
 874 }
 875
 876 static enum drm_connector_status
 877 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
 878 {
 879         struct tegra_output *output = connector_to_output(connector);
 880         struct tegra_hdmi *hdmi = to_hdmi(output);
 881         enum drm_connector_status status;
 882
 883         status = tegra_output_connector_detect(connector, force);
 884         if (status == connector_status_connected)
 885                 return status;
 886
 887         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
 888         return status;
 889 }
 890
 891 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
 892
 893 static const struct debugfs_reg32 tegra_hdmi_regs[] = {
 894         DEBUGFS_REG32(HDMI_CTXSW),
 895         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
 896         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
 897         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
 898         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
 899         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
 900         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
 901         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
 902         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
 903         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
 904         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
 905         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
 906         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
 907         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
 908         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
 909         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
 910         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
 911         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
 912         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
 913         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
 914         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
 915         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
 916         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
 917         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
 918         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
 919         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
 920         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
 921         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
 922         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
 923         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
 924         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
 925         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
 926         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
 927         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
 928         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
 929         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
 930         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
 931         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
 932         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
 933         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
 934         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
 935         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
 936         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
 937         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
 938         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
 939         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
 940         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
 941         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
 942         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
 943         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
 944         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
 945         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
 946         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
 947         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
 948         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
 949         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
 950         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
 951         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
 952         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
 953         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
 954         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
 955         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
 956         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
 957         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
 958         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
 959         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
 960         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
 961         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
 962         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
 963         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
 964         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
 965         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
 966         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
 967         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
 968         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
 969         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
 970         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
 971         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
 972         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
 973         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
 974         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
 975         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
 976         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
 977         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
 978         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
 979         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
 980         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
 981         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
 982         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
 983         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
 984         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
 985         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
 986         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
 987         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
 988         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
 989         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
 990         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
 991         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
 992         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
 993         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
 994         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
 995         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
 996         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
 997         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
 998         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
 999         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
1000         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
1001         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
1002         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1003         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1004         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1005         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1006         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1007         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1008         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1009         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1010         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1011         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1012         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1013         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1014         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1015         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1016         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1017         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1018         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1019         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1020         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1021         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1022         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1023         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1024         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1025         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1026         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1027         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1028         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1029         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1030         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1031         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1032         DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1033         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1034         DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1035         DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1036         DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1037         DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1038         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1039         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1040         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1041         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1042         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1043         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1044         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1045         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1046         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1047         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1048         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1049         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1050         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1051         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1052         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1053         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1054         DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1055         DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1056         DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1057         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1058 };
1059
1060 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1061 {
1062         struct drm_info_node *node = s->private;
1063         struct tegra_hdmi *hdmi = node->info_ent->data;
1064         struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1065         struct drm_device *drm = node->minor->dev;
1066         unsigned int i;
1067         int err = 0;
1068
1069         drm_modeset_lock_all(drm);
1070
1071         if (!crtc || !crtc->state->active) {
1072                 err = -EBUSY;
1073                 goto unlock;
1074         }
1075
1076         for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1077                 unsigned int offset = tegra_hdmi_regs[i].offset;
1078
1079                 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1080                            offset, tegra_hdmi_readl(hdmi, offset));
1081         }
1082
1083 unlock:
1084         drm_modeset_unlock_all(drm);
1085         return err;
1086 }
1087
1088 static struct drm_info_list debugfs_files[] = {
1089         { "regs", tegra_hdmi_show_regs, 0, NULL },
1090 };
1091
1092 static int tegra_hdmi_late_register(struct drm_connector *connector)
1093 {
1094         struct tegra_output *output = connector_to_output(connector);
1095         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1096         struct drm_minor *minor = connector->dev->primary;
1097         struct dentry *root = connector->debugfs_entry;
1098         struct tegra_hdmi *hdmi = to_hdmi(output);
1099
1100         hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1101                                       GFP_KERNEL);
1102         if (!hdmi->debugfs_files)
1103                 return -ENOMEM;
1104
1105         for (i = 0; i < count; i++)
1106                 hdmi->debugfs_files[i].data = hdmi;
1107
1108         drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1109
1110         return 0;
1111 }
1112
1113 static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1114 {
1115         struct tegra_output *output = connector_to_output(connector);
1116         struct drm_minor *minor = connector->dev->primary;
1117         unsigned int count = ARRAY_SIZE(debugfs_files);
1118         struct tegra_hdmi *hdmi = to_hdmi(output);
1119
1120         drm_debugfs_remove_files(hdmi->debugfs_files, count,
1121                                  connector->debugfs_entry, minor);
1122         kfree(hdmi->debugfs_files);
1123         hdmi->debugfs_files = NULL;
1124 }
1125
1126 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1127         .reset = drm_atomic_helper_connector_reset,
1128         .detect = tegra_hdmi_connector_detect,
1129         .fill_modes = drm_helper_probe_single_connector_modes,
1130         .destroy = tegra_output_connector_destroy,
1131         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1132         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1133         .late_register = tegra_hdmi_late_register,
1134         .early_unregister = tegra_hdmi_early_unregister,
1135 };
1136
1137 static enum drm_mode_status
1138 tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1139                                 struct drm_display_mode *mode)
1140 {
1141         struct tegra_output *output = connector_to_output(connector);
1142         struct tegra_hdmi *hdmi = to_hdmi(output);
1143         unsigned long pclk = mode->clock * 1000;
1144         enum drm_mode_status status = MODE_OK;
1145         struct clk *parent;
1146         long err;
1147
1148         parent = clk_get_parent(hdmi->clk_parent);
1149
1150         err = clk_round_rate(parent, pclk * 4);
1151         if (err <= 0)
1152                 status = MODE_NOCLOCK;
1153
1154         return status;
1155 }
1156
1157 static const struct drm_connector_helper_funcs
1158 tegra_hdmi_connector_helper_funcs = {
1159         .get_modes = tegra_output_connector_get_modes,
1160         .mode_valid = tegra_hdmi_connector_mode_valid,
1161 };
1162
1163 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1164 {
1165         struct tegra_output *output = encoder_to_output(encoder);
1166         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1167         struct tegra_hdmi *hdmi = to_hdmi(output);
1168         u32 value;
1169         int err;
1170
1171         tegra_hdmi_audio_lock(hdmi);
1172
1173         /*
1174          * The following accesses registers of the display controller, so make
1175          * sure it's only executed when the output is attached to one.
1176          */
1177         if (dc) {
1178                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1179                 value &= ~HDMI_ENABLE;
1180                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1181
1182                 tegra_dc_commit(dc);
1183         }
1184
1185         if (!hdmi->dvi) {
1186                 if (hdmi->stereo)
1187                         tegra_hdmi_disable_stereo_infoframe(hdmi);
1188
1189                 tegra_hdmi_disable_audio_infoframe(hdmi);
1190                 tegra_hdmi_disable_avi_infoframe(hdmi);
1191                 tegra_hdmi_disable_audio(hdmi);
1192         }
1193
1194         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1195         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1196
1197         hdmi->pixel_clock = 0;
1198
1199         tegra_hdmi_audio_unlock(hdmi);
1200
1201         err = host1x_client_suspend(&hdmi->client);
1202         if (err < 0)
1203                 dev_err(hdmi->dev, "failed to suspend: %d\n", err);
1204 }
1205
1206 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1207 {
1208         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1209         unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1210         struct tegra_output *output = encoder_to_output(encoder);
1211         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1212         struct tegra_hdmi *hdmi = to_hdmi(output);
1213         unsigned int pulse_start, div82;
1214         int retries = 1000;
1215         u32 value;
1216         int err;
1217
1218         err = host1x_client_resume(&hdmi->client);
1219         if (err < 0) {
1220                 dev_err(hdmi->dev, "failed to resume: %d\n", err);
1221                 return;
1222         }
1223
1224         tegra_hdmi_audio_lock(hdmi);
1225
1226         /*
1227          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1228          * is used for interoperability between the HDA codec driver and the
1229          * HDMI driver.
1230          */
1231         tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1232         tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1233
1234         hdmi->pixel_clock = mode->clock * 1000;
1235         h_sync_width = mode->hsync_end - mode->hsync_start;
1236         h_back_porch = mode->htotal - mode->hsync_end;
1237         h_front_porch = mode->hsync_start - mode->hdisplay;
1238
1239         err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock);
1240         if (err < 0) {
1241                 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1242                         err);
1243         }
1244
1245         DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1246
1247         /* power up sequence */
1248         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1249         value &= ~SOR_PLL_PDBG;
1250         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1251
1252         usleep_range(10, 20);
1253
1254         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1255         value &= ~SOR_PLL_PWR;
1256         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1257
1258         tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1259                         DC_DISP_DISP_TIMING_OPTIONS);
1260         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1261                         DC_DISP_DISP_COLOR_CONTROL);
1262
1263         /* video_preamble uses h_pulse2 */
1264         pulse_start = 1 + h_sync_width + h_back_porch - 10;
1265
1266         tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1267
1268         value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1269                 PULSE_LAST_END_A;
1270         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1271
1272         value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1273         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1274
1275         value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1276                 VSYNC_WINDOW_ENABLE;
1277         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1278
1279         if (dc->pipe)
1280                 value = HDMI_SRC_DISPLAYB;
1281         else
1282                 value = HDMI_SRC_DISPLAYA;
1283
1284         if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1285                                         (mode->vdisplay == 576)))
1286                 tegra_hdmi_writel(hdmi,
1287                                   value | ARM_VIDEO_RANGE_FULL,
1288                                   HDMI_NV_PDISP_INPUT_CONTROL);
1289         else
1290                 tegra_hdmi_writel(hdmi,
1291                                   value | ARM_VIDEO_RANGE_LIMITED,
1292                                   HDMI_NV_PDISP_INPUT_CONTROL);
1293
1294         div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1295         value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1296         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1297
1298         hdmi->dvi = !tegra_output_is_hdmi(output);
1299         if (!hdmi->dvi) {
1300                 /*
1301                  * Make sure that the audio format has been configured before
1302                  * enabling audio, otherwise we may try to divide by zero.
1303                 */
1304                 if (hdmi->format.sample_rate > 0) {
1305                         err = tegra_hdmi_setup_audio(hdmi);
1306                         if (err < 0)
1307                                 hdmi->dvi = true;
1308                 }
1309         }
1310
1311         if (hdmi->config->has_hda)
1312                 tegra_hdmi_write_eld(hdmi);
1313
1314         rekey = HDMI_REKEY_DEFAULT;
1315         value = HDMI_CTRL_REKEY(rekey);
1316         value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1317                                           h_front_porch - rekey - 18) / 32);
1318
1319         if (!hdmi->dvi)
1320                 value |= HDMI_CTRL_ENABLE;
1321
1322         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1323
1324         if (!hdmi->dvi) {
1325                 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1326                 tegra_hdmi_setup_audio_infoframe(hdmi);
1327
1328                 if (hdmi->stereo)
1329                         tegra_hdmi_setup_stereo_infoframe(hdmi);
1330         }
1331
1332         /* TMDS CONFIG */
1333         for (i = 0; i < hdmi->config->num_tmds; i++) {
1334                 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1335                         tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1336                         break;
1337                 }
1338         }
1339
1340         tegra_hdmi_writel(hdmi,
1341                           SOR_SEQ_PU_PC(0) |
1342                           SOR_SEQ_PU_PC_ALT(0) |
1343                           SOR_SEQ_PD_PC(8) |
1344                           SOR_SEQ_PD_PC_ALT(8),
1345                           HDMI_NV_PDISP_SOR_SEQ_CTL);
1346
1347         value = SOR_SEQ_INST_WAIT_TIME(1) |
1348                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1349                 SOR_SEQ_INST_HALT |
1350                 SOR_SEQ_INST_PIN_A_LOW |
1351                 SOR_SEQ_INST_PIN_B_LOW |
1352                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1353
1354         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1355         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1356
1357         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1358         value &= ~SOR_CSTM_ROTCLK(~0);
1359         value |= SOR_CSTM_ROTCLK(2);
1360         value |= SOR_CSTM_PLLDIV;
1361         value &= ~SOR_CSTM_LVDS_ENABLE;
1362         value &= ~SOR_CSTM_MODE_MASK;
1363         value |= SOR_CSTM_MODE_TMDS;
1364         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1365
1366         /* start SOR */
1367         tegra_hdmi_writel(hdmi,
1368                           SOR_PWR_NORMAL_STATE_PU |
1369                           SOR_PWR_NORMAL_START_NORMAL |
1370                           SOR_PWR_SAFE_STATE_PD |
1371                           SOR_PWR_SETTING_NEW_TRIGGER,
1372                           HDMI_NV_PDISP_SOR_PWR);
1373         tegra_hdmi_writel(hdmi,
1374                           SOR_PWR_NORMAL_STATE_PU |
1375                           SOR_PWR_NORMAL_START_NORMAL |
1376                           SOR_PWR_SAFE_STATE_PD |
1377                           SOR_PWR_SETTING_NEW_DONE,
1378                           HDMI_NV_PDISP_SOR_PWR);
1379
1380         do {
1381                 BUG_ON(--retries < 0);
1382                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1383         } while (value & SOR_PWR_SETTING_NEW_PENDING);
1384
1385         value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1386                 SOR_STATE_ASY_OWNER_HEAD0 |
1387                 SOR_STATE_ASY_SUBOWNER_BOTH |
1388                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1389                 SOR_STATE_ASY_DEPOL_POS;
1390
1391         /* setup sync polarities */
1392         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1393                 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1394
1395         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1396                 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1397
1398         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1399                 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1400
1401         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1402                 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1403
1404         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1405
1406         value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1407         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1408
1409         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1410         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1411         tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1412                           HDMI_NV_PDISP_SOR_STATE1);
1413         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1414
1415         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1416         value |= HDMI_ENABLE;
1417         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1418
1419         tegra_dc_commit(dc);
1420
1421         if (!hdmi->dvi) {
1422                 tegra_hdmi_enable_avi_infoframe(hdmi);
1423                 tegra_hdmi_enable_audio_infoframe(hdmi);
1424                 tegra_hdmi_enable_audio(hdmi);
1425
1426                 if (hdmi->stereo)
1427                         tegra_hdmi_enable_stereo_infoframe(hdmi);
1428         }
1429
1430         /* TODO: add HDCP support */
1431
1432         tegra_hdmi_audio_unlock(hdmi);
1433 }
1434
1435 static int
1436 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1437                                 struct drm_crtc_state *crtc_state,
1438                                 struct drm_connector_state *conn_state)
1439 {
1440         struct tegra_output *output = encoder_to_output(encoder);
1441         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1442         unsigned long pclk = crtc_state->mode.clock * 1000;
1443         struct tegra_hdmi *hdmi = to_hdmi(output);
1444         int err;
1445
1446         err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1447                                          pclk, 0);
1448         if (err < 0) {
1449                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1450                 return err;
1451         }
1452
1453         return err;
1454 }
1455
1456 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1457         .disable = tegra_hdmi_encoder_disable,
1458         .enable = tegra_hdmi_encoder_enable,
1459         .atomic_check = tegra_hdmi_encoder_atomic_check,
1460 };
1461
1462 static int tegra_hdmi_hw_params(struct device *dev, void *data,
1463                                 struct hdmi_codec_daifmt *fmt,
1464                                 struct hdmi_codec_params *hparms)
1465 {
1466         struct tegra_hdmi *hdmi = data;
1467         int ret = 0;
1468
1469         tegra_hdmi_audio_lock(hdmi);
1470
1471         hdmi->format.sample_rate = hparms->sample_rate;
1472         hdmi->format.channels = hparms->channels;
1473
1474         if (hdmi->pixel_clock && !hdmi->dvi)
1475                 ret = tegra_hdmi_reconfigure_audio(hdmi);
1476
1477         tegra_hdmi_audio_unlock(hdmi);
1478
1479         return ret;
1480 }
1481
1482 static int tegra_hdmi_audio_startup(struct device *dev, void *data)
1483 {
1484         struct tegra_hdmi *hdmi = data;
1485         int ret;
1486
1487         ret = host1x_client_resume(&hdmi->client);
1488         if (ret < 0)
1489                 dev_err(hdmi->dev, "failed to resume: %d\n", ret);
1490
1491         return ret;
1492 }
1493
1494 static void tegra_hdmi_audio_shutdown(struct device *dev, void *data)
1495 {
1496         struct tegra_hdmi *hdmi = data;
1497         int ret;
1498
1499         tegra_hdmi_audio_lock(hdmi);
1500
1501         hdmi->format.sample_rate = 0;
1502         hdmi->format.channels = 0;
1503
1504         tegra_hdmi_audio_unlock(hdmi);
1505
1506         ret = host1x_client_suspend(&hdmi->client);
1507         if (ret < 0)
1508                 dev_err(hdmi->dev, "failed to suspend: %d\n", ret);
1509 }
1510
1511 static const struct hdmi_codec_ops tegra_hdmi_codec_ops = {
1512         .hw_params = tegra_hdmi_hw_params,
1513         .audio_startup = tegra_hdmi_audio_startup,
1514         .audio_shutdown = tegra_hdmi_audio_shutdown,
1515 };
1516
1517 static int tegra_hdmi_codec_register(struct tegra_hdmi *hdmi)
1518 {
1519         struct hdmi_codec_pdata codec_data = {};
1520
1521         if (hdmi->config->has_hda)
1522                 return 0;
1523
1524         codec_data.ops = &tegra_hdmi_codec_ops;
1525         codec_data.data = hdmi;
1526         codec_data.spdif = 1;
1527
1528         hdmi->audio_pdev = platform_device_register_data(hdmi->dev,
1529                                                          HDMI_CODEC_DRV_NAME,
1530                                                          PLATFORM_DEVID_AUTO,
1531                                                          &codec_data,
1532                                                          sizeof(codec_data));
1533         if (IS_ERR(hdmi->audio_pdev))
1534                 return PTR_ERR(hdmi->audio_pdev);
1535
1536         hdmi->format.channels = 2;
1537
1538         return 0;
1539 }
1540
1541 static void tegra_hdmi_codec_unregister(struct tegra_hdmi *hdmi)
1542 {
1543         if (hdmi->audio_pdev)
1544                 platform_device_unregister(hdmi->audio_pdev);
1545 }
1546
1547 static int tegra_hdmi_init(struct host1x_client *client)
1548 {
1549         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1550         struct drm_device *drm = dev_get_drvdata(client->host);
1551         struct drm_connector *connector;
1552         int err;
1553
1554         hdmi->output.dev = client->dev;
1555
1556         drm_simple_encoder_init(drm, &hdmi->output.encoder,
1557                                 DRM_MODE_ENCODER_TMDS);
1558         drm_encoder_helper_add(&hdmi->output.encoder,
1559                                &tegra_hdmi_encoder_helper_funcs);
1560
1561         if (hdmi->output.bridge) {
1562                 err = drm_bridge_attach(&hdmi->output.encoder, hdmi->output.bridge,
1563                                         NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1564                 if (err) {
1565                         dev_err(client->dev, "failed to attach bridge: %d\n",
1566                                 err);
1567                         return err;
1568                 }
1569
1570                 connector = drm_bridge_connector_init(drm, &hdmi->output.encoder);
1571                 if (IS_ERR(connector)) {
1572                         dev_err(client->dev,
1573                                 "failed to initialize bridge connector: %pe\n",
1574                                 connector);
1575                         return PTR_ERR(connector);
1576                 }
1577
1578                 drm_connector_attach_encoder(connector, &hdmi->output.encoder);
1579         } else {
1580                 drm_connector_init_with_ddc(drm, &hdmi->output.connector,
1581                                             &tegra_hdmi_connector_funcs,
1582                                             DRM_MODE_CONNECTOR_HDMIA,
1583                                             hdmi->output.ddc);
1584                 drm_connector_helper_add(&hdmi->output.connector,
1585                                          &tegra_hdmi_connector_helper_funcs);
1586                 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1587
1588                 drm_connector_attach_encoder(&hdmi->output.connector,
1589                                              &hdmi->output.encoder);
1590                 drm_connector_register(&hdmi->output.connector);
1591         }
1592
1593         err = tegra_output_init(drm, &hdmi->output);
1594         if (err < 0) {
1595                 dev_err(client->dev, "failed to initialize output: %d\n", err);
1596                 return err;
1597         }
1598
1599         hdmi->output.encoder.possible_crtcs = 0x3;
1600
1601         err = regulator_enable(hdmi->hdmi);
1602         if (err < 0) {
1603                 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1604                         err);
1605                 goto output_exit;
1606         }
1607
1608         err = regulator_enable(hdmi->pll);
1609         if (err < 0) {
1610                 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1611                 goto disable_hdmi;
1612         }
1613
1614         err = regulator_enable(hdmi->vdd);
1615         if (err < 0) {
1616                 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1617                 goto disable_pll;
1618         }
1619
1620         err = tegra_hdmi_codec_register(hdmi);
1621         if (err < 0) {
1622                 dev_err(hdmi->dev, "failed to register audio codec: %d\n", err);
1623                 goto disable_vdd;
1624         }
1625
1626         return 0;
1627
1628 disable_vdd:
1629         regulator_disable(hdmi->vdd);
1630 disable_pll:
1631         regulator_disable(hdmi->pll);
1632 disable_hdmi:
1633         regulator_disable(hdmi->hdmi);
1634 output_exit:
1635         tegra_output_exit(&hdmi->output);
1636
1637         return err;
1638 }
1639
1640 static int tegra_hdmi_exit(struct host1x_client *client)
1641 {
1642         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1643
1644         tegra_hdmi_codec_unregister(hdmi);
1645
1646         tegra_output_exit(&hdmi->output);
1647
1648         regulator_disable(hdmi->vdd);
1649         regulator_disable(hdmi->pll);
1650         regulator_disable(hdmi->hdmi);
1651
1652         return 0;
1653 }
1654
1655 static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
1656 {
1657         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1658         struct device *dev = client->dev;
1659         int err;
1660
1661         err = reset_control_assert(hdmi->rst);
1662         if (err < 0) {
1663                 dev_err(dev, "failed to assert reset: %d\n", err);
1664                 return err;
1665         }
1666
1667         usleep_range(1000, 2000);
1668
1669         clk_disable_unprepare(hdmi->clk);
1670         pm_runtime_put_sync(dev);
1671
1672         return 0;
1673 }
1674
1675 static int tegra_hdmi_runtime_resume(struct host1x_client *client)
1676 {
1677         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1678         struct device *dev = client->dev;
1679         int err;
1680
1681         err = pm_runtime_resume_and_get(dev);
1682         if (err < 0) {
1683                 dev_err(dev, "failed to get runtime PM: %d\n", err);
1684                 return err;
1685         }
1686
1687         err = clk_prepare_enable(hdmi->clk);
1688         if (err < 0) {
1689                 dev_err(dev, "failed to enable clock: %d\n", err);
1690                 goto put_rpm;
1691         }
1692
1693         usleep_range(1000, 2000);
1694
1695         err = reset_control_deassert(hdmi->rst);
1696         if (err < 0) {
1697                 dev_err(dev, "failed to deassert reset: %d\n", err);
1698                 goto disable_clk;
1699         }
1700
1701         return 0;
1702
1703 disable_clk:
1704         clk_disable_unprepare(hdmi->clk);
1705 put_rpm:
1706         pm_runtime_put_sync(dev);
1707         return err;
1708 }
1709
1710 static const struct host1x_client_ops hdmi_client_ops = {
1711         .init = tegra_hdmi_init,
1712         .exit = tegra_hdmi_exit,
1713         .suspend = tegra_hdmi_runtime_suspend,
1714         .resume = tegra_hdmi_runtime_resume,
1715 };
1716
1717 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1718         .tmds = tegra20_tmds_config,
1719         .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1720         .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1721         .fuse_override_value = 1 << 31,
1722         .has_sor_io_peak_current = false,
1723         .has_hda = false,
1724         .has_hbr = false,
1725 };
1726
1727 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1728         .tmds = tegra30_tmds_config,
1729         .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1730         .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1731         .fuse_override_value = 1 << 31,
1732         .has_sor_io_peak_current = false,
1733         .has_hda = true,
1734         .has_hbr = false,
1735 };
1736
1737 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1738         .tmds = tegra114_tmds_config,
1739         .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1740         .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1741         .fuse_override_value = 1 << 31,
1742         .has_sor_io_peak_current = true,
1743         .has_hda = true,
1744         .has_hbr = true,
1745 };
1746
1747 static const struct tegra_hdmi_config tegra124_hdmi_config = {
1748         .tmds = tegra124_tmds_config,
1749         .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1750         .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1751         .fuse_override_value = 1 << 31,
1752         .has_sor_io_peak_current = true,
1753         .has_hda = true,
1754         .has_hbr = true,
1755 };
1756
1757 static const struct of_device_id tegra_hdmi_of_match[] = {
1758         { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1759         { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1760         { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1761         { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1762         { },
1763 };
1764 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1765
1766 static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1767 {
1768         struct tegra_hdmi *hdmi = data;
1769         u32 value;
1770
1771         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1772         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1773
1774         if (value & INT_CODEC_SCRATCH0) {
1775                 unsigned int format;
1776                 u32 value;
1777
1778                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1779
1780                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1781                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1782
1783                         tegra_hda_parse_format(format, &hdmi->format);
1784                         tegra_hdmi_reconfigure_audio(hdmi);
1785                 } else {
1786                         tegra_hdmi_disable_audio_infoframe(hdmi);
1787                         tegra_hdmi_disable_audio(hdmi);
1788                 }
1789         }
1790
1791         return IRQ_HANDLED;
1792 }
1793
1794 static int tegra_hdmi_probe(struct platform_device *pdev)
1795 {
1796         struct tegra_hdmi *hdmi;
1797         int err;
1798
1799         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1800         if (!hdmi)
1801                 return -ENOMEM;
1802
1803         hdmi->config = of_device_get_match_data(&pdev->dev);
1804         hdmi->dev = &pdev->dev;
1805
1806         hdmi->audio_source = AUTO;
1807         hdmi->stereo = false;
1808         hdmi->dvi = false;
1809
1810         mutex_init(&hdmi->audio_lock);
1811
1812         hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1813         if (IS_ERR(hdmi->clk)) {
1814                 dev_err(&pdev->dev, "failed to get clock\n");
1815                 return PTR_ERR(hdmi->clk);
1816         }
1817
1818         hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1819         if (IS_ERR(hdmi->rst)) {
1820                 dev_err(&pdev->dev, "failed to get reset\n");
1821                 return PTR_ERR(hdmi->rst);
1822         }
1823
1824         hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1825         if (IS_ERR(hdmi->clk_parent))
1826                 return PTR_ERR(hdmi->clk_parent);
1827
1828         err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1829         if (err < 0) {
1830                 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1831                 return err;
1832         }
1833
1834         hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1835         err = PTR_ERR_OR_ZERO(hdmi->hdmi);
1836         if (err)
1837                 return dev_err_probe(&pdev->dev, err,
1838                                      "failed to get HDMI regulator\n");
1839
1840         hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1841         err = PTR_ERR_OR_ZERO(hdmi->pll);
1842         if (err)
1843                 return dev_err_probe(&pdev->dev, err,
1844                                      "failed to get PLL regulator\n");
1845
1846         hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1847         err = PTR_ERR_OR_ZERO(hdmi->vdd);
1848         if (err)
1849                 return dev_err_probe(&pdev->dev, err,
1850                                      "failed to get VDD regulator\n");
1851
1852         hdmi->output.dev = &pdev->dev;
1853
1854         err = tegra_output_probe(&hdmi->output);
1855         if (err < 0)
1856                 return err;
1857
1858         hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
1859         if (IS_ERR(hdmi->regs))
1860                 return PTR_ERR(hdmi->regs);
1861
1862         err = platform_get_irq(pdev, 0);
1863         if (err < 0)
1864                 return err;
1865
1866         hdmi->irq = err;
1867
1868         err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1869                                dev_name(hdmi->dev), hdmi);
1870         if (err < 0) {
1871                 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1872                         hdmi->irq, err);
1873                 return err;
1874         }
1875
1876         platform_set_drvdata(pdev, hdmi);
1877
1878         err = devm_pm_runtime_enable(&pdev->dev);
1879         if (err)
1880                 return err;
1881
1882         err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1883         if (err)
1884                 return err;
1885
1886         INIT_LIST_HEAD(&hdmi->client.list);
1887         hdmi->client.ops = &hdmi_client_ops;
1888         hdmi->client.dev = &pdev->dev;
1889
1890         err = host1x_client_register(&hdmi->client);
1891         if (err < 0) {
1892                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1893                         err);
1894                 return err;
1895         }
1896
1897         return 0;
1898 }
1899
1900 static void tegra_hdmi_remove(struct platform_device *pdev)
1901 {
1902         struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1903
1904         host1x_client_unregister(&hdmi->client);
1905
1906         tegra_output_remove(&hdmi->output);
1907 }
1908
1909 struct platform_driver tegra_hdmi_driver = {
1910         .driver = {
1911                 .name = "tegra-hdmi",
1912                 .of_match_table = tegra_hdmi_of_match,
1913         },
1914         .probe = tegra_hdmi_probe,
1915         .remove_new = tegra_hdmi_remove,
1916 };