drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25
  26 #ifdef CONFIG_X86
  27 #include <asm/hypervisor.h>
  28 #endif
  29
  30 #include <drm/drm_drv.h>
  31 #include <xen/xen.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_ras.h"
  35 #include "vi.h"
  36 #include "soc15.h"
  37 #include "nv.h"
  38
  39 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
  40         do { \
  41                 vf2pf_info->ucode_info[ucode].id = ucode; \
  42                 vf2pf_info->ucode_info[ucode].version = ver; \
  43         } while (0)
  44
  45 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
  46 {
  47         /* By now all MMIO pages except mailbox are blocked */
  48         /* if blocking is enabled in hypervisor. Choose the */
  49         /* SCRATCH_REG0 to test. */
  50         return RREG32_NO_KIQ(0xc040) == 0xffffffff;
  51 }
  52
  53 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
  54 {
  55         struct drm_device *ddev = adev_to_drm(adev);
  56
  57         /* enable virtual display */
  58         if (adev->asic_type != CHIP_ALDEBARAN &&
  59             adev->asic_type != CHIP_ARCTURUS) {
  60                 if (adev->mode_info.num_crtc == 0)
  61                         adev->mode_info.num_crtc = 1;
  62                 adev->enable_virtual_display = true;
  63         }
  64         ddev->driver_features &= ~DRIVER_ATOMIC;
  65         adev->cg_flags = 0;
  66         adev->pg_flags = 0;
  67
  68         /* enable mcbp for sriov asic_type before soc21 */
  69         amdgpu_mcbp = (adev->asic_type < CHIP_IP_DISCOVERY) ? 1 : 0;
  70
  71 }
  72
  73 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
  74                                         uint32_t reg0, uint32_t reg1,
  75                                         uint32_t ref, uint32_t mask)
  76 {
  77         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
  78         struct amdgpu_ring *ring = &kiq->ring;
  79         signed long r, cnt = 0;
  80         unsigned long flags;
  81         uint32_t seq;
  82
  83         if (adev->mes.ring.sched.ready) {
  84                 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,
  85                                               ref, mask);
  86                 return;
  87         }
  88
  89         spin_lock_irqsave(&kiq->ring_lock, flags);
  90         amdgpu_ring_alloc(ring, 32);
  91         amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
  92                                             ref, mask);
  93         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
  94         if (r)
  95                 goto failed_undo;
  96
  97         amdgpu_ring_commit(ring);
  98         spin_unlock_irqrestore(&kiq->ring_lock, flags);
  99
 100         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 101
 102         /* don't wait anymore for IRQ context */
 103         if (r < 1 && in_interrupt())
 104                 goto failed_kiq;
 105
 106         might_sleep();
 107         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 108
 109                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 110                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 111         }
 112
 113         if (cnt > MAX_KIQ_REG_TRY)
 114                 goto failed_kiq;
 115
 116         return;
 117
 118 failed_undo:
 119         amdgpu_ring_undo(ring);
 120         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 121 failed_kiq:
 122         dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);
 123 }
 124
 125 /**
 126  * amdgpu_virt_request_full_gpu() - request full gpu access
 127  * @adev:       amdgpu device.
 128  * @init:       is driver init time.
 129  * When start to init/fini driver, first need to request full gpu access.
 130  * Return: Zero if request success, otherwise will return error.
 131  */
 132 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
 133 {
 134         struct amdgpu_virt *virt = &adev->virt;
 135         int r;
 136
 137         if (virt->ops && virt->ops->req_full_gpu) {
 138                 r = virt->ops->req_full_gpu(adev, init);
 139                 if (r)
 140                         return r;
 141
 142                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 143         }
 144
 145         return 0;
 146 }
 147
 148 /**
 149  * amdgpu_virt_release_full_gpu() - release full gpu access
 150  * @adev:       amdgpu device.
 151  * @init:       is driver init time.
 152  * When finishing driver init/fini, need to release full gpu access.
 153  * Return: Zero if release success, otherwise will returen error.
 154  */
 155 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
 156 {
 157         struct amdgpu_virt *virt = &adev->virt;
 158         int r;
 159
 160         if (virt->ops && virt->ops->rel_full_gpu) {
 161                 r = virt->ops->rel_full_gpu(adev, init);
 162                 if (r)
 163                         return r;
 164
 165                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 166         }
 167         return 0;
 168 }
 169
 170 /**
 171  * amdgpu_virt_reset_gpu() - reset gpu
 172  * @adev:       amdgpu device.
 173  * Send reset command to GPU hypervisor to reset GPU that VM is using
 174  * Return: Zero if reset success, otherwise will return error.
 175  */
 176 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
 177 {
 178         struct amdgpu_virt *virt = &adev->virt;
 179         int r;
 180
 181         if (virt->ops && virt->ops->reset_gpu) {
 182                 r = virt->ops->reset_gpu(adev);
 183                 if (r)
 184                         return r;
 185
 186                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 187         }
 188
 189         return 0;
 190 }
 191
 192 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
 193 {
 194         struct amdgpu_virt *virt = &adev->virt;
 195
 196         if (virt->ops && virt->ops->req_init_data)
 197                 virt->ops->req_init_data(adev);
 198
 199         if (adev->virt.req_init_data_ver > 0)
 200                 DRM_INFO("host supports REQ_INIT_DATA handshake\n");
 201         else
 202                 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");
 203 }
 204
 205 /**
 206  * amdgpu_virt_wait_reset() - wait for reset gpu completed
 207  * @adev:       amdgpu device.
 208  * Wait for GPU reset completed.
 209  * Return: Zero if reset success, otherwise will return error.
 210  */
 211 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
 212 {
 213         struct amdgpu_virt *virt = &adev->virt;
 214
 215         if (!virt->ops || !virt->ops->wait_reset)
 216                 return -EINVAL;
 217
 218         return virt->ops->wait_reset(adev);
 219 }
 220
 221 /**
 222  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
 223  * @adev:       amdgpu device.
 224  * MM table is used by UVD and VCE for its initialization
 225  * Return: Zero if allocate success.
 226  */
 227 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
 228 {
 229         int r;
 230
 231         if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
 232                 return 0;
 233
 234         r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
 235                                     AMDGPU_GEM_DOMAIN_VRAM,
 236                                     &adev->virt.mm_table.bo,
 237                                     &adev->virt.mm_table.gpu_addr,
 238                                     (void *)&adev->virt.mm_table.cpu_addr);
 239         if (r) {
 240                 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
 241                 return r;
 242         }
 243
 244         memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
 245         DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
 246                  adev->virt.mm_table.gpu_addr,
 247                  adev->virt.mm_table.cpu_addr);
 248         return 0;
 249 }
 250
 251 /**
 252  * amdgpu_virt_free_mm_table() - free mm table memory
 253  * @adev:       amdgpu device.
 254  * Free MM table memory
 255  */
 256 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
 257 {
 258         if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
 259                 return;
 260
 261         amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
 262                               &adev->virt.mm_table.gpu_addr,
 263                               (void *)&adev->virt.mm_table.cpu_addr);
 264         adev->virt.mm_table.gpu_addr = 0;
 265 }
 266
 267
 268 unsigned int amd_sriov_msg_checksum(void *obj,
 269                                 unsigned long obj_size,
 270                                 unsigned int key,
 271                                 unsigned int checksum)
 272 {
 273         unsigned int ret = key;
 274         unsigned long i = 0;
 275         unsigned char *pos;
 276
 277         pos = (char *)obj;
 278         /* calculate checksum */
 279         for (i = 0; i < obj_size; ++i)
 280                 ret += *(pos + i);
 281         /* minus the checksum itself */
 282         pos = (char *)&checksum;
 283         for (i = 0; i < sizeof(checksum); ++i)
 284                 ret -= *(pos + i);
 285         return ret;
 286 }
 287
 288 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
 289 {
 290         struct amdgpu_virt *virt = &adev->virt;
 291         struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
 292         /* GPU will be marked bad on host if bp count more then 10,
 293          * so alloc 512 is enough.
 294          */
 295         unsigned int align_space = 512;
 296         void *bps = NULL;
 297         struct amdgpu_bo **bps_bo = NULL;
 298
 299         *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL);
 300         if (!*data)
 301                 goto data_failure;
 302
 303         bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL);
 304         if (!bps)
 305                 goto bps_failure;
 306
 307         bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL);
 308         if (!bps_bo)
 309                 goto bps_bo_failure;
 310
 311         (*data)->bps = bps;
 312         (*data)->bps_bo = bps_bo;
 313         (*data)->count = 0;
 314         (*data)->last_reserved = 0;
 315
 316         virt->ras_init_done = true;
 317
 318         return 0;
 319
 320 bps_bo_failure:
 321         kfree(bps);
 322 bps_failure:
 323         kfree(*data);
 324 data_failure:
 325         return -ENOMEM;
 326 }
 327
 328 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
 329 {
 330         struct amdgpu_virt *virt = &adev->virt;
 331         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 332         struct amdgpu_bo *bo;
 333         int i;
 334
 335         if (!data)
 336                 return;
 337
 338         for (i = data->last_reserved - 1; i >= 0; i--) {
 339                 bo = data->bps_bo[i];
 340                 amdgpu_bo_free_kernel(&bo, NULL, NULL);
 341                 data->bps_bo[i] = bo;
 342                 data->last_reserved = i;
 343         }
 344 }
 345
 346 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
 347 {
 348         struct amdgpu_virt *virt = &adev->virt;
 349         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 350
 351         virt->ras_init_done = false;
 352
 353         if (!data)
 354                 return;
 355
 356         amdgpu_virt_ras_release_bp(adev);
 357
 358         kfree(data->bps);
 359         kfree(data->bps_bo);
 360         kfree(data);
 361         virt->virt_eh_data = NULL;
 362 }
 363
 364 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
 365                 struct eeprom_table_record *bps, int pages)
 366 {
 367         struct amdgpu_virt *virt = &adev->virt;
 368         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 369
 370         if (!data)
 371                 return;
 372
 373         memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
 374         data->count += pages;
 375 }
 376
 377 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
 378 {
 379         struct amdgpu_virt *virt = &adev->virt;
 380         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 381         struct amdgpu_bo *bo = NULL;
 382         uint64_t bp;
 383         int i;
 384
 385         if (!data)
 386                 return;
 387
 388         for (i = data->last_reserved; i < data->count; i++) {
 389                 bp = data->bps[i].retired_page;
 390
 391                 /* There are two cases of reserve error should be ignored:
 392                  * 1) a ras bad page has been allocated (used by someone);
 393                  * 2) a ras bad page has been reserved (duplicate error injection
 394                  *    for one page);
 395                  */
 396                 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
 397                                                AMDGPU_GPU_PAGE_SIZE,
 398                                                &bo, NULL))
 399                         DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
 400
 401                 data->bps_bo[i] = bo;
 402                 data->last_reserved = i + 1;
 403                 bo = NULL;
 404         }
 405 }
 406
 407 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
 408                 uint64_t retired_page)
 409 {
 410         struct amdgpu_virt *virt = &adev->virt;
 411         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 412         int i;
 413
 414         if (!data)
 415                 return true;
 416
 417         for (i = 0; i < data->count; i++)
 418                 if (retired_page == data->bps[i].retired_page)
 419                         return true;
 420
 421         return false;
 422 }
 423
 424 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
 425                 uint64_t bp_block_offset, uint32_t bp_block_size)
 426 {
 427         struct eeprom_table_record bp;
 428         uint64_t retired_page;
 429         uint32_t bp_idx, bp_cnt;
 430         void *vram_usage_va = NULL;
 431
 432         if (adev->mman.fw_vram_usage_va)
 433                 vram_usage_va = adev->mman.fw_vram_usage_va;
 434         else
 435                 vram_usage_va = adev->mman.drv_vram_usage_va;
 436
 437         if (bp_block_size) {
 438                 bp_cnt = bp_block_size / sizeof(uint64_t);
 439                 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
 440                         retired_page = *(uint64_t *)(vram_usage_va +
 441                                         bp_block_offset + bp_idx * sizeof(uint64_t));
 442                         bp.retired_page = retired_page;
 443
 444                         if (amdgpu_virt_ras_check_bad_page(adev, retired_page))
 445                                 continue;
 446
 447                         amdgpu_virt_ras_add_bps(adev, &bp, 1);
 448
 449                         amdgpu_virt_ras_reserve_bps(adev);
 450                 }
 451         }
 452 }
 453
 454 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
 455 {
 456         struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;
 457         uint32_t checksum;
 458         uint32_t checkval;
 459
 460         uint32_t i;
 461         uint32_t tmp;
 462
 463         if (adev->virt.fw_reserve.p_pf2vf == NULL)
 464                 return -EINVAL;
 465
 466         if (pf2vf_info->size > 1024) {
 467                 DRM_ERROR("invalid pf2vf message size\n");
 468                 return -EINVAL;
 469         }
 470
 471         switch (pf2vf_info->version) {
 472         case 1:
 473                 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum;
 474                 checkval = amd_sriov_msg_checksum(
 475                         adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
 476                         adev->virt.fw_reserve.checksum_key, checksum);
 477                 if (checksum != checkval) {
 478                         DRM_ERROR("invalid pf2vf message\n");
 479                         return -EINVAL;
 480                 }
 481
 482                 adev->virt.gim_feature =
 483                         ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags;
 484                 break;
 485         case 2:
 486                 /* TODO: missing key, need to add it later */
 487                 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum;
 488                 checkval = amd_sriov_msg_checksum(
 489                         adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
 490                         0, checksum);
 491                 if (checksum != checkval) {
 492                         DRM_ERROR("invalid pf2vf message\n");
 493                         return -EINVAL;
 494                 }
 495
 496                 adev->virt.vf2pf_update_interval_ms =
 497                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;
 498                 adev->virt.gim_feature =
 499                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;
 500                 adev->virt.reg_access =
 501                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all;
 502
 503                 adev->virt.decode_max_dimension_pixels = 0;
 504                 adev->virt.decode_max_frame_pixels = 0;
 505                 adev->virt.encode_max_dimension_pixels = 0;
 506                 adev->virt.encode_max_frame_pixels = 0;
 507                 adev->virt.is_mm_bw_enabled = false;
 508                 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) {
 509                         tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels;
 510                         adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);
 511
 512                         tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels;
 513                         adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);
 514
 515                         tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels;
 516                         adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);
 517
 518                         tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;
 519                         adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);
 520                 }
 521                 if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))
 522                         adev->virt.is_mm_bw_enabled = true;
 523
 524                 adev->unique_id =
 525                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid;
 526                 break;
 527         default:
 528                 DRM_ERROR("invalid pf2vf version\n");
 529                 return -EINVAL;
 530         }
 531
 532         /* correct too large or too little interval value */
 533         if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)
 534                 adev->virt.vf2pf_update_interval_ms = 2000;
 535
 536         return 0;
 537 }
 538
 539 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
 540 {
 541         struct amd_sriov_msg_vf2pf_info *vf2pf_info;
 542         vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
 543
 544         if (adev->virt.fw_reserve.p_vf2pf == NULL)
 545                 return;
 546
 547         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE,      adev->vce.fw_version);
 548         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD,      adev->uvd.fw_version);
 549         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC,       adev->gmc.fw_version);
 550         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME,       adev->gfx.me_fw_version);
 551         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP,      adev->gfx.pfp_fw_version);
 552         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE,       adev->gfx.ce_fw_version);
 553         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC,      adev->gfx.rlc_fw_version);
 554         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);
 555         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);
 556         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
 557         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC,      adev->gfx.mec_fw_version);
 558         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2,     adev->gfx.mec2_fw_version);
 559         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_IMU,      adev->gfx.imu_fw_version);
 560         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS,      adev->psp.sos.fw_version);
 561         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,
 562                             adev->psp.asd_context.bin_desc.fw_version);
 563         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS,
 564                             adev->psp.ras_context.context.bin_desc.fw_version);
 565         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI,
 566                             adev->psp.xgmi_context.context.bin_desc.fw_version);
 567         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC,      adev->pm.fw_version);
 568         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA,     adev->sdma.instance[0].fw_version);
 569         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2,    adev->sdma.instance[1].fw_version);
 570         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN,      adev->vcn.fw_version);
 571         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU,     adev->dm.dmcu_fw_version);
 572 }
 573
 574 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
 575 {
 576         struct amd_sriov_msg_vf2pf_info *vf2pf_info;
 577
 578         vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
 579
 580         if (adev->virt.fw_reserve.p_vf2pf == NULL)
 581                 return -EINVAL;
 582
 583         memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info));
 584
 585         vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info);
 586         vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER;
 587
 588 #ifdef MODULE
 589         if (THIS_MODULE->version != NULL)
 590                 strcpy(vf2pf_info->driver_version, THIS_MODULE->version);
 591         else
 592 #endif
 593                 strcpy(vf2pf_info->driver_version, "N/A");
 594
 595         vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all
 596         vf2pf_info->driver_cert = 0;
 597         vf2pf_info->os_info.all = 0;
 598
 599         vf2pf_info->fb_usage =
 600                 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20;
 601         vf2pf_info->fb_vis_usage =
 602                 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20;
 603         vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;
 604         vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;
 605
 606         amdgpu_virt_populate_vf2pf_ucode_info(adev);
 607
 608         /* TODO: read dynamic info */
 609         vf2pf_info->gfx_usage = 0;
 610         vf2pf_info->compute_usage = 0;
 611         vf2pf_info->encode_usage = 0;
 612         vf2pf_info->decode_usage = 0;
 613
 614         vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr;
 615         vf2pf_info->checksum =
 616                 amd_sriov_msg_checksum(
 617                 vf2pf_info, vf2pf_info->header.size, 0, 0);
 618
 619         return 0;
 620 }
 621
 622 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
 623 {
 624         struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);
 625         int ret;
 626
 627         ret = amdgpu_virt_read_pf2vf_data(adev);
 628         if (ret)
 629                 goto out;
 630         amdgpu_virt_write_vf2pf_data(adev);
 631
 632 out:
 633         schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
 634 }
 635
 636 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)
 637 {
 638         if (adev->virt.vf2pf_update_interval_ms != 0) {
 639                 DRM_INFO("clean up the vf2pf work item\n");
 640                 cancel_delayed_work_sync(&adev->virt.vf2pf_work);
 641                 adev->virt.vf2pf_update_interval_ms = 0;
 642         }
 643 }
 644
 645 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 646 {
 647         adev->virt.fw_reserve.p_pf2vf = NULL;
 648         adev->virt.fw_reserve.p_vf2pf = NULL;
 649         adev->virt.vf2pf_update_interval_ms = 0;
 650
 651         if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) {
 652                 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!");
 653         } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {
 654                 /* go through this logic in ip_init and reset to init workqueue*/
 655                 amdgpu_virt_exchange_data(adev);
 656
 657                 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
 658                 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
 659         } else if (adev->bios != NULL) {
 660                 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/
 661                 adev->virt.fw_reserve.p_pf2vf =
 662                         (struct amd_sriov_msg_pf2vf_info_header *)
 663                         (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 664
 665                 amdgpu_virt_read_pf2vf_data(adev);
 666         }
 667 }
 668
 669
 670 void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
 671 {
 672         uint64_t bp_block_offset = 0;
 673         uint32_t bp_block_size = 0;
 674         struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
 675
 676         if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {
 677                 if (adev->mman.fw_vram_usage_va) {
 678                         adev->virt.fw_reserve.p_pf2vf =
 679                                 (struct amd_sriov_msg_pf2vf_info_header *)
 680                                 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 681                         adev->virt.fw_reserve.p_vf2pf =
 682                                 (struct amd_sriov_msg_vf2pf_info_header *)
 683                                 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
 684                 } else if (adev->mman.drv_vram_usage_va) {
 685                         adev->virt.fw_reserve.p_pf2vf =
 686                                 (struct amd_sriov_msg_pf2vf_info_header *)
 687                                 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 688                         adev->virt.fw_reserve.p_vf2pf =
 689                                 (struct amd_sriov_msg_vf2pf_info_header *)
 690                                 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
 691                 }
 692
 693                 amdgpu_virt_read_pf2vf_data(adev);
 694                 amdgpu_virt_write_vf2pf_data(adev);
 695
 696                 /* bad page handling for version 2 */
 697                 if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
 698                         pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
 699
 700                         bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) |
 701                                 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000);
 702                         bp_block_size = pf2vf_v2->bp_block_size;
 703
 704                         if (bp_block_size && !adev->virt.ras_init_done)
 705                                 amdgpu_virt_init_ras_err_handler_data(adev);
 706
 707                         if (adev->virt.ras_init_done)
 708                                 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
 709                 }
 710         }
 711 }
 712
 713 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
 714 {
 715         uint32_t reg;
 716
 717         switch (adev->asic_type) {
 718         case CHIP_TONGA:
 719         case CHIP_FIJI:
 720                 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
 721                 break;
 722         case CHIP_VEGA10:
 723         case CHIP_VEGA20:
 724         case CHIP_NAVI10:
 725         case CHIP_NAVI12:
 726         case CHIP_SIENNA_CICHLID:
 727         case CHIP_ARCTURUS:
 728         case CHIP_ALDEBARAN:
 729         case CHIP_IP_DISCOVERY:
 730                 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
 731                 break;
 732         default: /* other chip doesn't support SRIOV */
 733                 reg = 0;
 734                 break;
 735         }
 736
 737         if (reg & 1)
 738                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 739
 740         if (reg & 0x80000000)
 741                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 742
 743         if (!reg) {
 744                 /* passthrough mode exclus sriov mod */
 745                 if (is_virtual_machine() && !xen_initial_domain())
 746                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 747         }
 748
 749         if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
 750                 /* VF MMIO access (except mailbox range) from CPU
 751                  * will be blocked during sriov runtime
 752                  */
 753                 adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;
 754
 755         /* we have the ability to check now */
 756         if (amdgpu_sriov_vf(adev)) {
 757                 switch (adev->asic_type) {
 758                 case CHIP_TONGA:
 759                 case CHIP_FIJI:
 760                         vi_set_virt_ops(adev);
 761                         break;
 762                 case CHIP_VEGA10:
 763                         soc15_set_virt_ops(adev);
 764 #ifdef CONFIG_X86
 765                         /* not send GPU_INIT_DATA with MS_HYPERV*/
 766                         if (!hypervisor_is_type(X86_HYPER_MS_HYPERV))
 767 #endif
 768                                 /* send a dummy GPU_INIT_DATA request to host on vega10 */
 769                                 amdgpu_virt_request_init_data(adev);
 770                         break;
 771                 case CHIP_VEGA20:
 772                 case CHIP_ARCTURUS:
 773                 case CHIP_ALDEBARAN:
 774                         soc15_set_virt_ops(adev);
 775                         break;
 776                 case CHIP_NAVI10:
 777                 case CHIP_NAVI12:
 778                 case CHIP_SIENNA_CICHLID:
 779                 case CHIP_IP_DISCOVERY:
 780                         nv_set_virt_ops(adev);
 781                         /* try send GPU_INIT_DATA request to host */
 782                         amdgpu_virt_request_init_data(adev);
 783                         break;
 784                 default: /* other chip doesn't support SRIOV */
 785                         DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);
 786                         break;
 787                 }
 788         }
 789 }
 790
 791 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
 792 {
 793         return amdgpu_sriov_is_debug(adev) ? true : false;
 794 }
 795
 796 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
 797 {
 798         return amdgpu_sriov_is_normal(adev) ? true : false;
 799 }
 800
 801 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
 802 {
 803         if (!amdgpu_sriov_vf(adev) ||
 804             amdgpu_virt_access_debugfs_is_kiq(adev))
 805                 return 0;
 806
 807         if (amdgpu_virt_access_debugfs_is_mmio(adev))
 808                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 809         else
 810                 return -EPERM;
 811
 812         return 0;
 813 }
 814
 815 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
 816 {
 817         if (amdgpu_sriov_vf(adev))
 818                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 819 }
 820
 821 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
 822 {
 823         enum amdgpu_sriov_vf_mode mode;
 824
 825         if (amdgpu_sriov_vf(adev)) {
 826                 if (amdgpu_sriov_is_pp_one_vf(adev))
 827                         mode = SRIOV_VF_MODE_ONE_VF;
 828                 else
 829                         mode = SRIOV_VF_MODE_MULTI_VF;
 830         } else {
 831                 mode = SRIOV_VF_MODE_BARE_METAL;
 832         }
 833
 834         return mode;
 835 }
 836
 837 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)
 838 {
 839         switch (adev->ip_versions[MP0_HWIP][0]) {
 840         case IP_VERSION(13, 0, 0):
 841                 /* no vf autoload, white list */
 842                 if (ucode_id == AMDGPU_UCODE_ID_VCN1 ||
 843                     ucode_id == AMDGPU_UCODE_ID_VCN)
 844                         return false;
 845                 else
 846                         return true;
 847         case IP_VERSION(13, 0, 10):
 848                 /* white list */
 849                 if (ucode_id == AMDGPU_UCODE_ID_CAP
 850                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP
 851                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME
 852                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC
 853                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK
 854                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK
 855                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK
 856                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK
 857                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK
 858                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK
 859                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK
 860                 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK
 861                 || ucode_id == AMDGPU_UCODE_ID_CP_MES
 862                 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA
 863                 || ucode_id == AMDGPU_UCODE_ID_CP_MES1
 864                 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA
 865                 || ucode_id == AMDGPU_UCODE_ID_VCN1
 866                 || ucode_id == AMDGPU_UCODE_ID_VCN)
 867                         return false;
 868                 else
 869                         return true;
 870         default:
 871                 /* lagacy black list */
 872                 if (ucode_id == AMDGPU_UCODE_ID_SDMA0
 873                     || ucode_id == AMDGPU_UCODE_ID_SDMA1
 874                     || ucode_id == AMDGPU_UCODE_ID_SDMA2
 875                     || ucode_id == AMDGPU_UCODE_ID_SDMA3
 876                     || ucode_id == AMDGPU_UCODE_ID_SDMA4
 877                     || ucode_id == AMDGPU_UCODE_ID_SDMA5
 878                     || ucode_id == AMDGPU_UCODE_ID_SDMA6
 879                     || ucode_id == AMDGPU_UCODE_ID_SDMA7
 880                     || ucode_id == AMDGPU_UCODE_ID_RLC_G
 881                     || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
 882                     || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
 883                     || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
 884                     || ucode_id == AMDGPU_UCODE_ID_SMC)
 885                         return true;
 886                 else
 887                         return false;
 888         }
 889 }
 890
 891 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
 892                         struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
 893                         struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)
 894 {
 895         uint32_t i;
 896
 897         if (!adev->virt.is_mm_bw_enabled)
 898                 return;
 899
 900         if (encode) {
 901                 for (i = 0; i < encode_array_size; i++) {
 902                         encode[i].max_width = adev->virt.encode_max_dimension_pixels;
 903                         encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;
 904                         if (encode[i].max_width > 0)
 905                                 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width;
 906                         else
 907                                 encode[i].max_height = 0;
 908                 }
 909         }
 910
 911         if (decode) {
 912                 for (i = 0; i < decode_array_size; i++) {
 913                         decode[i].max_width = adev->virt.decode_max_dimension_pixels;
 914                         decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;
 915                         if (decode[i].max_width > 0)
 916                                 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width;
 917                         else
 918                                 decode[i].max_height = 0;
 919                 }
 920         }
 921 }
 922
 923 static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
 924                                                  u32 acc_flags, u32 hwip,
 925                                                  bool write, u32 *rlcg_flag)
 926 {
 927         bool ret = false;
 928
 929         switch (hwip) {
 930         case GC_HWIP:
 931                 if (amdgpu_sriov_reg_indirect_gc(adev)) {
 932                         *rlcg_flag =
 933                                 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ;
 934                         ret = true;
 935                 /* only in new version, AMDGPU_REGS_NO_KIQ and
 936                  * AMDGPU_REGS_RLC are enabled simultaneously */
 937                 } else if ((acc_flags & AMDGPU_REGS_RLC) &&
 938                                 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
 939                         *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY;
 940                         ret = true;
 941                 }
 942                 break;
 943         case MMHUB_HWIP:
 944                 if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
 945                     (acc_flags & AMDGPU_REGS_RLC) && write) {
 946                         *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE;
 947                         ret = true;
 948                 }
 949                 break;
 950         default:
 951                 break;
 952         }
 953         return ret;
 954 }
 955
 956 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
 957 {
 958         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 959         uint32_t timeout = 50000;
 960         uint32_t i, tmp;
 961         uint32_t ret = 0;
 962         void *scratch_reg0;
 963         void *scratch_reg1;
 964         void *scratch_reg2;
 965         void *scratch_reg3;
 966         void *spare_int;
 967
 968         if (!adev->gfx.rlc.rlcg_reg_access_supported) {
 969                 dev_err(adev->dev,
 970                         "indirect registers access through rlcg is not available\n");
 971                 return 0;
 972         }
 973
 974         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
 975         scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;
 976         scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
 977         scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
 978         scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
 979         if (reg_access_ctrl->spare_int)
 980                 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
 981
 982         if (offset == reg_access_ctrl->grbm_cntl) {
 983                 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */
 984                 writel(v, scratch_reg2);
 985                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
 986         } else if (offset == reg_access_ctrl->grbm_idx) {
 987                 /* if the target reg offset is grbm_idx, write to scratch_reg3 */
 988                 writel(v, scratch_reg3);
 989                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
 990         } else {
 991                 /*
 992                  * SCRATCH_REG0         = read/write value
 993                  * SCRATCH_REG1[30:28]  = command
 994                  * SCRATCH_REG1[19:0]   = address in dword
 995                  * SCRATCH_REG1[26:24]  = Error reporting
 996                  */
 997                 writel(v, scratch_reg0);
 998                 writel((offset | flag), scratch_reg1);
 999                 if (reg_access_ctrl->spare_int)
1000                         writel(1, spare_int);
1001
1002                 for (i = 0; i < timeout; i++) {
1003                         tmp = readl(scratch_reg1);
1004                         if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK))
1005                                 break;
1006                         udelay(10);
1007                 }
1008
1009                 if (i >= timeout) {
1010                         if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {
1011                                 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) {
1012                                         dev_err(adev->dev,
1013                                                 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset);
1014                                 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) {
1015                                         dev_err(adev->dev,
1016                                                 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset);
1017                                 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) {
1018                                         dev_err(adev->dev,
1019                                                 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset);
1020                                 } else {
1021                                         dev_err(adev->dev,
1022                                                 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset);
1023                                 }
1024                         } else {
1025                                 dev_err(adev->dev,
1026                                         "timeout: rlcg faled to program reg: 0x%05x\n", offset);
1027                         }
1028                 }
1029         }
1030
1031         ret = readl(scratch_reg0);
1032         return ret;
1033 }
1034
1035 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
1036                        u32 offset, u32 value,
1037                        u32 acc_flags, u32 hwip)
1038 {
1039         u32 rlcg_flag;
1040
1041         if (!amdgpu_sriov_runtime(adev) &&
1042                 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
1043                 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag);
1044                 return;
1045         }
1046
1047         if (acc_flags & AMDGPU_REGS_NO_KIQ)
1048                 WREG32_NO_KIQ(offset, value);
1049         else
1050                 WREG32(offset, value);
1051 }
1052
1053 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
1054                       u32 offset, u32 acc_flags, u32 hwip)
1055 {
1056         u32 rlcg_flag;
1057
1058         if (!amdgpu_sriov_runtime(adev) &&
1059                 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
1060                 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag);
1061
1062         if (acc_flags & AMDGPU_REGS_NO_KIQ)
1063                 return RREG32_NO_KIQ(offset);
1064         else
1065                 return RREG32(offset);
1066 }