drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 103 {
 104         struct ras_err_data err_data = {0, 0, 0, NULL};
 105         struct eeprom_table_record err_rec;
 106
 107         if ((address >= adev->gmc.mc_vram_size) ||
 108             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 109                 dev_warn(adev->dev,
 110                          "RAS WARN: input address 0x%llx is invalid.\n",
 111                          address);
 112                 return -EINVAL;
 113         }
 114
 115         if (amdgpu_ras_check_bad_page(adev, address)) {
 116                 dev_warn(adev->dev,
 117                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 118                          address);
 119                 return 0;
 120         }
 121
 122         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 123
 124         err_rec.address = address;
 125         err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
 126         err_rec.ts = (uint64_t)ktime_get_real_seconds();
 127         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 128
 129         err_data.err_addr = &err_rec;
 130         err_data.err_addr_cnt = 1;
 131
 132         if (amdgpu_bad_page_threshold != 0) {
 133                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 134                                          err_data.err_addr_cnt);
 135                 amdgpu_ras_save_bad_pages(adev);
 136         }
 137
 138         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 139         dev_warn(adev->dev, "Clear EEPROM:\n");
 140         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 141
 142         return 0;
 143 }
 144
 145 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 146                                         size_t size, loff_t *pos)
 147 {
 148         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 149         struct ras_query_if info = {
 150                 .head = obj->head,
 151         };
 152         ssize_t s;
 153         char val[128];
 154
 155         if (amdgpu_ras_query_error_status(obj->adev, &info))
 156                 return -EINVAL;
 157
 158         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 159                         "ue", info.ue_count,
 160                         "ce", info.ce_count);
 161         if (*pos >= s)
 162                 return 0;
 163
 164         s -= *pos;
 165         s = min_t(u64, s, size);
 166
 167
 168         if (copy_to_user(buf, &val[*pos], s))
 169                 return -EINVAL;
 170
 171         *pos += s;
 172
 173         return s;
 174 }
 175
 176 static const struct file_operations amdgpu_ras_debugfs_ops = {
 177         .owner = THIS_MODULE,
 178         .read = amdgpu_ras_debugfs_read,
 179         .write = NULL,
 180         .llseek = default_llseek
 181 };
 182
 183 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 184 {
 185         int i;
 186
 187         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 188                 *block_id = i;
 189                 if (strcmp(name, ras_block_str(i)) == 0)
 190                         return 0;
 191         }
 192         return -EINVAL;
 193 }
 194
 195 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 196                 const char __user *buf, size_t size,
 197                 loff_t *pos, struct ras_debug_if *data)
 198 {
 199         ssize_t s = min_t(u64, 64, size);
 200         char str[65];
 201         char block_name[33];
 202         char err[9] = "ue";
 203         int op = -1;
 204         int block_id;
 205         uint32_t sub_block;
 206         u64 address, value;
 207
 208         if (*pos)
 209                 return -EINVAL;
 210         *pos = size;
 211
 212         memset(str, 0, sizeof(str));
 213         memset(data, 0, sizeof(*data));
 214
 215         if (copy_from_user(str, buf, s))
 216                 return -EINVAL;
 217
 218         if (sscanf(str, "disable %32s", block_name) == 1)
 219                 op = 0;
 220         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 221                 op = 1;
 222         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 223                 op = 2;
 224         else if (sscanf(str, "retire_page") == 0)
 225                 op = 3;
 226         else if (str[0] && str[1] && str[2] && str[3])
 227                 /* ascii string, but commands are not matched. */
 228                 return -EINVAL;
 229
 230         if (op != -1) {
 231                 if (op == 3) {
 232                         if (sscanf(str, "%*s %llx", &address) != 1)
 233                                 return -EINVAL;
 234
 235                         data->op = op;
 236                         data->inject.address = address;
 237
 238                         return 0;
 239                 }
 240
 241                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 242                         return -EINVAL;
 243
 244                 data->head.block = block_id;
 245                 /* only ue and ce errors are supported */
 246                 if (!memcmp("ue", err, 2))
 247                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 248                 else if (!memcmp("ce", err, 2))
 249                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 250                 else
 251                         return -EINVAL;
 252
 253                 data->op = op;
 254
 255                 if (op == 2) {
 256                         if (sscanf(str, "%*s %*s %*s %x %llx %llx",
 257                                    &sub_block, &address, &value) != 3)
 258                                 return -EINVAL;
 259                         data->head.sub_block_index = sub_block;
 260                         data->inject.address = address;
 261                         data->inject.value = value;
 262                 }
 263         } else {
 264                 if (size < sizeof(*data))
 265                         return -EINVAL;
 266
 267                 if (copy_from_user(data, buf, sizeof(*data)))
 268                         return -EINVAL;
 269         }
 270
 271         return 0;
 272 }
 273
 274 /**
 275  * DOC: AMDGPU RAS debugfs control interface
 276  *
 277  * It accepts struct ras_debug_if who has two members.
 278  *
 279  * First member: ras_debug_if::head or ras_debug_if::inject.
 280  *
 281  * head is used to indicate which IP block will be under control.
 282  *
 283  * head has four members, they are block, type, sub_block_index, name.
 284  * block: which IP will be under control.
 285  * type: what kind of error will be enabled/disabled/injected.
 286  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 287  * name: the name of IP.
 288  *
 289  * inject has two more members than head, they are address, value.
 290  * As their names indicate, inject operation will write the
 291  * value to the address.
 292  *
 293  * The second member: struct ras_debug_if::op.
 294  * It has three kinds of operations.
 295  *
 296  * - 0: disable RAS on the block. Take ::head as its data.
 297  * - 1: enable RAS on the block. Take ::head as its data.
 298  * - 2: inject errors on the block. Take ::inject as its data.
 299  *
 300  * How to use the interface?
 301  *
 302  * Programs
 303  *
 304  * Copy the struct ras_debug_if in your codes and initialize it.
 305  * Write the struct to the control node.
 306  *
 307  * Shells
 308  *
 309  * .. code-block:: bash
 310  *
 311  *      echo op block [error [sub_block address value]] > .../ras/ras_ctrl
 312  *
 313  * Parameters:
 314  *
 315  * op: disable, enable, inject
 316  *      disable: only block is needed
 317  *      enable: block and error are needed
 318  *      inject: error, address, value are needed
 319  * block: umc, sdma, gfx, .........
 320  *      see ras_block_string[] for details
 321  * error: ue, ce
 322  *      ue: multi_uncorrectable
 323  *      ce: single_correctable
 324  * sub_block:
 325  *      sub block index, pass 0 if there is no sub block
 326  *
 327  * here are some examples for bash commands:
 328  *
 329  * .. code-block:: bash
 330  *
 331  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 332  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 333  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 334  *
 335  * How to check the result?
 336  *
 337  * For disable/enable, please check ras features at
 338  * /sys/class/drm/card[0/1/2...]/device/ras/features
 339  *
 340  * For inject, please check corresponding err count at
 341  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 342  *
 343  * .. note::
 344  *      Operations are only allowed on blocks which are supported.
 345  *      Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
 346  *      to see which blocks support RAS on a particular asic.
 347  *
 348  */
 349 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 350                 size_t size, loff_t *pos)
 351 {
 352         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 353         struct ras_debug_if data;
 354         int ret = 0;
 355
 356         if (!amdgpu_ras_get_error_query_ready(adev)) {
 357                 dev_warn(adev->dev, "RAS WARN: error injection "
 358                                 "currently inaccessible\n");
 359                 return size;
 360         }
 361
 362         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 363         if (ret)
 364                 return -EINVAL;
 365
 366         if (data.op == 3) {
 367                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 368                 if (!ret)
 369                         return size;
 370                 else
 371                         return ret;
 372         }
 373
 374         if (!amdgpu_ras_is_supported(adev, data.head.block))
 375                 return -EINVAL;
 376
 377         switch (data.op) {
 378         case 0:
 379                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 380                 break;
 381         case 1:
 382                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 383                 break;
 384         case 2:
 385                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 386                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 387                         dev_warn(adev->dev, "RAS WARN: input address "
 388                                         "0x%llx is invalid.",
 389                                         data.inject.address);
 390                         ret = -EINVAL;
 391                         break;
 392                 }
 393
 394                 /* umc ce/ue error injection for a bad page is not allowed */
 395                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 396                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 397                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 398                                         "as bad before error injection!\n",
 399                                         data.inject.address);
 400                         break;
 401                 }
 402
 403                 /* data.inject.address is offset instead of absolute gpu address */
 404                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 405                 break;
 406         default:
 407                 ret = -EINVAL;
 408                 break;
 409         }
 410
 411         if (ret)
 412                 return -EINVAL;
 413
 414         return size;
 415 }
 416
 417 /**
 418  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 419  *
 420  * Some boards contain an EEPROM which is used to persistently store a list of
 421  * bad pages which experiences ECC errors in vram.  This interface provides
 422  * a way to reset the EEPROM, e.g., after testing error injection.
 423  *
 424  * Usage:
 425  *
 426  * .. code-block:: bash
 427  *
 428  *      echo 1 > ../ras/ras_eeprom_reset
 429  *
 430  * will reset EEPROM table to 0 entries.
 431  *
 432  */
 433 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 434                 size_t size, loff_t *pos)
 435 {
 436         struct amdgpu_device *adev =
 437                 (struct amdgpu_device *)file_inode(f)->i_private;
 438         int ret;
 439
 440         ret = amdgpu_ras_eeprom_reset_table(
 441                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 442
 443         if (ret == 1) {
 444                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 445                 return size;
 446         } else {
 447                 return -EIO;
 448         }
 449 }
 450
 451 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 452         .owner = THIS_MODULE,
 453         .read = NULL,
 454         .write = amdgpu_ras_debugfs_ctrl_write,
 455         .llseek = default_llseek
 456 };
 457
 458 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 459         .owner = THIS_MODULE,
 460         .read = NULL,
 461         .write = amdgpu_ras_debugfs_eeprom_write,
 462         .llseek = default_llseek
 463 };
 464
 465 /**
 466  * DOC: AMDGPU RAS sysfs Error Count Interface
 467  *
 468  * It allows the user to read the error count for each IP block on the gpu through
 469  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 470  *
 471  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 472  * (ce) error counts.
 473  *
 474  * The format of one line is below,
 475  *
 476  * [ce|ue]: count
 477  *
 478  * Example:
 479  *
 480  * .. code-block:: bash
 481  *
 482  *      ue: 0
 483  *      ce: 1
 484  *
 485  */
 486 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 487                 struct device_attribute *attr, char *buf)
 488 {
 489         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 490         struct ras_query_if info = {
 491                 .head = obj->head,
 492         };
 493
 494         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 495                 return sysfs_emit(buf, "Query currently inaccessible\n");
 496
 497         if (amdgpu_ras_query_error_status(obj->adev, &info))
 498                 return -EINVAL;
 499
 500         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 501                           "ce", info.ce_count);
 502 }
 503
 504 /* obj begin */
 505
 506 #define get_obj(obj) do { (obj)->use++; } while (0)
 507 #define alive_obj(obj) ((obj)->use)
 508
 509 static inline void put_obj(struct ras_manager *obj)
 510 {
 511         if (obj && (--obj->use == 0))
 512                 list_del(&obj->node);
 513         if (obj && (obj->use < 0))
 514                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 515 }
 516
 517 /* make one obj and return it. */
 518 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 519                 struct ras_common_if *head)
 520 {
 521         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 522         struct ras_manager *obj;
 523
 524         if (!adev->ras_features || !con)
 525                 return NULL;
 526
 527         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 528                 return NULL;
 529
 530         obj = &con->objs[head->block];
 531         /* already exist. return obj? */
 532         if (alive_obj(obj))
 533                 return NULL;
 534
 535         obj->head = *head;
 536         obj->adev = adev;
 537         list_add(&obj->node, &con->head);
 538         get_obj(obj);
 539
 540         return obj;
 541 }
 542
 543 /* return an obj equal to head, or the first when head is NULL */
 544 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 545                 struct ras_common_if *head)
 546 {
 547         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 548         struct ras_manager *obj;
 549         int i;
 550
 551         if (!adev->ras_features || !con)
 552                 return NULL;
 553
 554         if (head) {
 555                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 556                         return NULL;
 557
 558                 obj = &con->objs[head->block];
 559
 560                 if (alive_obj(obj)) {
 561                         WARN_ON(head->block != obj->head.block);
 562                         return obj;
 563                 }
 564         } else {
 565                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 566                         obj = &con->objs[i];
 567                         if (alive_obj(obj)) {
 568                                 WARN_ON(i != obj->head.block);
 569                                 return obj;
 570                         }
 571                 }
 572         }
 573
 574         return NULL;
 575 }
 576 /* obj end */
 577
 578 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 579                                          const char* invoke_type,
 580                                          const char* block_name,
 581                                          enum ta_ras_status ret)
 582 {
 583         switch (ret) {
 584         case TA_RAS_STATUS__SUCCESS:
 585                 return;
 586         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 587                 dev_warn(adev->dev,
 588                         "RAS WARN: %s %s currently unavailable\n",
 589                         invoke_type,
 590                         block_name);
 591                 break;
 592         default:
 593                 dev_err(adev->dev,
 594                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 595                         invoke_type,
 596                         block_name,
 597                         ret);
 598         }
 599 }
 600
 601 /* feature ctl begin */
 602 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 603                 struct ras_common_if *head)
 604 {
 605         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 606
 607         return con->hw_supported & BIT(head->block);
 608 }
 609
 610 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 611                 struct ras_common_if *head)
 612 {
 613         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 614
 615         return con->features & BIT(head->block);
 616 }
 617
 618 /*
 619  * if obj is not created, then create one.
 620  * set feature enable flag.
 621  */
 622 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 623                 struct ras_common_if *head, int enable)
 624 {
 625         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 626         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 627
 628         /* If hardware does not support ras, then do not create obj.
 629          * But if hardware support ras, we can create the obj.
 630          * Ras framework checks con->hw_supported to see if it need do
 631          * corresponding initialization.
 632          * IP checks con->support to see if it need disable ras.
 633          */
 634         if (!amdgpu_ras_is_feature_allowed(adev, head))
 635                 return 0;
 636         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 637                 return 0;
 638
 639         if (enable) {
 640                 if (!obj) {
 641                         obj = amdgpu_ras_create_obj(adev, head);
 642                         if (!obj)
 643                                 return -EINVAL;
 644                 } else {
 645                         /* In case we create obj somewhere else */
 646                         get_obj(obj);
 647                 }
 648                 con->features |= BIT(head->block);
 649         } else {
 650                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 651                         /* skip clean gfx ras context feature for VEGA20 Gaming.
 652                          * will clean later
 653                          */
 654                         if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)))
 655                                 con->features &= ~BIT(head->block);
 656                         put_obj(obj);
 657                 }
 658         }
 659
 660         return 0;
 661 }
 662
 663 /* wrapper of psp_ras_enable_features */
 664 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 665                 struct ras_common_if *head, bool enable)
 666 {
 667         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 668         union ta_ras_cmd_input *info;
 669         int ret;
 670
 671         if (!con)
 672                 return -EINVAL;
 673
 674         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 675         if (!info)
 676                 return -ENOMEM;
 677
 678         if (!enable) {
 679                 info->disable_features = (struct ta_ras_disable_features_input) {
 680                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 681                         .error_type = amdgpu_ras_error_to_ta(head->type),
 682                 };
 683         } else {
 684                 info->enable_features = (struct ta_ras_enable_features_input) {
 685                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 686                         .error_type = amdgpu_ras_error_to_ta(head->type),
 687                 };
 688         }
 689
 690         /* Do not enable if it is not allowed. */
 691         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 692         /* Are we alerady in that state we are going to set? */
 693         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 694                 ret = 0;
 695                 goto out;
 696         }
 697
 698         if (!amdgpu_ras_intr_triggered()) {
 699                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 700                 if (ret) {
 701                         amdgpu_ras_parse_status_code(adev,
 702                                                      enable ? "enable":"disable",
 703                                                      ras_block_str(head->block),
 704                                                     (enum ta_ras_status)ret);
 705                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 706                                 ret = -EAGAIN;
 707                         else
 708                                 ret = -EINVAL;
 709
 710                         goto out;
 711                 }
 712         }
 713
 714         /* setup the obj */
 715         __amdgpu_ras_feature_enable(adev, head, enable);
 716         ret = 0;
 717 out:
 718         kfree(info);
 719         return ret;
 720 }
 721
 722 /* Only used in device probe stage and called only once. */
 723 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 724                 struct ras_common_if *head, bool enable)
 725 {
 726         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 727         int ret;
 728
 729         if (!con)
 730                 return -EINVAL;
 731
 732         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 733                 if (enable) {
 734                         /* There is no harm to issue a ras TA cmd regardless of
 735                          * the currecnt ras state.
 736                          * If current state == target state, it will do nothing
 737                          * But sometimes it requests driver to reset and repost
 738                          * with error code -EAGAIN.
 739                          */
 740                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 741                         /* With old ras TA, we might fail to enable ras.
 742                          * Log it and just setup the object.
 743                          * TODO need remove this WA in the future.
 744                          */
 745                         if (ret == -EINVAL) {
 746                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 747                                 if (!ret)
 748                                         dev_info(adev->dev,
 749                                                 "RAS INFO: %s setup object\n",
 750                                                 ras_block_str(head->block));
 751                         }
 752                 } else {
 753                         /* setup the object then issue a ras TA disable cmd.*/
 754                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 755                         if (ret)
 756                                 return ret;
 757
 758                         /* gfx block ras dsiable cmd must send to ras-ta */
 759                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 760                                 con->features |= BIT(head->block);
 761
 762                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 763                 }
 764         } else
 765                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 766
 767         return ret;
 768 }
 769
 770 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 771                 bool bypass)
 772 {
 773         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 774         struct ras_manager *obj, *tmp;
 775
 776         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 777                 /* bypass psp.
 778                  * aka just release the obj and corresponding flags
 779                  */
 780                 if (bypass) {
 781                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 782                                 break;
 783                 } else {
 784                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 785                                 break;
 786                 }
 787         }
 788
 789         return con->features;
 790 }
 791
 792 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 793                 bool bypass)
 794 {
 795         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 796         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 797         int i;
 798         const enum amdgpu_ras_error_type default_ras_type =
 799                 AMDGPU_RAS_ERROR__NONE;
 800
 801         for (i = 0; i < ras_block_count; i++) {
 802                 struct ras_common_if head = {
 803                         .block = i,
 804                         .type = default_ras_type,
 805                         .sub_block_index = 0,
 806                 };
 807                 strcpy(head.name, ras_block_str(i));
 808                 if (bypass) {
 809                         /*
 810                          * bypass psp. vbios enable ras for us.
 811                          * so just create the obj
 812                          */
 813                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 814                                 break;
 815                 } else {
 816                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 817                                 break;
 818                 }
 819         }
 820
 821         return con->features;
 822 }
 823 /* feature ctl end */
 824
 825 /* query/inject/cure begin */
 826 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 827         struct ras_query_if *info)
 828 {
 829         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 830         struct ras_err_data err_data = {0, 0, 0, NULL};
 831         int i;
 832
 833         if (!obj)
 834                 return -EINVAL;
 835
 836         switch (info->head.block) {
 837         case AMDGPU_RAS_BLOCK__UMC:
 838                 if (adev->umc.ras_funcs &&
 839                     adev->umc.ras_funcs->query_ras_error_count)
 840                         adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
 841                 /* umc query_ras_error_address is also responsible for clearing
 842                  * error status
 843                  */
 844                 if (adev->umc.ras_funcs &&
 845                     adev->umc.ras_funcs->query_ras_error_address)
 846                         adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
 847                 break;
 848         case AMDGPU_RAS_BLOCK__SDMA:
 849                 if (adev->sdma.funcs->query_ras_error_count) {
 850                         for (i = 0; i < adev->sdma.num_instances; i++)
 851                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 852                                                                         &err_data);
 853                 }
 854                 break;
 855         case AMDGPU_RAS_BLOCK__GFX:
 856                 if (adev->gfx.ras_funcs &&
 857                     adev->gfx.ras_funcs->query_ras_error_count)
 858                         adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
 859
 860                 if (adev->gfx.ras_funcs &&
 861                     adev->gfx.ras_funcs->query_ras_error_status)
 862                         adev->gfx.ras_funcs->query_ras_error_status(adev);
 863                 break;
 864         case AMDGPU_RAS_BLOCK__MMHUB:
 865                 if (adev->mmhub.ras_funcs &&
 866                     adev->mmhub.ras_funcs->query_ras_error_count)
 867                         adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
 868
 869                 if (adev->mmhub.ras_funcs &&
 870                     adev->mmhub.ras_funcs->query_ras_error_status)
 871                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
 872                 break;
 873         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 874                 if (adev->nbio.ras_funcs &&
 875                     adev->nbio.ras_funcs->query_ras_error_count)
 876                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 877                 break;
 878         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 879                 if (adev->gmc.xgmi.ras_funcs &&
 880                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 881                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 882                 break;
 883         default:
 884                 break;
 885         }
 886
 887         obj->err_data.ue_count += err_data.ue_count;
 888         obj->err_data.ce_count += err_data.ce_count;
 889
 890         info->ue_count = obj->err_data.ue_count;
 891         info->ce_count = obj->err_data.ce_count;
 892
 893         if (err_data.ce_count) {
 894                 dev_info(adev->dev, "%ld correctable hardware errors "
 895                                         "detected in %s block, no user "
 896                                         "action is needed.\n",
 897                                         obj->err_data.ce_count,
 898                                         ras_block_str(info->head.block));
 899         }
 900         if (err_data.ue_count) {
 901                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 902                                         "detected in %s block\n",
 903                                         obj->err_data.ue_count,
 904                                         ras_block_str(info->head.block));
 905         }
 906
 907         return 0;
 908 }
 909
 910 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 911                 enum amdgpu_ras_block block)
 912 {
 913         if (!amdgpu_ras_is_supported(adev, block))
 914                 return -EINVAL;
 915
 916         switch (block) {
 917         case AMDGPU_RAS_BLOCK__GFX:
 918                 if (adev->gfx.ras_funcs &&
 919                     adev->gfx.ras_funcs->reset_ras_error_count)
 920                         adev->gfx.ras_funcs->reset_ras_error_count(adev);
 921
 922                 if (adev->gfx.ras_funcs &&
 923                     adev->gfx.ras_funcs->reset_ras_error_status)
 924                         adev->gfx.ras_funcs->reset_ras_error_status(adev);
 925                 break;
 926         case AMDGPU_RAS_BLOCK__MMHUB:
 927                 if (adev->mmhub.ras_funcs &&
 928                     adev->mmhub.ras_funcs->reset_ras_error_count)
 929                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
 930                 break;
 931         case AMDGPU_RAS_BLOCK__SDMA:
 932                 if (adev->sdma.funcs->reset_ras_error_count)
 933                         adev->sdma.funcs->reset_ras_error_count(adev);
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         return 0;
 940 }
 941
 942 /* Trigger XGMI/WAFL error */
 943 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 944                                  struct ta_ras_trigger_error_input *block_info)
 945 {
 946         int ret;
 947
 948         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 949                 dev_warn(adev->dev, "Failed to disallow df cstate");
 950
 951         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 952                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 953
 954         ret = psp_ras_trigger_error(&adev->psp, block_info);
 955
 956         if (amdgpu_ras_intr_triggered())
 957                 return ret;
 958
 959         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 960                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 961
 962         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 963                 dev_warn(adev->dev, "Failed to allow df cstate");
 964
 965         return ret;
 966 }
 967
 968 /* wrapper of psp_ras_trigger_error */
 969 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 970                 struct ras_inject_if *info)
 971 {
 972         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 973         struct ta_ras_trigger_error_input block_info = {
 974                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 975                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 976                 .sub_block_index = info->head.sub_block_index,
 977                 .address = info->address,
 978                 .value = info->value,
 979         };
 980         int ret = 0;
 981
 982         if (!obj)
 983                 return -EINVAL;
 984
 985         /* Calculate XGMI relative offset */
 986         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 987                 block_info.address =
 988                         amdgpu_xgmi_get_relative_phy_addr(adev,
 989                                                           block_info.address);
 990         }
 991
 992         switch (info->head.block) {
 993         case AMDGPU_RAS_BLOCK__GFX:
 994                 if (adev->gfx.ras_funcs &&
 995                     adev->gfx.ras_funcs->ras_error_inject)
 996                         ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
 997                 else
 998                         ret = -EINVAL;
 999                 break;
1000         case AMDGPU_RAS_BLOCK__UMC:
1001         case AMDGPU_RAS_BLOCK__SDMA:
1002         case AMDGPU_RAS_BLOCK__MMHUB:
1003         case AMDGPU_RAS_BLOCK__PCIE_BIF:
1004                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1005                 break;
1006         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1007                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1008                 break;
1009         default:
1010                 dev_info(adev->dev, "%s error injection is not supported yet\n",
1011                          ras_block_str(info->head.block));
1012                 ret = -EINVAL;
1013         }
1014
1015         amdgpu_ras_parse_status_code(adev,
1016                                      "inject",
1017                                      ras_block_str(info->head.block),
1018                                      (enum ta_ras_status)ret);
1019
1020         return ret;
1021 }
1022
1023 /* get the total error counts on all IPs */
1024 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1025                 bool is_ce)
1026 {
1027         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1028         struct ras_manager *obj;
1029         struct ras_err_data data = {0, 0};
1030
1031         if (!adev->ras_features || !con)
1032                 return 0;
1033
1034         list_for_each_entry(obj, &con->head, node) {
1035                 struct ras_query_if info = {
1036                         .head = obj->head,
1037                 };
1038
1039                 if (amdgpu_ras_query_error_status(adev, &info))
1040                         return 0;
1041
1042                 data.ce_count += info.ce_count;
1043                 data.ue_count += info.ue_count;
1044         }
1045
1046         return is_ce ? data.ce_count : data.ue_count;
1047 }
1048 /* query/inject/cure end */
1049
1050
1051 /* sysfs begin */
1052
1053 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1054                 struct ras_badpage **bps, unsigned int *count);
1055
1056 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1057 {
1058         switch (flags) {
1059         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1060                 return "R";
1061         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1062                 return "P";
1063         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1064         default:
1065                 return "F";
1066         }
1067 }
1068
1069 /**
1070  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1071  *
1072  * It allows user to read the bad pages of vram on the gpu through
1073  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1074  *
1075  * It outputs multiple lines, and each line stands for one gpu page.
1076  *
1077  * The format of one line is below,
1078  * gpu pfn : gpu page size : flags
1079  *
1080  * gpu pfn and gpu page size are printed in hex format.
1081  * flags can be one of below character,
1082  *
1083  * R: reserved, this gpu page is reserved and not able to use.
1084  *
1085  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1086  * in next window of page_reserve.
1087  *
1088  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1089  *
1090  * Examples:
1091  *
1092  * .. code-block:: bash
1093  *
1094  *      0x00000001 : 0x00001000 : R
1095  *      0x00000002 : 0x00001000 : P
1096  *
1097  */
1098
1099 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1100                 struct kobject *kobj, struct bin_attribute *attr,
1101                 char *buf, loff_t ppos, size_t count)
1102 {
1103         struct amdgpu_ras *con =
1104                 container_of(attr, struct amdgpu_ras, badpages_attr);
1105         struct amdgpu_device *adev = con->adev;
1106         const unsigned int element_size =
1107                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1108         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1109         unsigned int end = div64_ul(ppos + count - 1, element_size);
1110         ssize_t s = 0;
1111         struct ras_badpage *bps = NULL;
1112         unsigned int bps_count = 0;
1113
1114         memset(buf, 0, count);
1115
1116         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1117                 return 0;
1118
1119         for (; start < end && start < bps_count; start++)
1120                 s += scnprintf(&buf[s], element_size + 1,
1121                                 "0x%08x : 0x%08x : %1s\n",
1122                                 bps[start].bp,
1123                                 bps[start].size,
1124                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1125
1126         kfree(bps);
1127
1128         return s;
1129 }
1130
1131 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1132                 struct device_attribute *attr, char *buf)
1133 {
1134         struct amdgpu_ras *con =
1135                 container_of(attr, struct amdgpu_ras, features_attr);
1136
1137         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1138 }
1139
1140 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1141 {
1142         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1143
1144         sysfs_remove_file_from_group(&adev->dev->kobj,
1145                                 &con->badpages_attr.attr,
1146                                 RAS_FS_NAME);
1147 }
1148
1149 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1150 {
1151         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1152         struct attribute *attrs[] = {
1153                 &con->features_attr.attr,
1154                 NULL
1155         };
1156         struct attribute_group group = {
1157                 .name = RAS_FS_NAME,
1158                 .attrs = attrs,
1159         };
1160
1161         sysfs_remove_group(&adev->dev->kobj, &group);
1162
1163         return 0;
1164 }
1165
1166 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1167                 struct ras_fs_if *head)
1168 {
1169         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1170
1171         if (!obj || obj->attr_inuse)
1172                 return -EINVAL;
1173
1174         get_obj(obj);
1175
1176         memcpy(obj->fs_data.sysfs_name,
1177                         head->sysfs_name,
1178                         sizeof(obj->fs_data.sysfs_name));
1179
1180         obj->sysfs_attr = (struct device_attribute){
1181                 .attr = {
1182                         .name = obj->fs_data.sysfs_name,
1183                         .mode = S_IRUGO,
1184                 },
1185                         .show = amdgpu_ras_sysfs_read,
1186         };
1187         sysfs_attr_init(&obj->sysfs_attr.attr);
1188
1189         if (sysfs_add_file_to_group(&adev->dev->kobj,
1190                                 &obj->sysfs_attr.attr,
1191                                 RAS_FS_NAME)) {
1192                 put_obj(obj);
1193                 return -EINVAL;
1194         }
1195
1196         obj->attr_inuse = 1;
1197
1198         return 0;
1199 }
1200
1201 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1202                 struct ras_common_if *head)
1203 {
1204         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1205
1206         if (!obj || !obj->attr_inuse)
1207                 return -EINVAL;
1208
1209         sysfs_remove_file_from_group(&adev->dev->kobj,
1210                                 &obj->sysfs_attr.attr,
1211                                 RAS_FS_NAME);
1212         obj->attr_inuse = 0;
1213         put_obj(obj);
1214
1215         return 0;
1216 }
1217
1218 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1219 {
1220         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1221         struct ras_manager *obj, *tmp;
1222
1223         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1224                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1225         }
1226
1227         if (amdgpu_bad_page_threshold != 0)
1228                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1229
1230         amdgpu_ras_sysfs_remove_feature_node(adev);
1231
1232         return 0;
1233 }
1234 /* sysfs end */
1235
1236 /**
1237  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1238  *
1239  * Normally when there is an uncorrectable error, the driver will reset
1240  * the GPU to recover.  However, in the event of an unrecoverable error,
1241  * the driver provides an interface to reboot the system automatically
1242  * in that event.
1243  *
1244  * The following file in debugfs provides that interface:
1245  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1246  *
1247  * Usage:
1248  *
1249  * .. code-block:: bash
1250  *
1251  *      echo true > .../ras/auto_reboot
1252  *
1253  */
1254 /* debugfs begin */
1255 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1256 {
1257         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1258         struct dentry *dir;
1259         struct drm_minor *minor = adev_to_drm(adev)->primary;
1260
1261         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1262         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1263                             &amdgpu_ras_debugfs_ctrl_ops);
1264         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1265                             &amdgpu_ras_debugfs_eeprom_ops);
1266         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1267                            &con->bad_page_cnt_threshold);
1268
1269         /*
1270          * After one uncorrectable error happens, usually GPU recovery will
1271          * be scheduled. But due to the known problem in GPU recovery failing
1272          * to bring GPU back, below interface provides one direct way to
1273          * user to reboot system automatically in such case within
1274          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1275          * will never be called.
1276          */
1277         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1278
1279         /*
1280          * User could set this not to clean up hardware's error count register
1281          * of RAS IPs during ras recovery.
1282          */
1283         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1284                             &con->disable_ras_err_cnt_harvest);
1285         return dir;
1286 }
1287
1288 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1289                                       struct ras_fs_if *head,
1290                                       struct dentry *dir)
1291 {
1292         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1293
1294         if (!obj || !dir)
1295                 return;
1296
1297         get_obj(obj);
1298
1299         memcpy(obj->fs_data.debugfs_name,
1300                         head->debugfs_name,
1301                         sizeof(obj->fs_data.debugfs_name));
1302
1303         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1304                             obj, &amdgpu_ras_debugfs_ops);
1305 }
1306
1307 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1308 {
1309         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1310         struct dentry *dir;
1311         struct ras_manager *obj;
1312         struct ras_fs_if fs_info;
1313
1314         /*
1315          * it won't be called in resume path, no need to check
1316          * suspend and gpu reset status
1317          */
1318         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1319                 return;
1320
1321         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1322
1323         list_for_each_entry(obj, &con->head, node) {
1324                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1325                         (obj->attr_inuse == 1)) {
1326                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1327                                         ras_block_str(obj->head.block));
1328                         fs_info.head = obj->head;
1329                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1330                 }
1331         }
1332 }
1333
1334 /* debugfs end */
1335
1336 /* ras fs */
1337 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1338                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1339 static DEVICE_ATTR(features, S_IRUGO,
1340                 amdgpu_ras_sysfs_features_read, NULL);
1341 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1342 {
1343         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1344         struct attribute_group group = {
1345                 .name = RAS_FS_NAME,
1346         };
1347         struct attribute *attrs[] = {
1348                 &con->features_attr.attr,
1349                 NULL
1350         };
1351         struct bin_attribute *bin_attrs[] = {
1352                 NULL,
1353                 NULL,
1354         };
1355         int r;
1356
1357         /* add features entry */
1358         con->features_attr = dev_attr_features;
1359         group.attrs = attrs;
1360         sysfs_attr_init(attrs[0]);
1361
1362         if (amdgpu_bad_page_threshold != 0) {
1363                 /* add bad_page_features entry */
1364                 bin_attr_gpu_vram_bad_pages.private = NULL;
1365                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1366                 bin_attrs[0] = &con->badpages_attr;
1367                 group.bin_attrs = bin_attrs;
1368                 sysfs_bin_attr_init(bin_attrs[0]);
1369         }
1370
1371         r = sysfs_create_group(&adev->dev->kobj, &group);
1372         if (r)
1373                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1374
1375         return 0;
1376 }
1377
1378 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1379 {
1380         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1381         struct ras_manager *con_obj, *ip_obj, *tmp;
1382
1383         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1384                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1385                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1386                         if (ip_obj)
1387                                 put_obj(ip_obj);
1388                 }
1389         }
1390
1391         amdgpu_ras_sysfs_remove_all(adev);
1392         return 0;
1393 }
1394 /* ras fs end */
1395
1396 /* ih begin */
1397 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1398 {
1399         struct ras_ih_data *data = &obj->ih_data;
1400         struct amdgpu_iv_entry entry;
1401         int ret;
1402         struct ras_err_data err_data = {0, 0, 0, NULL};
1403
1404         while (data->rptr != data->wptr) {
1405                 rmb();
1406                 memcpy(&entry, &data->ring[data->rptr],
1407                                 data->element_size);
1408
1409                 wmb();
1410                 data->rptr = (data->aligned_element_size +
1411                                 data->rptr) % data->ring_size;
1412
1413                 /* Let IP handle its data, maybe we need get the output
1414                  * from the callback to udpate the error type/count, etc
1415                  */
1416                 if (data->cb) {
1417                         ret = data->cb(obj->adev, &err_data, &entry);
1418                         /* ue will trigger an interrupt, and in that case
1419                          * we need do a reset to recovery the whole system.
1420                          * But leave IP do that recovery, here we just dispatch
1421                          * the error.
1422                          */
1423                         if (ret == AMDGPU_RAS_SUCCESS) {
1424                                 /* these counts could be left as 0 if
1425                                  * some blocks do not count error number
1426                                  */
1427                                 obj->err_data.ue_count += err_data.ue_count;
1428                                 obj->err_data.ce_count += err_data.ce_count;
1429                         }
1430                 }
1431         }
1432 }
1433
1434 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1435 {
1436         struct ras_ih_data *data =
1437                 container_of(work, struct ras_ih_data, ih_work);
1438         struct ras_manager *obj =
1439                 container_of(data, struct ras_manager, ih_data);
1440
1441         amdgpu_ras_interrupt_handler(obj);
1442 }
1443
1444 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1445                 struct ras_dispatch_if *info)
1446 {
1447         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1448         struct ras_ih_data *data = &obj->ih_data;
1449
1450         if (!obj)
1451                 return -EINVAL;
1452
1453         if (data->inuse == 0)
1454                 return 0;
1455
1456         /* Might be overflow... */
1457         memcpy(&data->ring[data->wptr], info->entry,
1458                         data->element_size);
1459
1460         wmb();
1461         data->wptr = (data->aligned_element_size +
1462                         data->wptr) % data->ring_size;
1463
1464         schedule_work(&data->ih_work);
1465
1466         return 0;
1467 }
1468
1469 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1470                 struct ras_ih_if *info)
1471 {
1472         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1473         struct ras_ih_data *data;
1474
1475         if (!obj)
1476                 return -EINVAL;
1477
1478         data = &obj->ih_data;
1479         if (data->inuse == 0)
1480                 return 0;
1481
1482         cancel_work_sync(&data->ih_work);
1483
1484         kfree(data->ring);
1485         memset(data, 0, sizeof(*data));
1486         put_obj(obj);
1487
1488         return 0;
1489 }
1490
1491 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1492                 struct ras_ih_if *info)
1493 {
1494         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1495         struct ras_ih_data *data;
1496
1497         if (!obj) {
1498                 /* in case we registe the IH before enable ras feature */
1499                 obj = amdgpu_ras_create_obj(adev, &info->head);
1500                 if (!obj)
1501                         return -EINVAL;
1502         } else
1503                 get_obj(obj);
1504
1505         data = &obj->ih_data;
1506         /* add the callback.etc */
1507         *data = (struct ras_ih_data) {
1508                 .inuse = 0,
1509                 .cb = info->cb,
1510                 .element_size = sizeof(struct amdgpu_iv_entry),
1511                 .rptr = 0,
1512                 .wptr = 0,
1513         };
1514
1515         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1516
1517         data->aligned_element_size = ALIGN(data->element_size, 8);
1518         /* the ring can store 64 iv entries. */
1519         data->ring_size = 64 * data->aligned_element_size;
1520         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1521         if (!data->ring) {
1522                 put_obj(obj);
1523                 return -ENOMEM;
1524         }
1525
1526         /* IH is ready */
1527         data->inuse = 1;
1528
1529         return 0;
1530 }
1531
1532 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1533 {
1534         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1535         struct ras_manager *obj, *tmp;
1536
1537         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1538                 struct ras_ih_if info = {
1539                         .head = obj->head,
1540                 };
1541                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1542         }
1543
1544         return 0;
1545 }
1546 /* ih end */
1547
1548 /* traversal all IPs except NBIO to query error counter */
1549 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1550 {
1551         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1552         struct ras_manager *obj;
1553
1554         if (!adev->ras_features || !con)
1555                 return;
1556
1557         list_for_each_entry(obj, &con->head, node) {
1558                 struct ras_query_if info = {
1559                         .head = obj->head,
1560                 };
1561
1562                 /*
1563                  * PCIE_BIF IP has one different isr by ras controller
1564                  * interrupt, the specific ras counter query will be
1565                  * done in that isr. So skip such block from common
1566                  * sync flood interrupt isr calling.
1567                  */
1568                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1569                         continue;
1570
1571                 amdgpu_ras_query_error_status(adev, &info);
1572         }
1573 }
1574
1575 /* Parse RdRspStatus and WrRspStatus */
1576 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1577                                           struct ras_query_if *info)
1578 {
1579         /*
1580          * Only two block need to query read/write
1581          * RspStatus at current state
1582          */
1583         switch (info->head.block) {
1584         case AMDGPU_RAS_BLOCK__GFX:
1585                 if (adev->gfx.ras_funcs &&
1586                     adev->gfx.ras_funcs->query_ras_error_status)
1587                         adev->gfx.ras_funcs->query_ras_error_status(adev);
1588                 break;
1589         case AMDGPU_RAS_BLOCK__MMHUB:
1590                 if (adev->mmhub.ras_funcs &&
1591                     adev->mmhub.ras_funcs->query_ras_error_status)
1592                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
1593                 break;
1594         default:
1595                 break;
1596         }
1597 }
1598
1599 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1600 {
1601         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1602         struct ras_manager *obj;
1603
1604         if (!adev->ras_features || !con)
1605                 return;
1606
1607         list_for_each_entry(obj, &con->head, node) {
1608                 struct ras_query_if info = {
1609                         .head = obj->head,
1610                 };
1611
1612                 amdgpu_ras_error_status_query(adev, &info);
1613         }
1614 }
1615
1616 /* recovery begin */
1617
1618 /* return 0 on success.
1619  * caller need free bps.
1620  */
1621 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1622                 struct ras_badpage **bps, unsigned int *count)
1623 {
1624         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1625         struct ras_err_handler_data *data;
1626         int i = 0;
1627         int ret = 0, status;
1628
1629         if (!con || !con->eh_data || !bps || !count)
1630                 return -EINVAL;
1631
1632         mutex_lock(&con->recovery_lock);
1633         data = con->eh_data;
1634         if (!data || data->count == 0) {
1635                 *bps = NULL;
1636                 ret = -EINVAL;
1637                 goto out;
1638         }
1639
1640         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1641         if (!*bps) {
1642                 ret = -ENOMEM;
1643                 goto out;
1644         }
1645
1646         for (; i < data->count; i++) {
1647                 (*bps)[i] = (struct ras_badpage){
1648                         .bp = data->bps[i].retired_page,
1649                         .size = AMDGPU_GPU_PAGE_SIZE,
1650                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1651                 };
1652                 status = amdgpu_vram_mgr_query_page_status(
1653                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1654                                 data->bps[i].retired_page);
1655                 if (status == -EBUSY)
1656                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1657                 else if (status == -ENOENT)
1658                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1659         }
1660
1661         *count = data->count;
1662 out:
1663         mutex_unlock(&con->recovery_lock);
1664         return ret;
1665 }
1666
1667 static void amdgpu_ras_do_recovery(struct work_struct *work)
1668 {
1669         struct amdgpu_ras *ras =
1670                 container_of(work, struct amdgpu_ras, recovery_work);
1671         struct amdgpu_device *remote_adev = NULL;
1672         struct amdgpu_device *adev = ras->adev;
1673         struct list_head device_list, *device_list_handle =  NULL;
1674
1675         if (!ras->disable_ras_err_cnt_harvest) {
1676                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1677
1678                 /* Build list of devices to query RAS related errors */
1679                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1680                         device_list_handle = &hive->device_list;
1681                 } else {
1682                         INIT_LIST_HEAD(&device_list);
1683                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1684                         device_list_handle = &device_list;
1685                 }
1686
1687                 list_for_each_entry(remote_adev,
1688                                 device_list_handle, gmc.xgmi.head) {
1689                         amdgpu_ras_query_err_status(remote_adev);
1690                         amdgpu_ras_log_on_err_counter(remote_adev);
1691                 }
1692
1693                 amdgpu_put_xgmi_hive(hive);
1694         }
1695
1696         if (amdgpu_device_should_recover_gpu(ras->adev))
1697                 amdgpu_device_gpu_recover(ras->adev, NULL);
1698         atomic_set(&ras->in_recovery, 0);
1699 }
1700
1701 /* alloc/realloc bps array */
1702 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1703                 struct ras_err_handler_data *data, int pages)
1704 {
1705         unsigned int old_space = data->count + data->space_left;
1706         unsigned int new_space = old_space + pages;
1707         unsigned int align_space = ALIGN(new_space, 512);
1708         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1709
1710         if (!bps) {
1711                 kfree(bps);
1712                 return -ENOMEM;
1713         }
1714
1715         if (data->bps) {
1716                 memcpy(bps, data->bps,
1717                                 data->count * sizeof(*data->bps));
1718                 kfree(data->bps);
1719         }
1720
1721         data->bps = bps;
1722         data->space_left += align_space - old_space;
1723         return 0;
1724 }
1725
1726 /* it deal with vram only. */
1727 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1728                 struct eeprom_table_record *bps, int pages)
1729 {
1730         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1731         struct ras_err_handler_data *data;
1732         int ret = 0;
1733         uint32_t i;
1734
1735         if (!con || !con->eh_data || !bps || pages <= 0)
1736                 return 0;
1737
1738         mutex_lock(&con->recovery_lock);
1739         data = con->eh_data;
1740         if (!data)
1741                 goto out;
1742
1743         for (i = 0; i < pages; i++) {
1744                 if (amdgpu_ras_check_bad_page_unlock(con,
1745                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1746                         continue;
1747
1748                 if (!data->space_left &&
1749                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1750                         ret = -ENOMEM;
1751                         goto out;
1752                 }
1753
1754                 amdgpu_vram_mgr_reserve_range(
1755                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1756                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1757                         AMDGPU_GPU_PAGE_SIZE);
1758
1759                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1760                 data->count++;
1761                 data->space_left--;
1762         }
1763 out:
1764         mutex_unlock(&con->recovery_lock);
1765
1766         return ret;
1767 }
1768
1769 /*
1770  * write error record array to eeprom, the function should be
1771  * protected by recovery_lock
1772  */
1773 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1774 {
1775         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1776         struct ras_err_handler_data *data;
1777         struct amdgpu_ras_eeprom_control *control;
1778         int save_count;
1779
1780         if (!con || !con->eh_data)
1781                 return 0;
1782
1783         control = &con->eeprom_control;
1784         data = con->eh_data;
1785         save_count = data->count - control->num_recs;
1786         /* only new entries are saved */
1787         if (save_count > 0) {
1788                 if (amdgpu_ras_eeprom_process_recods(control,
1789                                                         &data->bps[control->num_recs],
1790                                                         true,
1791                                                         save_count)) {
1792                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1793                         return -EIO;
1794                 }
1795
1796                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1797         }
1798
1799         return 0;
1800 }
1801
1802 /*
1803  * read error record array in eeprom and reserve enough space for
1804  * storing new bad pages
1805  */
1806 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1807 {
1808         struct amdgpu_ras_eeprom_control *control =
1809                                         &adev->psp.ras.ras->eeprom_control;
1810         struct eeprom_table_record *bps = NULL;
1811         int ret = 0;
1812
1813         /* no bad page record, skip eeprom access */
1814         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1815                 return ret;
1816
1817         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1818         if (!bps)
1819                 return -ENOMEM;
1820
1821         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1822                 control->num_recs)) {
1823                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1824                 ret = -EIO;
1825                 goto out;
1826         }
1827
1828         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1829
1830 out:
1831         kfree(bps);
1832         return ret;
1833 }
1834
1835 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1836                                 uint64_t addr)
1837 {
1838         struct ras_err_handler_data *data = con->eh_data;
1839         int i;
1840
1841         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1842         for (i = 0; i < data->count; i++)
1843                 if (addr == data->bps[i].retired_page)
1844                         return true;
1845
1846         return false;
1847 }
1848
1849 /*
1850  * check if an address belongs to bad page
1851  *
1852  * Note: this check is only for umc block
1853  */
1854 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1855                                 uint64_t addr)
1856 {
1857         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1858         bool ret = false;
1859
1860         if (!con || !con->eh_data)
1861                 return ret;
1862
1863         mutex_lock(&con->recovery_lock);
1864         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1865         mutex_unlock(&con->recovery_lock);
1866         return ret;
1867 }
1868
1869 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1870                                         uint32_t max_length)
1871 {
1872         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1873         int tmp_threshold = amdgpu_bad_page_threshold;
1874         u64 val;
1875
1876         /*
1877          * Justification of value bad_page_cnt_threshold in ras structure
1878          *
1879          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1880          * in eeprom, and introduce two scenarios accordingly.
1881          *
1882          * Bad page retirement enablement:
1883          *    - If amdgpu_bad_page_threshold = -1,
1884          *      bad_page_cnt_threshold = typical value by formula.
1885          *
1886          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1887          *      max record length in eeprom, use it directly.
1888          *
1889          * Bad page retirement disablement:
1890          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1891          *      functionality is disabled, and bad_page_cnt_threshold will
1892          *      take no effect.
1893          */
1894
1895         if (tmp_threshold < -1)
1896                 tmp_threshold = -1;
1897         else if (tmp_threshold > max_length)
1898                 tmp_threshold = max_length;
1899
1900         if (tmp_threshold == -1) {
1901                 val = adev->gmc.mc_vram_size;
1902                 do_div(val, RAS_BAD_PAGE_RATE);
1903                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1904                                                 max_length);
1905         } else {
1906                 con->bad_page_cnt_threshold = tmp_threshold;
1907         }
1908 }
1909
1910 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1911 {
1912         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1913         struct ras_err_handler_data **data;
1914         uint32_t max_eeprom_records_len = 0;
1915         bool exc_err_limit = false;
1916         int ret;
1917
1918         if (adev->ras_features && con)
1919                 data = &con->eh_data;
1920         else
1921                 return 0;
1922
1923         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1924         if (!*data) {
1925                 ret = -ENOMEM;
1926                 goto out;
1927         }
1928
1929         mutex_init(&con->recovery_lock);
1930         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1931         atomic_set(&con->in_recovery, 0);
1932         con->adev = adev;
1933
1934         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1935         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1936
1937         /* Todo: During test the SMU might fail to read the eeprom through I2C
1938          * when the GPU is pending on XGMI reset during probe time
1939          * (Mostly after second bus reset), skip it now
1940          */
1941         if (adev->gmc.xgmi.pending_reset)
1942                 return 0;
1943         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1944         /*
1945          * This calling fails when exc_err_limit is true or
1946          * ret != 0.
1947          */
1948         if (exc_err_limit || ret)
1949                 goto free;
1950
1951         if (con->eeprom_control.num_recs) {
1952                 ret = amdgpu_ras_load_bad_pages(adev);
1953                 if (ret)
1954                         goto free;
1955         }
1956
1957         return 0;
1958
1959 free:
1960         kfree((*data)->bps);
1961         kfree(*data);
1962         con->eh_data = NULL;
1963 out:
1964         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1965
1966         /*
1967          * Except error threshold exceeding case, other failure cases in this
1968          * function would not fail amdgpu driver init.
1969          */
1970         if (!exc_err_limit)
1971                 ret = 0;
1972         else
1973                 ret = -EINVAL;
1974
1975         return ret;
1976 }
1977
1978 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1979 {
1980         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1981         struct ras_err_handler_data *data = con->eh_data;
1982
1983         /* recovery_init failed to init it, fini is useless */
1984         if (!data)
1985                 return 0;
1986
1987         cancel_work_sync(&con->recovery_work);
1988
1989         mutex_lock(&con->recovery_lock);
1990         con->eh_data = NULL;
1991         kfree(data->bps);
1992         kfree(data);
1993         mutex_unlock(&con->recovery_lock);
1994
1995         return 0;
1996 }
1997 /* recovery end */
1998
1999 /* return 0 if ras will reset gpu and repost.*/
2000 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2001                 unsigned int block)
2002 {
2003         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2004
2005         if (!ras)
2006                 return -EINVAL;
2007
2008         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2009         return 0;
2010 }
2011
2012 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2013 {
2014         return adev->asic_type == CHIP_VEGA10 ||
2015                 adev->asic_type == CHIP_VEGA20 ||
2016                 adev->asic_type == CHIP_ARCTURUS ||
2017                 adev->asic_type == CHIP_ALDEBARAN ||
2018                 adev->asic_type == CHIP_SIENNA_CICHLID;
2019 }
2020
2021 /*
2022  * check hardware's ras ability which will be saved in hw_supported.
2023  * if hardware does not support ras, we can skip some ras initializtion and
2024  * forbid some ras operations from IP.
2025  * if software itself, say boot parameter, limit the ras ability. We still
2026  * need allow IP do some limited operations, like disable. In such case,
2027  * we have to initialize ras as normal. but need check if operation is
2028  * allowed or not in each function.
2029  */
2030 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
2031                 uint32_t *hw_supported, uint32_t *supported)
2032 {
2033         *hw_supported = 0;
2034         *supported = 0;
2035
2036         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2037             !amdgpu_ras_asic_supported(adev))
2038                 return;
2039
2040         if (!adev->gmc.xgmi.connected_to_cpu) {
2041                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2042                         dev_info(adev->dev, "MEM ECC is active.\n");
2043                         *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
2044                                         1 << AMDGPU_RAS_BLOCK__DF);
2045                 } else {
2046                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2047                 }
2048
2049                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2050                         dev_info(adev->dev, "SRAM ECC is active.\n");
2051                         *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2052                                         1 << AMDGPU_RAS_BLOCK__DF);
2053                 } else {
2054                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2055                 }
2056         } else {
2057                 /* driver only manages a few IP blocks RAS feature
2058                  * when GPU is connected cpu through XGMI */
2059                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX |
2060                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2061                                 1 << AMDGPU_RAS_BLOCK__MMHUB);
2062         }
2063
2064         /* hw_supported needs to be aligned with RAS block mask. */
2065         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
2066
2067         *supported = amdgpu_ras_enable == 0 ?
2068                         0 : *hw_supported & amdgpu_ras_mask;
2069         adev->ras_features = *supported;
2070 }
2071
2072 int amdgpu_ras_init(struct amdgpu_device *adev)
2073 {
2074         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2075         int r;
2076
2077         if (con)
2078                 return 0;
2079
2080         con = kmalloc(sizeof(struct amdgpu_ras) +
2081                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2082                         GFP_KERNEL|__GFP_ZERO);
2083         if (!con)
2084                 return -ENOMEM;
2085
2086         con->objs = (struct ras_manager *)(con + 1);
2087
2088         amdgpu_ras_set_context(adev, con);
2089
2090         amdgpu_ras_check_supported(adev, &con->hw_supported,
2091                         &con->supported);
2092         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2093                 /* set gfx block ras context feature for VEGA20 Gaming
2094                  * send ras disable cmd to ras ta during ras late init.
2095                  */
2096                 if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
2097                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2098
2099                         return 0;
2100                 }
2101
2102                 r = 0;
2103                 goto release_con;
2104         }
2105
2106         con->features = 0;
2107         INIT_LIST_HEAD(&con->head);
2108         /* Might need get this flag from vbios. */
2109         con->flags = RAS_DEFAULT_FLAGS;
2110
2111         /* initialize nbio ras function ahead of any other
2112          * ras functions so hardware fatal error interrupt
2113          * can be enabled as early as possible */
2114         switch (adev->asic_type) {
2115         case CHIP_VEGA20:
2116         case CHIP_ARCTURUS:
2117         case CHIP_ALDEBARAN:
2118                 if (!adev->gmc.xgmi.connected_to_cpu)
2119                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2120                 break;
2121         default:
2122                 /* nbio ras is not available */
2123                 break;
2124         }
2125
2126         if (adev->nbio.ras_funcs &&
2127             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2128                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2129                 if (r)
2130                         goto release_con;
2131         }
2132
2133         if (adev->nbio.ras_funcs &&
2134             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2135                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2136                 if (r)
2137                         goto release_con;
2138         }
2139
2140         if (amdgpu_ras_fs_init(adev)) {
2141                 r = -EINVAL;
2142                 goto release_con;
2143         }
2144
2145         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2146                         "hardware ability[%x] ras_mask[%x]\n",
2147                         con->hw_supported, con->supported);
2148         return 0;
2149 release_con:
2150         amdgpu_ras_set_context(adev, NULL);
2151         kfree(con);
2152
2153         return r;
2154 }
2155
2156 static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2157 {
2158         if (adev->gmc.xgmi.connected_to_cpu)
2159                 return 1;
2160         return 0;
2161 }
2162
2163 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2164                                         struct ras_common_if *ras_block)
2165 {
2166         struct ras_query_if info = {
2167                 .head = *ras_block,
2168         };
2169
2170         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2171                 return 0;
2172
2173         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2174                 DRM_WARN("RAS init harvest failure");
2175
2176         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2177                 DRM_WARN("RAS init harvest reset failure");
2178
2179         return 0;
2180 }
2181
2182 /* helper function to handle common stuff in ip late init phase */
2183 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2184                          struct ras_common_if *ras_block,
2185                          struct ras_fs_if *fs_info,
2186                          struct ras_ih_if *ih_info)
2187 {
2188         int r;
2189
2190         /* disable RAS feature per IP block if it is not supported */
2191         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2192                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2193                 return 0;
2194         }
2195
2196         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2197         if (r) {
2198                 if (r == -EAGAIN) {
2199                         /* request gpu reset. will run again */
2200                         amdgpu_ras_request_reset_on_boot(adev,
2201                                         ras_block->block);
2202                         return 0;
2203                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2204                         /* in resume phase, if fail to enable ras,
2205                          * clean up all ras fs nodes, and disable ras */
2206                         goto cleanup;
2207                 } else
2208                         return r;
2209         }
2210
2211         /* check for errors on warm reset edc persisant supported ASIC */
2212         amdgpu_persistent_edc_harvesting(adev, ras_block);
2213
2214         /* in resume phase, no need to create ras fs node */
2215         if (adev->in_suspend || amdgpu_in_reset(adev))
2216                 return 0;
2217
2218         if (ih_info->cb) {
2219                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2220                 if (r)
2221                         goto interrupt;
2222         }
2223
2224         r = amdgpu_ras_sysfs_create(adev, fs_info);
2225         if (r)
2226                 goto sysfs;
2227
2228         return 0;
2229 cleanup:
2230         amdgpu_ras_sysfs_remove(adev, ras_block);
2231 sysfs:
2232         if (ih_info->cb)
2233                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2234 interrupt:
2235         amdgpu_ras_feature_enable(adev, ras_block, 0);
2236         return r;
2237 }
2238
2239 /* helper function to remove ras fs node and interrupt handler */
2240 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2241                           struct ras_common_if *ras_block,
2242                           struct ras_ih_if *ih_info)
2243 {
2244         if (!ras_block || !ih_info)
2245                 return;
2246
2247         amdgpu_ras_sysfs_remove(adev, ras_block);
2248         if (ih_info->cb)
2249                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2250         amdgpu_ras_feature_enable(adev, ras_block, 0);
2251 }
2252
2253 /* do some init work after IP late init as dependence.
2254  * and it runs in resume/gpu reset/booting up cases.
2255  */
2256 void amdgpu_ras_resume(struct amdgpu_device *adev)
2257 {
2258         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2259         struct ras_manager *obj, *tmp;
2260
2261         if (!adev->ras_features || !con) {
2262                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2263                 amdgpu_release_ras_context(adev);
2264
2265                 return;
2266         }
2267
2268         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2269                 /* Set up all other IPs which are not implemented. There is a
2270                  * tricky thing that IP's actual ras error type should be
2271                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2272                  * ERROR_NONE make sense anyway.
2273                  */
2274                 amdgpu_ras_enable_all_features(adev, 1);
2275
2276                 /* We enable ras on all hw_supported block, but as boot
2277                  * parameter might disable some of them and one or more IP has
2278                  * not implemented yet. So we disable them on behalf.
2279                  */
2280                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2281                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2282                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2283                                 /* there should be no any reference. */
2284                                 WARN_ON(alive_obj(obj));
2285                         }
2286                 }
2287         }
2288
2289         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2290                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2291                 /* setup ras obj state as disabled.
2292                  * for init_by_vbios case.
2293                  * if we want to enable ras, just enable it in a normal way.
2294                  * If we want do disable it, need setup ras obj as enabled,
2295                  * then issue another TA disable cmd.
2296                  * See feature_enable_on_boot
2297                  */
2298                 amdgpu_ras_disable_all_features(adev, 1);
2299                 amdgpu_ras_reset_gpu(adev);
2300         }
2301 }
2302
2303 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2304 {
2305         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2306
2307         if (!adev->ras_features || !con)
2308                 return;
2309
2310         amdgpu_ras_disable_all_features(adev, 0);
2311         /* Make sure all ras objects are disabled. */
2312         if (con->features)
2313                 amdgpu_ras_disable_all_features(adev, 1);
2314 }
2315
2316 /* do some fini work before IP fini as dependence */
2317 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2318 {
2319         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2320
2321         if (!adev->ras_features || !con)
2322                 return 0;
2323
2324         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2325         amdgpu_ras_disable_all_features(adev, 0);
2326         amdgpu_ras_recovery_fini(adev);
2327         return 0;
2328 }
2329
2330 int amdgpu_ras_fini(struct amdgpu_device *adev)
2331 {
2332         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2333
2334         if (!adev->ras_features || !con)
2335                 return 0;
2336
2337         amdgpu_ras_fs_fini(adev);
2338         amdgpu_ras_interrupt_remove_all(adev);
2339
2340         WARN(con->features, "Feature mask is not cleared");
2341
2342         if (con->features)
2343                 amdgpu_ras_disable_all_features(adev, 1);
2344
2345         amdgpu_ras_set_context(adev, NULL);
2346         kfree(con);
2347
2348         return 0;
2349 }
2350
2351 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2352 {
2353         uint32_t hw_supported, supported;
2354
2355         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2356         if (!hw_supported)
2357                 return;
2358
2359         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2360                 dev_info(adev->dev, "uncorrectable hardware error"
2361                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2362
2363                 amdgpu_ras_reset_gpu(adev);
2364         }
2365 }
2366
2367 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2368 {
2369         if (adev->asic_type == CHIP_VEGA20 &&
2370             adev->pm.fw_version <= 0x283400) {
2371                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2372                                 amdgpu_ras_intr_triggered();
2373         }
2374
2375         return false;
2376 }
2377
2378 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2379 {
2380         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2381
2382         if (!con)
2383                 return;
2384
2385         if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2386                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2387                 amdgpu_ras_set_context(adev, NULL);
2388                 kfree(con);
2389         }
2390 }