drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "si_dpm.h"
  34 #include "cik_dpm.h"
  35 #include "vi_dpm.h"
  36
  37 static int amdgpu_create_pp_handle(struct amdgpu_device *adev)
  38 {
  39         struct amd_pp_init pp_init;
  40         struct amd_powerplay *amd_pp;
  41         int ret;
  42
  43         amd_pp = &(adev->powerplay);
  44         pp_init.chip_family = adev->family;
  45         pp_init.chip_id = adev->asic_type;
  46         pp_init.pm_en = amdgpu_dpm != 0 ? true : false;
  47         pp_init.feature_mask = amdgpu_pp_feature_mask;
  48         pp_init.device = amdgpu_cgs_create_device(adev);
  49         ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle));
  50         if (ret)
  51                 return -EINVAL;
  52         return 0;
  53 }
  54
  55 static int amdgpu_pp_early_init(void *handle)
  56 {
  57         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  58         struct amd_powerplay *amd_pp;
  59         int ret = 0;
  60
  61         amd_pp = &(adev->powerplay);
  62         adev->pp_enabled = false;
  63         amd_pp->pp_handle = (void *)adev;
  64
  65         switch (adev->asic_type) {
  66         case CHIP_POLARIS11:
  67         case CHIP_POLARIS10:
  68         case CHIP_POLARIS12:
  69         case CHIP_TONGA:
  70         case CHIP_FIJI:
  71         case CHIP_TOPAZ:
  72         case CHIP_CARRIZO:
  73         case CHIP_STONEY:
  74                 adev->pp_enabled = true;
  75                 if (amdgpu_create_pp_handle(adev))
  76                         return -EINVAL;
  77                 amd_pp->ip_funcs = &pp_ip_funcs;
  78                 amd_pp->pp_funcs = &pp_dpm_funcs;
  79                 break;
  80         /* These chips don't have powerplay implemenations */
  81 #ifdef CONFIG_DRM_AMDGPU_SI
  82         case CHIP_TAHITI:
  83         case CHIP_PITCAIRN:
  84         case CHIP_VERDE:
  85         case CHIP_OLAND:
  86         case CHIP_HAINAN:
  87                 amd_pp->ip_funcs = &si_dpm_ip_funcs;
  88         break;
  89 #endif
  90 #ifdef CONFIG_DRM_AMDGPU_CIK
  91         case CHIP_BONAIRE:
  92         case CHIP_HAWAII:
  93                 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  94                 break;
  95         case CHIP_KABINI:
  96         case CHIP_MULLINS:
  97         case CHIP_KAVERI:
  98                 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
  99                 break;
 100 #endif
 101         default:
 102                 ret = -EINVAL;
 103                 break;
 104         }
 105
 106         if (adev->powerplay.ip_funcs->early_init)
 107                 ret = adev->powerplay.ip_funcs->early_init(
 108                                         adev->powerplay.pp_handle);
 109
 110         if (ret == PP_DPM_DISABLED) {
 111                 adev->pm.dpm_enabled = false;
 112                 return 0;
 113         }
 114         return ret;
 115 }
 116
 117
 118 static int amdgpu_pp_late_init(void *handle)
 119 {
 120         int ret = 0;
 121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 122
 123         if (adev->powerplay.ip_funcs->late_init)
 124                 ret = adev->powerplay.ip_funcs->late_init(
 125                                         adev->powerplay.pp_handle);
 126
 127         if (adev->pp_enabled && adev->pm.dpm_enabled) {
 128                 amdgpu_pm_sysfs_init(adev);
 129                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
 130         }
 131
 132         return ret;
 133 }
 134
 135 static int amdgpu_pp_sw_init(void *handle)
 136 {
 137         int ret = 0;
 138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 139
 140         if (adev->powerplay.ip_funcs->sw_init)
 141                 ret = adev->powerplay.ip_funcs->sw_init(
 142                                         adev->powerplay.pp_handle);
 143
 144         return ret;
 145 }
 146
 147 static int amdgpu_pp_sw_fini(void *handle)
 148 {
 149         int ret = 0;
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151
 152         if (adev->powerplay.ip_funcs->sw_fini)
 153                 ret = adev->powerplay.ip_funcs->sw_fini(
 154                                         adev->powerplay.pp_handle);
 155         if (ret)
 156                 return ret;
 157
 158         return ret;
 159 }
 160
 161 static int amdgpu_pp_hw_init(void *handle)
 162 {
 163         int ret = 0;
 164         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 165
 166         if (adev->pp_enabled && adev->firmware.smu_load)
 167                 amdgpu_ucode_init_bo(adev);
 168
 169         if (adev->powerplay.ip_funcs->hw_init)
 170                 ret = adev->powerplay.ip_funcs->hw_init(
 171                                         adev->powerplay.pp_handle);
 172
 173         if (ret == PP_DPM_DISABLED) {
 174                 adev->pm.dpm_enabled = false;
 175                 return 0;
 176         }
 177
 178         if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
 179                 adev->pm.dpm_enabled = true;
 180
 181         return ret;
 182 }
 183
 184 static int amdgpu_pp_hw_fini(void *handle)
 185 {
 186         int ret = 0;
 187         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 188
 189         if (adev->powerplay.ip_funcs->hw_fini)
 190                 ret = adev->powerplay.ip_funcs->hw_fini(
 191                                         adev->powerplay.pp_handle);
 192
 193         if (adev->pp_enabled && adev->firmware.smu_load)
 194                 amdgpu_ucode_fini_bo(adev);
 195
 196         return ret;
 197 }
 198
 199 static void amdgpu_pp_late_fini(void *handle)
 200 {
 201         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 202
 203         if (adev->powerplay.ip_funcs->late_fini)
 204                 adev->powerplay.ip_funcs->late_fini(
 205                           adev->powerplay.pp_handle);
 206
 207         if (adev->pp_enabled && adev->pm.dpm_enabled)
 208                 amdgpu_pm_sysfs_fini(adev);
 209
 210         amd_powerplay_destroy(adev->powerplay.pp_handle);
 211 }
 212
 213 static int amdgpu_pp_suspend(void *handle)
 214 {
 215         int ret = 0;
 216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 217
 218         if (adev->powerplay.ip_funcs->suspend)
 219                 ret = adev->powerplay.ip_funcs->suspend(
 220                                          adev->powerplay.pp_handle);
 221         return ret;
 222 }
 223
 224 static int amdgpu_pp_resume(void *handle)
 225 {
 226         int ret = 0;
 227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 228
 229         if (adev->powerplay.ip_funcs->resume)
 230                 ret = adev->powerplay.ip_funcs->resume(
 231                                         adev->powerplay.pp_handle);
 232         return ret;
 233 }
 234
 235 static int amdgpu_pp_set_clockgating_state(void *handle,
 236                                         enum amd_clockgating_state state)
 237 {
 238         int ret = 0;
 239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 240
 241         if (adev->powerplay.ip_funcs->set_clockgating_state)
 242                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 243                                 adev->powerplay.pp_handle, state);
 244         return ret;
 245 }
 246
 247 static int amdgpu_pp_set_powergating_state(void *handle,
 248                                         enum amd_powergating_state state)
 249 {
 250         int ret = 0;
 251         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 252
 253         if (adev->powerplay.ip_funcs->set_powergating_state)
 254                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 255                                  adev->powerplay.pp_handle, state);
 256         return ret;
 257 }
 258
 259
 260 static bool amdgpu_pp_is_idle(void *handle)
 261 {
 262         bool ret = true;
 263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 264
 265         if (adev->powerplay.ip_funcs->is_idle)
 266                 ret = adev->powerplay.ip_funcs->is_idle(
 267                                         adev->powerplay.pp_handle);
 268         return ret;
 269 }
 270
 271 static int amdgpu_pp_wait_for_idle(void *handle)
 272 {
 273         int ret = 0;
 274         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 275
 276         if (adev->powerplay.ip_funcs->wait_for_idle)
 277                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 278                                         adev->powerplay.pp_handle);
 279         return ret;
 280 }
 281
 282 static int amdgpu_pp_soft_reset(void *handle)
 283 {
 284         int ret = 0;
 285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 286
 287         if (adev->powerplay.ip_funcs->soft_reset)
 288                 ret = adev->powerplay.ip_funcs->soft_reset(
 289                                         adev->powerplay.pp_handle);
 290         return ret;
 291 }
 292
 293 static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 294         .name = "amdgpu_powerplay",
 295         .early_init = amdgpu_pp_early_init,
 296         .late_init = amdgpu_pp_late_init,
 297         .sw_init = amdgpu_pp_sw_init,
 298         .sw_fini = amdgpu_pp_sw_fini,
 299         .hw_init = amdgpu_pp_hw_init,
 300         .hw_fini = amdgpu_pp_hw_fini,
 301         .late_fini = amdgpu_pp_late_fini,
 302         .suspend = amdgpu_pp_suspend,
 303         .resume = amdgpu_pp_resume,
 304         .is_idle = amdgpu_pp_is_idle,
 305         .wait_for_idle = amdgpu_pp_wait_for_idle,
 306         .soft_reset = amdgpu_pp_soft_reset,
 307         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 308         .set_powergating_state = amdgpu_pp_set_powergating_state,
 309 };
 310
 311 const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
 312 {
 313         .type = AMD_IP_BLOCK_TYPE_SMC,
 314         .major = 1,
 315         .minor = 0,
 316         .rev = 0,
 317         .funcs = &amdgpu_pp_ip_funcs,
 318 };