drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "dm_services_types.h"
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "amdgpu_dm_wb.h"
  32 #include "amdgpu_display.h"
  33 #include "dc.h"
  34
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_atomic_state_helper.h>
  37 #include <drm/drm_modeset_helper_vtables.h>
  38
  39 static const u32 amdgpu_dm_wb_formats[] = {
  40         DRM_FORMAT_XRGB2101010,
  41 };
  42
  43 static int amdgpu_dm_wb_encoder_atomic_check(struct drm_encoder *encoder,
  44                                         struct drm_crtc_state *crtc_state,
  45                                         struct drm_connector_state *conn_state)
  46 {
  47         struct drm_framebuffer *fb;
  48         const struct drm_display_mode *mode = &crtc_state->mode;
  49         bool found = false;
  50         uint8_t i;
  51
  52         if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
  53                 return 0;
  54
  55         fb = conn_state->writeback_job->fb;
  56         if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) {
  57                 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
  58                               fb->width, fb->height);
  59                 return -EINVAL;
  60         }
  61
  62         for (i = 0; i < sizeof(amdgpu_dm_wb_formats) / sizeof(u32); i++) {
  63                 if (fb->format->format == amdgpu_dm_wb_formats[i])
  64                         found = true;
  65         }
  66
  67         if (!found) {
  68                 DRM_DEBUG_KMS("Invalid pixel format %p4cc\n",
  69                               &fb->format->format);
  70                 return -EINVAL;
  71         }
  72
  73         return 0;
  74 }
  75
  76
  77 static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector)
  78 {
  79         /* Maximum resolution supported by DWB */
  80         return drm_add_modes_noedid(connector, 3840, 2160);
  81 }
  82
  83 static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector,
  84                                struct drm_writeback_job *job)
  85 {
  86         struct amdgpu_framebuffer *afb;
  87         struct drm_gem_object *obj;
  88         struct amdgpu_device *adev;
  89         struct amdgpu_bo *rbo;
  90         uint32_t domain;
  91         int r;
  92
  93         if (!job->fb) {
  94                 DRM_DEBUG_KMS("No FB bound\n");
  95                 return 0;
  96         }
  97
  98         afb = to_amdgpu_framebuffer(job->fb);
  99         obj = job->fb->obj[0];
 100         rbo = gem_to_amdgpu_bo(obj);
 101         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
 102
 103         r = amdgpu_bo_reserve(rbo, true);
 104         if (r) {
 105                 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
 106                 return r;
 107         }
 108
 109         r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
 110         if (r) {
 111                 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r);
 112                 goto error_unlock;
 113         }
 114
 115         domain = amdgpu_display_supported_domains(adev, rbo->flags);
 116
 117         r = amdgpu_bo_pin(rbo, domain);
 118         if (unlikely(r != 0)) {
 119                 if (r != -ERESTARTSYS)
 120                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
 121                 goto error_unlock;
 122         }
 123
 124         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
 125         if (unlikely(r != 0)) {
 126                 DRM_ERROR("%p bind failed\n", rbo);
 127                 goto error_unpin;
 128         }
 129
 130         amdgpu_bo_unreserve(rbo);
 131
 132         afb->address = amdgpu_bo_gpu_offset(rbo);
 133
 134         amdgpu_bo_ref(rbo);
 135
 136         return 0;
 137
 138 error_unpin:
 139         amdgpu_bo_unpin(rbo);
 140
 141 error_unlock:
 142         amdgpu_bo_unreserve(rbo);
 143         return r;
 144 }
 145
 146 static void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector,
 147                                 struct drm_writeback_job *job)
 148 {
 149         struct amdgpu_bo *rbo;
 150         int r;
 151
 152         if (!job->fb)
 153                 return;
 154
 155         rbo = gem_to_amdgpu_bo(job->fb->obj[0]);
 156         r = amdgpu_bo_reserve(rbo, false);
 157         if (unlikely(r)) {
 158                 DRM_ERROR("failed to reserve rbo before unpin\n");
 159                 return;
 160         }
 161
 162         amdgpu_bo_unpin(rbo);
 163         amdgpu_bo_unreserve(rbo);
 164         amdgpu_bo_unref(&rbo);
 165 }
 166
 167 static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = {
 168         .atomic_check = amdgpu_dm_wb_encoder_atomic_check,
 169 };
 170
 171 static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = {
 172         .fill_modes = drm_helper_probe_single_connector_modes,
 173         .destroy = drm_connector_cleanup,
 174         .reset = amdgpu_dm_connector_funcs_reset,
 175         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 176         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 177 };
 178
 179 static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = {
 180         .get_modes = amdgpu_dm_wb_connector_get_modes,
 181         .prepare_writeback_job = amdgpu_dm_wb_prepare_job,
 182         .cleanup_writeback_job = amdgpu_dm_wb_cleanup_job,
 183 };
 184
 185 int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm,
 186                                 struct amdgpu_dm_wb_connector *wbcon,
 187                                 uint32_t link_index)
 188 {
 189         struct dc *dc = dm->dc;
 190         struct dc_link *link = dc_get_link_at_index(dc, link_index);
 191         int res = 0;
 192
 193         wbcon->link = link;
 194
 195         drm_connector_helper_add(&wbcon->base.base, &amdgpu_dm_wb_conn_helper_funcs);
 196
 197         res = drm_writeback_connector_init(&dm->adev->ddev, &wbcon->base,
 198                                             &amdgpu_dm_wb_connector_funcs,
 199                                             &amdgpu_dm_wb_encoder_helper_funcs,
 200                                             amdgpu_dm_wb_formats,
 201                                             ARRAY_SIZE(amdgpu_dm_wb_formats),
 202                                             amdgpu_dm_get_encoder_crtc_mask(dm->adev));
 203
 204         if (res)
 205                 return res;
 206         /*
 207          * Some of the properties below require access to state, like bpc.
 208          * Allocate some default initial connector state with our reset helper.
 209          */
 210         if (wbcon->base.base.funcs->reset)
 211                 wbcon->base.base.funcs->reset(&wbcon->base.base);
 212
 213         return 0;
 214 }