drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_11_0_0_offset.h"
  30 #include "gc/gc_11_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v11_structs.h"
  33 #include "mes_v11_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
  41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
  42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin");
  43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
  44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
  45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin");
  46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
  47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
  48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin");
  49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
  50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");
  51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");
  52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");
  53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");
  54
  55
  56 static int mes_v11_0_hw_fini(void *handle);
  57 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
  58 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
  59
  60 #define MES_EOP_SIZE   2048
  61 #define GFX_MES_DRAM_SIZE       0x80000
  62
  63 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
  64 {
  65         struct amdgpu_device *adev = ring->adev;
  66
  67         if (ring->use_doorbell) {
  68                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  69                              ring->wptr);
  70                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  71         } else {
  72                 BUG();
  73         }
  74 }
  75
  76 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
  77 {
  78         return *ring->rptr_cpu_addr;
  79 }
  80
  81 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
  82 {
  83         u64 wptr;
  84
  85         if (ring->use_doorbell)
  86                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  87         else
  88                 BUG();
  89         return wptr;
  90 }
  91
  92 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
  93         .type = AMDGPU_RING_TYPE_MES,
  94         .align_mask = 1,
  95         .nop = 0,
  96         .support_64bit_ptrs = true,
  97         .get_rptr = mes_v11_0_ring_get_rptr,
  98         .get_wptr = mes_v11_0_ring_get_wptr,
  99         .set_wptr = mes_v11_0_ring_set_wptr,
 100         .insert_nop = amdgpu_ring_insert_nop,
 101 };
 102
 103 static const char *mes_v11_0_opcodes[] = {
 104         "SET_HW_RSRC",
 105         "SET_SCHEDULING_CONFIG",
 106         "ADD_QUEUE",
 107         "REMOVE_QUEUE",
 108         "PERFORM_YIELD",
 109         "SET_GANG_PRIORITY_LEVEL",
 110         "SUSPEND",
 111         "RESUME",
 112         "RESET",
 113         "SET_LOG_BUFFER",
 114         "CHANGE_GANG_PRORITY",
 115         "QUERY_SCHEDULER_STATUS",
 116         "PROGRAM_GDS",
 117         "SET_DEBUG_VMID",
 118         "MISC",
 119         "UPDATE_ROOT_PAGE_TABLE",
 120         "AMD_LOG",
 121 };
 122
 123 static const char *mes_v11_0_misc_opcodes[] = {
 124         "WRITE_REG",
 125         "INV_GART",
 126         "QUERY_STATUS",
 127         "READ_REG",
 128         "WAIT_REG_MEM",
 129         "SET_SHADER_DEBUGGER",
 130 };
 131
 132 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt)
 133 {
 134         const char *op_str = NULL;
 135
 136         if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes))
 137                 op_str = mes_v11_0_opcodes[x_pkt->header.opcode];
 138
 139         return op_str;
 140 }
 141
 142 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
 143 {
 144         const char *op_str = NULL;
 145
 146         if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
 147             (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes)))
 148                 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode];
 149
 150         return op_str;
 151 }
 152
 153 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
 154                                                     void *pkt, int size,
 155                                                     int api_status_off)
 156 {
 157         int ndw = size / 4;
 158         signed long r;
 159         union MESAPI__MISC *x_pkt = pkt;
 160         struct MES_API_STATUS *api_status;
 161         struct amdgpu_device *adev = mes->adev;
 162         struct amdgpu_ring *ring = &mes->ring;
 163         unsigned long flags;
 164         signed long timeout = 3000000; /* 3000 ms */
 165         const char *op_str, *misc_op_str;
 166         u32 fence_offset;
 167         u64 fence_gpu_addr;
 168         u64 *fence_ptr;
 169         int ret;
 170
 171         if (x_pkt->header.opcode >= MES_SCH_API_MAX)
 172                 return -EINVAL;
 173
 174         if (amdgpu_emu_mode) {
 175                 timeout *= 100;
 176         } else if (amdgpu_sriov_vf(adev)) {
 177                 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
 178                 timeout = 15 * 600 * 1000;
 179         }
 180         BUG_ON(size % 4 != 0);
 181
 182         ret = amdgpu_device_wb_get(adev, &fence_offset);
 183         if (ret)
 184                 return ret;
 185         fence_gpu_addr =
 186                 adev->wb.gpu_addr + (fence_offset * 4);
 187         fence_ptr = (u64 *)&adev->wb.wb[fence_offset];
 188         *fence_ptr = 0;
 189
 190         spin_lock_irqsave(&mes->ring_lock, flags);
 191         if (amdgpu_ring_alloc(ring, ndw)) {
 192                 spin_unlock_irqrestore(&mes->ring_lock, flags);
 193                 amdgpu_device_wb_free(adev, fence_offset);
 194                 return -ENOMEM;
 195         }
 196
 197         api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
 198         api_status->api_completion_fence_addr = fence_gpu_addr;
 199         api_status->api_completion_fence_value = 1;
 200
 201         amdgpu_ring_write_multiple(ring, pkt, ndw);
 202         amdgpu_ring_commit(ring);
 203         spin_unlock_irqrestore(&mes->ring_lock, flags);
 204
 205         op_str = mes_v11_0_get_op_string(x_pkt);
 206         misc_op_str = mes_v11_0_get_misc_op_string(x_pkt);
 207
 208         if (misc_op_str)
 209                 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, misc_op_str);
 210         else if (op_str)
 211                 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str);
 212         else
 213                 dev_dbg(adev->dev, "MES msg=%d was emitted\n", x_pkt->header.opcode);
 214
 215         r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout);
 216         amdgpu_device_wb_free(adev, fence_offset);
 217         if (r < 1) {
 218
 219                 if (misc_op_str)
 220                         dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n",
 221                                 op_str, misc_op_str);
 222                 else if (op_str)
 223                         dev_err(adev->dev, "MES failed to respond to msg=%s\n",
 224                                 op_str);
 225                 else
 226                         dev_err(adev->dev, "MES failed to respond to msg=%d\n",
 227                                 x_pkt->header.opcode);
 228
 229                 while (halt_if_hws_hang)
 230                         schedule();
 231
 232                 return -ETIMEDOUT;
 233         }
 234
 235         return 0;
 236 }
 237
 238 static int convert_to_mes_queue_type(int queue_type)
 239 {
 240         if (queue_type == AMDGPU_RING_TYPE_GFX)
 241                 return MES_QUEUE_TYPE_GFX;
 242         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 243                 return MES_QUEUE_TYPE_COMPUTE;
 244         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 245                 return MES_QUEUE_TYPE_SDMA;
 246         else
 247                 BUG();
 248         return -1;
 249 }
 250
 251 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 252                                   struct mes_add_queue_input *input)
 253 {
 254         struct amdgpu_device *adev = mes->adev;
 255         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 256         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
 257         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 258
 259         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 260
 261         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 262         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 263         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 264
 265         mes_add_queue_pkt.process_id = input->process_id;
 266         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 267         mes_add_queue_pkt.process_va_start = input->process_va_start;
 268         mes_add_queue_pkt.process_va_end = input->process_va_end;
 269         mes_add_queue_pkt.process_quantum = input->process_quantum;
 270         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 271         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 272         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 273         mes_add_queue_pkt.inprocess_gang_priority =
 274                 input->inprocess_gang_priority;
 275         mes_add_queue_pkt.gang_global_priority_level =
 276                 input->gang_global_priority_level;
 277         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 278         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 279
 280         if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
 281                         AMDGPU_MES_API_VERSION_SHIFT) >= 2)
 282                 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
 283         else
 284                 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 285
 286         mes_add_queue_pkt.queue_type =
 287                 convert_to_mes_queue_type(input->queue_type);
 288         mes_add_queue_pkt.paging = input->paging;
 289         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 290         mes_add_queue_pkt.gws_base = input->gws_base;
 291         mes_add_queue_pkt.gws_size = input->gws_size;
 292         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 293         mes_add_queue_pkt.tma_addr = input->tma_addr;
 294         mes_add_queue_pkt.trap_en = input->trap_en;
 295         mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
 296         mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 297
 298         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 299         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 300         mes_add_queue_pkt.gds_size = input->queue_size;
 301
 302         mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled;
 303
 304         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 305                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 306                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 307 }
 308
 309 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
 310                                      struct mes_remove_queue_input *input)
 311 {
 312         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 313
 314         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 315
 316         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 317         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 318         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 319
 320         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 321         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 322
 323         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 324                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 325                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 326 }
 327
 328 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 329                         struct mes_unmap_legacy_queue_input *input)
 330 {
 331         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 332
 333         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 334
 335         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 336         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 337         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 338
 339         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 340         mes_remove_queue_pkt.gang_context_addr = 0;
 341
 342         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 343         mes_remove_queue_pkt.queue_id = input->queue_id;
 344
 345         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 346                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 347                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 348                 mes_remove_queue_pkt.tf_data =
 349                         lower_32_bits(input->trail_fence_data);
 350         } else {
 351                 mes_remove_queue_pkt.unmap_legacy_queue = 1;
 352                 mes_remove_queue_pkt.queue_type =
 353                         convert_to_mes_queue_type(input->queue_type);
 354         }
 355
 356         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 357                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 358                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 359 }
 360
 361 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
 362                                   struct mes_suspend_gang_input *input)
 363 {
 364         return 0;
 365 }
 366
 367 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
 368                                  struct mes_resume_gang_input *input)
 369 {
 370         return 0;
 371 }
 372
 373 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
 374 {
 375         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 376
 377         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 378
 379         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 380         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 381         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 382
 383         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 384                         &mes_status_pkt, sizeof(mes_status_pkt),
 385                         offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
 386 }
 387
 388 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
 389                              struct mes_misc_op_input *input)
 390 {
 391         union MESAPI__MISC misc_pkt;
 392
 393         memset(&misc_pkt, 0, sizeof(misc_pkt));
 394
 395         misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
 396         misc_pkt.header.opcode = MES_SCH_API_MISC;
 397         misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 398
 399         switch (input->op) {
 400         case MES_MISC_OP_READ_REG:
 401                 misc_pkt.opcode = MESAPI_MISC__READ_REG;
 402                 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
 403                 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
 404                 break;
 405         case MES_MISC_OP_WRITE_REG:
 406                 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
 407                 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
 408                 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
 409                 break;
 410         case MES_MISC_OP_WRM_REG_WAIT:
 411                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 412                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
 413                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 414                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 415                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 416                 misc_pkt.wait_reg_mem.reg_offset2 = 0;
 417                 break;
 418         case MES_MISC_OP_WRM_REG_WR_WAIT:
 419                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 420                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
 421                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 422                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 423                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 424                 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
 425                 break;
 426         case MES_MISC_OP_SET_SHADER_DEBUGGER:
 427                 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
 428                 misc_pkt.set_shader_debugger.process_context_addr =
 429                                 input->set_shader_debugger.process_context_addr;
 430                 misc_pkt.set_shader_debugger.flags.u32all =
 431                                 input->set_shader_debugger.flags.u32all;
 432                 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
 433                                 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
 434                 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
 435                                 input->set_shader_debugger.tcp_watch_cntl,
 436                                 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
 437                 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
 438                 break;
 439         default:
 440                 DRM_ERROR("unsupported misc op (%d) \n", input->op);
 441                 return -EINVAL;
 442         }
 443
 444         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 445                         &misc_pkt, sizeof(misc_pkt),
 446                         offsetof(union MESAPI__MISC, api_status));
 447 }
 448
 449 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 450 {
 451         int i;
 452         struct amdgpu_device *adev = mes->adev;
 453         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 454
 455         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 456
 457         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 458         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 459         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 460
 461         mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 462         mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 463         mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 464         mes_set_hw_res_pkt.paging_vmid = 0;
 465         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
 466         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 467                 mes->query_status_fence_gpu_addr;
 468
 469         for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 470                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
 471                         mes->compute_hqd_mask[i];
 472
 473         for (i = 0; i < MAX_GFX_PIPES; i++)
 474                 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
 475
 476         for (i = 0; i < MAX_SDMA_PIPES; i++)
 477                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
 478
 479         for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 480                 mes_set_hw_res_pkt.aggregated_doorbells[i] =
 481                         mes->aggregated_doorbells[i];
 482
 483         for (i = 0; i < 5; i++) {
 484                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 485                 mes_set_hw_res_pkt.mmhub_base[i] =
 486                                 adev->reg_offset[MMHUB_HWIP][0][i];
 487                 mes_set_hw_res_pkt.osssys_base[i] =
 488                 adev->reg_offset[OSSSYS_HWIP][0][i];
 489         }
 490
 491         mes_set_hw_res_pkt.disable_reset = 1;
 492         mes_set_hw_res_pkt.disable_mes_log = 1;
 493         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 494         mes_set_hw_res_pkt.enable_reg_active_poll = 1;
 495         mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
 496         mes_set_hw_res_pkt.oversubscription_timer = 50;
 497         if (amdgpu_mes_log_enable) {
 498                 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
 499                 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
 500                                         mes->event_log_gpu_addr;
 501         }
 502
 503         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 504                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 505                         offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
 506 }
 507
 508 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
 509 {
 510         int size = 128 * PAGE_SIZE;
 511         int ret = 0;
 512         struct amdgpu_device *adev = mes->adev;
 513         union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
 514         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 515
 516         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 517         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
 518         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 519         mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
 520
 521         ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
 522                                 AMDGPU_GEM_DOMAIN_VRAM,
 523                                 &mes->resource_1,
 524                                 &mes->resource_1_gpu_addr,
 525                                 &mes->resource_1_addr);
 526         if (ret) {
 527                 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
 528                 return ret;
 529         }
 530
 531         mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr;
 532         mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size;
 533         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 534                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 535                         offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
 536 }
 537
 538 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
 539         .add_hw_queue = mes_v11_0_add_hw_queue,
 540         .remove_hw_queue = mes_v11_0_remove_hw_queue,
 541         .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
 542         .suspend_gang = mes_v11_0_suspend_gang,
 543         .resume_gang = mes_v11_0_resume_gang,
 544         .misc_op = mes_v11_0_misc_op,
 545 };
 546
 547 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 548                                            enum admgpu_mes_pipe pipe)
 549 {
 550         int r;
 551         const struct mes_firmware_header_v1_0 *mes_hdr;
 552         const __le32 *fw_data;
 553         unsigned fw_size;
 554
 555         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 556                 adev->mes.fw[pipe]->data;
 557
 558         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 559                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 560         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 561
 562         r = amdgpu_bo_create_reserved(adev, fw_size,
 563                                       PAGE_SIZE,
 564                                       AMDGPU_GEM_DOMAIN_VRAM |
 565                                       AMDGPU_GEM_DOMAIN_GTT,
 566                                       &adev->mes.ucode_fw_obj[pipe],
 567                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 568                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 569         if (r) {
 570                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 571                 return r;
 572         }
 573
 574         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 575
 576         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 577         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 578
 579         return 0;
 580 }
 581
 582 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 583                                                 enum admgpu_mes_pipe pipe)
 584 {
 585         int r;
 586         const struct mes_firmware_header_v1_0 *mes_hdr;
 587         const __le32 *fw_data;
 588         unsigned fw_size;
 589
 590         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 591                 adev->mes.fw[pipe]->data;
 592
 593         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 594                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 595         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 596
 597         if (fw_size > GFX_MES_DRAM_SIZE) {
 598                 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n",
 599                         pipe, fw_size, GFX_MES_DRAM_SIZE);
 600                 return -EINVAL;
 601         }
 602
 603         r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE,
 604                                       64 * 1024,
 605                                       AMDGPU_GEM_DOMAIN_VRAM |
 606                                       AMDGPU_GEM_DOMAIN_GTT,
 607                                       &adev->mes.data_fw_obj[pipe],
 608                                       &adev->mes.data_fw_gpu_addr[pipe],
 609                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 610         if (r) {
 611                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 612                 return r;
 613         }
 614
 615         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 616
 617         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 618         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 619
 620         return 0;
 621 }
 622
 623 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
 624                                          enum admgpu_mes_pipe pipe)
 625 {
 626         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 627                               &adev->mes.data_fw_gpu_addr[pipe],
 628                               (void **)&adev->mes.data_fw_ptr[pipe]);
 629
 630         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 631                               &adev->mes.ucode_fw_gpu_addr[pipe],
 632                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 633 }
 634
 635 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 636 {
 637         uint64_t ucode_addr;
 638         uint32_t pipe, data = 0;
 639
 640         if (enable) {
 641                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 642                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 643                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 644                              MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
 645                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 646
 647                 mutex_lock(&adev->srbm_mutex);
 648                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 649                         if (!adev->enable_mes_kiq &&
 650                             pipe == AMDGPU_MES_KIQ_PIPE)
 651                                 continue;
 652
 653                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 654
 655                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 656                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 657                                      lower_32_bits(ucode_addr));
 658                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 659                                      upper_32_bits(ucode_addr));
 660                 }
 661                 soc21_grbm_select(adev, 0, 0, 0, 0);
 662                 mutex_unlock(&adev->srbm_mutex);
 663
 664                 /* unhalt MES and activate pipe0 */
 665                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 666                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 667                                      adev->enable_mes_kiq ? 1 : 0);
 668                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 669
 670                 if (amdgpu_emu_mode)
 671                         msleep(100);
 672                 else
 673                         udelay(50);
 674         } else {
 675                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 676                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 677                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 678                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 679                                      MES_INVALIDATE_ICACHE, 1);
 680                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 681                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 682                                      adev->enable_mes_kiq ? 1 : 0);
 683                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 684                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 685         }
 686 }
 687
 688 /* This function is for backdoor MES firmware */
 689 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
 690                                     enum admgpu_mes_pipe pipe, bool prime_icache)
 691 {
 692         int r;
 693         uint32_t data;
 694         uint64_t ucode_addr;
 695
 696         mes_v11_0_enable(adev, false);
 697
 698         if (!adev->mes.fw[pipe])
 699                 return -EINVAL;
 700
 701         r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
 702         if (r)
 703                 return r;
 704
 705         r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
 706         if (r) {
 707                 mes_v11_0_free_ucode_buffers(adev, pipe);
 708                 return r;
 709         }
 710
 711         mutex_lock(&adev->srbm_mutex);
 712         /* me=3, pipe=0, queue=0 */
 713         soc21_grbm_select(adev, 3, pipe, 0, 0);
 714
 715         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 716
 717         /* set ucode start address */
 718         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 719         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 720                      lower_32_bits(ucode_addr));
 721         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 722                      upper_32_bits(ucode_addr));
 723
 724         /* set ucode fimrware address */
 725         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 726                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 727         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 728                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 729
 730         /* set ucode instruction cache boundary to 2M-1 */
 731         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 732
 733         /* set ucode data firmware address */
 734         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 735                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 736         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 737                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 738
 739         /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */
 740         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
 741
 742         if (prime_icache) {
 743                 /* invalidate ICACHE */
 744                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 745                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 746                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 747                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 748
 749                 /* prime the ICACHE. */
 750                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 751                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 752                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 753         }
 754
 755         soc21_grbm_select(adev, 0, 0, 0, 0);
 756         mutex_unlock(&adev->srbm_mutex);
 757
 758         return 0;
 759 }
 760
 761 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
 762                                       enum admgpu_mes_pipe pipe)
 763 {
 764         int r;
 765         u32 *eop;
 766
 767         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 768                               AMDGPU_GEM_DOMAIN_GTT,
 769                               &adev->mes.eop_gpu_obj[pipe],
 770                               &adev->mes.eop_gpu_addr[pipe],
 771                               (void **)&eop);
 772         if (r) {
 773                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 774                 return r;
 775         }
 776
 777         memset(eop, 0,
 778                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 779
 780         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 781         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 782
 783         return 0;
 784 }
 785
 786 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
 787 {
 788         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 789         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 790         uint32_t tmp;
 791
 792         memset(mqd, 0, sizeof(*mqd));
 793
 794         mqd->header = 0xC0310800;
 795         mqd->compute_pipelinestat_enable = 0x00000001;
 796         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 797         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 798         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 799         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 800         mqd->compute_misc_reserved = 0x00000007;
 801
 802         eop_base_addr = ring->eop_gpu_addr >> 8;
 803
 804         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 805         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 806         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 807                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 808
 809         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 810         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 811         mqd->cp_hqd_eop_control = tmp;
 812
 813         /* disable the queue if it's active */
 814         ring->wptr = 0;
 815         mqd->cp_hqd_pq_rptr = 0;
 816         mqd->cp_hqd_pq_wptr_lo = 0;
 817         mqd->cp_hqd_pq_wptr_hi = 0;
 818
 819         /* set the pointer to the MQD */
 820         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 821         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 822
 823         /* set MQD vmid to 0 */
 824         tmp = regCP_MQD_CONTROL_DEFAULT;
 825         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 826         mqd->cp_mqd_control = tmp;
 827
 828         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 829         hqd_gpu_addr = ring->gpu_addr >> 8;
 830         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 831         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 832
 833         /* set the wb address whether it's enabled or not */
 834         wb_gpu_addr = ring->rptr_gpu_addr;
 835         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 836         mqd->cp_hqd_pq_rptr_report_addr_hi =
 837                 upper_32_bits(wb_gpu_addr) & 0xffff;
 838
 839         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 840         wb_gpu_addr = ring->wptr_gpu_addr;
 841         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 842         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 843
 844         /* set up the HQD, this is similar to CP_RB0_CNTL */
 845         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 846         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 847                             (order_base_2(ring->ring_size / 4) - 1));
 848         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 849                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 850         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 851         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 852         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 853         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 854         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 855         mqd->cp_hqd_pq_control = tmp;
 856
 857         /* enable doorbell */
 858         tmp = 0;
 859         if (ring->use_doorbell) {
 860                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 861                                     DOORBELL_OFFSET, ring->doorbell_index);
 862                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 863                                     DOORBELL_EN, 1);
 864                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 865                                     DOORBELL_SOURCE, 0);
 866                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 867                                     DOORBELL_HIT, 0);
 868         } else
 869                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 870                                     DOORBELL_EN, 0);
 871         mqd->cp_hqd_pq_doorbell_control = tmp;
 872
 873         mqd->cp_hqd_vmid = 0;
 874         /* activate the queue */
 875         mqd->cp_hqd_active = 1;
 876
 877         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
 878         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
 879                             PRELOAD_SIZE, 0x55);
 880         mqd->cp_hqd_persistent_state = tmp;
 881
 882         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
 883         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
 884         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
 885
 886         amdgpu_device_flush_hdp(ring->adev, NULL);
 887         return 0;
 888 }
 889
 890 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
 891 {
 892         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 893         struct amdgpu_device *adev = ring->adev;
 894         uint32_t data = 0;
 895
 896         mutex_lock(&adev->srbm_mutex);
 897         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 898
 899         /* set CP_HQD_VMID.VMID = 0. */
 900         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
 901         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
 902         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
 903
 904         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
 905         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
 906         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
 907                              DOORBELL_EN, 0);
 908         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
 909
 910         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
 911         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
 912         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
 913
 914         /* set CP_MQD_CONTROL.VMID=0 */
 915         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
 916         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
 917         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
 918
 919         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
 920         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
 921         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
 922
 923         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
 924         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
 925                      mqd->cp_hqd_pq_rptr_report_addr_lo);
 926         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 927                      mqd->cp_hqd_pq_rptr_report_addr_hi);
 928
 929         /* set CP_HQD_PQ_CONTROL */
 930         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
 931
 932         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
 933         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
 934                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
 935         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 936                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
 937
 938         /* set CP_HQD_PQ_DOORBELL_CONTROL */
 939         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
 940                      mqd->cp_hqd_pq_doorbell_control);
 941
 942         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
 943         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
 944
 945         /* set CP_HQD_ACTIVE.ACTIVE=1 */
 946         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
 947
 948         soc21_grbm_select(adev, 0, 0, 0, 0);
 949         mutex_unlock(&adev->srbm_mutex);
 950 }
 951
 952 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
 953 {
 954         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 955         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
 956         int r;
 957
 958         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 959                 return -EINVAL;
 960
 961         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
 962         if (r) {
 963                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 964                 return r;
 965         }
 966
 967         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
 968
 969         return amdgpu_ring_test_helper(kiq_ring);
 970 }
 971
 972 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
 973                                 enum admgpu_mes_pipe pipe)
 974 {
 975         struct amdgpu_ring *ring;
 976         int r;
 977
 978         if (pipe == AMDGPU_MES_KIQ_PIPE)
 979                 ring = &adev->gfx.kiq[0].ring;
 980         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 981                 ring = &adev->mes.ring;
 982         else
 983                 BUG();
 984
 985         if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
 986             (amdgpu_in_reset(adev) || adev->in_suspend)) {
 987                 *(ring->wptr_cpu_addr) = 0;
 988                 *(ring->rptr_cpu_addr) = 0;
 989                 amdgpu_ring_clear_ring(ring);
 990         }
 991
 992         r = mes_v11_0_mqd_init(ring);
 993         if (r)
 994                 return r;
 995
 996         if (pipe == AMDGPU_MES_SCHED_PIPE) {
 997                 r = mes_v11_0_kiq_enable_queue(adev);
 998                 if (r)
 999                         return r;
1000         } else {
1001                 mes_v11_0_queue_init_register(ring);
1002         }
1003
1004         /* get MES scheduler/KIQ versions */
1005         mutex_lock(&adev->srbm_mutex);
1006         soc21_grbm_select(adev, 3, pipe, 0, 0);
1007
1008         if (pipe == AMDGPU_MES_SCHED_PIPE)
1009                 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1010         else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1011                 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1012
1013         soc21_grbm_select(adev, 0, 0, 0, 0);
1014         mutex_unlock(&adev->srbm_mutex);
1015
1016         return 0;
1017 }
1018
1019 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
1020 {
1021         struct amdgpu_ring *ring;
1022
1023         ring = &adev->mes.ring;
1024
1025         ring->funcs = &mes_v11_0_ring_funcs;
1026
1027         ring->me = 3;
1028         ring->pipe = 0;
1029         ring->queue = 0;
1030
1031         ring->ring_obj = NULL;
1032         ring->use_doorbell = true;
1033         ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1034         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
1035         ring->no_scheduler = true;
1036         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1037
1038         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1039                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1040 }
1041
1042 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
1043 {
1044         struct amdgpu_ring *ring;
1045
1046         spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1047
1048         ring = &adev->gfx.kiq[0].ring;
1049
1050         ring->me = 3;
1051         ring->pipe = 1;
1052         ring->queue = 0;
1053
1054         ring->adev = NULL;
1055         ring->ring_obj = NULL;
1056         ring->use_doorbell = true;
1057         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1058         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1059         ring->no_scheduler = true;
1060         sprintf(ring->name, "mes_kiq_%d.%d.%d",
1061                 ring->me, ring->pipe, ring->queue);
1062
1063         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1064                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1065 }
1066
1067 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
1068                                  enum admgpu_mes_pipe pipe)
1069 {
1070         int r, mqd_size = sizeof(struct v11_compute_mqd);
1071         struct amdgpu_ring *ring;
1072
1073         if (pipe == AMDGPU_MES_KIQ_PIPE)
1074                 ring = &adev->gfx.kiq[0].ring;
1075         else if (pipe == AMDGPU_MES_SCHED_PIPE)
1076                 ring = &adev->mes.ring;
1077         else
1078                 BUG();
1079
1080         if (ring->mqd_obj)
1081                 return 0;
1082
1083         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1084                                     AMDGPU_GEM_DOMAIN_VRAM |
1085                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1086                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
1087         if (r) {
1088                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1089                 return r;
1090         }
1091
1092         memset(ring->mqd_ptr, 0, mqd_size);
1093
1094         /* prepare MQD backup */
1095         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1096         if (!adev->mes.mqd_backup[pipe]) {
1097                 dev_warn(adev->dev,
1098                          "no memory to create MQD backup for ring %s\n",
1099                          ring->name);
1100                 return -ENOMEM;
1101         }
1102
1103         return 0;
1104 }
1105
1106 static int mes_v11_0_sw_init(void *handle)
1107 {
1108         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1109         int pipe, r;
1110
1111         adev->mes.funcs = &mes_v11_0_funcs;
1112         adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1113         adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1114
1115         r = amdgpu_mes_init(adev);
1116         if (r)
1117                 return r;
1118
1119         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1120                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1121                         continue;
1122
1123                 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1124                 if (r)
1125                         return r;
1126
1127                 r = mes_v11_0_mqd_sw_init(adev, pipe);
1128                 if (r)
1129                         return r;
1130         }
1131
1132         if (adev->enable_mes_kiq) {
1133                 r = mes_v11_0_kiq_ring_init(adev);
1134                 if (r)
1135                         return r;
1136         }
1137
1138         r = mes_v11_0_ring_init(adev);
1139         if (r)
1140                 return r;
1141
1142         return 0;
1143 }
1144
1145 static int mes_v11_0_sw_fini(void *handle)
1146 {
1147         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1148         int pipe;
1149
1150         amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1151         amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1152
1153         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1154                 kfree(adev->mes.mqd_backup[pipe]);
1155
1156                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1157                                       &adev->mes.eop_gpu_addr[pipe],
1158                                       NULL);
1159                 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1160         }
1161
1162         amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1163                               &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1164                               &adev->gfx.kiq[0].ring.mqd_ptr);
1165
1166         amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1167                               &adev->mes.ring.mqd_gpu_addr,
1168                               &adev->mes.ring.mqd_ptr);
1169
1170         amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1171         amdgpu_ring_fini(&adev->mes.ring);
1172
1173         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1174                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1175                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1176         }
1177
1178         amdgpu_mes_fini(adev);
1179         return 0;
1180 }
1181
1182 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring)
1183 {
1184         uint32_t data;
1185         int i;
1186         struct amdgpu_device *adev = ring->adev;
1187
1188         mutex_lock(&adev->srbm_mutex);
1189         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1190
1191         /* disable the queue if it's active */
1192         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1193                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1194                 for (i = 0; i < adev->usec_timeout; i++) {
1195                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1196                                 break;
1197                         udelay(1);
1198                 }
1199         }
1200         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1201         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1202                                 DOORBELL_EN, 0);
1203         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1204                                 DOORBELL_HIT, 1);
1205         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1206
1207         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1208
1209         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1210         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1211         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1212
1213         soc21_grbm_select(adev, 0, 0, 0, 0);
1214         mutex_unlock(&adev->srbm_mutex);
1215 }
1216
1217 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1218 {
1219         uint32_t tmp;
1220         struct amdgpu_device *adev = ring->adev;
1221
1222         /* tell RLC which is KIQ queue */
1223         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1224         tmp &= 0xffffff00;
1225         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1226         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1227         tmp |= 0x80;
1228         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1229 }
1230
1231 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
1232 {
1233         uint32_t tmp;
1234
1235         /* tell RLC which is KIQ dequeue */
1236         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1237         tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
1238         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1239 }
1240
1241 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1242 {
1243         int r = 0;
1244
1245         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1246
1247                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1248                 if (r) {
1249                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1250                         return r;
1251                 }
1252
1253                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1254                 if (r) {
1255                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1256                         return r;
1257                 }
1258
1259         }
1260
1261         mes_v11_0_enable(adev, true);
1262
1263         mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
1264
1265         r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1266         if (r)
1267                 goto failure;
1268
1269         return r;
1270
1271 failure:
1272         mes_v11_0_hw_fini(adev);
1273         return r;
1274 }
1275
1276 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1277 {
1278         if (adev->mes.ring.sched.ready) {
1279                 mes_v11_0_kiq_dequeue(&adev->mes.ring);
1280                 adev->mes.ring.sched.ready = false;
1281         }
1282
1283         if (amdgpu_sriov_vf(adev)) {
1284                 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring);
1285                 mes_v11_0_kiq_clear(adev);
1286         }
1287
1288         mes_v11_0_enable(adev, false);
1289
1290         return 0;
1291 }
1292
1293 static int mes_v11_0_hw_init(void *handle)
1294 {
1295         int r;
1296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297
1298         if (!adev->enable_mes_kiq) {
1299                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1300                         r = mes_v11_0_load_microcode(adev,
1301                                              AMDGPU_MES_SCHED_PIPE, true);
1302                         if (r) {
1303                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1304                                 return r;
1305                         }
1306                 }
1307
1308                 mes_v11_0_enable(adev, true);
1309         }
1310
1311         r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1312         if (r)
1313                 goto failure;
1314
1315         r = mes_v11_0_set_hw_resources(&adev->mes);
1316         if (r)
1317                 goto failure;
1318
1319         if (amdgpu_sriov_is_mes_info_enable(adev)) {
1320                 r = mes_v11_0_set_hw_resources_1(&adev->mes);
1321                 if (r) {
1322                         DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
1323                         goto failure;
1324                 }
1325         }
1326
1327         r = mes_v11_0_query_sched_status(&adev->mes);
1328         if (r) {
1329                 DRM_ERROR("MES is busy\n");
1330                 goto failure;
1331         }
1332
1333         /*
1334          * Disable KIQ ring usage from the driver once MES is enabled.
1335          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1336          * with MES enabled.
1337          */
1338         adev->gfx.kiq[0].ring.sched.ready = false;
1339         adev->mes.ring.sched.ready = true;
1340
1341         return 0;
1342
1343 failure:
1344         mes_v11_0_hw_fini(adev);
1345         return r;
1346 }
1347
1348 static int mes_v11_0_hw_fini(void *handle)
1349 {
1350         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351         if (amdgpu_sriov_is_mes_info_enable(adev)) {
1352                 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
1353                                         &adev->mes.resource_1_addr);
1354         }
1355         return 0;
1356 }
1357
1358 static int mes_v11_0_suspend(void *handle)
1359 {
1360         int r;
1361         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362
1363         r = amdgpu_mes_suspend(adev);
1364         if (r)
1365                 return r;
1366
1367         return mes_v11_0_hw_fini(adev);
1368 }
1369
1370 static int mes_v11_0_resume(void *handle)
1371 {
1372         int r;
1373         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374
1375         r = mes_v11_0_hw_init(adev);
1376         if (r)
1377                 return r;
1378
1379         return amdgpu_mes_resume(adev);
1380 }
1381
1382 static int mes_v11_0_early_init(void *handle)
1383 {
1384         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1385         int pipe, r;
1386
1387         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1388                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1389                         continue;
1390                 r = amdgpu_mes_init_microcode(adev, pipe);
1391                 if (r)
1392                         return r;
1393         }
1394
1395         return 0;
1396 }
1397
1398 static int mes_v11_0_late_init(void *handle)
1399 {
1400         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1401
1402         /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1403         if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
1404             (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3)))
1405                 amdgpu_mes_self_test(adev);
1406
1407         return 0;
1408 }
1409
1410 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1411         .name = "mes_v11_0",
1412         .early_init = mes_v11_0_early_init,
1413         .late_init = mes_v11_0_late_init,
1414         .sw_init = mes_v11_0_sw_init,
1415         .sw_fini = mes_v11_0_sw_fini,
1416         .hw_init = mes_v11_0_hw_init,
1417         .hw_fini = mes_v11_0_hw_fini,
1418         .suspend = mes_v11_0_suspend,
1419         .resume = mes_v11_0_resume,
1420         .dump_ip_state = NULL,
1421         .print_ip_state = NULL,
1422 };
1423
1424 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1425         .type = AMD_IP_BLOCK_TYPE_MES,
1426         .major = 11,
1427         .minor = 0,
1428         .rev = 0,
1429         .funcs = &mes_v11_0_ip_funcs,
1430 };