drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, 2020 Intel Corporation
   4  */
   5 #ifndef __iwl_context_info_file_gen3_h__
   6 #define __iwl_context_info_file_gen3_h__
   7
   8 #include "iwl-context-info.h"
   9
  10 #define CSR_CTXT_INFO_BOOT_CTRL         0x0
  11 #define CSR_CTXT_INFO_ADDR              0x118
  12 #define CSR_IML_DATA_ADDR               0x120
  13 #define CSR_IML_SIZE_ADDR               0x128
  14 #define CSR_IML_RESP_ADDR               0x12c
  15
  16 /* Set bit for enabling automatic function boot */
  17 #define CSR_AUTO_FUNC_BOOT_ENA          BIT(1)
  18 /* Set bit for initiating function boot */
  19 #define CSR_AUTO_FUNC_INIT              BIT(7)
  20
  21 /**
  22  * enum iwl_prph_scratch_mtr_format - tfd size configuration
  23  * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd
  24  * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd
  25  * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd
  26  * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd
  27  */
  28 enum iwl_prph_scratch_mtr_format {
  29         IWL_PRPH_MTR_FORMAT_16B = 0x0,
  30         IWL_PRPH_MTR_FORMAT_32B = 0x40000,
  31         IWL_PRPH_MTR_FORMAT_64B = 0x80000,
  32         IWL_PRPH_MTR_FORMAT_256B = 0xC0000,
  33 };
  34
  35 /**
  36  * enum iwl_prph_scratch_flags - PRPH scratch control flags
  37  * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
  38  * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
  39  *      in hwm config.
  40  * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM
  41  * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for
  42  *      multicomm.
  43  * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW
  44  * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K)
  45  * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for
  46  *      completion descriptor, 1 for responses (legacy)
  47  * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd.
  48  *      There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit,
  49  *      3: 256 bit.
  50  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored
  51  *      by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K
  52  *      appropriately; use the below values for this.
  53  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
  54  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
  55  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
  56  */
  57 enum iwl_prph_scratch_flags {
  58         IWL_PRPH_SCRATCH_EARLY_DEBUG_EN         = BIT(4),
  59         IWL_PRPH_SCRATCH_EDBG_DEST_DRAM         = BIT(8),
  60         IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL     = BIT(9),
  61         IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER   = BIT(10),
  62         IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF      = BIT(11),
  63         IWL_PRPH_SCRATCH_RB_SIZE_4K             = BIT(16),
  64         IWL_PRPH_SCRATCH_MTR_MODE               = BIT(17),
  65         IWL_PRPH_SCRATCH_MTR_FORMAT             = BIT(18) | BIT(19),
  66         IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK       = 0xf << 20,
  67         IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K         = 8 << 20,
  68         IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K        = 9 << 20,
  69         IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K        = 10 << 20,
  70 };
  71
  72 /*
  73  * struct iwl_prph_scratch_version - version structure
  74  * @mac_id: SKU and revision id
  75  * @version: prph scratch information version id
  76  * @size: the size of the context information in DWs
  77  * @reserved: reserved
  78  */
  79 struct iwl_prph_scratch_version {
  80         __le16 mac_id;
  81         __le16 version;
  82         __le16 size;
  83         __le16 reserved;
  84 } __packed; /* PERIPH_SCRATCH_VERSION_S */
  85
  86 /*
  87  * struct iwl_prph_scratch_control - control structure
  88  * @control_flags: context information flags see &enum iwl_prph_scratch_flags
  89  * @reserved: reserved
  90  */
  91 struct iwl_prph_scratch_control {
  92         __le32 control_flags;
  93         __le32 reserved;
  94 } __packed; /* PERIPH_SCRATCH_CONTROL_S */
  95
  96 /*
  97  * struct iwl_prph_scratch_pnvm_cfg - ror config
  98  * @pnvm_base_addr: PNVM start address
  99  * @pnvm_size: PNVM size in DWs
 100  * @reserved: reserved
 101  */
 102 struct iwl_prph_scratch_pnvm_cfg {
 103         __le64 pnvm_base_addr;
 104         __le32 pnvm_size;
 105         __le32 reserved;
 106 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */
 107
 108 /*
 109  * struct iwl_prph_scratch_hwm_cfg - hwm config
 110  * @hwm_base_addr: hwm start address
 111  * @hwm_size: hwm size in DWs
 112  * @reserved: reserved
 113  */
 114 struct iwl_prph_scratch_hwm_cfg {
 115         __le64 hwm_base_addr;
 116         __le32 hwm_size;
 117         __le32 reserved;
 118 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */
 119
 120 /*
 121  * struct iwl_prph_scratch_rbd_cfg - RBDs configuration
 122  * @free_rbd_addr: default queue free RB CB base address
 123  * @reserved: reserved
 124  */
 125 struct iwl_prph_scratch_rbd_cfg {
 126         __le64 free_rbd_addr;
 127         __le32 reserved;
 128 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */
 129
 130 /*
 131  * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config
 132  * @version: version information of context info and HW
 133  * @control: control flags of FH configurations
 134  * @pnvm_cfg: ror configuration
 135  * @hwm_cfg: hwm configuration
 136  * @rbd_cfg: default RX queue configuration
 137  */
 138 struct iwl_prph_scratch_ctrl_cfg {
 139         struct iwl_prph_scratch_version version;
 140         struct iwl_prph_scratch_control control;
 141         struct iwl_prph_scratch_pnvm_cfg pnvm_cfg;
 142         struct iwl_prph_scratch_hwm_cfg hwm_cfg;
 143         struct iwl_prph_scratch_rbd_cfg rbd_cfg;
 144 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */
 145
 146 /*
 147  * struct iwl_prph_scratch - peripheral scratch mapping
 148  * @ctrl_cfg: control and configuration of prph scratch
 149  * @dram: firmware images addresses in DRAM
 150  * @reserved: reserved
 151  */
 152 struct iwl_prph_scratch {
 153         struct iwl_prph_scratch_ctrl_cfg ctrl_cfg;
 154         __le32 reserved[16];
 155         struct iwl_context_info_dram dram;
 156 } __packed; /* PERIPH_SCRATCH_S */
 157
 158 /*
 159  * struct iwl_prph_info - peripheral information
 160  * @boot_stage_mirror: reflects the value in the Boot Stage CSR register
 161  * @ipc_status_mirror: reflects the value in the IPC Status CSR register
 162  * @sleep_notif: indicates the peripheral sleep status
 163  * @reserved: reserved
 164  */
 165 struct iwl_prph_info {
 166         __le32 boot_stage_mirror;
 167         __le32 ipc_status_mirror;
 168         __le32 sleep_notif;
 169         __le32 reserved;
 170 } __packed; /* PERIPH_INFO_S */
 171
 172 /*
 173  * struct iwl_context_info_gen3 - device INIT configuration
 174  * @version: version of the context information
 175  * @size: size of context information in DWs
 176  * @config: context in which the peripheral would execute - a subset of
 177  *      capability csr register published by the peripheral
 178  * @prph_info_base_addr: the peripheral information structure start address
 179  * @cr_head_idx_arr_base_addr: the completion ring head index array
 180  *      start address
 181  * @tr_tail_idx_arr_base_addr: the transfer ring tail index array
 182  *      start address
 183  * @cr_tail_idx_arr_base_addr: the completion ring tail index array
 184  *      start address
 185  * @tr_head_idx_arr_base_addr: the transfer ring head index array
 186  *      start address
 187  * @cr_idx_arr_size: number of entries in the completion ring index array
 188  * @tr_idx_arr_size: number of entries in the transfer ring index array
 189  * @mtr_base_addr: the message transfer ring start address
 190  * @mcr_base_addr: the message completion ring start address
 191  * @mtr_size: number of entries which the message transfer ring can hold
 192  * @mcr_size: number of entries which the message completion ring can hold
 193  * @mtr_doorbell_vec: the doorbell vector associated with the message
 194  *      transfer ring
 195  * @mcr_doorbell_vec: the doorbell vector associated with the message
 196  *      completion ring
 197  * @mtr_msi_vec: the MSI which shall be generated by the peripheral after
 198  *      completing a transfer descriptor in the message transfer ring
 199  * @mcr_msi_vec: the MSI which shall be generated by the peripheral after
 200  *      completing a completion descriptor in the message completion ring
 201  * @mtr_opt_header_size: the size of the optional header in the transfer
 202  *      descriptor associated with the message transfer ring in DWs
 203  * @mtr_opt_footer_size: the size of the optional footer in the transfer
 204  *      descriptor associated with the message transfer ring in DWs
 205  * @mcr_opt_header_size: the size of the optional header in the completion
 206  *      descriptor associated with the message completion ring in DWs
 207  * @mcr_opt_footer_size: the size of the optional footer in the completion
 208  *      descriptor associated with the message completion ring in DWs
 209  * @msg_rings_ctrl_flags: message rings control flags
 210  * @prph_info_msi_vec: the MSI which shall be generated by the peripheral
 211  *      after updating the Peripheral Information structure
 212  * @prph_scratch_base_addr: the peripheral scratch structure start address
 213  * @prph_scratch_size: the size of the peripheral scratch structure in DWs
 214  * @reserved: reserved
 215  */
 216 struct iwl_context_info_gen3 {
 217         __le16 version;
 218         __le16 size;
 219         __le32 config;
 220         __le64 prph_info_base_addr;
 221         __le64 cr_head_idx_arr_base_addr;
 222         __le64 tr_tail_idx_arr_base_addr;
 223         __le64 cr_tail_idx_arr_base_addr;
 224         __le64 tr_head_idx_arr_base_addr;
 225         __le16 cr_idx_arr_size;
 226         __le16 tr_idx_arr_size;
 227         __le64 mtr_base_addr;
 228         __le64 mcr_base_addr;
 229         __le16 mtr_size;
 230         __le16 mcr_size;
 231         __le16 mtr_doorbell_vec;
 232         __le16 mcr_doorbell_vec;
 233         __le16 mtr_msi_vec;
 234         __le16 mcr_msi_vec;
 235         u8 mtr_opt_header_size;
 236         u8 mtr_opt_footer_size;
 237         u8 mcr_opt_header_size;
 238         u8 mcr_opt_footer_size;
 239         __le16 msg_rings_ctrl_flags;
 240         __le16 prph_info_msi_vec;
 241         __le64 prph_scratch_base_addr;
 242         __le32 prph_scratch_size;
 243         __le32 reserved;
 244 } __packed; /* IPC_CONTEXT_INFO_S */
 245
 246 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
 247                                  const struct fw_img *fw);
 248 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans);
 249
 250 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
 251                                           const void *data, u32 len);
 252
 253 #endif /* __iwl_context_info_file_gen3_h__ */