drivers/mtd/nand/raw/fsmc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ST Microelectronics
   4  * Flexible Static Memory Controller (FSMC)
   5  * Driver for NAND portions
   6  *
   7  * Copyright © 2010 ST Microelectronics
   8  * Vipin Kumar <[email protected]>
   9  * Ashish Priyadarshi
  10  *
  11  * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
  12  *  Copyright © 2007 STMicroelectronics Pvt. Ltd.
  13  *  Copyright © 2009 Alessandro Rubini
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/completion.h>
  18 #include <linux/dmaengine.h>
  19 #include <linux/dma-direction.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/resource.h>
  25 #include <linux/sched.h>
  26 #include <linux/types.h>
  27 #include <linux/mtd/mtd.h>
  28 #include <linux/mtd/rawnand.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/of.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/io.h>
  33 #include <linux/slab.h>
  34 #include <linux/amba/bus.h>
  35 #include <mtd/mtd-abi.h>
  36
  37 /* fsmc controller registers for NOR flash */
  38 #define CTRL                    0x0
  39         /* ctrl register definitions */
  40         #define BANK_ENABLE             BIT(0)
  41         #define MUXED                   BIT(1)
  42         #define NOR_DEV                 (2 << 2)
  43         #define WIDTH_16                BIT(4)
  44         #define RSTPWRDWN               BIT(6)
  45         #define WPROT                   BIT(7)
  46         #define WRT_ENABLE              BIT(12)
  47         #define WAIT_ENB                BIT(13)
  48
  49 #define CTRL_TIM                0x4
  50         /* ctrl_tim register definitions */
  51
  52 #define FSMC_NOR_BANK_SZ        0x8
  53 #define FSMC_NOR_REG_SIZE       0x40
  54
  55 #define FSMC_NOR_REG(base, bank, reg)   ((base) +                       \
  56                                          (FSMC_NOR_BANK_SZ * (bank)) +  \
  57                                          (reg))
  58
  59 /* fsmc controller registers for NAND flash */
  60 #define FSMC_PC                 0x00
  61         /* pc register definitions */
  62         #define FSMC_RESET              BIT(0)
  63         #define FSMC_WAITON             BIT(1)
  64         #define FSMC_ENABLE             BIT(2)
  65         #define FSMC_DEVTYPE_NAND       BIT(3)
  66         #define FSMC_DEVWID_16          BIT(4)
  67         #define FSMC_ECCEN              BIT(6)
  68         #define FSMC_ECCPLEN_256        BIT(7)
  69         #define FSMC_TCLR_SHIFT         (9)
  70         #define FSMC_TCLR_MASK          (0xF)
  71         #define FSMC_TAR_SHIFT          (13)
  72         #define FSMC_TAR_MASK           (0xF)
  73 #define STS                     0x04
  74         /* sts register definitions */
  75         #define FSMC_CODE_RDY           BIT(15)
  76 #define COMM                    0x08
  77         /* comm register definitions */
  78         #define FSMC_TSET_SHIFT         0
  79         #define FSMC_TSET_MASK          0xFF
  80         #define FSMC_TWAIT_SHIFT        8
  81         #define FSMC_TWAIT_MASK         0xFF
  82         #define FSMC_THOLD_SHIFT        16
  83         #define FSMC_THOLD_MASK         0xFF
  84         #define FSMC_THIZ_SHIFT         24
  85         #define FSMC_THIZ_MASK          0xFF
  86 #define ATTRIB                  0x0C
  87 #define IOATA                   0x10
  88 #define ECC1                    0x14
  89 #define ECC2                    0x18
  90 #define ECC3                    0x1C
  91 #define FSMC_NAND_BANK_SZ       0x20
  92
  93 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
  94
  95 struct fsmc_nand_timings {
  96         u8 tclr;
  97         u8 tar;
  98         u8 thiz;
  99         u8 thold;
 100         u8 twait;
 101         u8 tset;
 102 };
 103
 104 enum access_mode {
 105         USE_DMA_ACCESS = 1,
 106         USE_WORD_ACCESS,
 107 };
 108
 109 /**
 110  * struct fsmc_nand_data - structure for FSMC NAND device state
 111  *
 112  * @base:               Inherit from the nand_controller struct
 113  * @pid:                Part ID on the AMBA PrimeCell format
 114  * @nand:               Chip related info for a NAND flash.
 115  *
 116  * @bank:               Bank number for probed device.
 117  * @dev:                Parent device
 118  * @mode:               Access mode
 119  * @clk:                Clock structure for FSMC.
 120  *
 121  * @read_dma_chan:      DMA channel for read access
 122  * @write_dma_chan:     DMA channel for write access to NAND
 123  * @dma_access_complete: Completion structure
 124  *
 125  * @dev_timings:        NAND timings
 126  *
 127  * @data_pa:            NAND Physical port for Data.
 128  * @data_va:            NAND port for Data.
 129  * @cmd_va:             NAND port for Command.
 130  * @addr_va:            NAND port for Address.
 131  * @regs_va:            Registers base address for a given bank.
 132  */
 133 struct fsmc_nand_data {
 134         struct nand_controller  base;
 135         u32                     pid;
 136         struct nand_chip        nand;
 137
 138         unsigned int            bank;
 139         struct device           *dev;
 140         enum access_mode        mode;
 141         struct clk              *clk;
 142
 143         /* DMA related objects */
 144         struct dma_chan         *read_dma_chan;
 145         struct dma_chan         *write_dma_chan;
 146         struct completion       dma_access_complete;
 147
 148         struct fsmc_nand_timings *dev_timings;
 149
 150         dma_addr_t              data_pa;
 151         void __iomem            *data_va;
 152         void __iomem            *cmd_va;
 153         void __iomem            *addr_va;
 154         void __iomem            *regs_va;
 155 };
 156
 157 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 158                                    struct mtd_oob_region *oobregion)
 159 {
 160         struct nand_chip *chip = mtd_to_nand(mtd);
 161
 162         if (section >= chip->ecc.steps)
 163                 return -ERANGE;
 164
 165         oobregion->offset = (section * 16) + 2;
 166         oobregion->length = 3;
 167
 168         return 0;
 169 }
 170
 171 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 172                                     struct mtd_oob_region *oobregion)
 173 {
 174         struct nand_chip *chip = mtd_to_nand(mtd);
 175
 176         if (section >= chip->ecc.steps)
 177                 return -ERANGE;
 178
 179         oobregion->offset = (section * 16) + 8;
 180
 181         if (section < chip->ecc.steps - 1)
 182                 oobregion->length = 8;
 183         else
 184                 oobregion->length = mtd->oobsize - oobregion->offset;
 185
 186         return 0;
 187 }
 188
 189 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 190         .ecc = fsmc_ecc1_ooblayout_ecc,
 191         .free = fsmc_ecc1_ooblayout_free,
 192 };
 193
 194 /*
 195  * ECC placement definitions in oobfree type format.
 196  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 197  * consecutively and immediately after the 512 byte data block for hardware to
 198  * generate the error bit offsets in 512 byte data.
 199  */
 200 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 201                                    struct mtd_oob_region *oobregion)
 202 {
 203         struct nand_chip *chip = mtd_to_nand(mtd);
 204
 205         if (section >= chip->ecc.steps)
 206                 return -ERANGE;
 207
 208         oobregion->length = chip->ecc.bytes;
 209
 210         if (!section && mtd->writesize <= 512)
 211                 oobregion->offset = 0;
 212         else
 213                 oobregion->offset = (section * 16) + 2;
 214
 215         return 0;
 216 }
 217
 218 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 219                                     struct mtd_oob_region *oobregion)
 220 {
 221         struct nand_chip *chip = mtd_to_nand(mtd);
 222
 223         if (section >= chip->ecc.steps)
 224                 return -ERANGE;
 225
 226         oobregion->offset = (section * 16) + 15;
 227
 228         if (section < chip->ecc.steps - 1)
 229                 oobregion->length = 3;
 230         else
 231                 oobregion->length = mtd->oobsize - oobregion->offset;
 232
 233         return 0;
 234 }
 235
 236 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 237         .ecc = fsmc_ecc4_ooblayout_ecc,
 238         .free = fsmc_ecc4_ooblayout_free,
 239 };
 240
 241 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
 242 {
 243         return container_of(chip, struct fsmc_nand_data, nand);
 244 }
 245
 246 /*
 247  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 248  *
 249  * This routine initializes timing parameters related to NAND memory access in
 250  * FSMC registers
 251  */
 252 static void fsmc_nand_setup(struct fsmc_nand_data *host,
 253                             struct fsmc_nand_timings *tims)
 254 {
 255         u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 256         u32 tclr, tar, thiz, thold, twait, tset;
 257
 258         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 259         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 260         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 261         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 262         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 263         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 264
 265         if (host->nand.options & NAND_BUSWIDTH_16)
 266                 value |= FSMC_DEVWID_16;
 267
 268         writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
 269         writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
 270         writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
 271 }
 272
 273 static int fsmc_calc_timings(struct fsmc_nand_data *host,
 274                              const struct nand_sdr_timings *sdrt,
 275                              struct fsmc_nand_timings *tims)
 276 {
 277         unsigned long hclk = clk_get_rate(host->clk);
 278         unsigned long hclkn = NSEC_PER_SEC / hclk;
 279         u32 thiz, thold, twait, tset;
 280
 281         if (sdrt->tRC_min < 30000)
 282                 return -EOPNOTSUPP;
 283
 284         tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
 285         if (tims->tar > FSMC_TAR_MASK)
 286                 tims->tar = FSMC_TAR_MASK;
 287         tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
 288         if (tims->tclr > FSMC_TCLR_MASK)
 289                 tims->tclr = FSMC_TCLR_MASK;
 290
 291         thiz = sdrt->tCS_min - sdrt->tWP_min;
 292         tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
 293
 294         thold = sdrt->tDH_min;
 295         if (thold < sdrt->tCH_min)
 296                 thold = sdrt->tCH_min;
 297         if (thold < sdrt->tCLH_min)
 298                 thold = sdrt->tCLH_min;
 299         if (thold < sdrt->tWH_min)
 300                 thold = sdrt->tWH_min;
 301         if (thold < sdrt->tALH_min)
 302                 thold = sdrt->tALH_min;
 303         if (thold < sdrt->tREH_min)
 304                 thold = sdrt->tREH_min;
 305         tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
 306         if (tims->thold == 0)
 307                 tims->thold = 1;
 308         else if (tims->thold > FSMC_THOLD_MASK)
 309                 tims->thold = FSMC_THOLD_MASK;
 310
 311         twait = max(sdrt->tRP_min, sdrt->tWP_min);
 312         tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
 313         if (tims->twait == 0)
 314                 tims->twait = 1;
 315         else if (tims->twait > FSMC_TWAIT_MASK)
 316                 tims->twait = FSMC_TWAIT_MASK;
 317
 318         tset = max(sdrt->tCS_min - sdrt->tWP_min,
 319                    sdrt->tCEA_max - sdrt->tREA_max);
 320         tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
 321         if (tims->tset == 0)
 322                 tims->tset = 1;
 323         else if (tims->tset > FSMC_TSET_MASK)
 324                 tims->tset = FSMC_TSET_MASK;
 325
 326         return 0;
 327 }
 328
 329 static int fsmc_setup_interface(struct nand_chip *nand, int csline,
 330                                 const struct nand_interface_config *conf)
 331 {
 332         struct fsmc_nand_data *host = nand_to_fsmc(nand);
 333         struct fsmc_nand_timings tims;
 334         const struct nand_sdr_timings *sdrt;
 335         int ret;
 336
 337         sdrt = nand_get_sdr_timings(conf);
 338         if (IS_ERR(sdrt))
 339                 return PTR_ERR(sdrt);
 340
 341         ret = fsmc_calc_timings(host, sdrt, &tims);
 342         if (ret)
 343                 return ret;
 344
 345         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
 346                 return 0;
 347
 348         fsmc_nand_setup(host, &tims);
 349
 350         return 0;
 351 }
 352
 353 /*
 354  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 355  */
 356 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
 357 {
 358         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 359
 360         writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
 361                        host->regs_va + FSMC_PC);
 362         writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
 363                        host->regs_va + FSMC_PC);
 364         writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
 365                        host->regs_va + FSMC_PC);
 366 }
 367
 368 /*
 369  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 370  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 371  * max of 8-bits)
 372  */
 373 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
 374                                 u8 *ecc)
 375 {
 376         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 377         u32 ecc_tmp;
 378         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 379
 380         do {
 381                 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
 382                         break;
 383
 384                 cond_resched();
 385         } while (!time_after_eq(jiffies, deadline));
 386
 387         if (time_after_eq(jiffies, deadline)) {
 388                 dev_err(host->dev, "calculate ecc timed out\n");
 389                 return -ETIMEDOUT;
 390         }
 391
 392         ecc_tmp = readl_relaxed(host->regs_va + ECC1);
 393         ecc[0] = ecc_tmp;
 394         ecc[1] = ecc_tmp >> 8;
 395         ecc[2] = ecc_tmp >> 16;
 396         ecc[3] = ecc_tmp >> 24;
 397
 398         ecc_tmp = readl_relaxed(host->regs_va + ECC2);
 399         ecc[4] = ecc_tmp;
 400         ecc[5] = ecc_tmp >> 8;
 401         ecc[6] = ecc_tmp >> 16;
 402         ecc[7] = ecc_tmp >> 24;
 403
 404         ecc_tmp = readl_relaxed(host->regs_va + ECC3);
 405         ecc[8] = ecc_tmp;
 406         ecc[9] = ecc_tmp >> 8;
 407         ecc[10] = ecc_tmp >> 16;
 408         ecc[11] = ecc_tmp >> 24;
 409
 410         ecc_tmp = readl_relaxed(host->regs_va + STS);
 411         ecc[12] = ecc_tmp >> 16;
 412
 413         return 0;
 414 }
 415
 416 /*
 417  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 418  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 419  * max of 1-bit)
 420  */
 421 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
 422                                 u8 *ecc)
 423 {
 424         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 425         u32 ecc_tmp;
 426
 427         ecc_tmp = readl_relaxed(host->regs_va + ECC1);
 428         ecc[0] = ecc_tmp;
 429         ecc[1] = ecc_tmp >> 8;
 430         ecc[2] = ecc_tmp >> 16;
 431
 432         return 0;
 433 }
 434
 435 /* Count the number of 0's in buff upto a max of max_bits */
 436 static int count_written_bits(u8 *buff, int size, int max_bits)
 437 {
 438         int k, written_bits = 0;
 439
 440         for (k = 0; k < size; k++) {
 441                 written_bits += hweight8(~buff[k]);
 442                 if (written_bits > max_bits)
 443                         break;
 444         }
 445
 446         return written_bits;
 447 }
 448
 449 static void dma_complete(void *param)
 450 {
 451         struct fsmc_nand_data *host = param;
 452
 453         complete(&host->dma_access_complete);
 454 }
 455
 456 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 457                     enum dma_data_direction direction)
 458 {
 459         struct dma_chan *chan;
 460         struct dma_device *dma_dev;
 461         struct dma_async_tx_descriptor *tx;
 462         dma_addr_t dma_dst, dma_src, dma_addr;
 463         dma_cookie_t cookie;
 464         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 465         int ret;
 466         unsigned long time_left;
 467
 468         if (direction == DMA_TO_DEVICE)
 469                 chan = host->write_dma_chan;
 470         else if (direction == DMA_FROM_DEVICE)
 471                 chan = host->read_dma_chan;
 472         else
 473                 return -EINVAL;
 474
 475         dma_dev = chan->device;
 476         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 477
 478         if (direction == DMA_TO_DEVICE) {
 479                 dma_src = dma_addr;
 480                 dma_dst = host->data_pa;
 481         } else {
 482                 dma_src = host->data_pa;
 483                 dma_dst = dma_addr;
 484         }
 485
 486         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 487                         len, flags);
 488         if (!tx) {
 489                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 490                 ret = -EIO;
 491                 goto unmap_dma;
 492         }
 493
 494         tx->callback = dma_complete;
 495         tx->callback_param = host;
 496         cookie = tx->tx_submit(tx);
 497
 498         ret = dma_submit_error(cookie);
 499         if (ret) {
 500                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 501                 goto unmap_dma;
 502         }
 503
 504         dma_async_issue_pending(chan);
 505
 506         time_left =
 507         wait_for_completion_timeout(&host->dma_access_complete,
 508                                     msecs_to_jiffies(3000));
 509         if (time_left == 0) {
 510                 dmaengine_terminate_all(chan);
 511                 dev_err(host->dev, "wait_for_completion_timeout\n");
 512                 ret = -ETIMEDOUT;
 513                 goto unmap_dma;
 514         }
 515
 516         ret = 0;
 517
 518 unmap_dma:
 519         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 520
 521         return ret;
 522 }
 523
 524 /*
 525  * fsmc_write_buf - write buffer to chip
 526  * @host:       FSMC NAND controller
 527  * @buf:        data buffer
 528  * @len:        number of bytes to write
 529  */
 530 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
 531                            int len)
 532 {
 533         int i;
 534
 535         if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
 536             IS_ALIGNED(len, sizeof(u32))) {
 537                 u32 *p = (u32 *)buf;
 538
 539                 len = len >> 2;
 540                 for (i = 0; i < len; i++)
 541                         writel_relaxed(p[i], host->data_va);
 542         } else {
 543                 for (i = 0; i < len; i++)
 544                         writeb_relaxed(buf[i], host->data_va);
 545         }
 546 }
 547
 548 /*
 549  * fsmc_read_buf - read chip data into buffer
 550  * @host:       FSMC NAND controller
 551  * @buf:        buffer to store date
 552  * @len:        number of bytes to read
 553  */
 554 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
 555 {
 556         int i;
 557
 558         if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
 559             IS_ALIGNED(len, sizeof(u32))) {
 560                 u32 *p = (u32 *)buf;
 561
 562                 len = len >> 2;
 563                 for (i = 0; i < len; i++)
 564                         p[i] = readl_relaxed(host->data_va);
 565         } else {
 566                 for (i = 0; i < len; i++)
 567                         buf[i] = readb_relaxed(host->data_va);
 568         }
 569 }
 570
 571 /*
 572  * fsmc_read_buf_dma - read chip data into buffer
 573  * @host:       FSMC NAND controller
 574  * @buf:        buffer to store date
 575  * @len:        number of bytes to read
 576  */
 577 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
 578                               int len)
 579 {
 580         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 581 }
 582
 583 /*
 584  * fsmc_write_buf_dma - write buffer to chip
 585  * @host:       FSMC NAND controller
 586  * @buf:        data buffer
 587  * @len:        number of bytes to write
 588  */
 589 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
 590                                int len)
 591 {
 592         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 593 }
 594
 595 /*
 596  * fsmc_exec_op - hook called by the core to execute NAND operations
 597  *
 598  * This controller is simple enough and thus does not need to use the parser
 599  * provided by the core, instead, handle every situation here.
 600  */
 601 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
 602                         bool check_only)
 603 {
 604         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 605         const struct nand_op_instr *instr = NULL;
 606         int ret = 0;
 607         unsigned int op_id;
 608         int i;
 609
 610         if (check_only)
 611                 return 0;
 612
 613         pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
 614
 615         for (op_id = 0; op_id < op->ninstrs; op_id++) {
 616                 instr = &op->instrs[op_id];
 617
 618                 nand_op_trace("  ", instr);
 619
 620                 switch (instr->type) {
 621                 case NAND_OP_CMD_INSTR:
 622                         writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
 623                         break;
 624
 625                 case NAND_OP_ADDR_INSTR:
 626                         for (i = 0; i < instr->ctx.addr.naddrs; i++)
 627                                 writeb_relaxed(instr->ctx.addr.addrs[i],
 628                                                host->addr_va);
 629                         break;
 630
 631                 case NAND_OP_DATA_IN_INSTR:
 632                         if (host->mode == USE_DMA_ACCESS)
 633                                 fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
 634                                                   instr->ctx.data.len);
 635                         else
 636                                 fsmc_read_buf(host, instr->ctx.data.buf.in,
 637                                               instr->ctx.data.len);
 638                         break;
 639
 640                 case NAND_OP_DATA_OUT_INSTR:
 641                         if (host->mode == USE_DMA_ACCESS)
 642                                 fsmc_write_buf_dma(host,
 643                                                    instr->ctx.data.buf.out,
 644                                                    instr->ctx.data.len);
 645                         else
 646                                 fsmc_write_buf(host, instr->ctx.data.buf.out,
 647                                                instr->ctx.data.len);
 648                         break;
 649
 650                 case NAND_OP_WAITRDY_INSTR:
 651                         ret = nand_soft_waitrdy(chip,
 652                                                 instr->ctx.waitrdy.timeout_ms);
 653                         break;
 654                 }
 655         }
 656
 657         return ret;
 658 }
 659
 660 /*
 661  * fsmc_read_page_hwecc
 662  * @chip:       nand chip info structure
 663  * @buf:        buffer to store read data
 664  * @oob_required:       caller expects OOB data read to chip->oob_poi
 665  * @page:       page number to read
 666  *
 667  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 668  * performed in a strict sequence as follows:
 669  * data(512 byte) -> ecc(13 byte)
 670  * After this read, fsmc hardware generates and reports error data bits(up to a
 671  * max of 8 bits)
 672  */
 673 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
 674                                 int oob_required, int page)
 675 {
 676         struct mtd_info *mtd = nand_to_mtd(chip);
 677         int i, j, s, stat, eccsize = chip->ecc.size;
 678         int eccbytes = chip->ecc.bytes;
 679         int eccsteps = chip->ecc.steps;
 680         u8 *p = buf;
 681         u8 *ecc_calc = chip->ecc.calc_buf;
 682         u8 *ecc_code = chip->ecc.code_buf;
 683         int off, len, ret, group = 0;
 684         /*
 685          * ecc_oob is intentionally taken as u16. In 16bit devices, we
 686          * end up reading 14 bytes (7 words) from oob. The local array is
 687          * to maintain word alignment
 688          */
 689         u16 ecc_oob[7];
 690         u8 *oob = (u8 *)&ecc_oob[0];
 691         unsigned int max_bitflips = 0;
 692
 693         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 694                 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
 695                 chip->ecc.hwctl(chip, NAND_ECC_READ);
 696                 ret = nand_read_data_op(chip, p, eccsize, false, false);
 697                 if (ret)
 698                         return ret;
 699
 700                 for (j = 0; j < eccbytes;) {
 701                         struct mtd_oob_region oobregion;
 702
 703                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 704                         if (ret)
 705                                 return ret;
 706
 707                         off = oobregion.offset;
 708                         len = oobregion.length;
 709
 710                         /*
 711                          * length is intentionally kept a higher multiple of 2
 712                          * to read at least 13 bytes even in case of 16 bit NAND
 713                          * devices
 714                          */
 715                         if (chip->options & NAND_BUSWIDTH_16)
 716                                 len = roundup(len, 2);
 717
 718                         nand_read_oob_op(chip, page, off, oob + j, len);
 719                         j += len;
 720                 }
 721
 722                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 723                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
 724
 725                 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
 726                 if (stat < 0) {
 727                         mtd->ecc_stats.failed++;
 728                 } else {
 729                         mtd->ecc_stats.corrected += stat;
 730                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 731                 }
 732         }
 733
 734         return max_bitflips;
 735 }
 736
 737 /*
 738  * fsmc_bch8_correct_data
 739  * @mtd:        mtd info structure
 740  * @dat:        buffer of read data
 741  * @read_ecc:   ecc read from device spare area
 742  * @calc_ecc:   ecc calculated from read data
 743  *
 744  * calc_ecc is a 104 bit information containing maximum of 8 error
 745  * offset information of 13 bits each in 512 bytes of read data.
 746  */
 747 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
 748                                   u8 *read_ecc, u8 *calc_ecc)
 749 {
 750         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 751         u32 err_idx[8];
 752         u32 num_err, i;
 753         u32 ecc1, ecc2, ecc3, ecc4;
 754
 755         num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
 756
 757         /* no bit flipping */
 758         if (likely(num_err == 0))
 759                 return 0;
 760
 761         /* too many errors */
 762         if (unlikely(num_err > 8)) {
 763                 /*
 764                  * This is a temporary erase check. A newly erased page read
 765                  * would result in an ecc error because the oob data is also
 766                  * erased to FF and the calculated ecc for an FF data is not
 767                  * FF..FF.
 768                  * This is a workaround to skip performing correction in case
 769                  * data is FF..FF
 770                  *
 771                  * Logic:
 772                  * For every page, each bit written as 0 is counted until these
 773                  * number of bits are greater than 8 (the maximum correction
 774                  * capability of FSMC for each 512 + 13 bytes)
 775                  */
 776
 777                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 778                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 779
 780                 if ((bits_ecc + bits_data) <= 8) {
 781                         if (bits_data)
 782                                 memset(dat, 0xff, chip->ecc.size);
 783                         return bits_data;
 784                 }
 785
 786                 return -EBADMSG;
 787         }
 788
 789         /*
 790          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 791          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 792          *
 793          * calc_ecc is a 104 bit information containing maximum of 8 error
 794          * offset information of 13 bits each. calc_ecc is copied into a
 795          * u64 array and error offset indexes are populated in err_idx
 796          * array
 797          */
 798         ecc1 = readl_relaxed(host->regs_va + ECC1);
 799         ecc2 = readl_relaxed(host->regs_va + ECC2);
 800         ecc3 = readl_relaxed(host->regs_va + ECC3);
 801         ecc4 = readl_relaxed(host->regs_va + STS);
 802
 803         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 804         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 805         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 806         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 807         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 808         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 809         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 810         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 811
 812         i = 0;
 813         while (num_err--) {
 814                 err_idx[i] ^= 3;
 815
 816                 if (err_idx[i] < chip->ecc.size * 8) {
 817                         int err = err_idx[i];
 818
 819                         dat[err >> 3] ^= BIT(err & 7);
 820                         i++;
 821                 }
 822         }
 823         return i;
 824 }
 825
 826 static bool filter(struct dma_chan *chan, void *slave)
 827 {
 828         chan->private = slave;
 829         return true;
 830 }
 831
 832 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 833                                      struct fsmc_nand_data *host,
 834                                      struct nand_chip *nand)
 835 {
 836         struct device_node *np = pdev->dev.of_node;
 837         u32 val;
 838         int ret;
 839
 840         nand->options = 0;
 841
 842         if (!of_property_read_u32(np, "bank-width", &val)) {
 843                 if (val == 2) {
 844                         nand->options |= NAND_BUSWIDTH_16;
 845                 } else if (val != 1) {
 846                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 847                         return -EINVAL;
 848                 }
 849         }
 850
 851         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 852                 nand->options |= NAND_SKIP_BBTSCAN;
 853
 854         host->dev_timings = devm_kzalloc(&pdev->dev,
 855                                          sizeof(*host->dev_timings),
 856                                          GFP_KERNEL);
 857         if (!host->dev_timings)
 858                 return -ENOMEM;
 859
 860         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 861                                         sizeof(*host->dev_timings));
 862         if (ret)
 863                 host->dev_timings = NULL;
 864
 865         /* Set default NAND bank to 0 */
 866         host->bank = 0;
 867         if (!of_property_read_u32(np, "bank", &val)) {
 868                 if (val > 3) {
 869                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 870                         return -EINVAL;
 871                 }
 872                 host->bank = val;
 873         }
 874         return 0;
 875 }
 876
 877 static int fsmc_nand_attach_chip(struct nand_chip *nand)
 878 {
 879         struct mtd_info *mtd = nand_to_mtd(nand);
 880         struct fsmc_nand_data *host = nand_to_fsmc(nand);
 881
 882         if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
 883                 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
 884
 885         if (!nand->ecc.size)
 886                 nand->ecc.size = 512;
 887
 888         if (AMBA_REV_BITS(host->pid) >= 8) {
 889                 nand->ecc.read_page = fsmc_read_page_hwecc;
 890                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
 891                 nand->ecc.correct = fsmc_bch8_correct_data;
 892                 nand->ecc.bytes = 13;
 893                 nand->ecc.strength = 8;
 894         }
 895
 896         if (AMBA_REV_BITS(host->pid) >= 8) {
 897                 switch (mtd->oobsize) {
 898                 case 16:
 899                 case 64:
 900                 case 128:
 901                 case 224:
 902                 case 256:
 903                         break;
 904                 default:
 905                         dev_warn(host->dev,
 906                                  "No oob scheme defined for oobsize %d\n",
 907                                  mtd->oobsize);
 908                         return -EINVAL;
 909                 }
 910
 911                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
 912
 913                 return 0;
 914         }
 915
 916         switch (nand->ecc.engine_type) {
 917         case NAND_ECC_ENGINE_TYPE_ON_HOST:
 918                 dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
 919                 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
 920                 nand->ecc.correct = rawnand_sw_hamming_correct;
 921                 nand->ecc.hwctl = fsmc_enable_hwecc;
 922                 nand->ecc.bytes = 3;
 923                 nand->ecc.strength = 1;
 924                 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
 925                 break;
 926
 927         case NAND_ECC_ENGINE_TYPE_SOFT:
 928                 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
 929                         dev_info(host->dev,
 930                                  "Using 4-bit SW BCH ECC scheme\n");
 931                         break;
 932                 }
 933                 break;
 934
 935         case NAND_ECC_ENGINE_TYPE_ON_DIE:
 936                 break;
 937
 938         default:
 939                 dev_err(host->dev, "Unsupported ECC mode!\n");
 940                 return -ENOTSUPP;
 941         }
 942
 943         /*
 944          * Don't set layout for BCH4 SW ECC. This will be
 945          * generated later during BCH initialization.
 946          */
 947         if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
 948                 switch (mtd->oobsize) {
 949                 case 16:
 950                 case 64:
 951                 case 128:
 952                         mtd_set_ooblayout(mtd,
 953                                           &fsmc_ecc1_ooblayout_ops);
 954                         break;
 955                 default:
 956                         dev_warn(host->dev,
 957                                  "No oob scheme defined for oobsize %d\n",
 958                                  mtd->oobsize);
 959                         return -EINVAL;
 960                 }
 961         }
 962
 963         return 0;
 964 }
 965
 966 static const struct nand_controller_ops fsmc_nand_controller_ops = {
 967         .attach_chip = fsmc_nand_attach_chip,
 968         .exec_op = fsmc_exec_op,
 969         .setup_interface = fsmc_setup_interface,
 970 };
 971
 972 /**
 973  * fsmc_nand_disable() - Disables the NAND bank
 974  * @host: The instance to disable
 975  */
 976 static void fsmc_nand_disable(struct fsmc_nand_data *host)
 977 {
 978         u32 val;
 979
 980         val = readl(host->regs_va + FSMC_PC);
 981         val &= ~FSMC_ENABLE;
 982         writel(val, host->regs_va + FSMC_PC);
 983 }
 984
 985 /*
 986  * fsmc_nand_probe - Probe function
 987  * @pdev:       platform device structure
 988  */
 989 static int __init fsmc_nand_probe(struct platform_device *pdev)
 990 {
 991         struct fsmc_nand_data *host;
 992         struct mtd_info *mtd;
 993         struct nand_chip *nand;
 994         struct resource *res;
 995         void __iomem *base;
 996         dma_cap_mask_t mask;
 997         int ret = 0;
 998         u32 pid;
 999         int i;
1000
1001         /* Allocate memory for the device structure (and zero it) */
1002         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1003         if (!host)
1004                 return -ENOMEM;
1005
1006         nand = &host->nand;
1007
1008         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
1009         if (ret)
1010                 return ret;
1011
1012         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
1013         host->data_va = devm_ioremap_resource(&pdev->dev, res);
1014         if (IS_ERR(host->data_va))
1015                 return PTR_ERR(host->data_va);
1016
1017         host->data_pa = (dma_addr_t)res->start;
1018
1019         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
1020         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
1021         if (IS_ERR(host->addr_va))
1022                 return PTR_ERR(host->addr_va);
1023
1024         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
1025         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
1026         if (IS_ERR(host->cmd_va))
1027                 return PTR_ERR(host->cmd_va);
1028
1029         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
1030         base = devm_ioremap_resource(&pdev->dev, res);
1031         if (IS_ERR(base))
1032                 return PTR_ERR(base);
1033
1034         host->regs_va = base + FSMC_NOR_REG_SIZE +
1035                 (host->bank * FSMC_NAND_BANK_SZ);
1036
1037         host->clk = devm_clk_get(&pdev->dev, NULL);
1038         if (IS_ERR(host->clk)) {
1039                 dev_err(&pdev->dev, "failed to fetch block clock\n");
1040                 return PTR_ERR(host->clk);
1041         }
1042
1043         ret = clk_prepare_enable(host->clk);
1044         if (ret)
1045                 return ret;
1046
1047         /*
1048          * This device ID is actually a common AMBA ID as used on the
1049          * AMBA PrimeCell bus. However it is not a PrimeCell.
1050          */
1051         for (pid = 0, i = 0; i < 4; i++)
1052                 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1053                         255) << (i * 8);
1054
1055         host->pid = pid;
1056
1057         dev_info(&pdev->dev,
1058                  "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
1059                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1060                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1061
1062         host->dev = &pdev->dev;
1063
1064         if (host->mode == USE_DMA_ACCESS)
1065                 init_completion(&host->dma_access_complete);
1066
1067         /* Link all private pointers */
1068         mtd = nand_to_mtd(&host->nand);
1069         nand_set_flash_node(nand, pdev->dev.of_node);
1070
1071         mtd->dev.parent = &pdev->dev;
1072
1073         nand->badblockbits = 7;
1074
1075         if (host->mode == USE_DMA_ACCESS) {
1076                 dma_cap_zero(mask);
1077                 dma_cap_set(DMA_MEMCPY, mask);
1078                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
1079                 if (!host->read_dma_chan) {
1080                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
1081                         ret = -ENODEV;
1082                         goto disable_clk;
1083                 }
1084                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1085                 if (!host->write_dma_chan) {
1086                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1087                         ret = -ENODEV;
1088                         goto release_dma_read_chan;
1089                 }
1090         }
1091
1092         if (host->dev_timings) {
1093                 fsmc_nand_setup(host, host->dev_timings);
1094                 nand->options |= NAND_KEEP_TIMINGS;
1095         }
1096
1097         nand_controller_init(&host->base);
1098         host->base.ops = &fsmc_nand_controller_ops;
1099         nand->controller = &host->base;
1100
1101         /*
1102          * Scan to find existence of the device
1103          */
1104         ret = nand_scan(nand, 1);
1105         if (ret)
1106                 goto release_dma_write_chan;
1107
1108         mtd->name = "nand";
1109         ret = mtd_device_register(mtd, NULL, 0);
1110         if (ret)
1111                 goto cleanup_nand;
1112
1113         platform_set_drvdata(pdev, host);
1114         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1115
1116         return 0;
1117
1118 cleanup_nand:
1119         nand_cleanup(nand);
1120 release_dma_write_chan:
1121         if (host->mode == USE_DMA_ACCESS)
1122                 dma_release_channel(host->write_dma_chan);
1123 release_dma_read_chan:
1124         if (host->mode == USE_DMA_ACCESS)
1125                 dma_release_channel(host->read_dma_chan);
1126 disable_clk:
1127         fsmc_nand_disable(host);
1128         clk_disable_unprepare(host->clk);
1129
1130         return ret;
1131 }
1132
1133 /*
1134  * Clean up routine
1135  */
1136 static int fsmc_nand_remove(struct platform_device *pdev)
1137 {
1138         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1139
1140         if (host) {
1141                 struct nand_chip *chip = &host->nand;
1142                 int ret;
1143
1144                 ret = mtd_device_unregister(nand_to_mtd(chip));
1145                 WARN_ON(ret);
1146                 nand_cleanup(chip);
1147                 fsmc_nand_disable(host);
1148
1149                 if (host->mode == USE_DMA_ACCESS) {
1150                         dma_release_channel(host->write_dma_chan);
1151                         dma_release_channel(host->read_dma_chan);
1152                 }
1153                 clk_disable_unprepare(host->clk);
1154         }
1155
1156         return 0;
1157 }
1158
1159 #ifdef CONFIG_PM_SLEEP
1160 static int fsmc_nand_suspend(struct device *dev)
1161 {
1162         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1163
1164         if (host)
1165                 clk_disable_unprepare(host->clk);
1166
1167         return 0;
1168 }
1169
1170 static int fsmc_nand_resume(struct device *dev)
1171 {
1172         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1173
1174         if (host) {
1175                 clk_prepare_enable(host->clk);
1176                 if (host->dev_timings)
1177                         fsmc_nand_setup(host, host->dev_timings);
1178                 nand_reset(&host->nand, 0);
1179         }
1180
1181         return 0;
1182 }
1183 #endif
1184
1185 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1186
1187 static const struct of_device_id fsmc_nand_id_table[] = {
1188         { .compatible = "st,spear600-fsmc-nand" },
1189         { .compatible = "stericsson,fsmc-nand" },
1190         {}
1191 };
1192 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1193
1194 static struct platform_driver fsmc_nand_driver = {
1195         .remove = fsmc_nand_remove,
1196         .driver = {
1197                 .name = "fsmc-nand",
1198                 .of_match_table = fsmc_nand_id_table,
1199                 .pm = &fsmc_nand_pm_ops,
1200         },
1201 };
1202
1203 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1204
1205 MODULE_LICENSE("GPL v2");
1206 MODULE_AUTHOR("Vipin Kumar <[email protected]>, Ashish Priyadarshi");
1207 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");