drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_12_0_0_offset.h"
  30 #include "gc/gc_12_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v12_structs.h"
  33 #include "mes_v12_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin");
  41
  42 static int mes_v12_0_hw_init(void *handle);
  43 static int mes_v12_0_hw_fini(void *handle);
  44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);
  45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);
  46
  47 #define MES_EOP_SIZE   2048
  48
  49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)
  50 {
  51         struct amdgpu_device *adev = ring->adev;
  52
  53         if (ring->use_doorbell) {
  54                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  55                              ring->wptr);
  56                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  57         } else {
  58                 BUG();
  59         }
  60 }
  61
  62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)
  63 {
  64         return *ring->rptr_cpu_addr;
  65 }
  66
  67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)
  68 {
  69         u64 wptr;
  70
  71         if (ring->use_doorbell)
  72                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  73         else
  74                 BUG();
  75         return wptr;
  76 }
  77
  78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = {
  79         .type = AMDGPU_RING_TYPE_MES,
  80         .align_mask = 1,
  81         .nop = 0,
  82         .support_64bit_ptrs = true,
  83         .get_rptr = mes_v12_0_ring_get_rptr,
  84         .get_wptr = mes_v12_0_ring_get_wptr,
  85         .set_wptr = mes_v12_0_ring_set_wptr,
  86         .insert_nop = amdgpu_ring_insert_nop,
  87 };
  88
  89 static const char *mes_v12_0_opcodes[] = {
  90         "SET_HW_RSRC",
  91         "SET_SCHEDULING_CONFIG",
  92         "ADD_QUEUE",
  93         "REMOVE_QUEUE",
  94         "PERFORM_YIELD",
  95         "SET_GANG_PRIORITY_LEVEL",
  96         "SUSPEND",
  97         "RESUME",
  98         "RESET",
  99         "SET_LOG_BUFFER",
 100         "CHANGE_GANG_PRORITY",
 101         "QUERY_SCHEDULER_STATUS",
 102         "unused",
 103         "SET_DEBUG_VMID",
 104         "MISC",
 105         "UPDATE_ROOT_PAGE_TABLE",
 106         "AMD_LOG",
 107         "SET_SE_MODE",
 108         "SET_GANG_SUBMIT",
 109         "SET_HW_RSRC_1",
 110 };
 111
 112 static const char *mes_v12_0_misc_opcodes[] = {
 113         "WRITE_REG",
 114         "INV_GART",
 115         "QUERY_STATUS",
 116         "READ_REG",
 117         "WAIT_REG_MEM",
 118         "SET_SHADER_DEBUGGER",
 119         "NOTIFY_WORK_ON_UNMAPPED_QUEUE",
 120         "NOTIFY_TO_UNMAP_PROCESSES",
 121 };
 122
 123 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)
 124 {
 125         const char *op_str = NULL;
 126
 127         if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes))
 128                 op_str = mes_v12_0_opcodes[x_pkt->header.opcode];
 129
 130         return op_str;
 131 }
 132
 133 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
 134 {
 135         const char *op_str = NULL;
 136
 137         if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
 138             (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes)))
 139                 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode];
 140
 141         return op_str;
 142 }
 143
 144 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
 145                                             int pipe, void *pkt, int size,
 146                                             int api_status_off)
 147 {
 148         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 149         signed long timeout = 3000000; /* 3000 ms */
 150         struct amdgpu_device *adev = mes->adev;
 151         struct amdgpu_ring *ring = &mes->ring[pipe];
 152         spinlock_t *ring_lock = &mes->ring_lock[pipe];
 153         struct MES_API_STATUS *api_status;
 154         union MESAPI__MISC *x_pkt = pkt;
 155         const char *op_str, *misc_op_str;
 156         unsigned long flags;
 157         u64 status_gpu_addr;
 158         u32 seq, status_offset;
 159         u64 *status_ptr;
 160         signed long r;
 161         int ret;
 162
 163         if (x_pkt->header.opcode >= MES_SCH_API_MAX)
 164                 return -EINVAL;
 165
 166         if (amdgpu_emu_mode) {
 167                 timeout *= 100;
 168         } else if (amdgpu_sriov_vf(adev)) {
 169                 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
 170                 timeout = 15 * 600 * 1000;
 171         }
 172
 173         ret = amdgpu_device_wb_get(adev, &status_offset);
 174         if (ret)
 175                 return ret;
 176
 177         status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
 178         status_ptr = (u64 *)&adev->wb.wb[status_offset];
 179         *status_ptr = 0;
 180
 181         spin_lock_irqsave(ring_lock, flags);
 182         r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
 183         if (r)
 184                 goto error_unlock_free;
 185
 186         seq = ++ring->fence_drv.sync_seq;
 187         r = amdgpu_fence_wait_polling(ring,
 188                                       seq - ring->fence_drv.num_fences_mask,
 189                                       timeout);
 190         if (r < 1)
 191                 goto error_undo;
 192
 193         api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
 194         api_status->api_completion_fence_addr = status_gpu_addr;
 195         api_status->api_completion_fence_value = 1;
 196
 197         amdgpu_ring_write_multiple(ring, pkt, size / 4);
 198
 199         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 200         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 201         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 202         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 203         mes_status_pkt.api_status.api_completion_fence_addr =
 204                 ring->fence_drv.gpu_addr;
 205         mes_status_pkt.api_status.api_completion_fence_value = seq;
 206
 207         amdgpu_ring_write_multiple(ring, &mes_status_pkt,
 208                                    sizeof(mes_status_pkt) / 4);
 209
 210         amdgpu_ring_commit(ring);
 211         spin_unlock_irqrestore(ring_lock, flags);
 212
 213         op_str = mes_v12_0_get_op_string(x_pkt);
 214         misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);
 215
 216         if (misc_op_str)
 217                 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n",
 218                         pipe, op_str, misc_op_str);
 219         else if (op_str)
 220                 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n",
 221                         pipe, op_str);
 222         else
 223                 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n",
 224                         pipe, x_pkt->header.opcode);
 225
 226         r = amdgpu_fence_wait_polling(ring, seq, timeout);
 227         if (r < 1 || !*status_ptr) {
 228
 229                 if (misc_op_str)
 230                         dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n",
 231                                 pipe, op_str, misc_op_str);
 232                 else if (op_str)
 233                         dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n",
 234                                 pipe, op_str);
 235                 else
 236                         dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n",
 237                                 pipe, x_pkt->header.opcode);
 238
 239                 while (halt_if_hws_hang)
 240                         schedule();
 241
 242                 r = -ETIMEDOUT;
 243                 goto error_wb_free;
 244         }
 245
 246         amdgpu_device_wb_free(adev, status_offset);
 247         return 0;
 248
 249 error_undo:
 250         dev_err(adev->dev, "MES ring buffer is full.\n");
 251         amdgpu_ring_undo(ring);
 252
 253 error_unlock_free:
 254         spin_unlock_irqrestore(ring_lock, flags);
 255
 256 error_wb_free:
 257         amdgpu_device_wb_free(adev, status_offset);
 258         return r;
 259 }
 260
 261 static int convert_to_mes_queue_type(int queue_type)
 262 {
 263         if (queue_type == AMDGPU_RING_TYPE_GFX)
 264                 return MES_QUEUE_TYPE_GFX;
 265         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 266                 return MES_QUEUE_TYPE_COMPUTE;
 267         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 268                 return MES_QUEUE_TYPE_SDMA;
 269         else if (queue_type == AMDGPU_RING_TYPE_MES)
 270                 return MES_QUEUE_TYPE_SCHQ;
 271         else
 272                 BUG();
 273         return -1;
 274 }
 275
 276 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes,
 277                                   struct mes_add_queue_input *input)
 278 {
 279         struct amdgpu_device *adev = mes->adev;
 280         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 281         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
 282         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 283
 284         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 285
 286         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 287         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 288         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 289
 290         mes_add_queue_pkt.process_id = input->process_id;
 291         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 292         mes_add_queue_pkt.process_va_start = input->process_va_start;
 293         mes_add_queue_pkt.process_va_end = input->process_va_end;
 294         mes_add_queue_pkt.process_quantum = input->process_quantum;
 295         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 296         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 297         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 298         mes_add_queue_pkt.inprocess_gang_priority =
 299                 input->inprocess_gang_priority;
 300         mes_add_queue_pkt.gang_global_priority_level =
 301                 input->gang_global_priority_level;
 302         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 303         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 304
 305         mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
 306
 307         mes_add_queue_pkt.queue_type =
 308                 convert_to_mes_queue_type(input->queue_type);
 309         mes_add_queue_pkt.paging = input->paging;
 310         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 311         mes_add_queue_pkt.gws_base = input->gws_base;
 312         mes_add_queue_pkt.gws_size = input->gws_size;
 313         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 314         mes_add_queue_pkt.tma_addr = input->tma_addr;
 315         mes_add_queue_pkt.trap_en = input->trap_en;
 316         mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
 317         mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 318
 319         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 320         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 321         mes_add_queue_pkt.gds_size = input->queue_size;
 322
 323         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 324         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 325         mes_add_queue_pkt.gds_size = input->queue_size;
 326
 327         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 328                         AMDGPU_MES_SCHED_PIPE,
 329                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 330                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 331 }
 332
 333 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,
 334                                      struct mes_remove_queue_input *input)
 335 {
 336         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 337
 338         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 339
 340         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 341         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 342         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 343
 344         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 345         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 346
 347         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 348                         AMDGPU_MES_SCHED_PIPE,
 349                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 350                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 351 }
 352
 353 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,
 354                                       struct mes_map_legacy_queue_input *input)
 355 {
 356         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 357         int pipe;
 358
 359         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 360
 361         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 362         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 363         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 364
 365         mes_add_queue_pkt.pipe_id = input->pipe_id;
 366         mes_add_queue_pkt.queue_id = input->queue_id;
 367         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 368         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 369         mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 370         mes_add_queue_pkt.queue_type =
 371                 convert_to_mes_queue_type(input->queue_type);
 372         mes_add_queue_pkt.map_legacy_kq = 1;
 373
 374         if (mes->adev->enable_uni_mes)
 375                 pipe = AMDGPU_MES_KIQ_PIPE;
 376         else
 377                 pipe = AMDGPU_MES_SCHED_PIPE;
 378
 379         return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
 380                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 381                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 382 }
 383
 384 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 385                         struct mes_unmap_legacy_queue_input *input)
 386 {
 387         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 388         int pipe;
 389
 390         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 391
 392         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 393         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 394         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 395
 396         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 397         mes_remove_queue_pkt.gang_context_addr = 0;
 398
 399         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 400         mes_remove_queue_pkt.queue_id = input->queue_id;
 401
 402         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 403                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 404                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 405                 mes_remove_queue_pkt.tf_data =
 406                         lower_32_bits(input->trail_fence_data);
 407         } else {
 408                 mes_remove_queue_pkt.unmap_legacy_queue = 1;
 409                 mes_remove_queue_pkt.queue_type =
 410                         convert_to_mes_queue_type(input->queue_type);
 411         }
 412
 413         if (mes->adev->enable_uni_mes)
 414                 pipe = AMDGPU_MES_KIQ_PIPE;
 415         else
 416                 pipe = AMDGPU_MES_SCHED_PIPE;
 417
 418         return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
 419                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 420                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 421 }
 422
 423 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes,
 424                                   struct mes_suspend_gang_input *input)
 425 {
 426         return 0;
 427 }
 428
 429 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes,
 430                                  struct mes_resume_gang_input *input)
 431 {
 432         return 0;
 433 }
 434
 435 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe)
 436 {
 437         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 438
 439         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 440
 441         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 442         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 443         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 444
 445         return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
 446                         &mes_status_pkt, sizeof(mes_status_pkt),
 447                         offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
 448 }
 449
 450 static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
 451                              struct mes_misc_op_input *input)
 452 {
 453         union MESAPI__MISC misc_pkt;
 454         int pipe;
 455
 456         memset(&misc_pkt, 0, sizeof(misc_pkt));
 457
 458         misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
 459         misc_pkt.header.opcode = MES_SCH_API_MISC;
 460         misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 461
 462         switch (input->op) {
 463         case MES_MISC_OP_READ_REG:
 464                 misc_pkt.opcode = MESAPI_MISC__READ_REG;
 465                 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
 466                 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
 467                 break;
 468         case MES_MISC_OP_WRITE_REG:
 469                 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
 470                 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
 471                 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
 472                 break;
 473         case MES_MISC_OP_WRM_REG_WAIT:
 474                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 475                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
 476                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 477                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 478                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 479                 misc_pkt.wait_reg_mem.reg_offset2 = 0;
 480                 break;
 481         case MES_MISC_OP_WRM_REG_WR_WAIT:
 482                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 483                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
 484                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 485                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 486                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 487                 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
 488                 break;
 489         case MES_MISC_OP_SET_SHADER_DEBUGGER:
 490                 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
 491                 misc_pkt.set_shader_debugger.process_context_addr =
 492                                 input->set_shader_debugger.process_context_addr;
 493                 misc_pkt.set_shader_debugger.flags.u32all =
 494                                 input->set_shader_debugger.flags.u32all;
 495                 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
 496                                 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
 497                 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
 498                                 input->set_shader_debugger.tcp_watch_cntl,
 499                                 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
 500                 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
 501                 break;
 502         default:
 503                 DRM_ERROR("unsupported misc op (%d) \n", input->op);
 504                 return -EINVAL;
 505         }
 506
 507         if (mes->adev->enable_uni_mes)
 508                 pipe = AMDGPU_MES_KIQ_PIPE;
 509         else
 510                 pipe = AMDGPU_MES_SCHED_PIPE;
 511
 512         return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
 513                         &misc_pkt, sizeof(misc_pkt),
 514                         offsetof(union MESAPI__MISC, api_status));
 515 }
 516
 517 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
 518 {
 519         union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
 520
 521         memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
 522
 523         mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
 524         mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
 525         mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 526         mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;
 527
 528         return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
 529                         &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
 530                         offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
 531 }
 532
 533 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
 534 {
 535         int i;
 536         struct amdgpu_device *adev = mes->adev;
 537         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 538
 539         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 540
 541         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 542         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 543         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 544
 545         if (pipe == AMDGPU_MES_SCHED_PIPE) {
 546                 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 547                 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 548                 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 549                 mes_set_hw_res_pkt.paging_vmid = 0;
 550
 551                 for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 552                         mes_set_hw_res_pkt.compute_hqd_mask[i] =
 553                                 mes->compute_hqd_mask[i];
 554
 555                 for (i = 0; i < MAX_GFX_PIPES; i++)
 556                         mes_set_hw_res_pkt.gfx_hqd_mask[i] =
 557                                 mes->gfx_hqd_mask[i];
 558
 559                 for (i = 0; i < MAX_SDMA_PIPES; i++)
 560                         mes_set_hw_res_pkt.sdma_hqd_mask[i] =
 561                                 mes->sdma_hqd_mask[i];
 562
 563                 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 564                         mes_set_hw_res_pkt.aggregated_doorbells[i] =
 565                                 mes->aggregated_doorbells[i];
 566         }
 567
 568         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr =
 569                 mes->sch_ctx_gpu_addr[pipe];
 570         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 571                 mes->query_status_fence_gpu_addr[pipe];
 572
 573         for (i = 0; i < 5; i++) {
 574                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 575                 mes_set_hw_res_pkt.mmhub_base[i] =
 576                                 adev->reg_offset[MMHUB_HWIP][0][i];
 577                 mes_set_hw_res_pkt.osssys_base[i] =
 578                 adev->reg_offset[OSSSYS_HWIP][0][i];
 579         }
 580
 581         mes_set_hw_res_pkt.disable_reset = 1;
 582         mes_set_hw_res_pkt.disable_mes_log = 1;
 583         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 584         mes_set_hw_res_pkt.enable_reg_active_poll = 1;
 585
 586         /*
 587          * Keep oversubscribe timer for sdma . When we have unmapped doorbell
 588          * handling support, other queue will not use the oversubscribe timer.
 589          * handling  mode - 0: disabled; 1: basic version; 2: basic+ version
 590          */
 591         mes_set_hw_res_pkt.oversubscription_timer = 50;
 592         mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
 593
 594         if (amdgpu_mes_log_enable) {
 595                 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
 596                 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;
 597         }
 598
 599         return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
 600                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 601                         offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
 602 }
 603
 604 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
 605 {
 606         struct amdgpu_device *adev = mes->adev;
 607         uint32_t data;
 608
 609         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
 610         data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
 611                   CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
 612                   CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
 613         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
 614                 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
 615         data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
 616         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
 617
 618         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
 619         data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
 620                   CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
 621                   CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
 622         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
 623                 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
 624         data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
 625         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
 626
 627         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
 628         data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
 629                   CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
 630                   CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
 631         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
 632                 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
 633         data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
 634         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
 635
 636         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
 637         data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
 638                   CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
 639                   CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
 640         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
 641                 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
 642         data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
 643         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
 644
 645         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
 646         data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
 647                   CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
 648                   CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
 649         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
 650                 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
 651         data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
 652         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
 653
 654         data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
 655         WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
 656 }
 657
 658
 659 static void mes_v12_0_enable_unmapped_doorbell_handling(
 660                 struct amdgpu_mes *mes, bool enable)
 661 {
 662         struct amdgpu_device *adev = mes->adev;
 663         uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);
 664
 665         /*
 666          * The default PROC_LSB settng is 0xc which means doorbell
 667          * addr[16:12] gives the doorbell page number. For kfd, each
 668          * process will use 2 pages of doorbell, we need to change the
 669          * setting to 0xd
 670          */
 671         data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK;
 672         data |= 0xd <<  CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT;
 673
 674         data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;
 675
 676         WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data);
 677 }
 678
 679 static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
 680         .add_hw_queue = mes_v12_0_add_hw_queue,
 681         .remove_hw_queue = mes_v12_0_remove_hw_queue,
 682         .map_legacy_queue = mes_v12_0_map_legacy_queue,
 683         .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue,
 684         .suspend_gang = mes_v12_0_suspend_gang,
 685         .resume_gang = mes_v12_0_resume_gang,
 686         .misc_op = mes_v12_0_misc_op,
 687 };
 688
 689 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 690                                            enum admgpu_mes_pipe pipe)
 691 {
 692         int r;
 693         const struct mes_firmware_header_v1_0 *mes_hdr;
 694         const __le32 *fw_data;
 695         unsigned fw_size;
 696
 697         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 698                 adev->mes.fw[pipe]->data;
 699
 700         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 701                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 702         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 703
 704         r = amdgpu_bo_create_reserved(adev, fw_size,
 705                                       PAGE_SIZE,
 706                                       AMDGPU_GEM_DOMAIN_VRAM,
 707                                       &adev->mes.ucode_fw_obj[pipe],
 708                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 709                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 710         if (r) {
 711                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 712                 return r;
 713         }
 714
 715         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 716
 717         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 718         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 719
 720         return 0;
 721 }
 722
 723 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 724                                                 enum admgpu_mes_pipe pipe)
 725 {
 726         int r;
 727         const struct mes_firmware_header_v1_0 *mes_hdr;
 728         const __le32 *fw_data;
 729         unsigned fw_size;
 730
 731         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 732                 adev->mes.fw[pipe]->data;
 733
 734         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 735                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 736         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 737
 738         r = amdgpu_bo_create_reserved(adev, fw_size,
 739                                       64 * 1024,
 740                                       AMDGPU_GEM_DOMAIN_VRAM,
 741                                       &adev->mes.data_fw_obj[pipe],
 742                                       &adev->mes.data_fw_gpu_addr[pipe],
 743                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 744         if (r) {
 745                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 746                 return r;
 747         }
 748
 749         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 750
 751         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 752         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 753
 754         return 0;
 755 }
 756
 757 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,
 758                                          enum admgpu_mes_pipe pipe)
 759 {
 760         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 761                               &adev->mes.data_fw_gpu_addr[pipe],
 762                               (void **)&adev->mes.data_fw_ptr[pipe]);
 763
 764         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 765                               &adev->mes.ucode_fw_gpu_addr[pipe],
 766                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 767 }
 768
 769 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
 770 {
 771         uint64_t ucode_addr;
 772         uint32_t pipe, data = 0;
 773
 774         if (enable) {
 775                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 776                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 777                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
 778                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 779
 780                 mutex_lock(&adev->srbm_mutex);
 781                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 782                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 783
 784                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 785                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 786                                      lower_32_bits(ucode_addr));
 787                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 788                                      upper_32_bits(ucode_addr));
 789                 }
 790                 soc21_grbm_select(adev, 0, 0, 0, 0);
 791                 mutex_unlock(&adev->srbm_mutex);
 792
 793                 /* unhalt MES and activate pipe0 */
 794                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 795                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
 796                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 797
 798                 if (amdgpu_emu_mode)
 799                         msleep(100);
 800                 else if (adev->enable_uni_mes)
 801                         udelay(500);
 802                 else
 803                         udelay(50);
 804         } else {
 805                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 806                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 807                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 808                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 809                                      MES_INVALIDATE_ICACHE, 1);
 810                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 811                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
 812                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 813                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 814         }
 815 }
 816
 817 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)
 818 {
 819         uint64_t ucode_addr;
 820         int pipe;
 821
 822         mes_v12_0_enable(adev, false);
 823
 824         mutex_lock(&adev->srbm_mutex);
 825         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 826                 /* me=3, queue=0 */
 827                 soc21_grbm_select(adev, 3, pipe, 0, 0);
 828
 829                 /* set ucode start address */
 830                 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 831                 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 832                                 lower_32_bits(ucode_addr));
 833                 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 834                                 upper_32_bits(ucode_addr));
 835
 836                 soc21_grbm_select(adev, 0, 0, 0, 0);
 837         }
 838         mutex_unlock(&adev->srbm_mutex);
 839 }
 840
 841 /* This function is for backdoor MES firmware */
 842 static int mes_v12_0_load_microcode(struct amdgpu_device *adev,
 843                                     enum admgpu_mes_pipe pipe, bool prime_icache)
 844 {
 845         int r;
 846         uint32_t data;
 847
 848         mes_v12_0_enable(adev, false);
 849
 850         if (!adev->mes.fw[pipe])
 851                 return -EINVAL;
 852
 853         r = mes_v12_0_allocate_ucode_buffer(adev, pipe);
 854         if (r)
 855                 return r;
 856
 857         r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe);
 858         if (r) {
 859                 mes_v12_0_free_ucode_buffers(adev, pipe);
 860                 return r;
 861         }
 862
 863         mutex_lock(&adev->srbm_mutex);
 864         /* me=3, pipe=0, queue=0 */
 865         soc21_grbm_select(adev, 3, pipe, 0, 0);
 866
 867         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 868
 869         /* set ucode fimrware address */
 870         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 871                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 872         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 873                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 874
 875         /* set ucode instruction cache boundary to 2M-1 */
 876         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 877
 878         /* set ucode data firmware address */
 879         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 880                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 881         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 882                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 883
 884         /* Set data cache boundary CP_MES_MDBOUND_LO */
 885         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
 886
 887         if (prime_icache) {
 888                 /* invalidate ICACHE */
 889                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 890                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 891                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 892                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 893
 894                 /* prime the ICACHE. */
 895                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 896                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 897                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 898         }
 899
 900         soc21_grbm_select(adev, 0, 0, 0, 0);
 901         mutex_unlock(&adev->srbm_mutex);
 902
 903         return 0;
 904 }
 905
 906 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,
 907                                       enum admgpu_mes_pipe pipe)
 908 {
 909         int r;
 910         u32 *eop;
 911
 912         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 913                               AMDGPU_GEM_DOMAIN_GTT,
 914                               &adev->mes.eop_gpu_obj[pipe],
 915                               &adev->mes.eop_gpu_addr[pipe],
 916                               (void **)&eop);
 917         if (r) {
 918                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 919                 return r;
 920         }
 921
 922         memset(eop, 0,
 923                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 924
 925         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 926         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 927
 928         return 0;
 929 }
 930
 931 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)
 932 {
 933         struct v12_compute_mqd *mqd = ring->mqd_ptr;
 934         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 935         uint32_t tmp;
 936
 937         mqd->header = 0xC0310800;
 938         mqd->compute_pipelinestat_enable = 0x00000001;
 939         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 940         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 941         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 942         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 943         mqd->compute_misc_reserved = 0x00000007;
 944
 945         eop_base_addr = ring->eop_gpu_addr >> 8;
 946
 947         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 948         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 949         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 950                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 951
 952         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 953         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 954         mqd->cp_hqd_eop_control = tmp;
 955
 956         /* disable the queue if it's active */
 957         ring->wptr = 0;
 958         mqd->cp_hqd_pq_rptr = 0;
 959         mqd->cp_hqd_pq_wptr_lo = 0;
 960         mqd->cp_hqd_pq_wptr_hi = 0;
 961
 962         /* set the pointer to the MQD */
 963         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 964         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 965
 966         /* set MQD vmid to 0 */
 967         tmp = regCP_MQD_CONTROL_DEFAULT;
 968         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 969         mqd->cp_mqd_control = tmp;
 970
 971         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 972         hqd_gpu_addr = ring->gpu_addr >> 8;
 973         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 974         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 975
 976         /* set the wb address whether it's enabled or not */
 977         wb_gpu_addr = ring->rptr_gpu_addr;
 978         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 979         mqd->cp_hqd_pq_rptr_report_addr_hi =
 980                 upper_32_bits(wb_gpu_addr) & 0xffff;
 981
 982         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 983         wb_gpu_addr = ring->wptr_gpu_addr;
 984         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 985         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 986
 987         /* set up the HQD, this is similar to CP_RB0_CNTL */
 988         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 989         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 990                             (order_base_2(ring->ring_size / 4) - 1));
 991         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 992                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 993         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 994         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 995         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 996         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 997         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 998         mqd->cp_hqd_pq_control = tmp;
 999
1000         /* enable doorbell */
1001         tmp = 0;
1002         if (ring->use_doorbell) {
1003                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1004                                     DOORBELL_OFFSET, ring->doorbell_index);
1005                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1006                                     DOORBELL_EN, 1);
1007                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1008                                     DOORBELL_SOURCE, 0);
1009                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1010                                     DOORBELL_HIT, 0);
1011         } else {
1012                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1013                                     DOORBELL_EN, 0);
1014         }
1015         mqd->cp_hqd_pq_doorbell_control = tmp;
1016
1017         mqd->cp_hqd_vmid = 0;
1018         /* activate the queue */
1019         mqd->cp_hqd_active = 1;
1020
1021         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
1022         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
1023                             PRELOAD_SIZE, 0x55);
1024         mqd->cp_hqd_persistent_state = tmp;
1025
1026         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
1027         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
1028         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
1029
1030         /*
1031          * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped
1032          * doorbell handling. This is a reserved CP internal register can
1033          * not be accesss by others
1034          */
1035         mqd->reserved_184 = BIT(15);
1036
1037         return 0;
1038 }
1039
1040 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring)
1041 {
1042         struct v12_compute_mqd *mqd = ring->mqd_ptr;
1043         struct amdgpu_device *adev = ring->adev;
1044         uint32_t data = 0;
1045
1046         mutex_lock(&adev->srbm_mutex);
1047         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1048
1049         /* set CP_HQD_VMID.VMID = 0. */
1050         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
1051         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1052         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
1053
1054         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1055         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1056         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1057                              DOORBELL_EN, 0);
1058         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1059
1060         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1061         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1062         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1063
1064         /* set CP_MQD_CONTROL.VMID=0 */
1065         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
1066         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1067         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
1068
1069         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1070         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1071         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1072
1073         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1074         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
1075                      mqd->cp_hqd_pq_rptr_report_addr_lo);
1076         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1077                      mqd->cp_hqd_pq_rptr_report_addr_hi);
1078
1079         /* set CP_HQD_PQ_CONTROL */
1080         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1081
1082         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1083         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
1084                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
1085         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1086                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
1087
1088         /* set CP_HQD_PQ_DOORBELL_CONTROL */
1089         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
1090                      mqd->cp_hqd_pq_doorbell_control);
1091
1092         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1093         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1094
1095         /* set CP_HQD_ACTIVE.ACTIVE=1 */
1096         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1097
1098         soc21_grbm_select(adev, 0, 0, 0, 0);
1099         mutex_unlock(&adev->srbm_mutex);
1100 }
1101
1102 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)
1103 {
1104         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1105         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1106         int r;
1107
1108         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1109                 return -EINVAL;
1110
1111         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1112         if (r) {
1113                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1114                 return r;
1115         }
1116
1117         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
1118
1119         r = amdgpu_ring_test_ring(kiq_ring);
1120         if (r) {
1121                 DRM_ERROR("kfq enable failed\n");
1122                 kiq_ring->sched.ready = false;
1123         }
1124         return r;
1125 }
1126
1127 static int mes_v12_0_queue_init(struct amdgpu_device *adev,
1128                                 enum admgpu_mes_pipe pipe)
1129 {
1130         struct amdgpu_ring *ring;
1131         int r;
1132
1133         if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1134                 ring = &adev->gfx.kiq[0].ring;
1135         else
1136                 ring = &adev->mes.ring[pipe];
1137
1138         if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) &&
1139             (amdgpu_in_reset(adev) || adev->in_suspend)) {
1140                 *(ring->wptr_cpu_addr) = 0;
1141                 *(ring->rptr_cpu_addr) = 0;
1142                 amdgpu_ring_clear_ring(ring);
1143         }
1144
1145         r = mes_v12_0_mqd_init(ring);
1146         if (r)
1147                 return r;
1148
1149         if (pipe == AMDGPU_MES_SCHED_PIPE) {
1150                 if (adev->enable_uni_mes)
1151                         r = amdgpu_mes_map_legacy_queue(adev, ring);
1152                 else
1153                         r = mes_v12_0_kiq_enable_queue(adev);
1154                 if (r)
1155                         return r;
1156         } else {
1157                 mes_v12_0_queue_init_register(ring);
1158         }
1159
1160         /* get MES scheduler/KIQ versions */
1161         mutex_lock(&adev->srbm_mutex);
1162         soc21_grbm_select(adev, 3, pipe, 0, 0);
1163
1164         if (pipe == AMDGPU_MES_SCHED_PIPE)
1165                 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1166         else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1167                 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1168
1169         soc21_grbm_select(adev, 0, 0, 0, 0);
1170         mutex_unlock(&adev->srbm_mutex);
1171
1172         return 0;
1173 }
1174
1175 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe)
1176 {
1177         struct amdgpu_ring *ring;
1178
1179         ring = &adev->mes.ring[pipe];
1180
1181         ring->funcs = &mes_v12_0_ring_funcs;
1182
1183         ring->me = 3;
1184         ring->pipe = pipe;
1185         ring->queue = 0;
1186
1187         ring->ring_obj = NULL;
1188         ring->use_doorbell = true;
1189         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe];
1190         ring->no_scheduler = true;
1191         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1192
1193         if (pipe == AMDGPU_MES_SCHED_PIPE)
1194                 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1195         else
1196                 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1197
1198         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1199                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1200 }
1201
1202 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)
1203 {
1204         struct amdgpu_ring *ring;
1205
1206         spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1207
1208         ring = &adev->gfx.kiq[0].ring;
1209
1210         ring->me = 3;
1211         ring->pipe = 1;
1212         ring->queue = 0;
1213
1214         ring->adev = NULL;
1215         ring->ring_obj = NULL;
1216         ring->use_doorbell = true;
1217         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1218         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1219         ring->no_scheduler = true;
1220         sprintf(ring->name, "mes_kiq_%d.%d.%d",
1221                 ring->me, ring->pipe, ring->queue);
1222
1223         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1224                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1225 }
1226
1227 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,
1228                                  enum admgpu_mes_pipe pipe)
1229 {
1230         int r, mqd_size = sizeof(struct v12_compute_mqd);
1231         struct amdgpu_ring *ring;
1232
1233         if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1234                 ring = &adev->gfx.kiq[0].ring;
1235         else
1236                 ring = &adev->mes.ring[pipe];
1237
1238         if (ring->mqd_obj)
1239                 return 0;
1240
1241         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1242                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1243                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
1244         if (r) {
1245                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1246                 return r;
1247         }
1248
1249         memset(ring->mqd_ptr, 0, mqd_size);
1250
1251         /* prepare MQD backup */
1252         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1253         if (!adev->mes.mqd_backup[pipe])
1254                 dev_warn(adev->dev,
1255                          "no memory to create MQD backup for ring %s\n",
1256                          ring->name);
1257
1258         return 0;
1259 }
1260
1261 static int mes_v12_0_sw_init(void *handle)
1262 {
1263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1264         int pipe, r;
1265
1266         adev->mes.funcs = &mes_v12_0_funcs;
1267         adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
1268         adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
1269
1270         adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
1271
1272         r = amdgpu_mes_init(adev);
1273         if (r)
1274                 return r;
1275
1276         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1277                 r = mes_v12_0_allocate_eop_buf(adev, pipe);
1278                 if (r)
1279                         return r;
1280
1281                 r = mes_v12_0_mqd_sw_init(adev, pipe);
1282                 if (r)
1283                         return r;
1284
1285                 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1286                         r = mes_v12_0_kiq_ring_init(adev);
1287                 else
1288                         r = mes_v12_0_ring_init(adev, pipe);
1289                 if (r)
1290                         return r;
1291         }
1292
1293         return 0;
1294 }
1295
1296 static int mes_v12_0_sw_fini(void *handle)
1297 {
1298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299         int pipe;
1300
1301         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1302                 kfree(adev->mes.mqd_backup[pipe]);
1303
1304                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1305                                       &adev->mes.eop_gpu_addr[pipe],
1306                                       NULL);
1307                 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1308
1309                 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {
1310                         amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj,
1311                                               &adev->mes.ring[pipe].mqd_gpu_addr,
1312                                               &adev->mes.ring[pipe].mqd_ptr);
1313                         amdgpu_ring_fini(&adev->mes.ring[pipe]);
1314                 }
1315         }
1316
1317         if (!adev->enable_uni_mes) {
1318                 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1319                                       &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1320                                       &adev->gfx.kiq[0].ring.mqd_ptr);
1321                 amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1322         }
1323
1324         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1325                 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1326                 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1327         }
1328
1329         amdgpu_mes_fini(adev);
1330         return 0;
1331 }
1332
1333 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)
1334 {
1335         uint32_t data;
1336         int i;
1337
1338         mutex_lock(&adev->srbm_mutex);
1339         soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
1340
1341         /* disable the queue if it's active */
1342         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1343                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1344                 for (i = 0; i < adev->usec_timeout; i++) {
1345                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1346                                 break;
1347                         udelay(1);
1348                 }
1349         }
1350         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1351         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1352                                 DOORBELL_EN, 0);
1353         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1354                                 DOORBELL_HIT, 1);
1355         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1356
1357         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1358
1359         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1360         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1361         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1362
1363         soc21_grbm_select(adev, 0, 0, 0, 0);
1364         mutex_unlock(&adev->srbm_mutex);
1365
1366         adev->mes.ring[0].sched.ready = false;
1367 }
1368
1369 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)
1370 {
1371         uint32_t tmp;
1372         struct amdgpu_device *adev = ring->adev;
1373
1374         /* tell RLC which is KIQ queue */
1375         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1376         tmp &= 0xffffff00;
1377         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1378         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1379         tmp |= 0x80;
1380         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1381 }
1382
1383 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
1384 {
1385         int r = 0;
1386
1387         if (adev->enable_uni_mes)
1388                 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]);
1389         else
1390                 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring);
1391
1392         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1393
1394                 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1395                 if (r) {
1396                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1397                         return r;
1398                 }
1399
1400                 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1401                 if (r) {
1402                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1403                         return r;
1404                 }
1405
1406                 mes_v12_0_set_ucode_start_addr(adev);
1407
1408         } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1409                 mes_v12_0_set_ucode_start_addr(adev);
1410
1411         mes_v12_0_enable(adev, true);
1412
1413         r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1414         if (r)
1415                 goto failure;
1416
1417         if (adev->enable_uni_mes) {
1418                 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1419                 if (r)
1420                         goto failure;
1421
1422                 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1423         }
1424
1425         r = mes_v12_0_hw_init(adev);
1426         if (r)
1427                 goto failure;
1428
1429         return r;
1430
1431 failure:
1432         mes_v12_0_hw_fini(adev);
1433         return r;
1434 }
1435
1436 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)
1437 {
1438         if (adev->mes.ring[0].sched.ready) {
1439                 if (adev->enable_uni_mes)
1440                         amdgpu_mes_unmap_legacy_queue(adev,
1441                                       &adev->mes.ring[AMDGPU_MES_SCHED_PIPE],
1442                                       RESET_QUEUES, 0, 0);
1443                 else
1444                         mes_v12_0_kiq_dequeue_sched(adev);
1445
1446                 adev->mes.ring[0].sched.ready = false;
1447         }
1448
1449         mes_v12_0_enable(adev, false);
1450
1451         return 0;
1452 }
1453
1454 static int mes_v12_0_hw_init(void *handle)
1455 {
1456         int r;
1457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1458
1459         if (adev->mes.ring[0].sched.ready)
1460                 goto out;
1461
1462         if (!adev->enable_mes_kiq) {
1463                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1464                         r = mes_v12_0_load_microcode(adev,
1465                                              AMDGPU_MES_SCHED_PIPE, true);
1466                         if (r) {
1467                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1468                                 return r;
1469                         }
1470
1471                         mes_v12_0_set_ucode_start_addr(adev);
1472
1473                 } else if (adev->firmware.load_type ==
1474                            AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1475
1476                         mes_v12_0_set_ucode_start_addr(adev);
1477                 }
1478
1479                 mes_v12_0_enable(adev, true);
1480         }
1481
1482         /* Enable the MES to handle doorbell ring on unmapped queue */
1483         mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true);
1484
1485         r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1486         if (r)
1487                 goto failure;
1488
1489         r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1490         if (r)
1491                 goto failure;
1492
1493         if (adev->enable_uni_mes)
1494                 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1495
1496         mes_v12_0_init_aggregated_doorbell(&adev->mes);
1497
1498         r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1499         if (r) {
1500                 DRM_ERROR("MES is busy\n");
1501                 goto failure;
1502         }
1503
1504 out:
1505         /*
1506          * Disable KIQ ring usage from the driver once MES is enabled.
1507          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1508          * with MES enabled.
1509          */
1510         adev->gfx.kiq[0].ring.sched.ready = false;
1511         adev->mes.ring[0].sched.ready = true;
1512
1513         return 0;
1514
1515 failure:
1516         mes_v12_0_hw_fini(adev);
1517         return r;
1518 }
1519
1520 static int mes_v12_0_hw_fini(void *handle)
1521 {
1522         return 0;
1523 }
1524
1525 static int mes_v12_0_suspend(void *handle)
1526 {
1527         int r;
1528         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1529
1530         r = amdgpu_mes_suspend(adev);
1531         if (r)
1532                 return r;
1533
1534         return mes_v12_0_hw_fini(adev);
1535 }
1536
1537 static int mes_v12_0_resume(void *handle)
1538 {
1539         int r;
1540         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1541
1542         r = mes_v12_0_hw_init(adev);
1543         if (r)
1544                 return r;
1545
1546         return amdgpu_mes_resume(adev);
1547 }
1548
1549 static int mes_v12_0_early_init(void *handle)
1550 {
1551         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1552         int pipe, r;
1553
1554         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1555                 r = amdgpu_mes_init_microcode(adev, pipe);
1556                 if (r)
1557                         return r;
1558         }
1559
1560         return 0;
1561 }
1562
1563 static int mes_v12_0_late_init(void *handle)
1564 {
1565         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1566
1567         /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1568         if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend)
1569                 amdgpu_mes_self_test(adev);
1570
1571         return 0;
1572 }
1573
1574 static const struct amd_ip_funcs mes_v12_0_ip_funcs = {
1575         .name = "mes_v12_0",
1576         .early_init = mes_v12_0_early_init,
1577         .late_init = mes_v12_0_late_init,
1578         .sw_init = mes_v12_0_sw_init,
1579         .sw_fini = mes_v12_0_sw_fini,
1580         .hw_init = mes_v12_0_hw_init,
1581         .hw_fini = mes_v12_0_hw_fini,
1582         .suspend = mes_v12_0_suspend,
1583         .resume = mes_v12_0_resume,
1584 };
1585
1586 const struct amdgpu_ip_block_version mes_v12_0_ip_block = {
1587         .type = AMD_IP_BLOCK_TYPE_MES,
1588         .major = 12,
1589         .minor = 0,
1590         .rev = 0,
1591         .funcs = &mes_v12_0_ip_funcs,
1592 };