drivers/gpu/drm/msm/msm_mdss.c

   1 /*
   2  * SPDX-License-Identifier: GPL-2.0
   3  * Copyright (c) 2018, The Linux Foundation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/interconnect.h>
   9 #include <linux/irq.h>
  10 #include <linux/irqchip.h>
  11 #include <linux/irqdesc.h>
  12 #include <linux/irqchip/chained_irq.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/reset.h>
  15
  16 #include "msm_drv.h"
  17 #include "msm_kms.h"
  18
  19 /* for DPU_HW_* defines */
  20 #include "disp/dpu1/dpu_hw_catalog.h"
  21
  22 #define HW_REV                          0x0
  23 #define HW_INTR_STATUS                  0x0010
  24
  25 #define UBWC_DEC_HW_VERSION             0x58
  26 #define UBWC_STATIC                     0x144
  27 #define UBWC_CTRL_2                     0x150
  28 #define UBWC_PREDICTION_MODE            0x154
  29
  30 #define MIN_IB_BW       400000000UL /* Min ib vote 400MB */
  31
  32 struct msm_mdss {
  33         struct device *dev;
  34
  35         void __iomem *mmio;
  36         struct clk_bulk_data *clocks;
  37         size_t num_clocks;
  38         bool is_mdp5;
  39         struct {
  40                 unsigned long enabled_mask;
  41                 struct irq_domain *domain;
  42         } irq_controller;
  43         struct icc_path *path[2];
  44         u32 num_paths;
  45 };
  46
  47 static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
  48                                             struct msm_mdss *msm_mdss)
  49 {
  50         struct icc_path *path0 = of_icc_get(dev, "mdp0-mem");
  51         struct icc_path *path1 = of_icc_get(dev, "mdp1-mem");
  52
  53         if (IS_ERR_OR_NULL(path0))
  54                 return PTR_ERR_OR_ZERO(path0);
  55
  56         msm_mdss->path[0] = path0;
  57         msm_mdss->num_paths = 1;
  58
  59         if (!IS_ERR_OR_NULL(path1)) {
  60                 msm_mdss->path[1] = path1;
  61                 msm_mdss->num_paths++;
  62         }
  63
  64         return 0;
  65 }
  66
  67 static void msm_mdss_put_icc_path(void *data)
  68 {
  69         struct msm_mdss *msm_mdss = data;
  70         int i;
  71
  72         for (i = 0; i < msm_mdss->num_paths; i++)
  73                 icc_put(msm_mdss->path[i]);
  74 }
  75
  76 static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw)
  77 {
  78         int i;
  79
  80         for (i = 0; i < msm_mdss->num_paths; i++)
  81                 icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw));
  82 }
  83
  84 static void msm_mdss_irq(struct irq_desc *desc)
  85 {
  86         struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
  87         struct irq_chip *chip = irq_desc_get_chip(desc);
  88         u32 interrupts;
  89
  90         chained_irq_enter(chip, desc);
  91
  92         interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS);
  93
  94         while (interrupts) {
  95                 irq_hw_number_t hwirq = fls(interrupts) - 1;
  96                 int rc;
  97
  98                 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
  99                                                hwirq);
 100                 if (rc < 0) {
 101                         dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
 102                                   hwirq, rc);
 103                         break;
 104                 }
 105
 106                 interrupts &= ~(1 << hwirq);
 107         }
 108
 109         chained_irq_exit(chip, desc);
 110 }
 111
 112 static void msm_mdss_irq_mask(struct irq_data *irqd)
 113 {
 114         struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
 115
 116         /* memory barrier */
 117         smp_mb__before_atomic();
 118         clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
 119         /* memory barrier */
 120         smp_mb__after_atomic();
 121 }
 122
 123 static void msm_mdss_irq_unmask(struct irq_data *irqd)
 124 {
 125         struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
 126
 127         /* memory barrier */
 128         smp_mb__before_atomic();
 129         set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
 130         /* memory barrier */
 131         smp_mb__after_atomic();
 132 }
 133
 134 static struct irq_chip msm_mdss_irq_chip = {
 135         .name = "msm_mdss",
 136         .irq_mask = msm_mdss_irq_mask,
 137         .irq_unmask = msm_mdss_irq_unmask,
 138 };
 139
 140 static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key;
 141
 142 static int msm_mdss_irqdomain_map(struct irq_domain *domain,
 143                 unsigned int irq, irq_hw_number_t hwirq)
 144 {
 145         struct msm_mdss *msm_mdss = domain->host_data;
 146
 147         irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key);
 148         irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq);
 149
 150         return irq_set_chip_data(irq, msm_mdss);
 151 }
 152
 153 static const struct irq_domain_ops msm_mdss_irqdomain_ops = {
 154         .map = msm_mdss_irqdomain_map,
 155         .xlate = irq_domain_xlate_onecell,
 156 };
 157
 158 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
 159 {
 160         struct device *dev;
 161         struct irq_domain *domain;
 162
 163         dev = msm_mdss->dev;
 164
 165         domain = irq_domain_add_linear(dev->of_node, 32,
 166                         &msm_mdss_irqdomain_ops, msm_mdss);
 167         if (!domain) {
 168                 dev_err(dev, "failed to add irq_domain\n");
 169                 return -EINVAL;
 170         }
 171
 172         msm_mdss->irq_controller.enabled_mask = 0;
 173         msm_mdss->irq_controller.domain = domain;
 174
 175         return 0;
 176 }
 177
 178 #define UBWC_1_0 0x10000000
 179 #define UBWC_2_0 0x20000000
 180 #define UBWC_3_0 0x30000000
 181 #define UBWC_4_0 0x40000000
 182
 183 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss,
 184                                        u32 ubwc_static)
 185 {
 186         writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC);
 187 }
 188
 189 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss,
 190                                        unsigned int ubwc_version,
 191                                        u32 ubwc_swizzle,
 192                                        u32 highest_bank_bit,
 193                                        u32 macrotile_mode)
 194 {
 195         u32 value = (ubwc_swizzle & 0x1) |
 196                     (highest_bank_bit & 0x3) << 4 |
 197                     (macrotile_mode & 0x1) << 12;
 198
 199         if (ubwc_version == UBWC_3_0)
 200                 value |= BIT(10);
 201
 202         if (ubwc_version == UBWC_1_0)
 203                 value |= BIT(8);
 204
 205         writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
 206 }
 207
 208 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss,
 209                                        unsigned int ubwc_version,
 210                                        u32 ubwc_swizzle,
 211                                        u32 ubwc_static,
 212                                        u32 highest_bank_bit,
 213                                        u32 macrotile_mode)
 214 {
 215         u32 value = (ubwc_swizzle & 0x7) |
 216                     (ubwc_static & 0x1) << 3 |
 217                     (highest_bank_bit & 0x7) << 4 |
 218                     (macrotile_mode & 0x1) << 12;
 219
 220         writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
 221
 222         if (ubwc_version == UBWC_3_0) {
 223                 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
 224                 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
 225         } else {
 226                 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
 227                 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
 228         }
 229 }
 230
 231 static int msm_mdss_enable(struct msm_mdss *msm_mdss)
 232 {
 233         int ret;
 234         u32 hw_rev;
 235
 236         /*
 237          * Several components have AXI clocks that can only be turned on if
 238          * the interconnect is enabled (non-zero bandwidth). Let's make sure
 239          * that the interconnects are at least at a minimum amount.
 240          */
 241         msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW);
 242
 243         ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
 244         if (ret) {
 245                 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
 246                 return ret;
 247         }
 248
 249         /*
 250          * HW_REV requires MDSS_MDP_CLK, which is not enabled by the mdss on
 251          * mdp5 hardware. Skip reading it for now.
 252          */
 253         if (msm_mdss->is_mdp5)
 254                 return 0;
 255
 256         hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV);
 257         dev_dbg(msm_mdss->dev, "HW_REV: 0x%x\n", hw_rev);
 258         dev_dbg(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
 259                 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));
 260
 261         /*
 262          * ubwc config is part of the "mdss" region which is not accessible
 263          * from the rest of the driver. hardcode known configurations here
 264          *
 265          * Decoder version can be read from the UBWC_DEC_HW_VERSION reg,
 266          * UBWC_n and the rest of params comes from hw_catalog.
 267          * Unforunately this driver can not access hw catalog, so we have to
 268          * hardcode them here.
 269          */
 270         switch (hw_rev) {
 271         case DPU_HW_VER_500:
 272         case DPU_HW_VER_501:
 273                 msm_mdss_setup_ubwc_dec_30(msm_mdss, UBWC_3_0, 0, 2, 0);
 274                 break;
 275         case DPU_HW_VER_600:
 276                 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
 277                 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
 278                 break;
 279         case DPU_HW_VER_620:
 280                 /* UBWC_2_0 */
 281                 msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
 282                 break;
 283         case DPU_HW_VER_630:
 284                 /* UBWC_2_0 */
 285                 msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f);
 286                 break;
 287         case DPU_HW_VER_720:
 288                 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
 289                 break;
 290         }
 291
 292         return ret;
 293 }
 294
 295 static int msm_mdss_disable(struct msm_mdss *msm_mdss)
 296 {
 297         clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
 298         msm_mdss_icc_request_bw(msm_mdss, 0);
 299
 300         return 0;
 301 }
 302
 303 static void msm_mdss_destroy(struct msm_mdss *msm_mdss)
 304 {
 305         struct platform_device *pdev = to_platform_device(msm_mdss->dev);
 306         int irq;
 307
 308         pm_runtime_suspend(msm_mdss->dev);
 309         pm_runtime_disable(msm_mdss->dev);
 310         irq_domain_remove(msm_mdss->irq_controller.domain);
 311         msm_mdss->irq_controller.domain = NULL;
 312         irq = platform_get_irq(pdev, 0);
 313         irq_set_chained_handler_and_data(irq, NULL, NULL);
 314 }
 315
 316 static int msm_mdss_reset(struct device *dev)
 317 {
 318         struct reset_control *reset;
 319
 320         reset = reset_control_get_optional_exclusive(dev, NULL);
 321         if (!reset) {
 322                 /* Optional reset not specified */
 323                 return 0;
 324         } else if (IS_ERR(reset)) {
 325                 return dev_err_probe(dev, PTR_ERR(reset),
 326                                      "failed to acquire mdss reset\n");
 327         }
 328
 329         reset_control_assert(reset);
 330         /*
 331          * Tests indicate that reset has to be held for some period of time,
 332          * make it one frame in a typical system
 333          */
 334         msleep(20);
 335         reset_control_deassert(reset);
 336
 337         reset_control_put(reset);
 338
 339         return 0;
 340 }
 341
 342 /*
 343  * MDP5 MDSS uses at most three specified clocks.
 344  */
 345 #define MDP5_MDSS_NUM_CLOCKS 3
 346 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks)
 347 {
 348         struct clk_bulk_data *bulk;
 349         int num_clocks = 0;
 350         int ret;
 351
 352         if (!pdev)
 353                 return -EINVAL;
 354
 355         bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);
 356         if (!bulk)
 357                 return -ENOMEM;
 358
 359         bulk[num_clocks++].id = "iface";
 360         bulk[num_clocks++].id = "bus";
 361         bulk[num_clocks++].id = "vsync";
 362
 363         ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
 364         if (ret)
 365                 return ret;
 366
 367         *clocks = bulk;
 368
 369         return num_clocks;
 370 }
 371
 372 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
 373 {
 374         struct msm_mdss *msm_mdss;
 375         int ret;
 376         int irq;
 377
 378         ret = msm_mdss_reset(&pdev->dev);
 379         if (ret)
 380                 return ERR_PTR(ret);
 381
 382         msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
 383         if (!msm_mdss)
 384                 return ERR_PTR(-ENOMEM);
 385
 386         msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
 387         if (IS_ERR(msm_mdss->mmio))
 388                 return ERR_CAST(msm_mdss->mmio);
 389
 390         dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
 391
 392         ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
 393         if (ret)
 394                 return ERR_PTR(ret);
 395         ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss);
 396         if (ret)
 397                 return ERR_PTR(ret);
 398
 399         if (is_mdp5)
 400                 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
 401         else
 402                 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
 403         if (ret < 0) {
 404                 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);
 405                 return ERR_PTR(ret);
 406         }
 407         msm_mdss->num_clocks = ret;
 408         msm_mdss->is_mdp5 = is_mdp5;
 409
 410         msm_mdss->dev = &pdev->dev;
 411
 412         irq = platform_get_irq(pdev, 0);
 413         if (irq < 0)
 414                 return ERR_PTR(irq);
 415
 416         ret = _msm_mdss_irq_domain_add(msm_mdss);
 417         if (ret)
 418                 return ERR_PTR(ret);
 419
 420         irq_set_chained_handler_and_data(irq, msm_mdss_irq,
 421                                          msm_mdss);
 422
 423         pm_runtime_enable(&pdev->dev);
 424
 425         return msm_mdss;
 426 }
 427
 428 static int __maybe_unused mdss_runtime_suspend(struct device *dev)
 429 {
 430         struct msm_mdss *mdss = dev_get_drvdata(dev);
 431
 432         DBG("");
 433
 434         return msm_mdss_disable(mdss);
 435 }
 436
 437 static int __maybe_unused mdss_runtime_resume(struct device *dev)
 438 {
 439         struct msm_mdss *mdss = dev_get_drvdata(dev);
 440
 441         DBG("");
 442
 443         return msm_mdss_enable(mdss);
 444 }
 445
 446 static int __maybe_unused mdss_pm_suspend(struct device *dev)
 447 {
 448
 449         if (pm_runtime_suspended(dev))
 450                 return 0;
 451
 452         return mdss_runtime_suspend(dev);
 453 }
 454
 455 static int __maybe_unused mdss_pm_resume(struct device *dev)
 456 {
 457         if (pm_runtime_suspended(dev))
 458                 return 0;
 459
 460         return mdss_runtime_resume(dev);
 461 }
 462
 463 static const struct dev_pm_ops mdss_pm_ops = {
 464         SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume)
 465         SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL)
 466 };
 467
 468 static int mdss_probe(struct platform_device *pdev)
 469 {
 470         struct msm_mdss *mdss;
 471         bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");
 472         struct device *dev = &pdev->dev;
 473         int ret;
 474
 475         mdss = msm_mdss_init(pdev, is_mdp5);
 476         if (IS_ERR(mdss))
 477                 return PTR_ERR(mdss);
 478
 479         platform_set_drvdata(pdev, mdss);
 480
 481         /*
 482          * MDP5/DPU based devices don't have a flat hierarchy. There is a top
 483          * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
 484          * Populate the children devices, find the MDP5/DPU node, and then add
 485          * the interfaces to our components list.
 486          */
 487         ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
 488         if (ret) {
 489                 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
 490                 msm_mdss_destroy(mdss);
 491                 return ret;
 492         }
 493
 494         return 0;
 495 }
 496
 497 static int mdss_remove(struct platform_device *pdev)
 498 {
 499         struct msm_mdss *mdss = platform_get_drvdata(pdev);
 500
 501         of_platform_depopulate(&pdev->dev);
 502
 503         msm_mdss_destroy(mdss);
 504
 505         return 0;
 506 }
 507
 508 static const struct of_device_id mdss_dt_match[] = {
 509         { .compatible = "qcom,mdss" },
 510         { .compatible = "qcom,msm8998-mdss" },
 511         { .compatible = "qcom,qcm2290-mdss" },
 512         { .compatible = "qcom,sdm845-mdss" },
 513         { .compatible = "qcom,sc7180-mdss" },
 514         { .compatible = "qcom,sc7280-mdss" },
 515         { .compatible = "qcom,sc8180x-mdss" },
 516         { .compatible = "qcom,sm6115-mdss" },
 517         { .compatible = "qcom,sm8150-mdss" },
 518         { .compatible = "qcom,sm8250-mdss" },
 519         {}
 520 };
 521 MODULE_DEVICE_TABLE(of, mdss_dt_match);
 522
 523 static struct platform_driver mdss_platform_driver = {
 524         .probe      = mdss_probe,
 525         .remove     = mdss_remove,
 526         .driver     = {
 527                 .name   = "msm-mdss",
 528                 .of_match_table = mdss_dt_match,
 529                 .pm     = &mdss_pm_ops,
 530         },
 531 };
 532
 533 void __init msm_mdss_register(void)
 534 {
 535         platform_driver_register(&mdss_platform_driver);
 536 }
 537
 538 void __exit msm_mdss_unregister(void)
 539 {
 540         platform_driver_unregister(&mdss_platform_driver);
 541 }