drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string_helpers.h>
  27 #include <linux/uaccess.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_debugfs.h"
  33 #include "dm_helpers.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "resource.h"
  36 #include "dsc.h"
  37 #include "link_hwss.h"
  38 #include "dc/dc_dmub_srv.h"
  39 #include "link/protocols/link_dp_capability.h"
  40
  41 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
  42 #include "amdgpu_dm_psr.h"
  43 #endif
  44
  45 struct dmub_debugfs_trace_header {
  46         uint32_t entry_count;
  47         uint32_t reserved[3];
  48 };
  49
  50 struct dmub_debugfs_trace_entry {
  51         uint32_t trace_code;
  52         uint32_t tick_count;
  53         uint32_t param0;
  54         uint32_t param1;
  55 };
  56
  57 static const char *const mst_progress_status[] = {
  58         "probe",
  59         "remote_edid",
  60         "allocate_new_payload",
  61         "clear_allocated_payload",
  62 };
  63
  64 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  65  *
  66  * Function takes in attributes passed to debugfs write entry
  67  * and writes into param array.
  68  * The user passes max_param_num to identify maximum number of
  69  * parameters that could be parsed.
  70  *
  71  */
  72 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  73                                           long *param, const char __user *buf,
  74                                           int max_param_num,
  75                                           uint8_t *param_nums)
  76 {
  77         char *wr_buf_ptr = NULL;
  78         uint32_t wr_buf_count = 0;
  79         int r;
  80         char *sub_str = NULL;
  81         const char delimiter[3] = {' ', '\n', '\0'};
  82         uint8_t param_index = 0;
  83
  84         *param_nums = 0;
  85
  86         wr_buf_ptr = wr_buf;
  87
  88         /* r is bytes not be copied */
  89         if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
  90                 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
  91                 return -EFAULT;
  92         }
  93
  94         /* check number of parameters. isspace could not differ space and \n */
  95         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  96                 /* skip space*/
  97                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  98                         wr_buf_ptr++;
  99                         wr_buf_count++;
 100                         }
 101
 102                 if (wr_buf_count == wr_buf_size)
 103                         break;
 104
 105                 /* skip non-space*/
 106                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 107                         wr_buf_ptr++;
 108                         wr_buf_count++;
 109                 }
 110
 111                 (*param_nums)++;
 112
 113                 if (wr_buf_count == wr_buf_size)
 114                         break;
 115         }
 116
 117         if (*param_nums > max_param_num)
 118                 *param_nums = max_param_num;
 119
 120         wr_buf_ptr = wr_buf; /* reset buf pointer */
 121         wr_buf_count = 0; /* number of char already checked */
 122
 123         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 124                 wr_buf_ptr++;
 125                 wr_buf_count++;
 126         }
 127
 128         while (param_index < *param_nums) {
 129                 /* after strsep, wr_buf_ptr will be moved to after space */
 130                 sub_str = strsep(&wr_buf_ptr, delimiter);
 131
 132                 r = kstrtol(sub_str, 16, &(param[param_index]));
 133
 134                 if (r)
 135                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 136
 137                 param_index++;
 138         }
 139
 140         return 0;
 141 }
 142
 143 /* function description
 144  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 145  *
 146  * valid lane count value: 1, 2, 4
 147  * valid link rate value:
 148  * 06h = 1.62Gbps per lane
 149  * 0Ah = 2.7Gbps per lane
 150  * 0Ch = 3.24Gbps per lane
 151  * 14h = 5.4Gbps per lane
 152  * 1Eh = 8.1Gbps per lane
 153  *
 154  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 155  *
 156  * --- to get dp configuration
 157  *
 158  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 159  *
 160  * It will list current, verified, reported, preferred dp configuration.
 161  * current -- for current video mode
 162  * verified --- maximum configuration which pass link training
 163  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 164  * preferred --- user force settings
 165  *
 166  * --- set (or force) dp configuration
 167  *
 168  * echo <lane_count>  <link_rate> > link_settings
 169  *
 170  * for example, to force to  2 lane, 2.7GHz,
 171  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 172  *
 173  * spread_spectrum could not be changed dynamically.
 174  *
 175  * in case invalid lane count, link rate are force, no hw programming will be
 176  * done. please check link settings after force operation to see if HW get
 177  * programming.
 178  *
 179  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 180  *
 181  * check current and preferred settings.
 182  *
 183  */
 184 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 185                                  size_t size, loff_t *pos)
 186 {
 187         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 188         struct dc_link *link = connector->dc_link;
 189         char *rd_buf = NULL;
 190         char *rd_buf_ptr = NULL;
 191         const uint32_t rd_buf_size = 100;
 192         uint32_t result = 0;
 193         uint8_t str_len = 0;
 194         int r;
 195
 196         if (*pos & 3 || size & 3)
 197                 return -EINVAL;
 198
 199         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 200         if (!rd_buf)
 201                 return 0;
 202
 203         rd_buf_ptr = rd_buf;
 204
 205         str_len = strlen("Current:  %d  0x%x  %d  ");
 206         snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 207                         link->cur_link_settings.lane_count,
 208                         link->cur_link_settings.link_rate,
 209                         link->cur_link_settings.link_spread);
 210         rd_buf_ptr += str_len;
 211
 212         str_len = strlen("Verified:  %d  0x%x  %d  ");
 213         snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 214                         link->verified_link_cap.lane_count,
 215                         link->verified_link_cap.link_rate,
 216                         link->verified_link_cap.link_spread);
 217         rd_buf_ptr += str_len;
 218
 219         str_len = strlen("Reported:  %d  0x%x  %d  ");
 220         snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 221                         link->reported_link_cap.lane_count,
 222                         link->reported_link_cap.link_rate,
 223                         link->reported_link_cap.link_spread);
 224         rd_buf_ptr += str_len;
 225
 226         str_len = strlen("Preferred:  %d  0x%x  %d  ");
 227         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 228                         link->preferred_link_setting.lane_count,
 229                         link->preferred_link_setting.link_rate,
 230                         link->preferred_link_setting.link_spread);
 231
 232         while (size) {
 233                 if (*pos >= rd_buf_size)
 234                         break;
 235
 236                 r = put_user(*(rd_buf + result), buf);
 237                 if (r) {
 238                         kfree(rd_buf);
 239                         return r; /* r = -EFAULT */
 240                 }
 241
 242                 buf += 1;
 243                 size -= 1;
 244                 *pos += 1;
 245                 result += 1;
 246         }
 247
 248         kfree(rd_buf);
 249         return result;
 250 }
 251
 252 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 253                                  size_t size, loff_t *pos)
 254 {
 255         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 256         struct dc_link *link = connector->dc_link;
 257         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
 258         struct dc *dc = (struct dc *)link->dc;
 259         struct dc_link_settings prefer_link_settings;
 260         char *wr_buf = NULL;
 261         const uint32_t wr_buf_size = 40;
 262         /* 0: lane_count; 1: link_rate */
 263         int max_param_num = 2;
 264         uint8_t param_nums = 0;
 265         long param[2];
 266         bool valid_input = true;
 267
 268         if (size == 0)
 269                 return -EINVAL;
 270
 271         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 272         if (!wr_buf)
 273                 return -ENOSPC;
 274
 275         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 276                                            (long *)param, buf,
 277                                            max_param_num,
 278                                            &param_nums)) {
 279                 kfree(wr_buf);
 280                 return -EINVAL;
 281         }
 282
 283         if (param_nums <= 0) {
 284                 kfree(wr_buf);
 285                 DRM_DEBUG_DRIVER("user data not be read\n");
 286                 return -EINVAL;
 287         }
 288
 289         switch (param[0]) {
 290         case LANE_COUNT_ONE:
 291         case LANE_COUNT_TWO:
 292         case LANE_COUNT_FOUR:
 293                 break;
 294         default:
 295                 valid_input = false;
 296                 break;
 297         }
 298
 299         switch (param[1]) {
 300         case LINK_RATE_LOW:
 301         case LINK_RATE_HIGH:
 302         case LINK_RATE_RBR2:
 303         case LINK_RATE_HIGH2:
 304         case LINK_RATE_HIGH3:
 305         case LINK_RATE_UHBR10:
 306         case LINK_RATE_UHBR13_5:
 307         case LINK_RATE_UHBR20:
 308                 break;
 309         default:
 310                 valid_input = false;
 311                 break;
 312         }
 313
 314         if (!valid_input) {
 315                 kfree(wr_buf);
 316                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 317                 mutex_lock(&adev->dm.dc_lock);
 318                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 319                 mutex_unlock(&adev->dm.dc_lock);
 320                 return size;
 321         }
 322
 323         /* save user force lane_count, link_rate to preferred settings
 324          * spread spectrum will not be changed
 325          */
 326         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 327         prefer_link_settings.use_link_rate_set = false;
 328         prefer_link_settings.lane_count = param[0];
 329         prefer_link_settings.link_rate = param[1];
 330
 331         mutex_lock(&adev->dm.dc_lock);
 332         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
 333         mutex_unlock(&adev->dm.dc_lock);
 334
 335         kfree(wr_buf);
 336         return size;
 337 }
 338
 339 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
 340 {
 341         bool is_end_device = false;
 342         struct drm_dp_mst_topology_mgr *mgr = NULL;
 343         struct drm_dp_mst_port *port = NULL;
 344
 345         if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) {
 346                 mgr = &aconnector->mst_root->mst_mgr;
 347                 port = aconnector->mst_output_port;
 348
 349                 drm_modeset_lock(&mgr->base.lock, NULL);
 350                 if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
 351                         port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV)
 352                         is_end_device = true;
 353                 drm_modeset_unlock(&mgr->base.lock);
 354         }
 355
 356         return is_end_device;
 357 }
 358
 359 /* Change MST link setting
 360  *
 361  * valid lane count value: 1, 2, 4
 362  * valid link rate value:
 363  * 06h = 1.62Gbps per lane
 364  * 0Ah = 2.7Gbps per lane
 365  * 0Ch = 3.24Gbps per lane
 366  * 14h = 5.4Gbps per lane
 367  * 1Eh = 8.1Gbps per lane
 368  * 3E8h = 10.0Gbps per lane
 369  * 546h = 13.5Gbps per lane
 370  * 7D0h = 20.0Gbps per lane
 371  *
 372  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings
 373  *
 374  * for example, to force to  2 lane, 10.0GHz,
 375  * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings
 376  *
 377  * Valid input will trigger hotplug event to get new link setting applied
 378  * Invalid input will trigger training setting reset
 379  *
 380  * The usage can be referred to link_settings entry
 381  *
 382  */
 383 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,
 384                                  size_t size, loff_t *pos)
 385 {
 386         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 387         struct dc_link *link = aconnector->dc_link;
 388         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
 389         struct dc *dc = (struct dc *)link->dc;
 390         struct dc_link_settings prefer_link_settings;
 391         char *wr_buf = NULL;
 392         const uint32_t wr_buf_size = 40;
 393         /* 0: lane_count; 1: link_rate */
 394         int max_param_num = 2;
 395         uint8_t param_nums = 0;
 396         long param[2];
 397         bool valid_input = true;
 398
 399         if (!dp_mst_is_end_device(aconnector))
 400                 return -EINVAL;
 401
 402         if (size == 0)
 403                 return -EINVAL;
 404
 405         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 406         if (!wr_buf)
 407                 return -ENOSPC;
 408
 409         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 410                                            (long *)param, buf,
 411                                            max_param_num,
 412                                            &param_nums)) {
 413                 kfree(wr_buf);
 414                 return -EINVAL;
 415         }
 416
 417         if (param_nums <= 0) {
 418                 kfree(wr_buf);
 419                 DRM_DEBUG_DRIVER("user data not be read\n");
 420                 return -EINVAL;
 421         }
 422
 423         switch (param[0]) {
 424         case LANE_COUNT_ONE:
 425         case LANE_COUNT_TWO:
 426         case LANE_COUNT_FOUR:
 427                 break;
 428         default:
 429                 valid_input = false;
 430                 break;
 431         }
 432
 433         switch (param[1]) {
 434         case LINK_RATE_LOW:
 435         case LINK_RATE_HIGH:
 436         case LINK_RATE_RBR2:
 437         case LINK_RATE_HIGH2:
 438         case LINK_RATE_HIGH3:
 439         case LINK_RATE_UHBR10:
 440         case LINK_RATE_UHBR13_5:
 441         case LINK_RATE_UHBR20:
 442                 break;
 443         default:
 444                 valid_input = false;
 445                 break;
 446         }
 447
 448         if (!valid_input) {
 449                 kfree(wr_buf);
 450                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 451                 mutex_lock(&adev->dm.dc_lock);
 452                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 453                 mutex_unlock(&adev->dm.dc_lock);
 454                 return -EINVAL;
 455         }
 456
 457         /* save user force lane_count, link_rate to preferred settings
 458          * spread spectrum will not be changed
 459          */
 460         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 461         prefer_link_settings.use_link_rate_set = false;
 462         prefer_link_settings.lane_count = param[0];
 463         prefer_link_settings.link_rate = param[1];
 464
 465         /* skip immediate retrain, and train to new link setting after hotplug event triggered */
 466         mutex_lock(&adev->dm.dc_lock);
 467         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
 468         mutex_unlock(&adev->dm.dc_lock);
 469
 470         mutex_lock(&aconnector->base.dev->mode_config.mutex);
 471         aconnector->base.force = DRM_FORCE_OFF;
 472         mutex_unlock(&aconnector->base.dev->mode_config.mutex);
 473         drm_kms_helper_hotplug_event(aconnector->base.dev);
 474
 475         msleep(100);
 476
 477         mutex_lock(&aconnector->base.dev->mode_config.mutex);
 478         aconnector->base.force = DRM_FORCE_UNSPECIFIED;
 479         mutex_unlock(&aconnector->base.dev->mode_config.mutex);
 480         drm_kms_helper_hotplug_event(aconnector->base.dev);
 481
 482         kfree(wr_buf);
 483         return size;
 484 }
 485
 486 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 487  * post-cursor2 (defined by VESA DP specification)
 488  *
 489  * valid values
 490  * voltage swing: 0,1,2,3
 491  * pre-emphasis : 0,1,2,3
 492  * post cursor2 : 0,1,2,3
 493  *
 494  *
 495  * how to use this debugfs
 496  *
 497  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 498  *
 499  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 500  *
 501  * To figure out which DP-x is the display for DP to be check,
 502  * cd DP-x
 503  * ls -ll
 504  * There should be debugfs file, like link_settings, phy_settings.
 505  * cat link_settings
 506  * from lane_count, link_rate to figure which DP-x is for display to be worked
 507  * on
 508  *
 509  * To get current DP PHY settings,
 510  * cat phy_settings
 511  *
 512  * To change DP PHY settings,
 513  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 514  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 515  * 0,
 516  * echo 2 3 0 > phy_settings
 517  *
 518  * To check if change be applied, get current phy settings by
 519  * cat phy_settings
 520  *
 521  * In case invalid values are set by user, like
 522  * echo 1 4 0 > phy_settings
 523  *
 524  * HW will NOT be programmed by these settings.
 525  * cat phy_settings will show the previous valid settings.
 526  */
 527 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 528                                  size_t size, loff_t *pos)
 529 {
 530         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 531         struct dc_link *link = connector->dc_link;
 532         char *rd_buf = NULL;
 533         const uint32_t rd_buf_size = 20;
 534         uint32_t result = 0;
 535         int r;
 536
 537         if (*pos & 3 || size & 3)
 538                 return -EINVAL;
 539
 540         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 541         if (!rd_buf)
 542                 return -EINVAL;
 543
 544         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 545                         link->cur_lane_setting[0].VOLTAGE_SWING,
 546                         link->cur_lane_setting[0].PRE_EMPHASIS,
 547                         link->cur_lane_setting[0].POST_CURSOR2);
 548
 549         while (size) {
 550                 if (*pos >= rd_buf_size)
 551                         break;
 552
 553                 r = put_user((*(rd_buf + result)), buf);
 554                 if (r) {
 555                         kfree(rd_buf);
 556                         return r; /* r = -EFAULT */
 557                 }
 558
 559                 buf += 1;
 560                 size -= 1;
 561                 *pos += 1;
 562                 result += 1;
 563         }
 564
 565         kfree(rd_buf);
 566         return result;
 567 }
 568
 569 static int dp_lttpr_status_show(struct seq_file *m, void *unused)
 570 {
 571         struct drm_connector *connector = m->private;
 572         struct amdgpu_dm_connector *aconnector =
 573                 to_amdgpu_dm_connector(connector);
 574         struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
 575
 576         if (connector->status != connector_status_connected)
 577                 return -ENODEV;
 578
 579         seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n",
 580                    dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt),
 581                    caps.phy_repeater_cnt);
 582
 583         seq_puts(m, "phy repeater mode: ");
 584
 585         switch (caps.mode) {
 586         case DP_PHY_REPEATER_MODE_TRANSPARENT:
 587                 seq_puts(m, "transparent");
 588                 break;
 589         case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
 590                 seq_puts(m, "non-transparent");
 591                 break;
 592         case 0x00:
 593                 seq_puts(m, "non lttpr");
 594                 break;
 595         default:
 596                 seq_printf(m, "read error (raw: 0x%x)", caps.mode);
 597                 break;
 598         }
 599
 600         seq_puts(m, "\n");
 601         return 0;
 602 }
 603
 604 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 605                                  size_t size, loff_t *pos)
 606 {
 607         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 608         struct dc_link *link = connector->dc_link;
 609         struct dc *dc = (struct dc *)link->dc;
 610         char *wr_buf = NULL;
 611         uint32_t wr_buf_size = 40;
 612         long param[3];
 613         bool use_prefer_link_setting;
 614         struct link_training_settings link_lane_settings;
 615         int max_param_num = 3;
 616         uint8_t param_nums = 0;
 617         int r = 0;
 618
 619
 620         if (size == 0)
 621                 return -EINVAL;
 622
 623         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 624         if (!wr_buf)
 625                 return -ENOSPC;
 626
 627         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 628                                            (long *)param, buf,
 629                                            max_param_num,
 630                                            &param_nums)) {
 631                 kfree(wr_buf);
 632                 return -EINVAL;
 633         }
 634
 635         if (param_nums <= 0) {
 636                 kfree(wr_buf);
 637                 DRM_DEBUG_DRIVER("user data not be read\n");
 638                 return -EINVAL;
 639         }
 640
 641         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 642                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 643                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 644                 kfree(wr_buf);
 645                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 646                 return size;
 647         }
 648
 649         /* get link settings: lane count, link rate */
 650         use_prefer_link_setting =
 651                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 652                 (link->test_pattern_enabled));
 653
 654         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 655
 656         if (use_prefer_link_setting) {
 657                 link_lane_settings.link_settings.lane_count =
 658                                 link->preferred_link_setting.lane_count;
 659                 link_lane_settings.link_settings.link_rate =
 660                                 link->preferred_link_setting.link_rate;
 661                 link_lane_settings.link_settings.link_spread =
 662                                 link->preferred_link_setting.link_spread;
 663         } else {
 664                 link_lane_settings.link_settings.lane_count =
 665                                 link->cur_link_settings.lane_count;
 666                 link_lane_settings.link_settings.link_rate =
 667                                 link->cur_link_settings.link_rate;
 668                 link_lane_settings.link_settings.link_spread =
 669                                 link->cur_link_settings.link_spread;
 670         }
 671
 672         /* apply phy settings from user */
 673         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 674                 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 675                                 (enum dc_voltage_swing) (param[0]);
 676                 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 677                                 (enum dc_pre_emphasis) (param[1]);
 678                 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 679                                 (enum dc_post_cursor2) (param[2]);
 680         }
 681
 682         /* program ASIC registers and DPCD registers */
 683         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 684
 685         kfree(wr_buf);
 686         return size;
 687 }
 688
 689 /* function description
 690  *
 691  * set PHY layer or Link layer test pattern
 692  * PHY test pattern is used for PHY SI check.
 693  * Link layer test will not affect PHY SI.
 694  *
 695  * Reset Test Pattern:
 696  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 697  *
 698  * PHY test pattern supported:
 699  * 1 = DP_TEST_PATTERN_D102
 700  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 701  * 3 = DP_TEST_PATTERN_PRBS7
 702  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 703  * 5 = DP_TEST_PATTERN_CP2520_1
 704  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 705  * 7 = DP_TEST_PATTERN_CP2520_3
 706  *
 707  * DP PHY Link Training Patterns
 708  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 709  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 710  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 711  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 712  *
 713  * DP Link Layer Test pattern
 714  * c = DP_TEST_PATTERN_COLOR_SQUARES
 715  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 716  * e = DP_TEST_PATTERN_VERTICAL_BARS
 717  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 718  * 10= DP_TEST_PATTERN_COLOR_RAMP
 719  *
 720  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 721  *
 722  * --- set test pattern
 723  * echo <test pattern #> > test_pattern
 724  *
 725  * If test pattern # is not supported, NO HW programming will be done.
 726  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 727  * for the user pattern. input 10 bytes data are separated by space
 728  *
 729  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 730  *
 731  * --- reset test pattern
 732  * echo 0 > test_pattern
 733  *
 734  * --- HPD detection is disabled when set PHY test pattern
 735  *
 736  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 737  * is disable. User could unplug DP display from DP connected and plug scope to
 738  * check test pattern PHY SI.
 739  * If there is need unplug scope and plug DP display back, do steps below:
 740  * echo 0 > phy_test_pattern
 741  * unplug scope
 742  * plug DP display.
 743  *
 744  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 745  * driver could detect "unplug scope" and "plug DP display"
 746  */
 747 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 748                                  size_t size, loff_t *pos)
 749 {
 750         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 751         struct dc_link *link = connector->dc_link;
 752         char *wr_buf = NULL;
 753         uint32_t wr_buf_size = 100;
 754         long param[11] = {0x0};
 755         int max_param_num = 11;
 756         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 757         bool disable_hpd = false;
 758         bool valid_test_pattern = false;
 759         uint8_t param_nums = 0;
 760         /* init with default 80bit custom pattern */
 761         uint8_t custom_pattern[10] = {
 762                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 763                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 764                         };
 765         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 766                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 767         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 768                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 769         struct link_training_settings link_training_settings;
 770         int i;
 771
 772         if (size == 0)
 773                 return -EINVAL;
 774
 775         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 776         if (!wr_buf)
 777                 return -ENOSPC;
 778
 779         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 780                                            (long *)param, buf,
 781                                            max_param_num,
 782                                            &param_nums)) {
 783                 kfree(wr_buf);
 784                 return -EINVAL;
 785         }
 786
 787         if (param_nums <= 0) {
 788                 kfree(wr_buf);
 789                 DRM_DEBUG_DRIVER("user data not be read\n");
 790                 return -EINVAL;
 791         }
 792
 793
 794         test_pattern = param[0];
 795
 796         switch (test_pattern) {
 797         case DP_TEST_PATTERN_VIDEO_MODE:
 798         case DP_TEST_PATTERN_COLOR_SQUARES:
 799         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 800         case DP_TEST_PATTERN_VERTICAL_BARS:
 801         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 802         case DP_TEST_PATTERN_COLOR_RAMP:
 803                 valid_test_pattern = true;
 804                 break;
 805
 806         case DP_TEST_PATTERN_D102:
 807         case DP_TEST_PATTERN_SYMBOL_ERROR:
 808         case DP_TEST_PATTERN_PRBS7:
 809         case DP_TEST_PATTERN_80BIT_CUSTOM:
 810         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 811         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 812                 disable_hpd = true;
 813                 valid_test_pattern = true;
 814                 break;
 815
 816         default:
 817                 valid_test_pattern = false;
 818                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 819                 break;
 820         }
 821
 822         if (!valid_test_pattern) {
 823                 kfree(wr_buf);
 824                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 825                 return size;
 826         }
 827
 828         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 829                 for (i = 0; i < 10; i++) {
 830                         if ((uint8_t) param[i + 1] != 0x0)
 831                                 break;
 832                 }
 833
 834                 if (i < 10) {
 835                         /* not use default value */
 836                         for (i = 0; i < 10; i++)
 837                                 custom_pattern[i] = (uint8_t) param[i + 1];
 838                 }
 839         }
 840
 841         /* Usage: set DP physical test pattern using debugfs with normal DP
 842          * panel. Then plug out DP panel and connect a scope to measure
 843          * For normal video mode and test pattern generated from CRCT,
 844          * they are visibile to user. So do not disable HPD.
 845          * Video Mode is also set to clear the test pattern, so enable HPD
 846          * because it might have been disabled after a test pattern was set.
 847          * AUX depends on HPD * sequence dependent, do not move!
 848          */
 849         if (!disable_hpd)
 850                 dc_link_enable_hpd(link);
 851
 852         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 853         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 854         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 855
 856         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 857         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 858         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 859
 860         link_training_settings.link_settings = cur_link_settings;
 861
 862
 863         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 864                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 865                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 866                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 867                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 868                         link_training_settings.link_settings = prefer_link_settings;
 869         }
 870
 871         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 872                 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 873
 874         dc_link_dp_set_test_pattern(
 875                 link,
 876                 test_pattern,
 877                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 878                 &link_training_settings,
 879                 custom_pattern,
 880                 10);
 881
 882         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 883          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 884          * Need disable interrupt to avoid SW driver disable DP output. This is
 885          * done after the test pattern is set.
 886          */
 887         if (valid_test_pattern && disable_hpd)
 888                 dc_link_disable_hpd(link);
 889
 890         kfree(wr_buf);
 891
 892         return size;
 893 }
 894
 895 /*
 896  * Returns the DMCUB tracebuffer contents.
 897  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 898  */
 899 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 900 {
 901         struct amdgpu_device *adev = m->private;
 902         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 903         struct dmub_debugfs_trace_entry *entries;
 904         uint8_t *tbuf_base;
 905         uint32_t tbuf_size, max_entries, num_entries, i;
 906
 907         if (!fb_info)
 908                 return 0;
 909
 910         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 911         if (!tbuf_base)
 912                 return 0;
 913
 914         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 915         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 916                       sizeof(struct dmub_debugfs_trace_entry);
 917
 918         num_entries =
 919                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 920
 921         num_entries = min(num_entries, max_entries);
 922
 923         entries = (struct dmub_debugfs_trace_entry
 924                            *)(tbuf_base +
 925                               sizeof(struct dmub_debugfs_trace_header));
 926
 927         for (i = 0; i < num_entries; ++i) {
 928                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 929
 930                 seq_printf(m,
 931                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 932                            entry->trace_code, entry->tick_count, entry->param0,
 933                            entry->param1);
 934         }
 935
 936         return 0;
 937 }
 938
 939 /*
 940  * Returns the DMCUB firmware state contents.
 941  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 942  */
 943 static int dmub_fw_state_show(struct seq_file *m, void *data)
 944 {
 945         struct amdgpu_device *adev = m->private;
 946         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 947         uint8_t *state_base;
 948         uint32_t state_size;
 949
 950         if (!fb_info)
 951                 return 0;
 952
 953         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 954         if (!state_base)
 955                 return 0;
 956
 957         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 958
 959         return seq_write(m, state_base, state_size);
 960 }
 961
 962 /* psr_capability_show() - show eDP panel PSR capability
 963  *
 964  * The read function: sink_psr_capability_show
 965  * Shows if sink has PSR capability or not.
 966  * If yes - the PSR version is appended
 967  *
 968  *      cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
 969  *
 970  * Expected output:
 971  * "Sink support: no\n" - if panel doesn't support PSR
 972  * "Sink support: yes [0x01]\n" - if panel supports PSR1
 973  * "Driver support: no\n" - if driver doesn't support PSR
 974  * "Driver support: yes [0x01]\n" - if driver supports PSR1
 975  */
 976 static int psr_capability_show(struct seq_file *m, void *data)
 977 {
 978         struct drm_connector *connector = m->private;
 979         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 980         struct dc_link *link = aconnector->dc_link;
 981
 982         if (!link)
 983                 return -ENODEV;
 984
 985         if (link->type == dc_connection_none)
 986                 return -ENODEV;
 987
 988         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
 989                 return -ENODEV;
 990
 991         seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
 992         if (link->dpcd_caps.psr_info.psr_version)
 993                 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
 994         seq_puts(m, "\n");
 995
 996         seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
 997         if (link->psr_settings.psr_version)
 998                 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
 999         seq_puts(m, "\n");
1000
1001         return 0;
1002 }
1003
1004 /*
1005  * Returns the current bpc for the crtc.
1006  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
1007  */
1008 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
1009 {
1010         struct drm_crtc *crtc = m->private;
1011         struct drm_device *dev = crtc->dev;
1012         struct dm_crtc_state *dm_crtc_state = NULL;
1013         int res = -ENODEV;
1014         unsigned int bpc;
1015
1016         mutex_lock(&dev->mode_config.mutex);
1017         drm_modeset_lock(&crtc->mutex, NULL);
1018         if (crtc->state == NULL)
1019                 goto unlock;
1020
1021         dm_crtc_state = to_dm_crtc_state(crtc->state);
1022         if (dm_crtc_state->stream == NULL)
1023                 goto unlock;
1024
1025         switch (dm_crtc_state->stream->timing.display_color_depth) {
1026         case COLOR_DEPTH_666:
1027                 bpc = 6;
1028                 break;
1029         case COLOR_DEPTH_888:
1030                 bpc = 8;
1031                 break;
1032         case COLOR_DEPTH_101010:
1033                 bpc = 10;
1034                 break;
1035         case COLOR_DEPTH_121212:
1036                 bpc = 12;
1037                 break;
1038         case COLOR_DEPTH_161616:
1039                 bpc = 16;
1040                 break;
1041         default:
1042                 goto unlock;
1043         }
1044
1045         seq_printf(m, "Current: %u\n", bpc);
1046         res = 0;
1047
1048 unlock:
1049         drm_modeset_unlock(&crtc->mutex);
1050         mutex_unlock(&dev->mode_config.mutex);
1051
1052         return res;
1053 }
1054 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
1055
1056 /*
1057  * Returns the current colorspace for the crtc.
1058  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
1059  */
1060 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
1061 {
1062         struct drm_crtc *crtc = m->private;
1063         struct drm_device *dev = crtc->dev;
1064         struct dm_crtc_state *dm_crtc_state = NULL;
1065         int res = -ENODEV;
1066
1067         mutex_lock(&dev->mode_config.mutex);
1068         drm_modeset_lock(&crtc->mutex, NULL);
1069         if (crtc->state == NULL)
1070                 goto unlock;
1071
1072         dm_crtc_state = to_dm_crtc_state(crtc->state);
1073         if (dm_crtc_state->stream == NULL)
1074                 goto unlock;
1075
1076         switch (dm_crtc_state->stream->output_color_space) {
1077         case COLOR_SPACE_SRGB:
1078                 seq_puts(m, "sRGB");
1079                 break;
1080         case COLOR_SPACE_YCBCR601:
1081         case COLOR_SPACE_YCBCR601_LIMITED:
1082                 seq_puts(m, "BT601_YCC");
1083                 break;
1084         case COLOR_SPACE_YCBCR709:
1085         case COLOR_SPACE_YCBCR709_LIMITED:
1086                 seq_puts(m, "BT709_YCC");
1087                 break;
1088         case COLOR_SPACE_ADOBERGB:
1089                 seq_puts(m, "opRGB");
1090                 break;
1091         case COLOR_SPACE_2020_RGB_FULLRANGE:
1092                 seq_puts(m, "BT2020_RGB");
1093                 break;
1094         case COLOR_SPACE_2020_YCBCR:
1095                 seq_puts(m, "BT2020_YCC");
1096                 break;
1097         default:
1098                 goto unlock;
1099         }
1100         res = 0;
1101
1102 unlock:
1103         drm_modeset_unlock(&crtc->mutex);
1104         mutex_unlock(&dev->mode_config.mutex);
1105
1106         return res;
1107 }
1108 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
1109
1110
1111 /*
1112  * Example usage:
1113  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1114  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1115  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1116  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1117  */
1118 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
1119                                  size_t size, loff_t *pos)
1120 {
1121         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1122         char *wr_buf = NULL;
1123         uint32_t wr_buf_size = 42;
1124         int max_param_num = 1;
1125         long param;
1126         uint8_t param_nums = 0;
1127
1128         if (size == 0)
1129                 return -EINVAL;
1130
1131         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1132
1133         if (!wr_buf) {
1134                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1135                 return -ENOSPC;
1136         }
1137
1138         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1139                                            &param, buf,
1140                                            max_param_num,
1141                                            &param_nums)) {
1142                 kfree(wr_buf);
1143                 return -EINVAL;
1144         }
1145
1146         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
1147
1148         kfree(wr_buf);
1149         return 0;
1150 }
1151
1152 /*
1153  * Returns the HDCP capability of the Display (1.4 for now).
1154  *
1155  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
1156  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
1157  *
1158  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
1159  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
1160  */
1161 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
1162 {
1163         struct drm_connector *connector = m->private;
1164         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1165         bool hdcp_cap, hdcp2_cap;
1166
1167         if (connector->status != connector_status_connected)
1168                 return -ENODEV;
1169
1170         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
1171
1172         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1173         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1174
1175
1176         if (hdcp_cap)
1177                 seq_printf(m, "%s ", "HDCP1.4");
1178         if (hdcp2_cap)
1179                 seq_printf(m, "%s ", "HDCP2.2");
1180
1181         if (!hdcp_cap && !hdcp2_cap)
1182                 seq_printf(m, "%s ", "None");
1183
1184         seq_puts(m, "\n");
1185
1186         return 0;
1187 }
1188
1189 /*
1190  * Returns whether the connected display is internal and not hotpluggable.
1191  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1192  */
1193 static int internal_display_show(struct seq_file *m, void *data)
1194 {
1195         struct drm_connector *connector = m->private;
1196         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1197         struct dc_link *link = aconnector->dc_link;
1198
1199         seq_printf(m, "Internal: %u\n", link->is_internal_display);
1200
1201         return 0;
1202 }
1203
1204 /* function description
1205  *
1206  * generic SDP message access for testing
1207  *
1208  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1209  *
1210  * SDP header
1211  * Hb0 : Secondary-Data Packet ID
1212  * Hb1 : Secondary-Data Packet type
1213  * Hb2 : Secondary-Data-packet-specific header, Byte 0
1214  * Hb3 : Secondary-Data-packet-specific header, Byte 1
1215  *
1216  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1217  */
1218 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1219                                  size_t size, loff_t *pos)
1220 {
1221         int r;
1222         uint8_t data[36];
1223         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1224         struct dm_crtc_state *acrtc_state;
1225         uint32_t write_size = 36;
1226
1227         if (connector->base.status != connector_status_connected)
1228                 return -ENODEV;
1229
1230         if (size == 0)
1231                 return 0;
1232
1233         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1234
1235         r = copy_from_user(data, buf, write_size);
1236
1237         write_size -= r;
1238
1239         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1240
1241         return write_size;
1242 }
1243
1244 /* function: Read link's DSC & FEC capabilities
1245  *
1246  *
1247  * Access it with the following command (you need to specify
1248  * connector like DP-1):
1249  *
1250  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1251  *
1252  */
1253 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1254 {
1255         struct drm_connector *connector = m->private;
1256         struct drm_modeset_acquire_ctx ctx;
1257         struct drm_device *dev = connector->dev;
1258         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1259         int ret = 0;
1260         bool try_again = false;
1261         bool is_fec_supported = false;
1262         bool is_dsc_supported = false;
1263         struct dpcd_caps dpcd_caps;
1264
1265         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1266         do {
1267                 try_again = false;
1268                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1269                 if (ret) {
1270                         if (ret == -EDEADLK) {
1271                                 ret = drm_modeset_backoff(&ctx);
1272                                 if (!ret) {
1273                                         try_again = true;
1274                                         continue;
1275                                 }
1276                         }
1277                         break;
1278                 }
1279                 if (connector->status != connector_status_connected) {
1280                         ret = -ENODEV;
1281                         break;
1282                 }
1283                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1284                 if (aconnector->mst_output_port) {
1285                         /* aconnector sets dsc_aux during get_modes call
1286                          * if MST connector has it means it can either
1287                          * enable DSC on the sink device or on MST branch
1288                          * its connected to.
1289                          */
1290                         if (aconnector->dsc_aux) {
1291                                 is_fec_supported = true;
1292                                 is_dsc_supported = true;
1293                         }
1294                 } else {
1295                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1296                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1297                 }
1298         } while (try_again);
1299
1300         drm_modeset_drop_locks(&ctx);
1301         drm_modeset_acquire_fini(&ctx);
1302
1303         seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1304         seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1305
1306         return ret;
1307 }
1308
1309 /* function: Trigger virtual HPD redetection on connector
1310  *
1311  * This function will perform link rediscovery, link disable
1312  * and enable, and dm connector state update.
1313  *
1314  * Retrigger HPD on an existing connector by echoing 1 into
1315  * its respectful "trigger_hotplug" debugfs entry:
1316  *
1317  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1318  *
1319  * This function can perform HPD unplug:
1320  *
1321  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1322  *
1323  */
1324 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1325                                                         size_t size, loff_t *pos)
1326 {
1327         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1328         struct drm_connector *connector = &aconnector->base;
1329         struct dc_link *link = NULL;
1330         struct drm_device *dev = connector->dev;
1331         struct amdgpu_device *adev = drm_to_adev(dev);
1332         enum dc_connection_type new_connection_type = dc_connection_none;
1333         char *wr_buf = NULL;
1334         uint32_t wr_buf_size = 42;
1335         int max_param_num = 1;
1336         long param[1] = {0};
1337         uint8_t param_nums = 0;
1338         bool ret = false;
1339
1340         if (!aconnector || !aconnector->dc_link)
1341                 return -EINVAL;
1342
1343         if (size == 0)
1344                 return -EINVAL;
1345
1346         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1347
1348         if (!wr_buf) {
1349                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1350                 return -ENOSPC;
1351         }
1352
1353         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1354                                                 (long *)param, buf,
1355                                                 max_param_num,
1356                                                 &param_nums)) {
1357                 kfree(wr_buf);
1358                 return -EINVAL;
1359         }
1360
1361         kfree(wr_buf);
1362
1363         if (param_nums <= 0) {
1364                 DRM_DEBUG_DRIVER("user data not be read\n");
1365                 return -EINVAL;
1366         }
1367
1368         mutex_lock(&aconnector->hpd_lock);
1369
1370         /* Don't support for mst end device*/
1371         if (aconnector->mst_root) {
1372                 mutex_unlock(&aconnector->hpd_lock);
1373                 return -EINVAL;
1374         }
1375
1376         if (param[0] == 1) {
1377
1378                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) &&
1379                         new_connection_type != dc_connection_none)
1380                         goto unlock;
1381
1382                 mutex_lock(&adev->dm.dc_lock);
1383                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1384                 mutex_unlock(&adev->dm.dc_lock);
1385
1386                 if (!ret)
1387                         goto unlock;
1388
1389                 amdgpu_dm_update_connector_after_detect(aconnector);
1390
1391                 drm_modeset_lock_all(dev);
1392                 dm_restore_drm_connector_state(dev, connector);
1393                 drm_modeset_unlock_all(dev);
1394
1395                 drm_kms_helper_connector_hotplug_event(connector);
1396         } else if (param[0] == 0) {
1397                 if (!aconnector->dc_link)
1398                         goto unlock;
1399
1400                 link = aconnector->dc_link;
1401
1402                 if (link->local_sink) {
1403                         dc_sink_release(link->local_sink);
1404                         link->local_sink = NULL;
1405                 }
1406
1407                 link->dpcd_sink_count = 0;
1408                 link->type = dc_connection_none;
1409                 link->dongle_max_pix_clk = 0;
1410
1411                 amdgpu_dm_update_connector_after_detect(aconnector);
1412
1413                 /* If the aconnector is the root node in mst topology */
1414                 if (aconnector->mst_mgr.mst_state == true)
1415                         dc_link_reset_cur_dp_mst_topology(link);
1416
1417                 drm_modeset_lock_all(dev);
1418                 dm_restore_drm_connector_state(dev, connector);
1419                 drm_modeset_unlock_all(dev);
1420
1421                 drm_kms_helper_connector_hotplug_event(connector);
1422         }
1423
1424 unlock:
1425         mutex_unlock(&aconnector->hpd_lock);
1426
1427         return size;
1428 }
1429
1430 /* function: read DSC status on the connector
1431  *
1432  * The read function: dp_dsc_clock_en_read
1433  * returns current status of DSC clock on the connector.
1434  * The return is a boolean flag: 1 or 0.
1435  *
1436  * Access it with the following command (you need to specify
1437  * connector like DP-1):
1438  *
1439  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1440  *
1441  * Expected output:
1442  * 1 - means that DSC is currently enabled
1443  * 0 - means that DSC is disabled
1444  */
1445 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1446                                     size_t size, loff_t *pos)
1447 {
1448         char *rd_buf = NULL;
1449         char *rd_buf_ptr = NULL;
1450         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1451         struct display_stream_compressor *dsc;
1452         struct dcn_dsc_state dsc_state = {0};
1453         const uint32_t rd_buf_size = 10;
1454         struct pipe_ctx *pipe_ctx;
1455         ssize_t result = 0;
1456         int i, r, str_len = 30;
1457
1458         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1459
1460         if (!rd_buf)
1461                 return -ENOMEM;
1462
1463         rd_buf_ptr = rd_buf;
1464
1465         for (i = 0; i < MAX_PIPES; i++) {
1466                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1467                 if (pipe_ctx->stream &&
1468                     pipe_ctx->stream->link == aconnector->dc_link)
1469                         break;
1470         }
1471
1472         dsc = pipe_ctx->stream_res.dsc;
1473         if (dsc)
1474                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1475
1476         snprintf(rd_buf_ptr, str_len,
1477                 "%d\n",
1478                 dsc_state.dsc_clock_en);
1479         rd_buf_ptr += str_len;
1480
1481         while (size) {
1482                 if (*pos >= rd_buf_size)
1483                         break;
1484
1485                 r = put_user(*(rd_buf + result), buf);
1486                 if (r) {
1487                         kfree(rd_buf);
1488                         return r; /* r = -EFAULT */
1489                 }
1490
1491                 buf += 1;
1492                 size -= 1;
1493                 *pos += 1;
1494                 result += 1;
1495         }
1496
1497         kfree(rd_buf);
1498         return result;
1499 }
1500
1501 /* function: write force DSC on the connector
1502  *
1503  * The write function: dp_dsc_clock_en_write
1504  * enables to force DSC on the connector.
1505  * User can write to either force enable or force disable DSC
1506  * on the next modeset or set it to driver default
1507  *
1508  * Accepted inputs:
1509  * 0 - default DSC enablement policy
1510  * 1 - force enable DSC on the connector
1511  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1512  *
1513  * Writing DSC settings is done with the following command:
1514  * - To force enable DSC (you need to specify
1515  * connector like DP-1):
1516  *
1517  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1518  *
1519  * - To return to default state set the flag to zero and
1520  * let driver deal with DSC automatically
1521  * (you need to specify connector like DP-1):
1522  *
1523  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1524  *
1525  */
1526 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1527                                      size_t size, loff_t *pos)
1528 {
1529         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1530         struct drm_connector *connector = &aconnector->base;
1531         struct drm_device *dev = connector->dev;
1532         struct drm_crtc *crtc = NULL;
1533         struct dm_crtc_state *dm_crtc_state = NULL;
1534         struct pipe_ctx *pipe_ctx;
1535         int i;
1536         char *wr_buf = NULL;
1537         uint32_t wr_buf_size = 42;
1538         int max_param_num = 1;
1539         long param[1] = {0};
1540         uint8_t param_nums = 0;
1541
1542         if (size == 0)
1543                 return -EINVAL;
1544
1545         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1546
1547         if (!wr_buf) {
1548                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1549                 return -ENOSPC;
1550         }
1551
1552         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1553                                             (long *)param, buf,
1554                                             max_param_num,
1555                                             &param_nums)) {
1556                 kfree(wr_buf);
1557                 return -EINVAL;
1558         }
1559
1560         if (param_nums <= 0) {
1561                 DRM_DEBUG_DRIVER("user data not be read\n");
1562                 kfree(wr_buf);
1563                 return -EINVAL;
1564         }
1565
1566         for (i = 0; i < MAX_PIPES; i++) {
1567                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1568                 if (pipe_ctx->stream &&
1569                     pipe_ctx->stream->link == aconnector->dc_link)
1570                         break;
1571         }
1572
1573         if (!pipe_ctx->stream)
1574                 goto done;
1575
1576         // Get CRTC state
1577         mutex_lock(&dev->mode_config.mutex);
1578         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1579
1580         if (connector->state == NULL)
1581                 goto unlock;
1582
1583         crtc = connector->state->crtc;
1584         if (crtc == NULL)
1585                 goto unlock;
1586
1587         drm_modeset_lock(&crtc->mutex, NULL);
1588         if (crtc->state == NULL)
1589                 goto unlock;
1590
1591         dm_crtc_state = to_dm_crtc_state(crtc->state);
1592         if (dm_crtc_state->stream == NULL)
1593                 goto unlock;
1594
1595         if (param[0] == 1)
1596                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1597         else if (param[0] == 2)
1598                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1599         else
1600                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1601
1602         dm_crtc_state->dsc_force_changed = true;
1603
1604 unlock:
1605         if (crtc)
1606                 drm_modeset_unlock(&crtc->mutex);
1607         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1608         mutex_unlock(&dev->mode_config.mutex);
1609
1610 done:
1611         kfree(wr_buf);
1612         return size;
1613 }
1614
1615 /* function: read DSC slice width parameter on the connector
1616  *
1617  * The read function: dp_dsc_slice_width_read
1618  * returns dsc slice width used in the current configuration
1619  * The return is an integer: 0 or other positive number
1620  *
1621  * Access the status with the following command:
1622  *
1623  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1624  *
1625  * 0 - means that DSC is disabled
1626  *
1627  * Any other number more than zero represents the
1628  * slice width currently used by DSC in pixels
1629  *
1630  */
1631 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1632                                     size_t size, loff_t *pos)
1633 {
1634         char *rd_buf = NULL;
1635         char *rd_buf_ptr = NULL;
1636         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1637         struct display_stream_compressor *dsc;
1638         struct dcn_dsc_state dsc_state = {0};
1639         const uint32_t rd_buf_size = 100;
1640         struct pipe_ctx *pipe_ctx;
1641         ssize_t result = 0;
1642         int i, r, str_len = 30;
1643
1644         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1645
1646         if (!rd_buf)
1647                 return -ENOMEM;
1648
1649         rd_buf_ptr = rd_buf;
1650
1651         for (i = 0; i < MAX_PIPES; i++) {
1652                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1653                 if (pipe_ctx->stream &&
1654                     pipe_ctx->stream->link == aconnector->dc_link)
1655                         break;
1656         }
1657
1658         dsc = pipe_ctx->stream_res.dsc;
1659         if (dsc)
1660                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1661
1662         snprintf(rd_buf_ptr, str_len,
1663                 "%d\n",
1664                 dsc_state.dsc_slice_width);
1665         rd_buf_ptr += str_len;
1666
1667         while (size) {
1668                 if (*pos >= rd_buf_size)
1669                         break;
1670
1671                 r = put_user(*(rd_buf + result), buf);
1672                 if (r) {
1673                         kfree(rd_buf);
1674                         return r; /* r = -EFAULT */
1675                 }
1676
1677                 buf += 1;
1678                 size -= 1;
1679                 *pos += 1;
1680                 result += 1;
1681         }
1682
1683         kfree(rd_buf);
1684         return result;
1685 }
1686
1687 /* function: write DSC slice width parameter
1688  *
1689  * The write function: dp_dsc_slice_width_write
1690  * overwrites automatically generated DSC configuration
1691  * of slice width.
1692  *
1693  * The user has to write the slice width divisible by the
1694  * picture width.
1695  *
1696  * Also the user has to write width in hexidecimal
1697  * rather than in decimal.
1698  *
1699  * Writing DSC settings is done with the following command:
1700  * - To force overwrite slice width: (example sets to 1920 pixels)
1701  *
1702  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1703  *
1704  *  - To stop overwriting and let driver find the optimal size,
1705  * set the width to zero:
1706  *
1707  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1708  *
1709  */
1710 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1711                                      size_t size, loff_t *pos)
1712 {
1713         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1714         struct pipe_ctx *pipe_ctx;
1715         struct drm_connector *connector = &aconnector->base;
1716         struct drm_device *dev = connector->dev;
1717         struct drm_crtc *crtc = NULL;
1718         struct dm_crtc_state *dm_crtc_state = NULL;
1719         int i;
1720         char *wr_buf = NULL;
1721         uint32_t wr_buf_size = 42;
1722         int max_param_num = 1;
1723         long param[1] = {0};
1724         uint8_t param_nums = 0;
1725
1726         if (size == 0)
1727                 return -EINVAL;
1728
1729         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1730
1731         if (!wr_buf) {
1732                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1733                 return -ENOSPC;
1734         }
1735
1736         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1737                                             (long *)param, buf,
1738                                             max_param_num,
1739                                             &param_nums)) {
1740                 kfree(wr_buf);
1741                 return -EINVAL;
1742         }
1743
1744         if (param_nums <= 0) {
1745                 DRM_DEBUG_DRIVER("user data not be read\n");
1746                 kfree(wr_buf);
1747                 return -EINVAL;
1748         }
1749
1750         for (i = 0; i < MAX_PIPES; i++) {
1751                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1752                 if (pipe_ctx->stream &&
1753                     pipe_ctx->stream->link == aconnector->dc_link)
1754                         break;
1755         }
1756
1757         if (!pipe_ctx->stream)
1758                 goto done;
1759
1760         // Safely get CRTC state
1761         mutex_lock(&dev->mode_config.mutex);
1762         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1763
1764         if (connector->state == NULL)
1765                 goto unlock;
1766
1767         crtc = connector->state->crtc;
1768         if (crtc == NULL)
1769                 goto unlock;
1770
1771         drm_modeset_lock(&crtc->mutex, NULL);
1772         if (crtc->state == NULL)
1773                 goto unlock;
1774
1775         dm_crtc_state = to_dm_crtc_state(crtc->state);
1776         if (dm_crtc_state->stream == NULL)
1777                 goto unlock;
1778
1779         if (param[0] > 0)
1780                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1781                                         pipe_ctx->stream->timing.h_addressable,
1782                                         param[0]);
1783         else
1784                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1785
1786         dm_crtc_state->dsc_force_changed = true;
1787
1788 unlock:
1789         if (crtc)
1790                 drm_modeset_unlock(&crtc->mutex);
1791         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1792         mutex_unlock(&dev->mode_config.mutex);
1793
1794 done:
1795         kfree(wr_buf);
1796         return size;
1797 }
1798
1799 /* function: read DSC slice height parameter on the connector
1800  *
1801  * The read function: dp_dsc_slice_height_read
1802  * returns dsc slice height used in the current configuration
1803  * The return is an integer: 0 or other positive number
1804  *
1805  * Access the status with the following command:
1806  *
1807  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1808  *
1809  * 0 - means that DSC is disabled
1810  *
1811  * Any other number more than zero represents the
1812  * slice height currently used by DSC in pixels
1813  *
1814  */
1815 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1816                                     size_t size, loff_t *pos)
1817 {
1818         char *rd_buf = NULL;
1819         char *rd_buf_ptr = NULL;
1820         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1821         struct display_stream_compressor *dsc;
1822         struct dcn_dsc_state dsc_state = {0};
1823         const uint32_t rd_buf_size = 100;
1824         struct pipe_ctx *pipe_ctx;
1825         ssize_t result = 0;
1826         int i, r, str_len = 30;
1827
1828         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1829
1830         if (!rd_buf)
1831                 return -ENOMEM;
1832
1833         rd_buf_ptr = rd_buf;
1834
1835         for (i = 0; i < MAX_PIPES; i++) {
1836                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1837                 if (pipe_ctx->stream &&
1838                     pipe_ctx->stream->link == aconnector->dc_link)
1839                         break;
1840         }
1841
1842         dsc = pipe_ctx->stream_res.dsc;
1843         if (dsc)
1844                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1845
1846         snprintf(rd_buf_ptr, str_len,
1847                 "%d\n",
1848                 dsc_state.dsc_slice_height);
1849         rd_buf_ptr += str_len;
1850
1851         while (size) {
1852                 if (*pos >= rd_buf_size)
1853                         break;
1854
1855                 r = put_user(*(rd_buf + result), buf);
1856                 if (r) {
1857                         kfree(rd_buf);
1858                         return r; /* r = -EFAULT */
1859                 }
1860
1861                 buf += 1;
1862                 size -= 1;
1863                 *pos += 1;
1864                 result += 1;
1865         }
1866
1867         kfree(rd_buf);
1868         return result;
1869 }
1870
1871 /* function: write DSC slice height parameter
1872  *
1873  * The write function: dp_dsc_slice_height_write
1874  * overwrites automatically generated DSC configuration
1875  * of slice height.
1876  *
1877  * The user has to write the slice height divisible by the
1878  * picture height.
1879  *
1880  * Also the user has to write height in hexidecimal
1881  * rather than in decimal.
1882  *
1883  * Writing DSC settings is done with the following command:
1884  * - To force overwrite slice height (example sets to 128 pixels):
1885  *
1886  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1887  *
1888  *  - To stop overwriting and let driver find the optimal size,
1889  * set the height to zero:
1890  *
1891  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1892  *
1893  */
1894 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1895                                      size_t size, loff_t *pos)
1896 {
1897         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1898         struct drm_connector *connector = &aconnector->base;
1899         struct drm_device *dev = connector->dev;
1900         struct drm_crtc *crtc = NULL;
1901         struct dm_crtc_state *dm_crtc_state = NULL;
1902         struct pipe_ctx *pipe_ctx;
1903         int i;
1904         char *wr_buf = NULL;
1905         uint32_t wr_buf_size = 42;
1906         int max_param_num = 1;
1907         uint8_t param_nums = 0;
1908         long param[1] = {0};
1909
1910         if (size == 0)
1911                 return -EINVAL;
1912
1913         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1914
1915         if (!wr_buf) {
1916                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1917                 return -ENOSPC;
1918         }
1919
1920         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1921                                             (long *)param, buf,
1922                                             max_param_num,
1923                                             &param_nums)) {
1924                 kfree(wr_buf);
1925                 return -EINVAL;
1926         }
1927
1928         if (param_nums <= 0) {
1929                 DRM_DEBUG_DRIVER("user data not be read\n");
1930                 kfree(wr_buf);
1931                 return -EINVAL;
1932         }
1933
1934         for (i = 0; i < MAX_PIPES; i++) {
1935                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1936                 if (pipe_ctx->stream &&
1937                     pipe_ctx->stream->link == aconnector->dc_link)
1938                         break;
1939         }
1940
1941         if (!pipe_ctx->stream)
1942                 goto done;
1943
1944         // Get CRTC state
1945         mutex_lock(&dev->mode_config.mutex);
1946         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1947
1948         if (connector->state == NULL)
1949                 goto unlock;
1950
1951         crtc = connector->state->crtc;
1952         if (crtc == NULL)
1953                 goto unlock;
1954
1955         drm_modeset_lock(&crtc->mutex, NULL);
1956         if (crtc->state == NULL)
1957                 goto unlock;
1958
1959         dm_crtc_state = to_dm_crtc_state(crtc->state);
1960         if (dm_crtc_state->stream == NULL)
1961                 goto unlock;
1962
1963         if (param[0] > 0)
1964                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1965                                         pipe_ctx->stream->timing.v_addressable,
1966                                         param[0]);
1967         else
1968                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1969
1970         dm_crtc_state->dsc_force_changed = true;
1971
1972 unlock:
1973         if (crtc)
1974                 drm_modeset_unlock(&crtc->mutex);
1975         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1976         mutex_unlock(&dev->mode_config.mutex);
1977
1978 done:
1979         kfree(wr_buf);
1980         return size;
1981 }
1982
1983 /* function: read DSC target rate on the connector in bits per pixel
1984  *
1985  * The read function: dp_dsc_bits_per_pixel_read
1986  * returns target rate of compression in bits per pixel
1987  * The return is an integer: 0 or other positive integer
1988  *
1989  * Access it with the following command:
1990  *
1991  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1992  *
1993  *  0 - means that DSC is disabled
1994  */
1995 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1996                                     size_t size, loff_t *pos)
1997 {
1998         char *rd_buf = NULL;
1999         char *rd_buf_ptr = NULL;
2000         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2001         struct display_stream_compressor *dsc;
2002         struct dcn_dsc_state dsc_state = {0};
2003         const uint32_t rd_buf_size = 100;
2004         struct pipe_ctx *pipe_ctx;
2005         ssize_t result = 0;
2006         int i, r, str_len = 30;
2007
2008         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2009
2010         if (!rd_buf)
2011                 return -ENOMEM;
2012
2013         rd_buf_ptr = rd_buf;
2014
2015         for (i = 0; i < MAX_PIPES; i++) {
2016                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2017                 if (pipe_ctx->stream &&
2018                     pipe_ctx->stream->link == aconnector->dc_link)
2019                         break;
2020         }
2021
2022         dsc = pipe_ctx->stream_res.dsc;
2023         if (dsc)
2024                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2025
2026         snprintf(rd_buf_ptr, str_len,
2027                 "%d\n",
2028                 dsc_state.dsc_bits_per_pixel);
2029         rd_buf_ptr += str_len;
2030
2031         while (size) {
2032                 if (*pos >= rd_buf_size)
2033                         break;
2034
2035                 r = put_user(*(rd_buf + result), buf);
2036                 if (r) {
2037                         kfree(rd_buf);
2038                         return r; /* r = -EFAULT */
2039                 }
2040
2041                 buf += 1;
2042                 size -= 1;
2043                 *pos += 1;
2044                 result += 1;
2045         }
2046
2047         kfree(rd_buf);
2048         return result;
2049 }
2050
2051 /* function: write DSC target rate in bits per pixel
2052  *
2053  * The write function: dp_dsc_bits_per_pixel_write
2054  * overwrites automatically generated DSC configuration
2055  * of DSC target bit rate.
2056  *
2057  * Also the user has to write bpp in hexidecimal
2058  * rather than in decimal.
2059  *
2060  * Writing DSC settings is done with the following command:
2061  * - To force overwrite rate (example sets to 256 bpp x 1/16):
2062  *
2063  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2064  *
2065  *  - To stop overwriting and let driver find the optimal rate,
2066  * set the rate to zero:
2067  *
2068  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2069  *
2070  */
2071 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
2072                                      size_t size, loff_t *pos)
2073 {
2074         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2075         struct drm_connector *connector = &aconnector->base;
2076         struct drm_device *dev = connector->dev;
2077         struct drm_crtc *crtc = NULL;
2078         struct dm_crtc_state *dm_crtc_state = NULL;
2079         struct pipe_ctx *pipe_ctx;
2080         int i;
2081         char *wr_buf = NULL;
2082         uint32_t wr_buf_size = 42;
2083         int max_param_num = 1;
2084         uint8_t param_nums = 0;
2085         long param[1] = {0};
2086
2087         if (size == 0)
2088                 return -EINVAL;
2089
2090         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2091
2092         if (!wr_buf) {
2093                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2094                 return -ENOSPC;
2095         }
2096
2097         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2098                                             (long *)param, buf,
2099                                             max_param_num,
2100                                             &param_nums)) {
2101                 kfree(wr_buf);
2102                 return -EINVAL;
2103         }
2104
2105         if (param_nums <= 0) {
2106                 DRM_DEBUG_DRIVER("user data not be read\n");
2107                 kfree(wr_buf);
2108                 return -EINVAL;
2109         }
2110
2111         for (i = 0; i < MAX_PIPES; i++) {
2112                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2113                 if (pipe_ctx->stream &&
2114                     pipe_ctx->stream->link == aconnector->dc_link)
2115                         break;
2116         }
2117
2118         if (!pipe_ctx->stream)
2119                 goto done;
2120
2121         // Get CRTC state
2122         mutex_lock(&dev->mode_config.mutex);
2123         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2124
2125         if (connector->state == NULL)
2126                 goto unlock;
2127
2128         crtc = connector->state->crtc;
2129         if (crtc == NULL)
2130                 goto unlock;
2131
2132         drm_modeset_lock(&crtc->mutex, NULL);
2133         if (crtc->state == NULL)
2134                 goto unlock;
2135
2136         dm_crtc_state = to_dm_crtc_state(crtc->state);
2137         if (dm_crtc_state->stream == NULL)
2138                 goto unlock;
2139
2140         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2141
2142         dm_crtc_state->dsc_force_changed = true;
2143
2144 unlock:
2145         if (crtc)
2146                 drm_modeset_unlock(&crtc->mutex);
2147         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2148         mutex_unlock(&dev->mode_config.mutex);
2149
2150 done:
2151         kfree(wr_buf);
2152         return size;
2153 }
2154
2155 /* function: read DSC picture width parameter on the connector
2156  *
2157  * The read function: dp_dsc_pic_width_read
2158  * returns dsc picture width used in the current configuration
2159  * It is the same as h_addressable of the current
2160  * display's timing
2161  * The return is an integer: 0 or other positive integer
2162  * If 0 then DSC is disabled.
2163  *
2164  * Access it with the following command:
2165  *
2166  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2167  *
2168  * 0 - means that DSC is disabled
2169  */
2170 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2171                                     size_t size, loff_t *pos)
2172 {
2173         char *rd_buf = NULL;
2174         char *rd_buf_ptr = NULL;
2175         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2176         struct display_stream_compressor *dsc;
2177         struct dcn_dsc_state dsc_state = {0};
2178         const uint32_t rd_buf_size = 100;
2179         struct pipe_ctx *pipe_ctx;
2180         ssize_t result = 0;
2181         int i, r, str_len = 30;
2182
2183         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2184
2185         if (!rd_buf)
2186                 return -ENOMEM;
2187
2188         rd_buf_ptr = rd_buf;
2189
2190         for (i = 0; i < MAX_PIPES; i++) {
2191                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2192                 if (pipe_ctx->stream &&
2193                     pipe_ctx->stream->link == aconnector->dc_link)
2194                         break;
2195         }
2196
2197         dsc = pipe_ctx->stream_res.dsc;
2198         if (dsc)
2199                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2200
2201         snprintf(rd_buf_ptr, str_len,
2202                 "%d\n",
2203                 dsc_state.dsc_pic_width);
2204         rd_buf_ptr += str_len;
2205
2206         while (size) {
2207                 if (*pos >= rd_buf_size)
2208                         break;
2209
2210                 r = put_user(*(rd_buf + result), buf);
2211                 if (r) {
2212                         kfree(rd_buf);
2213                         return r; /* r = -EFAULT */
2214                 }
2215
2216                 buf += 1;
2217                 size -= 1;
2218                 *pos += 1;
2219                 result += 1;
2220         }
2221
2222         kfree(rd_buf);
2223         return result;
2224 }
2225
2226 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2227                                     size_t size, loff_t *pos)
2228 {
2229         char *rd_buf = NULL;
2230         char *rd_buf_ptr = NULL;
2231         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2232         struct display_stream_compressor *dsc;
2233         struct dcn_dsc_state dsc_state = {0};
2234         const uint32_t rd_buf_size = 100;
2235         struct pipe_ctx *pipe_ctx;
2236         ssize_t result = 0;
2237         int i, r, str_len = 30;
2238
2239         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2240
2241         if (!rd_buf)
2242                 return -ENOMEM;
2243
2244         rd_buf_ptr = rd_buf;
2245
2246         for (i = 0; i < MAX_PIPES; i++) {
2247                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2248                 if (pipe_ctx->stream &&
2249                     pipe_ctx->stream->link == aconnector->dc_link)
2250                         break;
2251         }
2252
2253         dsc = pipe_ctx->stream_res.dsc;
2254         if (dsc)
2255                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2256
2257         snprintf(rd_buf_ptr, str_len,
2258                 "%d\n",
2259                 dsc_state.dsc_pic_height);
2260         rd_buf_ptr += str_len;
2261
2262         while (size) {
2263                 if (*pos >= rd_buf_size)
2264                         break;
2265
2266                 r = put_user(*(rd_buf + result), buf);
2267                 if (r) {
2268                         kfree(rd_buf);
2269                         return r; /* r = -EFAULT */
2270                 }
2271
2272                 buf += 1;
2273                 size -= 1;
2274                 *pos += 1;
2275                 result += 1;
2276         }
2277
2278         kfree(rd_buf);
2279         return result;
2280 }
2281
2282 /* function: read DSC chunk size parameter on the connector
2283  *
2284  * The read function: dp_dsc_chunk_size_read
2285  * returns dsc chunk size set in the current configuration
2286  * The value is calculated automatically by DSC code
2287  * and depends on slice parameters and bpp target rate
2288  * The return is an integer: 0 or other positive integer
2289  * If 0 then DSC is disabled.
2290  *
2291  * Access it with the following command:
2292  *
2293  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2294  *
2295  * 0 - means that DSC is disabled
2296  */
2297 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2298                                     size_t size, loff_t *pos)
2299 {
2300         char *rd_buf = NULL;
2301         char *rd_buf_ptr = NULL;
2302         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2303         struct display_stream_compressor *dsc;
2304         struct dcn_dsc_state dsc_state = {0};
2305         const uint32_t rd_buf_size = 100;
2306         struct pipe_ctx *pipe_ctx;
2307         ssize_t result = 0;
2308         int i, r, str_len = 30;
2309
2310         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2311
2312         if (!rd_buf)
2313                 return -ENOMEM;
2314
2315         rd_buf_ptr = rd_buf;
2316
2317         for (i = 0; i < MAX_PIPES; i++) {
2318                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2319                 if (pipe_ctx->stream &&
2320                     pipe_ctx->stream->link == aconnector->dc_link)
2321                         break;
2322         }
2323
2324         dsc = pipe_ctx->stream_res.dsc;
2325         if (dsc)
2326                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2327
2328         snprintf(rd_buf_ptr, str_len,
2329                 "%d\n",
2330                 dsc_state.dsc_chunk_size);
2331         rd_buf_ptr += str_len;
2332
2333         while (size) {
2334                 if (*pos >= rd_buf_size)
2335                         break;
2336
2337                 r = put_user(*(rd_buf + result), buf);
2338                 if (r) {
2339                         kfree(rd_buf);
2340                         return r; /* r = -EFAULT */
2341                 }
2342
2343                 buf += 1;
2344                 size -= 1;
2345                 *pos += 1;
2346                 result += 1;
2347         }
2348
2349         kfree(rd_buf);
2350         return result;
2351 }
2352
2353 /* function: read DSC slice bpg offset on the connector
2354  *
2355  * The read function: dp_dsc_slice_bpg_offset_read
2356  * returns dsc bpg slice offset set in the current configuration
2357  * The value is calculated automatically by DSC code
2358  * and depends on slice parameters and bpp target rate
2359  * The return is an integer: 0 or other positive integer
2360  * If 0 then DSC is disabled.
2361  *
2362  * Access it with the following command:
2363  *
2364  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2365  *
2366  * 0 - means that DSC is disabled
2367  */
2368 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2369                                     size_t size, loff_t *pos)
2370 {
2371         char *rd_buf = NULL;
2372         char *rd_buf_ptr = NULL;
2373         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2374         struct display_stream_compressor *dsc;
2375         struct dcn_dsc_state dsc_state = {0};
2376         const uint32_t rd_buf_size = 100;
2377         struct pipe_ctx *pipe_ctx;
2378         ssize_t result = 0;
2379         int i, r, str_len = 30;
2380
2381         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2382
2383         if (!rd_buf)
2384                 return -ENOMEM;
2385
2386         rd_buf_ptr = rd_buf;
2387
2388         for (i = 0; i < MAX_PIPES; i++) {
2389                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2390                 if (pipe_ctx->stream &&
2391                     pipe_ctx->stream->link == aconnector->dc_link)
2392                         break;
2393         }
2394
2395         dsc = pipe_ctx->stream_res.dsc;
2396         if (dsc)
2397                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2398
2399         snprintf(rd_buf_ptr, str_len,
2400                 "%d\n",
2401                 dsc_state.dsc_slice_bpg_offset);
2402         rd_buf_ptr += str_len;
2403
2404         while (size) {
2405                 if (*pos >= rd_buf_size)
2406                         break;
2407
2408                 r = put_user(*(rd_buf + result), buf);
2409                 if (r) {
2410                         kfree(rd_buf);
2411                         return r; /* r = -EFAULT */
2412                 }
2413
2414                 buf += 1;
2415                 size -= 1;
2416                 *pos += 1;
2417                 result += 1;
2418         }
2419
2420         kfree(rd_buf);
2421         return result;
2422 }
2423
2424
2425 /*
2426  * function description: Read max_requested_bpc property from the connector
2427  *
2428  * Access it with the following command:
2429  *
2430  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2431  *
2432  */
2433 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2434                 size_t size, loff_t *pos)
2435 {
2436         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2437         struct drm_connector *connector = &aconnector->base;
2438         struct drm_device *dev = connector->dev;
2439         struct dm_connector_state *state;
2440         ssize_t result = 0;
2441         char *rd_buf = NULL;
2442         char *rd_buf_ptr = NULL;
2443         const uint32_t rd_buf_size = 10;
2444         int r;
2445
2446         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2447
2448         if (!rd_buf)
2449                 return -ENOMEM;
2450
2451         mutex_lock(&dev->mode_config.mutex);
2452         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2453
2454         if (connector->state == NULL)
2455                 goto unlock;
2456
2457         state = to_dm_connector_state(connector->state);
2458
2459         rd_buf_ptr = rd_buf;
2460         snprintf(rd_buf_ptr, rd_buf_size,
2461                 "%u\n",
2462                 state->base.max_requested_bpc);
2463
2464         while (size) {
2465                 if (*pos >= rd_buf_size)
2466                         break;
2467
2468                 r = put_user(*(rd_buf + result), buf);
2469                 if (r) {
2470                         result = r; /* r = -EFAULT */
2471                         goto unlock;
2472                 }
2473                 buf += 1;
2474                 size -= 1;
2475                 *pos += 1;
2476                 result += 1;
2477         }
2478 unlock:
2479         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2480         mutex_unlock(&dev->mode_config.mutex);
2481         kfree(rd_buf);
2482         return result;
2483 }
2484
2485
2486 /*
2487  * function description: Set max_requested_bpc property on the connector
2488  *
2489  * This function will not force the input BPC on connector, it will only
2490  * change the max value. This is equivalent to setting max_bpc through
2491  * xrandr.
2492  *
2493  * The BPC value written must be >= 6 and <= 16. Values outside of this
2494  * range will result in errors.
2495  *
2496  * BPC values:
2497  *      0x6 - 6 BPC
2498  *      0x8 - 8 BPC
2499  *      0xa - 10 BPC
2500  *      0xc - 12 BPC
2501  *      0x10 - 16 BPC
2502  *
2503  * Write the max_bpc in the following way:
2504  *
2505  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2506  *
2507  */
2508 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2509                                      size_t size, loff_t *pos)
2510 {
2511         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2512         struct drm_connector *connector = &aconnector->base;
2513         struct dm_connector_state *state;
2514         struct drm_device *dev = connector->dev;
2515         char *wr_buf = NULL;
2516         uint32_t wr_buf_size = 42;
2517         int max_param_num = 1;
2518         long param[1] = {0};
2519         uint8_t param_nums = 0;
2520
2521         if (size == 0)
2522                 return -EINVAL;
2523
2524         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2525
2526         if (!wr_buf) {
2527                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2528                 return -ENOSPC;
2529         }
2530
2531         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2532                                            (long *)param, buf,
2533                                            max_param_num,
2534                                            &param_nums)) {
2535                 kfree(wr_buf);
2536                 return -EINVAL;
2537         }
2538
2539         if (param_nums <= 0) {
2540                 DRM_DEBUG_DRIVER("user data not be read\n");
2541                 kfree(wr_buf);
2542                 return -EINVAL;
2543         }
2544
2545         if (param[0] < 6 || param[0] > 16) {
2546                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2547                 kfree(wr_buf);
2548                 return -EINVAL;
2549         }
2550
2551         mutex_lock(&dev->mode_config.mutex);
2552         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2553
2554         if (connector->state == NULL)
2555                 goto unlock;
2556
2557         state = to_dm_connector_state(connector->state);
2558         state->base.max_requested_bpc = param[0];
2559 unlock:
2560         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2561         mutex_unlock(&dev->mode_config.mutex);
2562
2563         kfree(wr_buf);
2564         return size;
2565 }
2566
2567 /*
2568  * Backlight at this moment.  Read only.
2569  * As written to display, taking ABM and backlight lut into account.
2570  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2571  *
2572  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2573  */
2574 static int current_backlight_show(struct seq_file *m, void *unused)
2575 {
2576         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2577         struct dc_link *link = aconnector->dc_link;
2578         unsigned int backlight;
2579
2580         backlight = dc_link_get_backlight_level(link);
2581         seq_printf(m, "0x%x\n", backlight);
2582
2583         return 0;
2584 }
2585
2586 /*
2587  * Backlight value that is being approached.  Read only.
2588  * As written to display, taking ABM and backlight lut into account.
2589  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2590  *
2591  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2592  */
2593 static int target_backlight_show(struct seq_file *m, void *unused)
2594 {
2595         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2596         struct dc_link *link = aconnector->dc_link;
2597         unsigned int backlight;
2598
2599         backlight = dc_link_get_target_backlight_pwm(link);
2600         seq_printf(m, "0x%x\n", backlight);
2601
2602         return 0;
2603 }
2604
2605 /*
2606  * function description: Determine if the connector is mst connector
2607  *
2608  * This function helps to determine whether a connector is a mst connector.
2609  * - "root" stands for the root connector of the topology
2610  * - "branch" stands for branch device of the topology
2611  * - "end" stands for leaf node connector of the topology
2612  * - "no" stands for the connector is not a device of a mst topology
2613  * Access it with the following command:
2614  *
2615  *      cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2616  *
2617  */
2618 static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2619 {
2620         struct drm_connector *connector = m->private;
2621         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2622         struct drm_dp_mst_topology_mgr *mgr = NULL;
2623         struct drm_dp_mst_port *port = NULL;
2624         char *role = NULL;
2625
2626         mutex_lock(&aconnector->hpd_lock);
2627
2628         if (aconnector->mst_mgr.mst_state) {
2629                 role = "root";
2630         } else if (aconnector->mst_root &&
2631                 aconnector->mst_root->mst_mgr.mst_state) {
2632
2633                 role = "end";
2634
2635                 mgr = &aconnector->mst_root->mst_mgr;
2636                 port = aconnector->mst_output_port;
2637
2638                 drm_modeset_lock(&mgr->base.lock, NULL);
2639                 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2640                         port->mcs)
2641                         role = "branch";
2642                 drm_modeset_unlock(&mgr->base.lock);
2643
2644         } else {
2645                 role = "no";
2646         }
2647
2648         seq_printf(m, "%s\n", role);
2649
2650         mutex_unlock(&aconnector->hpd_lock);
2651
2652         return 0;
2653 }
2654
2655 /*
2656  * function description: Read out the mst progress status
2657  *
2658  * This function helps to determine the mst progress status of
2659  * a mst connector.
2660  *
2661  * Access it with the following command:
2662  *
2663  *      cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2664  *
2665  */
2666 static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2667 {
2668         struct drm_connector *connector = m->private;
2669         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2670         struct amdgpu_device *adev = drm_to_adev(connector->dev);
2671         int i;
2672
2673         mutex_lock(&aconnector->hpd_lock);
2674         mutex_lock(&adev->dm.dc_lock);
2675
2676         if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2677                 seq_puts(m, "disabled\n");
2678         } else {
2679                 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2680                         seq_printf(m, "%s:%s\n",
2681                                 mst_progress_status[i],
2682                                 aconnector->mst_status & BIT(i) ? "done" : "not_done");
2683         }
2684
2685         mutex_unlock(&adev->dm.dc_lock);
2686         mutex_unlock(&aconnector->hpd_lock);
2687
2688         return 0;
2689 }
2690
2691 /*
2692  * Reports whether the connected display is a USB4 DPIA tunneled display
2693  * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2694  */
2695 static int is_dpia_link_show(struct seq_file *m, void *data)
2696 {
2697         struct drm_connector *connector = m->private;
2698         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2699         struct dc_link *link = aconnector->dc_link;
2700
2701         if (connector->status != connector_status_connected)
2702                 return -ENODEV;
2703
2704         seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2705                                 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2706
2707         return 0;
2708 }
2709
2710 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2711 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2712 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2713 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2714 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2715 DEFINE_SHOW_ATTRIBUTE(internal_display);
2716 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2717 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2718 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2719 DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
2720
2721 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2722         .owner = THIS_MODULE,
2723         .read = dp_dsc_clock_en_read,
2724         .write = dp_dsc_clock_en_write,
2725         .llseek = default_llseek
2726 };
2727
2728 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2729         .owner = THIS_MODULE,
2730         .read = dp_dsc_slice_width_read,
2731         .write = dp_dsc_slice_width_write,
2732         .llseek = default_llseek
2733 };
2734
2735 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2736         .owner = THIS_MODULE,
2737         .read = dp_dsc_slice_height_read,
2738         .write = dp_dsc_slice_height_write,
2739         .llseek = default_llseek
2740 };
2741
2742 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2743         .owner = THIS_MODULE,
2744         .read = dp_dsc_bits_per_pixel_read,
2745         .write = dp_dsc_bits_per_pixel_write,
2746         .llseek = default_llseek
2747 };
2748
2749 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2750         .owner = THIS_MODULE,
2751         .read = dp_dsc_pic_width_read,
2752         .llseek = default_llseek
2753 };
2754
2755 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2756         .owner = THIS_MODULE,
2757         .read = dp_dsc_pic_height_read,
2758         .llseek = default_llseek
2759 };
2760
2761 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2762         .owner = THIS_MODULE,
2763         .read = dp_dsc_chunk_size_read,
2764         .llseek = default_llseek
2765 };
2766
2767 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2768         .owner = THIS_MODULE,
2769         .read = dp_dsc_slice_bpg_offset_read,
2770         .llseek = default_llseek
2771 };
2772
2773 static const struct file_operations trigger_hotplug_debugfs_fops = {
2774         .owner = THIS_MODULE,
2775         .write = trigger_hotplug,
2776         .llseek = default_llseek
2777 };
2778
2779 static const struct file_operations dp_link_settings_debugfs_fops = {
2780         .owner = THIS_MODULE,
2781         .read = dp_link_settings_read,
2782         .write = dp_link_settings_write,
2783         .llseek = default_llseek
2784 };
2785
2786 static const struct file_operations dp_phy_settings_debugfs_fop = {
2787         .owner = THIS_MODULE,
2788         .read = dp_phy_settings_read,
2789         .write = dp_phy_settings_write,
2790         .llseek = default_llseek
2791 };
2792
2793 static const struct file_operations dp_phy_test_pattern_fops = {
2794         .owner = THIS_MODULE,
2795         .write = dp_phy_test_pattern_debugfs_write,
2796         .llseek = default_llseek
2797 };
2798
2799 static const struct file_operations sdp_message_fops = {
2800         .owner = THIS_MODULE,
2801         .write = dp_sdp_message_debugfs_write,
2802         .llseek = default_llseek
2803 };
2804
2805 static const struct file_operations dp_max_bpc_debugfs_fops = {
2806         .owner = THIS_MODULE,
2807         .read = dp_max_bpc_read,
2808         .write = dp_max_bpc_write,
2809         .llseek = default_llseek
2810 };
2811
2812 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2813         .owner = THIS_MODULE,
2814         .write = dp_dsc_passthrough_set,
2815         .llseek = default_llseek
2816 };
2817
2818 static const struct file_operations dp_mst_link_settings_debugfs_fops = {
2819         .owner = THIS_MODULE,
2820         .write = dp_mst_link_setting,
2821         .llseek = default_llseek
2822 };
2823
2824 static const struct {
2825         char *name;
2826         const struct file_operations *fops;
2827 } dp_debugfs_entries[] = {
2828                 {"link_settings", &dp_link_settings_debugfs_fops},
2829                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2830                 {"lttpr_status", &dp_lttpr_status_fops},
2831                 {"test_pattern", &dp_phy_test_pattern_fops},
2832                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2833                 {"sdp_message", &sdp_message_fops},
2834                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2835                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2836                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2837                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2838                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2839                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2840                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2841                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2842                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2843                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2844                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2845                 {"is_mst_connector", &dp_is_mst_connector_fops},
2846                 {"mst_progress_status", &dp_mst_progress_status_fops},
2847                 {"is_dpia_link", &is_dpia_link_fops},
2848                 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops}
2849 };
2850
2851 static const struct {
2852         char *name;
2853         const struct file_operations *fops;
2854 } hdmi_debugfs_entries[] = {
2855                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2856 };
2857
2858 /*
2859  * Force YUV420 output if available from the given mode
2860  */
2861 static int force_yuv420_output_set(void *data, u64 val)
2862 {
2863         struct amdgpu_dm_connector *connector = data;
2864
2865         connector->force_yuv420_output = (bool)val;
2866
2867         return 0;
2868 }
2869
2870 /*
2871  * Check if YUV420 is forced when available from the given mode
2872  */
2873 static int force_yuv420_output_get(void *data, u64 *val)
2874 {
2875         struct amdgpu_dm_connector *connector = data;
2876
2877         *val = connector->force_yuv420_output;
2878
2879         return 0;
2880 }
2881
2882 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2883                          force_yuv420_output_set, "%llu\n");
2884
2885 /*
2886  *  Read PSR state
2887  */
2888 static int psr_get(void *data, u64 *val)
2889 {
2890         struct amdgpu_dm_connector *connector = data;
2891         struct dc_link *link = connector->dc_link;
2892         enum dc_psr_state state = PSR_STATE0;
2893
2894         dc_link_get_psr_state(link, &state);
2895
2896         *val = state;
2897
2898         return 0;
2899 }
2900
2901 /*
2902  *  Read PSR state residency
2903  */
2904 static int psr_read_residency(void *data, u64 *val)
2905 {
2906         struct amdgpu_dm_connector *connector = data;
2907         struct dc_link *link = connector->dc_link;
2908         u32 residency;
2909
2910         link->dc->link_srv->edp_get_psr_residency(link, &residency);
2911
2912         *val = (u64)residency;
2913
2914         return 0;
2915 }
2916
2917 /* read allow_edp_hotplug_detection */
2918 static int allow_edp_hotplug_detection_get(void *data, u64 *val)
2919 {
2920         struct amdgpu_dm_connector *aconnector = data;
2921         struct drm_connector *connector = &aconnector->base;
2922         struct drm_device *dev = connector->dev;
2923         struct amdgpu_device *adev = drm_to_adev(dev);
2924
2925         *val = adev->dm.dc->config.allow_edp_hotplug_detection;
2926
2927         return 0;
2928 }
2929
2930 /* set allow_edp_hotplug_detection */
2931 static int allow_edp_hotplug_detection_set(void *data, u64 val)
2932 {
2933         struct amdgpu_dm_connector *aconnector = data;
2934         struct drm_connector *connector = &aconnector->base;
2935         struct drm_device *dev = connector->dev;
2936         struct amdgpu_device *adev = drm_to_adev(dev);
2937
2938         adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
2939
2940         return 0;
2941 }
2942
2943 /*
2944  * Set dmcub trace event IRQ enable or disable.
2945  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2946  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2947  */
2948 static int dmcub_trace_event_state_set(void *data, u64 val)
2949 {
2950         struct amdgpu_device *adev = data;
2951
2952         if (val == 1 || val == 0) {
2953                 dc_dmub_trace_event_control(adev->dm.dc, val);
2954                 adev->dm.dmcub_trace_event_en = (bool)val;
2955         } else
2956                 return 0;
2957
2958         return 0;
2959 }
2960
2961 /*
2962  * The interface doesn't need get function, so it will return the
2963  * value of zero
2964  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2965  */
2966 static int dmcub_trace_event_state_get(void *data, u64 *val)
2967 {
2968         struct amdgpu_device *adev = data;
2969
2970         *val = adev->dm.dmcub_trace_event_en;
2971         return 0;
2972 }
2973
2974 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2975                          dmcub_trace_event_state_set, "%llu\n");
2976
2977 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2978 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
2979                          "%llu\n");
2980
2981 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
2982                         allow_edp_hotplug_detection_get,
2983                         allow_edp_hotplug_detection_set, "%llu\n");
2984
2985 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2986 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2987
2988 static const struct {
2989         char *name;
2990         const struct file_operations *fops;
2991 } connector_debugfs_entries[] = {
2992                 {"force_yuv420_output", &force_yuv420_output_fops},
2993                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
2994                 {"internal_display", &internal_display_fops}
2995 };
2996
2997 /*
2998  * Returns supported customized link rates by this eDP panel.
2999  * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3000  */
3001 static int edp_ilr_show(struct seq_file *m, void *unused)
3002 {
3003         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
3004         struct dc_link *link = aconnector->dc_link;
3005         uint8_t supported_link_rates[16];
3006         uint32_t link_rate_in_khz;
3007         uint32_t entry = 0;
3008         uint8_t dpcd_rev;
3009
3010         memset(supported_link_rates, 0, sizeof(supported_link_rates));
3011         dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3012                 supported_link_rates, sizeof(supported_link_rates));
3013
3014         dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3015
3016         if (dpcd_rev >= DP_DPCD_REV_13 &&
3017                 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
3018
3019                 for (entry = 0; entry < 16; entry += 2) {
3020                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3021                                                                                 supported_link_rates[entry]) * 200;
3022                         seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
3023                 }
3024         } else {
3025                 seq_puts(m, "ILR is not supported by this eDP panel.\n");
3026         }
3027
3028         return 0;
3029 }
3030
3031 /*
3032  * Set supported customized link rate to eDP panel.
3033  *
3034  * echo <lane_count>  <link_rate option> > ilr_setting
3035  *
3036  * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
3037  * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3038  * to set 4 lanes and 2.16 GHz
3039  */
3040 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
3041                                  size_t size, loff_t *pos)
3042 {
3043         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
3044         struct dc_link *link = connector->dc_link;
3045         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3046         struct dc *dc = (struct dc *)link->dc;
3047         struct dc_link_settings prefer_link_settings;
3048         char *wr_buf = NULL;
3049         const uint32_t wr_buf_size = 40;
3050         /* 0: lane_count; 1: link_rate */
3051         int max_param_num = 2;
3052         uint8_t param_nums = 0;
3053         long param[2];
3054         bool valid_input = true;
3055
3056         if (size == 0)
3057                 return -EINVAL;
3058
3059         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3060         if (!wr_buf)
3061                 return -ENOMEM;
3062
3063         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3064                                            (long *)param, buf,
3065                                            max_param_num,
3066                                            &param_nums)) {
3067                 kfree(wr_buf);
3068                 return -EINVAL;
3069         }
3070
3071         if (param_nums <= 0) {
3072                 kfree(wr_buf);
3073                 return -EINVAL;
3074         }
3075
3076         switch (param[0]) {
3077         case LANE_COUNT_ONE:
3078         case LANE_COUNT_TWO:
3079         case LANE_COUNT_FOUR:
3080                 break;
3081         default:
3082                 valid_input = false;
3083                 break;
3084         }
3085
3086         if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
3087                 valid_input = false;
3088
3089         if (!valid_input) {
3090                 kfree(wr_buf);
3091                 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
3092                 prefer_link_settings.use_link_rate_set = false;
3093                 mutex_lock(&adev->dm.dc_lock);
3094                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
3095                 mutex_unlock(&adev->dm.dc_lock);
3096                 return size;
3097         }
3098
3099         /* save user force lane_count, link_rate to preferred settings
3100          * spread spectrum will not be changed
3101          */
3102         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
3103         prefer_link_settings.lane_count = param[0];
3104         prefer_link_settings.use_link_rate_set = true;
3105         prefer_link_settings.link_rate_set = param[1];
3106         prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
3107
3108         mutex_lock(&adev->dm.dc_lock);
3109         dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
3110                                                 NULL, link, false);
3111         mutex_unlock(&adev->dm.dc_lock);
3112
3113         kfree(wr_buf);
3114         return size;
3115 }
3116
3117 static int edp_ilr_open(struct inode *inode, struct file *file)
3118 {
3119         return single_open(file, edp_ilr_show, inode->i_private);
3120 }
3121
3122 static const struct file_operations edp_ilr_debugfs_fops = {
3123         .owner = THIS_MODULE,
3124         .open = edp_ilr_open,
3125         .read = seq_read,
3126         .llseek = seq_lseek,
3127         .release = single_release,
3128         .write = edp_ilr_write
3129 };
3130
3131 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3132 {
3133         int i;
3134         struct dentry *dir = connector->base.debugfs_entry;
3135
3136         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3137             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3138                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3139                         debugfs_create_file(dp_debugfs_entries[i].name,
3140                                             0644, dir, connector,
3141                                             dp_debugfs_entries[i].fops);
3142                 }
3143         }
3144         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3145                 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3146                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3147                 debugfs_create_file_unsafe("psr_residency", 0444, dir,
3148                                            connector, &psr_residency_fops);
3149                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3150                                     &current_backlight_fops);
3151                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3152                                     &target_backlight_fops);
3153                 debugfs_create_file("ilr_setting", 0644, dir, connector,
3154                                         &edp_ilr_debugfs_fops);
3155                 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3156                                         &allow_edp_hotplug_detection_fops);
3157         }
3158
3159         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3160                 debugfs_create_file(connector_debugfs_entries[i].name,
3161                                     0644, dir, connector,
3162                                     connector_debugfs_entries[i].fops);
3163         }
3164
3165         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3166                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3167                         debugfs_create_file(hdmi_debugfs_entries[i].name,
3168                                             0644, dir, connector,
3169                                             hdmi_debugfs_entries[i].fops);
3170                 }
3171         }
3172 }
3173
3174 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3175 /*
3176  * Set crc window coordinate x start
3177  */
3178 static int crc_win_x_start_set(void *data, u64 val)
3179 {
3180         struct drm_crtc *crtc = data;
3181         struct drm_device *drm_dev = crtc->dev;
3182         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3183
3184         spin_lock_irq(&drm_dev->event_lock);
3185         acrtc->dm_irq_params.window_param.x_start = (uint16_t) val;
3186         acrtc->dm_irq_params.window_param.update_win = false;
3187         spin_unlock_irq(&drm_dev->event_lock);
3188
3189         return 0;
3190 }
3191
3192 /*
3193  * Get crc window coordinate x start
3194  */
3195 static int crc_win_x_start_get(void *data, u64 *val)
3196 {
3197         struct drm_crtc *crtc = data;
3198         struct drm_device *drm_dev = crtc->dev;
3199         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3200
3201         spin_lock_irq(&drm_dev->event_lock);
3202         *val = acrtc->dm_irq_params.window_param.x_start;
3203         spin_unlock_irq(&drm_dev->event_lock);
3204
3205         return 0;
3206 }
3207
3208 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3209                          crc_win_x_start_set, "%llu\n");
3210
3211
3212 /*
3213  * Set crc window coordinate y start
3214  */
3215 static int crc_win_y_start_set(void *data, u64 val)
3216 {
3217         struct drm_crtc *crtc = data;
3218         struct drm_device *drm_dev = crtc->dev;
3219         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3220
3221         spin_lock_irq(&drm_dev->event_lock);
3222         acrtc->dm_irq_params.window_param.y_start = (uint16_t) val;
3223         acrtc->dm_irq_params.window_param.update_win = false;
3224         spin_unlock_irq(&drm_dev->event_lock);
3225
3226         return 0;
3227 }
3228
3229 /*
3230  * Get crc window coordinate y start
3231  */
3232 static int crc_win_y_start_get(void *data, u64 *val)
3233 {
3234         struct drm_crtc *crtc = data;
3235         struct drm_device *drm_dev = crtc->dev;
3236         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3237
3238         spin_lock_irq(&drm_dev->event_lock);
3239         *val = acrtc->dm_irq_params.window_param.y_start;
3240         spin_unlock_irq(&drm_dev->event_lock);
3241
3242         return 0;
3243 }
3244
3245 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3246                          crc_win_y_start_set, "%llu\n");
3247
3248 /*
3249  * Set crc window coordinate x end
3250  */
3251 static int crc_win_x_end_set(void *data, u64 val)
3252 {
3253         struct drm_crtc *crtc = data;
3254         struct drm_device *drm_dev = crtc->dev;
3255         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3256
3257         spin_lock_irq(&drm_dev->event_lock);
3258         acrtc->dm_irq_params.window_param.x_end = (uint16_t) val;
3259         acrtc->dm_irq_params.window_param.update_win = false;
3260         spin_unlock_irq(&drm_dev->event_lock);
3261
3262         return 0;
3263 }
3264
3265 /*
3266  * Get crc window coordinate x end
3267  */
3268 static int crc_win_x_end_get(void *data, u64 *val)
3269 {
3270         struct drm_crtc *crtc = data;
3271         struct drm_device *drm_dev = crtc->dev;
3272         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3273
3274         spin_lock_irq(&drm_dev->event_lock);
3275         *val = acrtc->dm_irq_params.window_param.x_end;
3276         spin_unlock_irq(&drm_dev->event_lock);
3277
3278         return 0;
3279 }
3280
3281 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3282                          crc_win_x_end_set, "%llu\n");
3283
3284 /*
3285  * Set crc window coordinate y end
3286  */
3287 static int crc_win_y_end_set(void *data, u64 val)
3288 {
3289         struct drm_crtc *crtc = data;
3290         struct drm_device *drm_dev = crtc->dev;
3291         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3292
3293         spin_lock_irq(&drm_dev->event_lock);
3294         acrtc->dm_irq_params.window_param.y_end = (uint16_t) val;
3295         acrtc->dm_irq_params.window_param.update_win = false;
3296         spin_unlock_irq(&drm_dev->event_lock);
3297
3298         return 0;
3299 }
3300
3301 /*
3302  * Get crc window coordinate y end
3303  */
3304 static int crc_win_y_end_get(void *data, u64 *val)
3305 {
3306         struct drm_crtc *crtc = data;
3307         struct drm_device *drm_dev = crtc->dev;
3308         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3309
3310         spin_lock_irq(&drm_dev->event_lock);
3311         *val = acrtc->dm_irq_params.window_param.y_end;
3312         spin_unlock_irq(&drm_dev->event_lock);
3313
3314         return 0;
3315 }
3316
3317 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3318                          crc_win_y_end_set, "%llu\n");
3319 /*
3320  * Trigger to commit crc window
3321  */
3322 static int crc_win_update_set(void *data, u64 val)
3323 {
3324         struct drm_crtc *crtc = data;
3325         struct amdgpu_crtc *acrtc;
3326         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3327
3328         if (val) {
3329                 acrtc = to_amdgpu_crtc(crtc);
3330                 mutex_lock(&adev->dm.dc_lock);
3331                 /* PSR may write to OTG CRC window control register,
3332                  * so close it before starting secure_display.
3333                  */
3334                 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream);
3335
3336                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3337
3338                 acrtc->dm_irq_params.window_param.activated = true;
3339                 acrtc->dm_irq_params.window_param.update_win = true;
3340                 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
3341
3342                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3343                 mutex_unlock(&adev->dm.dc_lock);
3344         }
3345
3346         return 0;
3347 }
3348
3349 /*
3350  * Get crc window update flag
3351  */
3352 static int crc_win_update_get(void *data, u64 *val)
3353 {
3354         *val = 0;
3355         return 0;
3356 }
3357
3358 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3359                          crc_win_update_set, "%llu\n");
3360 #endif
3361 void crtc_debugfs_init(struct drm_crtc *crtc)
3362 {
3363 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3364         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3365
3366         if (!dir)
3367                 return;
3368
3369         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3370                                    &crc_win_x_start_fops);
3371         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3372                                    &crc_win_y_start_fops);
3373         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3374                                    &crc_win_x_end_fops);
3375         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3376                                    &crc_win_y_end_fops);
3377         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3378                                    &crc_win_update_fops);
3379         dput(dir);
3380 #endif
3381         debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3382                             crtc, &amdgpu_current_bpc_fops);
3383         debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry,
3384                             crtc, &amdgpu_current_colorspace_fops);
3385 }
3386
3387 /*
3388  * Writes DTN log state to the user supplied buffer.
3389  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3390  */
3391 static ssize_t dtn_log_read(
3392         struct file *f,
3393         char __user *buf,
3394         size_t size,
3395         loff_t *pos)
3396 {
3397         struct amdgpu_device *adev = file_inode(f)->i_private;
3398         struct dc *dc = adev->dm.dc;
3399         struct dc_log_buffer_ctx log_ctx = { 0 };
3400         ssize_t result = 0;
3401
3402         if (!buf || !size)
3403                 return -EINVAL;
3404
3405         if (!dc->hwss.log_hw_state)
3406                 return 0;
3407
3408         dc->hwss.log_hw_state(dc, &log_ctx);
3409
3410         if (*pos < log_ctx.pos) {
3411                 size_t to_copy = log_ctx.pos - *pos;
3412
3413                 to_copy = min(to_copy, size);
3414
3415                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3416                         *pos += to_copy;
3417                         result = to_copy;
3418                 }
3419         }
3420
3421         kfree(log_ctx.buf);
3422
3423         return result;
3424 }
3425
3426 /*
3427  * Writes DTN log state to dmesg when triggered via a write.
3428  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3429  */
3430 static ssize_t dtn_log_write(
3431         struct file *f,
3432         const char __user *buf,
3433         size_t size,
3434         loff_t *pos)
3435 {
3436         struct amdgpu_device *adev = file_inode(f)->i_private;
3437         struct dc *dc = adev->dm.dc;
3438
3439         /* Write triggers log output via dmesg. */
3440         if (size == 0)
3441                 return 0;
3442
3443         if (dc->hwss.log_hw_state)
3444                 dc->hwss.log_hw_state(dc, NULL);
3445
3446         return size;
3447 }
3448
3449 static int mst_topo_show(struct seq_file *m, void *unused)
3450 {
3451         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3452         struct drm_device *dev = adev_to_drm(adev);
3453         struct drm_connector *connector;
3454         struct drm_connector_list_iter conn_iter;
3455         struct amdgpu_dm_connector *aconnector;
3456
3457         drm_connector_list_iter_begin(dev, &conn_iter);
3458         drm_for_each_connector_iter(connector, &conn_iter) {
3459                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3460                         continue;
3461
3462                 aconnector = to_amdgpu_dm_connector(connector);
3463
3464                 /* Ensure we're only dumping the topology of a root mst node */
3465                 if (!aconnector->mst_mgr.mst_state)
3466                         continue;
3467
3468                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3469                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3470         }
3471         drm_connector_list_iter_end(&conn_iter);
3472
3473         return 0;
3474 }
3475
3476 /*
3477  * Sets trigger hpd for MST topologies.
3478  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3479  * All topologies will be disconnected if val of 0 is set .
3480  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3481  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3482  */
3483 static int trigger_hpd_mst_set(void *data, u64 val)
3484 {
3485         struct amdgpu_device *adev = data;
3486         struct drm_device *dev = adev_to_drm(adev);
3487         struct drm_connector_list_iter iter;
3488         struct amdgpu_dm_connector *aconnector;
3489         struct drm_connector *connector;
3490         struct dc_link *link = NULL;
3491
3492         if (val == 1) {
3493                 drm_connector_list_iter_begin(dev, &iter);
3494                 drm_for_each_connector_iter(connector, &iter) {
3495                         aconnector = to_amdgpu_dm_connector(connector);
3496                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3497                             aconnector->mst_mgr.aux) {
3498                                 mutex_lock(&adev->dm.dc_lock);
3499                                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3500                                 mutex_unlock(&adev->dm.dc_lock);
3501
3502                                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3503                         }
3504                 }
3505         } else if (val == 0) {
3506                 drm_connector_list_iter_begin(dev, &iter);
3507                 drm_for_each_connector_iter(connector, &iter) {
3508                         aconnector = to_amdgpu_dm_connector(connector);
3509                         if (!aconnector->dc_link)
3510                                 continue;
3511
3512                         if (!aconnector->mst_root)
3513                                 continue;
3514
3515                         link = aconnector->dc_link;
3516                         dc_link_dp_receiver_power_ctrl(link, false);
3517                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
3518                         link->mst_stream_alloc_table.stream_count = 0;
3519                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3520                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3521                 }
3522         } else {
3523                 return 0;
3524         }
3525         drm_kms_helper_hotplug_event(dev);
3526
3527         return 0;
3528 }
3529
3530 /*
3531  * The interface doesn't need get function, so it will return the
3532  * value of zero
3533  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3534  */
3535 static int trigger_hpd_mst_get(void *data, u64 *val)
3536 {
3537         *val = 0;
3538         return 0;
3539 }
3540
3541 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3542                          trigger_hpd_mst_set, "%llu\n");
3543
3544
3545 /*
3546  * Sets the force_timing_sync debug option from the given string.
3547  * All connected displays will be force synchronized immediately.
3548  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3549  */
3550 static int force_timing_sync_set(void *data, u64 val)
3551 {
3552         struct amdgpu_device *adev = data;
3553
3554         adev->dm.force_timing_sync = (bool)val;
3555
3556         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3557
3558         return 0;
3559 }
3560
3561 /*
3562  * Gets the force_timing_sync debug option value into the given buffer.
3563  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3564  */
3565 static int force_timing_sync_get(void *data, u64 *val)
3566 {
3567         struct amdgpu_device *adev = data;
3568
3569         *val = adev->dm.force_timing_sync;
3570
3571         return 0;
3572 }
3573
3574 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3575                          force_timing_sync_set, "%llu\n");
3576
3577
3578 /*
3579  * Disables all HPD and HPD RX interrupt handling in the
3580  * driver when set to 1. Default is 0.
3581  */
3582 static int disable_hpd_set(void *data, u64 val)
3583 {
3584         struct amdgpu_device *adev = data;
3585
3586         adev->dm.disable_hpd_irq = (bool)val;
3587
3588         return 0;
3589 }
3590
3591
3592 /*
3593  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3594  * 0 otherwise.
3595  */
3596 static int disable_hpd_get(void *data, u64 *val)
3597 {
3598         struct amdgpu_device *adev = data;
3599
3600         *val = adev->dm.disable_hpd_irq;
3601
3602         return 0;
3603 }
3604
3605 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3606                          disable_hpd_set, "%llu\n");
3607
3608 /*
3609  * Temporary w/a to force sst sequence in M42D DP2 mst receiver
3610  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
3611  */
3612 static int dp_force_sst_set(void *data, u64 val)
3613 {
3614         struct amdgpu_device *adev = data;
3615
3616         adev->dm.dc->debug.set_mst_en_for_sst = val;
3617
3618         return 0;
3619 }
3620
3621 static int dp_force_sst_get(void *data, u64 *val)
3622 {
3623         struct amdgpu_device *adev = data;
3624
3625         *val = adev->dm.dc->debug.set_mst_en_for_sst;
3626
3627         return 0;
3628 }
3629 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
3630                          dp_force_sst_set, "%llu\n");
3631
3632 /*
3633  * Force DP2 sequence without VESA certified cable.
3634  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
3635  */
3636 static int dp_ignore_cable_id_set(void *data, u64 val)
3637 {
3638         struct amdgpu_device *adev = data;
3639
3640         adev->dm.dc->debug.ignore_cable_id = val;
3641
3642         return 0;
3643 }
3644
3645 static int dp_ignore_cable_id_get(void *data, u64 *val)
3646 {
3647         struct amdgpu_device *adev = data;
3648
3649         *val = adev->dm.dc->debug.ignore_cable_id;
3650
3651         return 0;
3652 }
3653 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
3654                          dp_ignore_cable_id_set, "%llu\n");
3655
3656 /*
3657  * Sets the DC visual confirm debug option from the given string.
3658  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3659  */
3660 static int visual_confirm_set(void *data, u64 val)
3661 {
3662         struct amdgpu_device *adev = data;
3663
3664         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3665
3666         return 0;
3667 }
3668
3669 /*
3670  * Reads the DC visual confirm debug option value into the given buffer.
3671  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3672  */
3673 static int visual_confirm_get(void *data, u64 *val)
3674 {
3675         struct amdgpu_device *adev = data;
3676
3677         *val = adev->dm.dc->debug.visual_confirm;
3678
3679         return 0;
3680 }
3681
3682 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3683 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3684                          visual_confirm_set, "%llu\n");
3685
3686
3687 /*
3688  * Sets the DC skip_detection_link_training debug option from the given string.
3689  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
3690  */
3691 static int skip_detection_link_training_set(void *data, u64 val)
3692 {
3693         struct amdgpu_device *adev = data;
3694
3695         if (val == 0)
3696                 adev->dm.dc->debug.skip_detection_link_training = false;
3697         else
3698                 adev->dm.dc->debug.skip_detection_link_training = true;
3699
3700         return 0;
3701 }
3702
3703 /*
3704  * Reads the DC skip_detection_link_training debug option value into the given buffer.
3705  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
3706  */
3707 static int skip_detection_link_training_get(void *data, u64 *val)
3708 {
3709         struct amdgpu_device *adev = data;
3710
3711         *val = adev->dm.dc->debug.skip_detection_link_training;
3712
3713         return 0;
3714 }
3715
3716 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
3717                          skip_detection_link_training_get,
3718                          skip_detection_link_training_set, "%llu\n");
3719
3720 /*
3721  * Dumps the DCC_EN bit for each pipe.
3722  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3723  */
3724 static ssize_t dcc_en_bits_read(
3725         struct file *f,
3726         char __user *buf,
3727         size_t size,
3728         loff_t *pos)
3729 {
3730         struct amdgpu_device *adev = file_inode(f)->i_private;
3731         struct dc *dc = adev->dm.dc;
3732         char *rd_buf = NULL;
3733         const uint32_t rd_buf_size = 32;
3734         uint32_t result = 0;
3735         int offset = 0;
3736         int num_pipes = dc->res_pool->pipe_count;
3737         int *dcc_en_bits;
3738         int i, r;
3739
3740         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3741         if (!dcc_en_bits)
3742                 return -ENOMEM;
3743
3744         if (!dc->hwss.get_dcc_en_bits) {
3745                 kfree(dcc_en_bits);
3746                 return 0;
3747         }
3748
3749         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3750
3751         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3752         if (!rd_buf) {
3753                 kfree(dcc_en_bits);
3754                 return -ENOMEM;
3755         }
3756
3757         for (i = 0; i < num_pipes; i++)
3758                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3759                                    "%d  ", dcc_en_bits[i]);
3760         rd_buf[strlen(rd_buf)] = '\n';
3761
3762         kfree(dcc_en_bits);
3763
3764         while (size) {
3765                 if (*pos >= rd_buf_size)
3766                         break;
3767                 r = put_user(*(rd_buf + result), buf);
3768                 if (r) {
3769                         kfree(rd_buf);
3770                         return r; /* r = -EFAULT */
3771                 }
3772                 buf += 1;
3773                 size -= 1;
3774                 *pos += 1;
3775                 result += 1;
3776         }
3777
3778         kfree(rd_buf);
3779         return result;
3780 }
3781
3782 void dtn_debugfs_init(struct amdgpu_device *adev)
3783 {
3784         static const struct file_operations dtn_log_fops = {
3785                 .owner = THIS_MODULE,
3786                 .read = dtn_log_read,
3787                 .write = dtn_log_write,
3788                 .llseek = default_llseek
3789         };
3790         static const struct file_operations dcc_en_bits_fops = {
3791                 .owner = THIS_MODULE,
3792                 .read = dcc_en_bits_read,
3793                 .llseek = default_llseek
3794         };
3795
3796         struct drm_minor *minor = adev_to_drm(adev)->primary;
3797         struct dentry *root = minor->debugfs_root;
3798
3799         debugfs_create_file("amdgpu_mst_topology", 0444, root,
3800                             adev, &mst_topo_fops);
3801         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
3802                             &dtn_log_fops);
3803         debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
3804                                 &dp_set_mst_en_for_sst_ops);
3805         debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
3806                                 &dp_ignore_cable_id_ops);
3807
3808         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
3809                                    &visual_confirm_fops);
3810
3811         debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
3812                                    &skip_detection_link_training_fops);
3813
3814         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3815                                    adev, &dmub_tracebuffer_fops);
3816
3817         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3818                                    adev, &dmub_fw_state_fops);
3819
3820         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3821                                    adev, &force_timing_sync_ops);
3822
3823         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3824                                    adev, &dmcub_trace_event_state_fops);
3825
3826         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
3827                                    adev, &trigger_hpd_mst_ops);
3828
3829         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
3830                                    &dcc_en_bits_fops);
3831
3832         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
3833                                    &disable_hpd_ops);
3834
3835 }