drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  42 static int gmc_v7_0_wait_for_idle(void *handle);
  43
  44 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  45 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  46 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  47
  48 static const u32 golden_settings_iceland_a11[] =
  49 {
  50         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  51         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  52         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  53         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  54 };
  55
  56 static const u32 iceland_mgcg_cgcg_init[] =
  57 {
  58         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  59 };
  60
  61 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  62 {
  63         switch (adev->asic_type) {
  64         case CHIP_TOPAZ:
  65                 amdgpu_program_register_sequence(adev,
  66                                                  iceland_mgcg_cgcg_init,
  67                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  68                 amdgpu_program_register_sequence(adev,
  69                                                  golden_settings_iceland_a11,
  70                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  71                 break;
  72         default:
  73                 break;
  74         }
  75 }
  76
  77 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
  78                              struct amdgpu_mode_mc_save *save)
  79 {
  80         u32 blackout;
  81
  82         if (adev->mode_info.num_crtc)
  83                 amdgpu_display_stop_mc_access(adev, save);
  84
  85         gmc_v7_0_wait_for_idle((void *)adev);
  86
  87         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  88         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  89                 /* Block CPU access */
  90                 WREG32(mmBIF_FB_EN, 0);
  91                 /* blackout the MC */
  92                 blackout = REG_SET_FIELD(blackout,
  93                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  94                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  95         }
  96         /* wait for the MC to settle */
  97         udelay(100);
  98 }
  99
 100 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
 101                                struct amdgpu_mode_mc_save *save)
 102 {
 103         u32 tmp;
 104
 105         /* unblackout the MC */
 106         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 107         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 108         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 109         /* allow CPU access */
 110         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 111         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 112         WREG32(mmBIF_FB_EN, tmp);
 113
 114         if (adev->mode_info.num_crtc)
 115                 amdgpu_display_resume_mc_access(adev, save);
 116 }
 117
 118 /**
 119  * gmc_v7_0_init_microcode - load ucode images from disk
 120  *
 121  * @adev: amdgpu_device pointer
 122  *
 123  * Use the firmware interface to load the ucode images into
 124  * the driver (not loaded into hw).
 125  * Returns 0 on success, error on failure.
 126  */
 127 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 128 {
 129         const char *chip_name;
 130         char fw_name[30];
 131         int err;
 132
 133         DRM_DEBUG("\n");
 134
 135         switch (adev->asic_type) {
 136         case CHIP_BONAIRE:
 137                 chip_name = "bonaire";
 138                 break;
 139         case CHIP_HAWAII:
 140                 chip_name = "hawaii";
 141                 break;
 142         case CHIP_TOPAZ:
 143                 chip_name = "topaz";
 144                 break;
 145         case CHIP_KAVERI:
 146         case CHIP_KABINI:
 147         case CHIP_MULLINS:
 148                 return 0;
 149         default: BUG();
 150         }
 151
 152         if (adev->asic_type == CHIP_TOPAZ)
 153                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 154         else
 155                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 156
 157         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 158         if (err)
 159                 goto out;
 160         err = amdgpu_ucode_validate(adev->mc.fw);
 161
 162 out:
 163         if (err) {
 164                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 165                 release_firmware(adev->mc.fw);
 166                 adev->mc.fw = NULL;
 167         }
 168         return err;
 169 }
 170
 171 /**
 172  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 173  *
 174  * @adev: amdgpu_device pointer
 175  *
 176  * Load the GDDR MC ucode into the hw (CIK).
 177  * Returns 0 on success, error on failure.
 178  */
 179 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 180 {
 181         const struct mc_firmware_header_v1_0 *hdr;
 182         const __le32 *fw_data = NULL;
 183         const __le32 *io_mc_regs = NULL;
 184         u32 running;
 185         int i, ucode_size, regs_size;
 186
 187         if (!adev->mc.fw)
 188                 return -EINVAL;
 189
 190         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 191         amdgpu_ucode_print_mc_hdr(&hdr->header);
 192
 193         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 194         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 195         io_mc_regs = (const __le32 *)
 196                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 197         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 198         fw_data = (const __le32 *)
 199                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 200
 201         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 202
 203         if (running == 0) {
 204                 /* reset the engine and set to writable */
 205                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 206                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 207
 208                 /* load mc io regs */
 209                 for (i = 0; i < regs_size; i++) {
 210                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 211                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 212                 }
 213                 /* load the MC ucode */
 214                 for (i = 0; i < ucode_size; i++)
 215                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 216
 217                 /* put the engine back into the active state */
 218                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 219                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 220                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 221
 222                 /* wait for training to complete */
 223                 for (i = 0; i < adev->usec_timeout; i++) {
 224                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 225                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 226                                 break;
 227                         udelay(1);
 228                 }
 229                 for (i = 0; i < adev->usec_timeout; i++) {
 230                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 231                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 232                                 break;
 233                         udelay(1);
 234                 }
 235         }
 236
 237         return 0;
 238 }
 239
 240 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 241                                        struct amdgpu_mc *mc)
 242 {
 243         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 244                 /* leave room for at least 1024M GTT */
 245                 dev_warn(adev->dev, "limiting VRAM\n");
 246                 mc->real_vram_size = 0xFFC0000000ULL;
 247                 mc->mc_vram_size = 0xFFC0000000ULL;
 248         }
 249         amdgpu_vram_location(adev, &adev->mc, 0);
 250         adev->mc.gtt_base_align = 0;
 251         amdgpu_gtt_location(adev, mc);
 252 }
 253
 254 /**
 255  * gmc_v7_0_mc_program - program the GPU memory controller
 256  *
 257  * @adev: amdgpu_device pointer
 258  *
 259  * Set the location of vram, gart, and AGP in the GPU's
 260  * physical address space (CIK).
 261  */
 262 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 263 {
 264         struct amdgpu_mode_mc_save save;
 265         u32 tmp;
 266         int i, j;
 267
 268         /* Initialize HDP */
 269         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 270                 WREG32((0xb05 + j), 0x00000000);
 271                 WREG32((0xb06 + j), 0x00000000);
 272                 WREG32((0xb07 + j), 0x00000000);
 273                 WREG32((0xb08 + j), 0x00000000);
 274                 WREG32((0xb09 + j), 0x00000000);
 275         }
 276         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 277
 278         if (adev->mode_info.num_crtc)
 279                 amdgpu_display_set_vga_render_state(adev, false);
 280
 281         gmc_v7_0_mc_stop(adev, &save);
 282         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 283                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 284         }
 285         /* Update configuration */
 286         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 287                adev->mc.vram_start >> 12);
 288         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 289                adev->mc.vram_end >> 12);
 290         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 291                adev->vram_scratch.gpu_addr >> 12);
 292         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 293         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 294         WREG32(mmMC_VM_FB_LOCATION, tmp);
 295         /* XXX double check these! */
 296         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 297         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 298         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 299         WREG32(mmMC_VM_AGP_BASE, 0);
 300         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 301         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 302         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 303                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 304         }
 305         gmc_v7_0_mc_resume(adev, &save);
 306
 307         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 308
 309         tmp = RREG32(mmHDP_MISC_CNTL);
 310         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 311         WREG32(mmHDP_MISC_CNTL, tmp);
 312
 313         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 314         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 315 }
 316
 317 /**
 318  * gmc_v7_0_mc_init - initialize the memory controller driver params
 319  *
 320  * @adev: amdgpu_device pointer
 321  *
 322  * Look up the amount of vram, vram width, and decide how to place
 323  * vram and gart within the GPU's physical address space (CIK).
 324  * Returns 0 for success.
 325  */
 326 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 327 {
 328         u32 tmp;
 329         int chansize, numchan;
 330
 331         /* Get VRAM informations */
 332         tmp = RREG32(mmMC_ARB_RAMCFG);
 333         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 334                 chansize = 64;
 335         } else {
 336                 chansize = 32;
 337         }
 338         tmp = RREG32(mmMC_SHARED_CHMAP);
 339         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 340         case 0:
 341         default:
 342                 numchan = 1;
 343                 break;
 344         case 1:
 345                 numchan = 2;
 346                 break;
 347         case 2:
 348                 numchan = 4;
 349                 break;
 350         case 3:
 351                 numchan = 8;
 352                 break;
 353         case 4:
 354                 numchan = 3;
 355                 break;
 356         case 5:
 357                 numchan = 6;
 358                 break;
 359         case 6:
 360                 numchan = 10;
 361                 break;
 362         case 7:
 363                 numchan = 12;
 364                 break;
 365         case 8:
 366                 numchan = 16;
 367                 break;
 368         }
 369         adev->mc.vram_width = numchan * chansize;
 370         /* Could aper size report 0 ? */
 371         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 372         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 373         /* size in MB on si */
 374         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 375         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 376
 377 #ifdef CONFIG_X86_64
 378         if (adev->flags & AMD_IS_APU) {
 379                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 380                 adev->mc.aper_size = adev->mc.real_vram_size;
 381         }
 382 #endif
 383
 384         /* In case the PCI BAR is larger than the actual amount of vram */
 385         adev->mc.visible_vram_size = adev->mc.aper_size;
 386         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 387                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 388
 389         /* unless the user had overridden it, set the gart
 390          * size equal to the 1024 or vram, whichever is larger.
 391          */
 392         if (amdgpu_gart_size == -1)
 393                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 394         else
 395                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 396
 397         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 398
 399         return 0;
 400 }
 401
 402 /*
 403  * GART
 404  * VMID 0 is the physical GPU addresses as used by the kernel.
 405  * VMIDs 1-15 are used for userspace clients and are handled
 406  * by the amdgpu vm/hsa code.
 407  */
 408
 409 /**
 410  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 411  *
 412  * @adev: amdgpu_device pointer
 413  * @vmid: vm instance to flush
 414  *
 415  * Flush the TLB for the requested page table (CIK).
 416  */
 417 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 418                                         uint32_t vmid)
 419 {
 420         /* flush hdp cache */
 421         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 422
 423         /* bits 0-15 are the VM contexts0-15 */
 424         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 425 }
 426
 427 /**
 428  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 429  *
 430  * @adev: amdgpu_device pointer
 431  * @cpu_pt_addr: cpu address of the page table
 432  * @gpu_page_idx: entry in the page table to update
 433  * @addr: dst addr to write into pte/pde
 434  * @flags: access flags
 435  *
 436  * Update the page tables using the CPU.
 437  */
 438 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 439                                      void *cpu_pt_addr,
 440                                      uint32_t gpu_page_idx,
 441                                      uint64_t addr,
 442                                      uint32_t flags)
 443 {
 444         void __iomem *ptr = (void *)cpu_pt_addr;
 445         uint64_t value;
 446
 447         value = addr & 0xFFFFFFFFFFFFF000ULL;
 448         value |= flags;
 449         writeq(value, ptr + (gpu_page_idx * 8));
 450
 451         return 0;
 452 }
 453
 454 /**
 455  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 456  *
 457  * @adev: amdgpu_device pointer
 458  * @value: true redirects VM faults to the default page
 459  */
 460 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 461                                               bool value)
 462 {
 463         u32 tmp;
 464
 465         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 466         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 467                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 468         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 469                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 470         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 471                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 472         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 473                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 474         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 475                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 476         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 477                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 478         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 479 }
 480
 481 /**
 482  * gmc_v7_0_set_prt - set PRT VM fault
 483  *
 484  * @adev: amdgpu_device pointer
 485  * @enable: enable/disable VM fault handling for PRT
 486  */
 487 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 488 {
 489         uint32_t tmp;
 490
 491         if (enable && !adev->mc.prt_warning) {
 492                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 493                 adev->mc.prt_warning = true;
 494         }
 495
 496         tmp = RREG32(mmVM_PRT_CNTL);
 497         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 498                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 499         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 500                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 501         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 502                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 503         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 504                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 505         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 506                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 507         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 508                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 509         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 510                             MASK_PDE0_FAULT, enable);
 511         WREG32(mmVM_PRT_CNTL, tmp);
 512
 513         if (enable) {
 514                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 515                 uint32_t high = adev->vm_manager.max_pfn;
 516
 517                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 518                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 519                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 520                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 521                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 522                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 523                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 524                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 525         } else {
 526                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 527                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 528                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 529                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 530                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 531                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 532                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 533                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 534         }
 535 }
 536
 537 /**
 538  * gmc_v7_0_gart_enable - gart enable
 539  *
 540  * @adev: amdgpu_device pointer
 541  *
 542  * This sets up the TLBs, programs the page tables for VMID0,
 543  * sets up the hw for VMIDs 1-15 which are allocated on
 544  * demand, and sets up the global locations for the LDS, GDS,
 545  * and GPUVM for FSA64 clients (CIK).
 546  * Returns 0 for success, errors for failure.
 547  */
 548 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 549 {
 550         int r, i;
 551         u32 tmp;
 552
 553         if (adev->gart.robj == NULL) {
 554                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 555                 return -EINVAL;
 556         }
 557         r = amdgpu_gart_table_vram_pin(adev);
 558         if (r)
 559                 return r;
 560         /* Setup TLB control */
 561         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 562         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 563         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 564         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 565         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 566         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 567         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 568         /* Setup L2 cache */
 569         tmp = RREG32(mmVM_L2_CNTL);
 570         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 571         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 572         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 573         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 574         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 575         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 576         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 577         WREG32(mmVM_L2_CNTL, tmp);
 578         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 579         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 580         WREG32(mmVM_L2_CNTL2, tmp);
 581         tmp = RREG32(mmVM_L2_CNTL3);
 582         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 583         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 584         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 585         WREG32(mmVM_L2_CNTL3, tmp);
 586         /* setup context0 */
 587         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 588         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 589         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 590         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 591                         (u32)(adev->dummy_page.addr >> 12));
 592         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 593         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 594         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 595         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 596         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 597         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 598
 599         WREG32(0x575, 0);
 600         WREG32(0x576, 0);
 601         WREG32(0x577, 0);
 602
 603         /* empty context1-15 */
 604         /* FIXME start with 4G, once using 2 level pt switch to full
 605          * vm size space
 606          */
 607         /* set vm size, must be a multiple of 4 */
 608         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 609         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 610         for (i = 1; i < 16; i++) {
 611                 if (i < 8)
 612                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 613                                adev->gart.table_addr >> 12);
 614                 else
 615                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 616                                adev->gart.table_addr >> 12);
 617         }
 618
 619         /* enable context1-15 */
 620         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 621                (u32)(adev->dummy_page.addr >> 12));
 622         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 623         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 624         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 625         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 626         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 627                             amdgpu_vm_block_size - 9);
 628         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 629         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 630                 gmc_v7_0_set_fault_enable_default(adev, false);
 631         else
 632                 gmc_v7_0_set_fault_enable_default(adev, true);
 633
 634         if (adev->asic_type == CHIP_KAVERI) {
 635                 tmp = RREG32(mmCHUB_CONTROL);
 636                 tmp &= ~BYPASS_VM;
 637                 WREG32(mmCHUB_CONTROL, tmp);
 638         }
 639
 640         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 641         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 642                  (unsigned)(adev->mc.gtt_size >> 20),
 643                  (unsigned long long)adev->gart.table_addr);
 644         adev->gart.ready = true;
 645         return 0;
 646 }
 647
 648 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 649 {
 650         int r;
 651
 652         if (adev->gart.robj) {
 653                 WARN(1, "R600 PCIE GART already initialized\n");
 654                 return 0;
 655         }
 656         /* Initialize common gart structure */
 657         r = amdgpu_gart_init(adev);
 658         if (r)
 659                 return r;
 660         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 661         return amdgpu_gart_table_vram_alloc(adev);
 662 }
 663
 664 /**
 665  * gmc_v7_0_gart_disable - gart disable
 666  *
 667  * @adev: amdgpu_device pointer
 668  *
 669  * This disables all VM page table (CIK).
 670  */
 671 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 672 {
 673         u32 tmp;
 674
 675         /* Disable all tables */
 676         WREG32(mmVM_CONTEXT0_CNTL, 0);
 677         WREG32(mmVM_CONTEXT1_CNTL, 0);
 678         /* Setup TLB control */
 679         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 680         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 681         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 682         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 683         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 684         /* Setup L2 cache */
 685         tmp = RREG32(mmVM_L2_CNTL);
 686         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 687         WREG32(mmVM_L2_CNTL, tmp);
 688         WREG32(mmVM_L2_CNTL2, 0);
 689         amdgpu_gart_table_vram_unpin(adev);
 690 }
 691
 692 /**
 693  * gmc_v7_0_gart_fini - vm fini callback
 694  *
 695  * @adev: amdgpu_device pointer
 696  *
 697  * Tears down the driver GART/VM setup (CIK).
 698  */
 699 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 700 {
 701         amdgpu_gart_table_vram_free(adev);
 702         amdgpu_gart_fini(adev);
 703 }
 704
 705 /*
 706  * vm
 707  * VMID 0 is the physical GPU addresses as used by the kernel.
 708  * VMIDs 1-15 are used for userspace clients and are handled
 709  * by the amdgpu vm/hsa code.
 710  */
 711 /**
 712  * gmc_v7_0_vm_init - cik vm init callback
 713  *
 714  * @adev: amdgpu_device pointer
 715  *
 716  * Inits cik specific vm parameters (number of VMs, base of vram for
 717  * VMIDs 1-15) (CIK).
 718  * Returns 0 for success.
 719  */
 720 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 721 {
 722         /*
 723          * number of VMs
 724          * VMID 0 is reserved for System
 725          * amdgpu graphics/compute will use VMIDs 1-7
 726          * amdkfd will use VMIDs 8-15
 727          */
 728         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 729         amdgpu_vm_manager_init(adev);
 730
 731         /* base offset of vram pages */
 732         if (adev->flags & AMD_IS_APU) {
 733                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 734                 tmp <<= 22;
 735                 adev->vm_manager.vram_base_offset = tmp;
 736         } else
 737                 adev->vm_manager.vram_base_offset = 0;
 738
 739         return 0;
 740 }
 741
 742 /**
 743  * gmc_v7_0_vm_fini - cik vm fini callback
 744  *
 745  * @adev: amdgpu_device pointer
 746  *
 747  * Tear down any asic specific VM setup (CIK).
 748  */
 749 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
 750 {
 751 }
 752
 753 /**
 754  * gmc_v7_0_vm_decode_fault - print human readable fault info
 755  *
 756  * @adev: amdgpu_device pointer
 757  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 758  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 759  *
 760  * Print human readable fault information (CIK).
 761  */
 762 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 763                                      u32 status, u32 addr, u32 mc_client)
 764 {
 765         u32 mc_id;
 766         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 767         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 768                                         PROTECTIONS);
 769         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 770                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 771
 772         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 773                               MEMORY_CLIENT_ID);
 774
 775         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 776                protections, vmid, addr,
 777                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 778                              MEMORY_CLIENT_RW) ?
 779                "write" : "read", block, mc_client, mc_id);
 780 }
 781
 782
 783 static const u32 mc_cg_registers[] = {
 784         mmMC_HUB_MISC_HUB_CG,
 785         mmMC_HUB_MISC_SIP_CG,
 786         mmMC_HUB_MISC_VM_CG,
 787         mmMC_XPB_CLK_GAT,
 788         mmATC_MISC_CG,
 789         mmMC_CITF_MISC_WR_CG,
 790         mmMC_CITF_MISC_RD_CG,
 791         mmMC_CITF_MISC_VM_CG,
 792         mmVM_L2_CG,
 793 };
 794
 795 static const u32 mc_cg_ls_en[] = {
 796         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 797         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 798         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 799         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 800         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 801         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 802         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 803         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 804         VM_L2_CG__MEM_LS_ENABLE_MASK,
 805 };
 806
 807 static const u32 mc_cg_en[] = {
 808         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 809         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 810         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 811         MC_XPB_CLK_GAT__ENABLE_MASK,
 812         ATC_MISC_CG__ENABLE_MASK,
 813         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 814         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 815         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 816         VM_L2_CG__ENABLE_MASK,
 817 };
 818
 819 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 820                                   bool enable)
 821 {
 822         int i;
 823         u32 orig, data;
 824
 825         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 826                 orig = data = RREG32(mc_cg_registers[i]);
 827                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 828                         data |= mc_cg_ls_en[i];
 829                 else
 830                         data &= ~mc_cg_ls_en[i];
 831                 if (data != orig)
 832                         WREG32(mc_cg_registers[i], data);
 833         }
 834 }
 835
 836 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 837                                     bool enable)
 838 {
 839         int i;
 840         u32 orig, data;
 841
 842         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 843                 orig = data = RREG32(mc_cg_registers[i]);
 844                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 845                         data |= mc_cg_en[i];
 846                 else
 847                         data &= ~mc_cg_en[i];
 848                 if (data != orig)
 849                         WREG32(mc_cg_registers[i], data);
 850         }
 851 }
 852
 853 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 854                                      bool enable)
 855 {
 856         u32 orig, data;
 857
 858         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 859
 860         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 861                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 862                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 863                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 864                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 865         } else {
 866                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 867                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 868                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 869                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 870         }
 871
 872         if (orig != data)
 873                 WREG32_PCIE(ixPCIE_CNTL2, data);
 874 }
 875
 876 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 877                                      bool enable)
 878 {
 879         u32 orig, data;
 880
 881         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 882
 883         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 884                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 885         else
 886                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 887
 888         if (orig != data)
 889                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 890 }
 891
 892 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 893                                    bool enable)
 894 {
 895         u32 orig, data;
 896
 897         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 898
 899         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 900                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 901         else
 902                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 903
 904         if (orig != data)
 905                 WREG32(mmHDP_MEM_POWER_LS, data);
 906 }
 907
 908 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 909 {
 910         switch (mc_seq_vram_type) {
 911         case MC_SEQ_MISC0__MT__GDDR1:
 912                 return AMDGPU_VRAM_TYPE_GDDR1;
 913         case MC_SEQ_MISC0__MT__DDR2:
 914                 return AMDGPU_VRAM_TYPE_DDR2;
 915         case MC_SEQ_MISC0__MT__GDDR3:
 916                 return AMDGPU_VRAM_TYPE_GDDR3;
 917         case MC_SEQ_MISC0__MT__GDDR4:
 918                 return AMDGPU_VRAM_TYPE_GDDR4;
 919         case MC_SEQ_MISC0__MT__GDDR5:
 920                 return AMDGPU_VRAM_TYPE_GDDR5;
 921         case MC_SEQ_MISC0__MT__HBM:
 922                 return AMDGPU_VRAM_TYPE_HBM;
 923         case MC_SEQ_MISC0__MT__DDR3:
 924                 return AMDGPU_VRAM_TYPE_DDR3;
 925         default:
 926                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 927         }
 928 }
 929
 930 static int gmc_v7_0_early_init(void *handle)
 931 {
 932         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 933
 934         gmc_v7_0_set_gart_funcs(adev);
 935         gmc_v7_0_set_irq_funcs(adev);
 936
 937         return 0;
 938 }
 939
 940 static int gmc_v7_0_late_init(void *handle)
 941 {
 942         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 943
 944         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 945                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 946         else
 947                 return 0;
 948 }
 949
 950 static int gmc_v7_0_sw_init(void *handle)
 951 {
 952         int r;
 953         int dma_bits;
 954         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 955
 956         if (adev->flags & AMD_IS_APU) {
 957                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 958         } else {
 959                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 960                 tmp &= MC_SEQ_MISC0__MT__MASK;
 961                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 962         }
 963
 964         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 965         if (r)
 966                 return r;
 967
 968         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 969         if (r)
 970                 return r;
 971
 972         /* Adjust VM size here.
 973          * Currently set to 4GB ((1 << 20) 4k pages).
 974          * Max GPUVM size for cayman and SI is 40 bits.
 975          */
 976         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 977
 978         /* Set the internal MC address mask
 979          * This is the max address of the GPU's
 980          * internal address space.
 981          */
 982         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 983
 984         /* set DMA mask + need_dma32 flags.
 985          * PCIE - can handle 40-bits.
 986          * IGP - can handle 40-bits
 987          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 988          */
 989         adev->need_dma32 = false;
 990         dma_bits = adev->need_dma32 ? 32 : 40;
 991         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 992         if (r) {
 993                 adev->need_dma32 = true;
 994                 dma_bits = 32;
 995                 pr_warn("amdgpu: No suitable DMA available\n");
 996         }
 997         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 998         if (r) {
 999                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1000                 pr_warn("amdgpu: No coherent DMA available\n");
1001         }
1002
1003         r = gmc_v7_0_init_microcode(adev);
1004         if (r) {
1005                 DRM_ERROR("Failed to load mc firmware!\n");
1006                 return r;
1007         }
1008
1009         r = gmc_v7_0_mc_init(adev);
1010         if (r)
1011                 return r;
1012
1013         /* Memory manager */
1014         r = amdgpu_bo_init(adev);
1015         if (r)
1016                 return r;
1017
1018         r = gmc_v7_0_gart_init(adev);
1019         if (r)
1020                 return r;
1021
1022         if (!adev->vm_manager.enabled) {
1023                 r = gmc_v7_0_vm_init(adev);
1024                 if (r) {
1025                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1026                         return r;
1027                 }
1028                 adev->vm_manager.enabled = true;
1029         }
1030
1031         return r;
1032 }
1033
1034 static int gmc_v7_0_sw_fini(void *handle)
1035 {
1036         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1037
1038         if (adev->vm_manager.enabled) {
1039                 amdgpu_vm_manager_fini(adev);
1040                 gmc_v7_0_vm_fini(adev);
1041                 adev->vm_manager.enabled = false;
1042         }
1043         gmc_v7_0_gart_fini(adev);
1044         amdgpu_gem_force_release(adev);
1045         amdgpu_bo_fini(adev);
1046
1047         return 0;
1048 }
1049
1050 static int gmc_v7_0_hw_init(void *handle)
1051 {
1052         int r;
1053         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054
1055         gmc_v7_0_init_golden_registers(adev);
1056
1057         gmc_v7_0_mc_program(adev);
1058
1059         if (!(adev->flags & AMD_IS_APU)) {
1060                 r = gmc_v7_0_mc_load_microcode(adev);
1061                 if (r) {
1062                         DRM_ERROR("Failed to load MC firmware!\n");
1063                         return r;
1064                 }
1065         }
1066
1067         r = gmc_v7_0_gart_enable(adev);
1068         if (r)
1069                 return r;
1070
1071         return r;
1072 }
1073
1074 static int gmc_v7_0_hw_fini(void *handle)
1075 {
1076         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1077
1078         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1079         gmc_v7_0_gart_disable(adev);
1080
1081         return 0;
1082 }
1083
1084 static int gmc_v7_0_suspend(void *handle)
1085 {
1086         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1087
1088         if (adev->vm_manager.enabled) {
1089                 gmc_v7_0_vm_fini(adev);
1090                 adev->vm_manager.enabled = false;
1091         }
1092         gmc_v7_0_hw_fini(adev);
1093
1094         return 0;
1095 }
1096
1097 static int gmc_v7_0_resume(void *handle)
1098 {
1099         int r;
1100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1101
1102         r = gmc_v7_0_hw_init(adev);
1103         if (r)
1104                 return r;
1105
1106         if (!adev->vm_manager.enabled) {
1107                 r = gmc_v7_0_vm_init(adev);
1108                 if (r) {
1109                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1110                         return r;
1111                 }
1112                 adev->vm_manager.enabled = true;
1113         }
1114
1115         return r;
1116 }
1117
1118 static bool gmc_v7_0_is_idle(void *handle)
1119 {
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121         u32 tmp = RREG32(mmSRBM_STATUS);
1122
1123         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1124                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1125                 return false;
1126
1127         return true;
1128 }
1129
1130 static int gmc_v7_0_wait_for_idle(void *handle)
1131 {
1132         unsigned i;
1133         u32 tmp;
1134         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1135
1136         for (i = 0; i < adev->usec_timeout; i++) {
1137                 /* read MC_STATUS */
1138                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1139                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1140                                                SRBM_STATUS__MCC_BUSY_MASK |
1141                                                SRBM_STATUS__MCD_BUSY_MASK |
1142                                                SRBM_STATUS__VMC_BUSY_MASK);
1143                 if (!tmp)
1144                         return 0;
1145                 udelay(1);
1146         }
1147         return -ETIMEDOUT;
1148
1149 }
1150
1151 static int gmc_v7_0_soft_reset(void *handle)
1152 {
1153         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1154         struct amdgpu_mode_mc_save save;
1155         u32 srbm_soft_reset = 0;
1156         u32 tmp = RREG32(mmSRBM_STATUS);
1157
1158         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1159                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1160                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1161
1162         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1163                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1164                 if (!(adev->flags & AMD_IS_APU))
1165                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1166                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1167         }
1168
1169         if (srbm_soft_reset) {
1170                 gmc_v7_0_mc_stop(adev, &save);
1171                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1172                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1173                 }
1174
1175
1176                 tmp = RREG32(mmSRBM_SOFT_RESET);
1177                 tmp |= srbm_soft_reset;
1178                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1179                 WREG32(mmSRBM_SOFT_RESET, tmp);
1180                 tmp = RREG32(mmSRBM_SOFT_RESET);
1181
1182                 udelay(50);
1183
1184                 tmp &= ~srbm_soft_reset;
1185                 WREG32(mmSRBM_SOFT_RESET, tmp);
1186                 tmp = RREG32(mmSRBM_SOFT_RESET);
1187
1188                 /* Wait a little for things to settle down */
1189                 udelay(50);
1190
1191                 gmc_v7_0_mc_resume(adev, &save);
1192                 udelay(50);
1193         }
1194
1195         return 0;
1196 }
1197
1198 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1199                                              struct amdgpu_irq_src *src,
1200                                              unsigned type,
1201                                              enum amdgpu_interrupt_state state)
1202 {
1203         u32 tmp;
1204         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1205                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1206                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1207                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1208                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1209                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1210
1211         switch (state) {
1212         case AMDGPU_IRQ_STATE_DISABLE:
1213                 /* system context */
1214                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1215                 tmp &= ~bits;
1216                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1217                 /* VMs */
1218                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1219                 tmp &= ~bits;
1220                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1221                 break;
1222         case AMDGPU_IRQ_STATE_ENABLE:
1223                 /* system context */
1224                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1225                 tmp |= bits;
1226                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1227                 /* VMs */
1228                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1229                 tmp |= bits;
1230                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1231                 break;
1232         default:
1233                 break;
1234         }
1235
1236         return 0;
1237 }
1238
1239 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1240                                       struct amdgpu_irq_src *source,
1241                                       struct amdgpu_iv_entry *entry)
1242 {
1243         u32 addr, status, mc_client;
1244
1245         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1246         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1247         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1248         /* reset addr and status */
1249         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1250
1251         if (!addr && !status)
1252                 return 0;
1253
1254         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1255                 gmc_v7_0_set_fault_enable_default(adev, false);
1256
1257         if (printk_ratelimit()) {
1258                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1259                         entry->src_id, entry->src_data);
1260                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1261                         addr);
1262                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1263                         status);
1264                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int gmc_v7_0_set_clockgating_state(void *handle,
1271                                           enum amd_clockgating_state state)
1272 {
1273         bool gate = false;
1274         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1275
1276         if (state == AMD_CG_STATE_GATE)
1277                 gate = true;
1278
1279         if (!(adev->flags & AMD_IS_APU)) {
1280                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1281                 gmc_v7_0_enable_mc_ls(adev, gate);
1282         }
1283         gmc_v7_0_enable_bif_mgls(adev, gate);
1284         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1285         gmc_v7_0_enable_hdp_ls(adev, gate);
1286
1287         return 0;
1288 }
1289
1290 static int gmc_v7_0_set_powergating_state(void *handle,
1291                                           enum amd_powergating_state state)
1292 {
1293         return 0;
1294 }
1295
1296 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1297         .name = "gmc_v7_0",
1298         .early_init = gmc_v7_0_early_init,
1299         .late_init = gmc_v7_0_late_init,
1300         .sw_init = gmc_v7_0_sw_init,
1301         .sw_fini = gmc_v7_0_sw_fini,
1302         .hw_init = gmc_v7_0_hw_init,
1303         .hw_fini = gmc_v7_0_hw_fini,
1304         .suspend = gmc_v7_0_suspend,
1305         .resume = gmc_v7_0_resume,
1306         .is_idle = gmc_v7_0_is_idle,
1307         .wait_for_idle = gmc_v7_0_wait_for_idle,
1308         .soft_reset = gmc_v7_0_soft_reset,
1309         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1310         .set_powergating_state = gmc_v7_0_set_powergating_state,
1311 };
1312
1313 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1314         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1315         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1316         .set_prt = gmc_v7_0_set_prt,
1317 };
1318
1319 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1320         .set = gmc_v7_0_vm_fault_interrupt_state,
1321         .process = gmc_v7_0_process_interrupt,
1322 };
1323
1324 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1325 {
1326         if (adev->gart.gart_funcs == NULL)
1327                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1328 }
1329
1330 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1331 {
1332         adev->mc.vm_fault.num_types = 1;
1333         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1334 }
1335
1336 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1337 {
1338         .type = AMD_IP_BLOCK_TYPE_GMC,
1339         .major = 7,
1340         .minor = 0,
1341         .rev = 0,
1342         .funcs = &gmc_v7_0_ip_funcs,
1343 };
1344
1345 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1346 {
1347         .type = AMD_IP_BLOCK_TYPE_GMC,
1348         .major = 7,
1349         .minor = 4,
1350         .rev = 0,
1351         .funcs = &gmc_v7_0_ip_funcs,
1352 };