drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "mmhub_v2_3.h"
  26
  27 #include "mmhub/mmhub_2_3_0_offset.h"
  28 #include "mmhub/mmhub_2_3_0_sh_mask.h"
  29 #include "mmhub/mmhub_2_3_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 static const char *mmhub_client_ids_vangogh[][2] = {
  35         [0][0] = "MP0",
  36         [1][0] = "MP1",
  37         [2][0] = "DCEDMC",
  38         [3][0] = "DCEVGA",
  39         [13][0] = "UTCL2",
  40         [26][0] = "OSS",
  41         [27][0] = "HDP",
  42         [28][0] = "VCN",
  43         [29][0] = "VCNU",
  44         [30][0] = "JPEG",
  45         [0][1] = "MP0",
  46         [1][1] = "MP1",
  47         [2][1] = "DCEDMC",
  48         [3][1] = "DCEVGA",
  49         [4][1] = "DCEDWB",
  50         [5][1] = "XDP",
  51         [26][1] = "OSS",
  52         [27][1] = "HDP",
  53         [28][1] = "VCN",
  54         [29][1] = "VCNU",
  55         [30][1] = "JPEG",
  56 };
  57
  58 static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid,
  59                                               uint32_t flush_type)
  60 {
  61         u32 req = 0;
  62
  63         /* invalidate using legacy mode on vmid*/
  64         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
  65                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
  66         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
  67         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
  68         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
  69         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
  70         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
  71         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
  72         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
  73                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
  74
  75         return req;
  76 }
  77
  78 static void
  79 mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
  80                                              uint32_t status)
  81 {
  82         uint32_t cid, rw;
  83         const char *mmhub_cid = NULL;
  84
  85         cid = REG_GET_FIELD(status,
  86                             MMVM_L2_PROTECTION_FAULT_STATUS, CID);
  87         rw = REG_GET_FIELD(status,
  88                            MMVM_L2_PROTECTION_FAULT_STATUS, RW);
  89
  90         dev_err(adev->dev,
  91                 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
  92                 status);
  93         switch (adev->asic_type) {
  94         case CHIP_VANGOGH:
  95                 mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
  96                 break;
  97         default:
  98                 mmhub_cid = NULL;
  99                 break;
 100         }
 101         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 102                 mmhub_cid ? mmhub_cid : "unknown", cid);
 103         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 104                 REG_GET_FIELD(status,
 105                 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 106         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 107                 REG_GET_FIELD(status,
 108                 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 109         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 110                 REG_GET_FIELD(status,
 111                 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 112         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 113                 REG_GET_FIELD(status,
 114                 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 115         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 116 }
 117
 118 static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev,
 119                                         uint32_t vmid,
 120                                         uint64_t page_table_base)
 121 {
 122         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 123
 124         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 125                             hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
 126
 127         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 128                             hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
 129 }
 130
 131 static void mmhub_v2_3_init_gart_aperture_regs(struct amdgpu_device *adev)
 132 {
 133         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 134
 135         mmhub_v2_3_setup_vm_pt_regs(adev, 0, pt_base);
 136
 137         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 138                      (u32)(adev->gmc.gart_start >> 12));
 139         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 140                      (u32)(adev->gmc.gart_start >> 44));
 141
 142         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 143                      (u32)(adev->gmc.gart_end >> 12));
 144         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 145                      (u32)(adev->gmc.gart_end >> 44));
 146 }
 147
 148 static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev)
 149 {
 150         uint64_t value;
 151         uint32_t tmp;
 152
 153         /* Disable AGP. */
 154         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
 155         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 156         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 157
 158         /* Program the system aperture low logical page number. */
 159         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 160                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 161         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 162                      max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 163
 164         /* Set default page address. */
 165         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
 166         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 167                      (u32)(value >> 12));
 168         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 169                      (u32)(value >> 44));
 170
 171         /* Program "protection fault". */
 172         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 173                      (u32)(adev->dummy_page_addr >> 12));
 174         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 175                      (u32)((u64)adev->dummy_page_addr >> 44));
 176
 177         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
 178         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
 179                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 180         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 181 }
 182
 183 static void mmhub_v2_3_init_tlb_regs(struct amdgpu_device *adev)
 184 {
 185         uint32_t tmp;
 186
 187         /* Setup TLB control */
 188         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 189
 190         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 191         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 192         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 193                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 194         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 195                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 196         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 197         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 198                             MTYPE, MTYPE_UC); /* UC, uncached */
 199
 200         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 201 }
 202
 203 static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
 204 {
 205         uint32_t tmp;
 206
 207         /* Setup L2 cache */
 208         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 209         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 210         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 211         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
 212                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 213         /* XXX for emulation, Refer to closed source code.*/
 214         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 215                             0);
 216         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 217         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 218         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 219         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 220
 221         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
 222         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 223         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 224         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
 225
 226         tmp = mmMMVM_L2_CNTL3_DEFAULT;
 227         if (adev->gmc.translate_further) {
 228                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
 229                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 230                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 231         } else {
 232                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
 233                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 234                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 235         }
 236         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
 237
 238         tmp = mmMMVM_L2_CNTL4_DEFAULT;
 239         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 240         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 241         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
 242
 243         tmp = mmMMVM_L2_CNTL5_DEFAULT;
 244         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 245         WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
 246 }
 247
 248 static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)
 249 {
 250         uint32_t tmp;
 251
 252         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 253         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 254         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 255         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
 256                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 257         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
 258 }
 259
 260 static void mmhub_v2_3_disable_identity_aperture(struct amdgpu_device *adev)
 261 {
 262         WREG32_SOC15(MMHUB, 0,
 263                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 264                      0xFFFFFFFF);
 265         WREG32_SOC15(MMHUB, 0,
 266                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 267                      0x0000000F);
 268
 269         WREG32_SOC15(MMHUB, 0,
 270                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 271         WREG32_SOC15(MMHUB, 0,
 272                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 273
 274         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 275                      0);
 276         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 277                      0);
 278 }
 279
 280 static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
 281 {
 282         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 283         int i;
 284         uint32_t tmp;
 285
 286         for (i = 0; i <= 14; i++) {
 287                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
 288                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 289                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 290                                     adev->vm_manager.num_level);
 291                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 292                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 293                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 294                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 295                                     1);
 296                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 297                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 298                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 299                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 300                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 301                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 302                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 303                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 304                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 305                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 306                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 307                                     PAGE_TABLE_BLOCK_SIZE,
 308                                     adev->vm_manager.block_size - 9);
 309                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 310                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 311                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 312                                     !adev->gmc.noretry);
 313                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
 314                                     i * hub->ctx_distance, tmp);
 315                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 316                                     i * hub->ctx_addr_distance, 0);
 317                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 318                                     i * hub->ctx_addr_distance, 0);
 319                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 320                                     i * hub->ctx_addr_distance,
 321                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 322                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 323                                     i * hub->ctx_addr_distance,
 324                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 325         }
 326 }
 327
 328 static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev)
 329 {
 330         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 331         unsigned i;
 332
 333         for (i = 0; i < 18; ++i) {
 334                 WREG32_SOC15_OFFSET(MMHUB, 0,
 335                                     mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 336                                     i * hub->eng_addr_distance, 0xffffffff);
 337                 WREG32_SOC15_OFFSET(MMHUB, 0,
 338                                     mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 339                                     i * hub->eng_addr_distance, 0x1f);
 340         }
 341 }
 342
 343 static int mmhub_v2_3_gart_enable(struct amdgpu_device *adev)
 344 {
 345         if (amdgpu_sriov_vf(adev)) {
 346                 /*
 347                  * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 348                  * VF copy registers so vbios post doesn't program them, for
 349                  * SRIOV driver need to program them
 350                  */
 351                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
 352                              adev->gmc.vram_start >> 24);
 353                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
 354                              adev->gmc.vram_end >> 24);
 355         }
 356
 357         /* GART Enable. */
 358         mmhub_v2_3_init_gart_aperture_regs(adev);
 359         mmhub_v2_3_init_system_aperture_regs(adev);
 360         mmhub_v2_3_init_tlb_regs(adev);
 361         mmhub_v2_3_init_cache_regs(adev);
 362
 363         mmhub_v2_3_enable_system_domain(adev);
 364         mmhub_v2_3_disable_identity_aperture(adev);
 365         mmhub_v2_3_setup_vmid_config(adev);
 366         mmhub_v2_3_program_invalidation(adev);
 367
 368         return 0;
 369 }
 370
 371 static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
 372 {
 373         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 374         u32 tmp;
 375         u32 i;
 376
 377         /* Disable all tables */
 378         for (i = 0; i < AMDGPU_NUM_VMID; i++)
 379                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
 380                                     i * hub->ctx_distance, 0);
 381
 382         /* Setup TLB control */
 383         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 384         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 385         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 386                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 387         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 388
 389         /* Setup L2 cache */
 390         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 391         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 392         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 393         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
 394 }
 395
 396 /**
 397  * mmhub_v2_3_set_fault_enable_default - update GART/VM fault handling
 398  *
 399  * @adev: amdgpu_device pointer
 400  * @value: true redirects VM faults to the default page
 401  */
 402 static void mmhub_v2_3_set_fault_enable_default(struct amdgpu_device *adev,
 403                                                 bool value)
 404 {
 405         u32 tmp;
 406         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 407         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 408                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 409         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 410                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 411         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 412                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 413         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 414                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 415         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 416                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 417                             value);
 418         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 419                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 420         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 421                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 422         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 423                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 424         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 425                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 426         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 427                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 428         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 429                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 430         if (!value) {
 431                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 432                                 CRASH_ON_NO_RETRY_FAULT, 1);
 433                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 434                                 CRASH_ON_RETRY_FAULT, 1);
 435         }
 436         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
 437 }
 438
 439 static const struct amdgpu_vmhub_funcs mmhub_v2_3_vmhub_funcs = {
 440         .print_l2_protection_fault_status = mmhub_v2_3_print_l2_protection_fault_status,
 441         .get_invalidate_req = mmhub_v2_3_get_invalidate_req,
 442 };
 443
 444 static void mmhub_v2_3_init(struct amdgpu_device *adev)
 445 {
 446         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 447
 448         hub->ctx0_ptb_addr_lo32 =
 449                 SOC15_REG_OFFSET(MMHUB, 0,
 450                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 451         hub->ctx0_ptb_addr_hi32 =
 452                 SOC15_REG_OFFSET(MMHUB, 0,
 453                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 454         hub->vm_inv_eng0_sem =
 455                 SOC15_REG_OFFSET(MMHUB, 0,
 456                                  mmMMVM_INVALIDATE_ENG0_SEM);
 457         hub->vm_inv_eng0_req =
 458                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
 459         hub->vm_inv_eng0_ack =
 460                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
 461         hub->vm_context0_cntl =
 462                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 463         hub->vm_l2_pro_fault_status =
 464                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
 465         hub->vm_l2_pro_fault_cntl =
 466                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 467
 468         hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
 469         hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 470                 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 471         hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
 472                 mmMMVM_INVALIDATE_ENG0_REQ;
 473         hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 474                 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 475
 476         hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 477                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 478                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 479                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 480                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 481                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 482                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 483
 484         hub->vmhub_funcs = &mmhub_v2_3_vmhub_funcs;
 485 }
 486
 487 static void
 488 mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 489                                             bool enable)
 490 {
 491         uint32_t def, data, def1, data1;
 492
 493         def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);
 494         def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 495
 496         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 497                 data &= ~MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
 498                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 499                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 500                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 501                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 502                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 503                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 504
 505         } else {
 506                 data |= MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
 507                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 508                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 509                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 510                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 511                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 512                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 513         }
 514
 515         if (def != data)
 516                 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL, data);
 517         if (def1 != data1)
 518                 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 519 }
 520
 521 static void
 522 mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 523                                            bool enable)
 524 {
 525         uint32_t def, data, def1, data1, def2, data2;
 526
 527         def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);
 528         def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);
 529         def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);
 530
 531         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
 532                 data &= ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
 533                 data1 &= ~(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
 534                         DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
 535                         DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
 536                         DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
 537                         DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
 538                 data2 &= ~(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
 539                         DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
 540                         DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
 541                         DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
 542                         DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
 543         } else {
 544                 data |= MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
 545                 data1 |= (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
 546                         DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
 547                         DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
 548                         DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
 549                         DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
 550                 data2 |= (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
 551                         DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
 552                         DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
 553                         DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
 554                         DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
 555         }
 556
 557         if (def != data)
 558                 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL, data);
 559         if (def1 != data1)
 560                 WREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL, data1);
 561         if (def2 != data2)
 562                 WREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL, data2);
 563 }
 564
 565 static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev,
 566                                       enum amd_clockgating_state state)
 567 {
 568         if (amdgpu_sriov_vf(adev))
 569                 return 0;
 570
 571         mmhub_v2_3_update_medium_grain_clock_gating(adev,
 572                         state == AMD_CG_STATE_GATE ? true : false);
 573         mmhub_v2_3_update_medium_grain_light_sleep(adev,
 574                         state == AMD_CG_STATE_GATE ? true : false);
 575
 576         return 0;
 577 }
 578
 579 static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 580 {
 581         int data, data1, data2, data3;
 582
 583         if (amdgpu_sriov_vf(adev))
 584                 *flags = 0;
 585
 586         data = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 587         data1  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);
 588         data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);
 589         data3 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);
 590
 591         /* AMD_CG_SUPPORT_MC_MGCG */
 592         if (!(data & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 593                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 594                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 595                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 596                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 597                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))
 598                 && !(data1 & MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK)) {
 599                         *flags |= AMD_CG_SUPPORT_MC_MGCG;
 600         }
 601
 602         /* AMD_CG_SUPPORT_MC_LS */
 603         if (!(data1 & MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK)
 604                 && !(data2 & (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
 605                                 DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
 606                                 DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
 607                                 DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
 608                                 DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK))
 609                 && !(data3 & (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
 610                                 DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
 611                                 DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
 612                                 DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
 613                                 DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK)))
 614                 *flags |= AMD_CG_SUPPORT_MC_LS;
 615 }
 616
 617 const struct amdgpu_mmhub_funcs mmhub_v2_3_funcs = {
 618         .init = mmhub_v2_3_init,
 619         .gart_enable = mmhub_v2_3_gart_enable,
 620         .set_fault_enable_default = mmhub_v2_3_set_fault_enable_default,
 621         .gart_disable = mmhub_v2_3_gart_disable,
 622         .set_clockgating = mmhub_v2_3_set_clockgating,
 623         .get_clockgating = mmhub_v2_3_get_clockgating,
 624         .setup_vm_pt_regs = mmhub_v2_3_setup_vm_pt_regs,
 625 };