drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _AMDGPU_RAS_H
  25 #define _AMDGPU_RAS_H
  26
  27 #include <linux/debugfs.h>
  28 #include <linux/list.h>
  29 #include <linux/kfifo.h>
  30 #include <linux/radix-tree.h>
  31 #include <linux/siphash.h>
  32 #include "ta_ras_if.h"
  33 #include "amdgpu_ras_eeprom.h"
  34 #include "amdgpu_smuio.h"
  35 #include "amdgpu_aca.h"
  36
  37 struct amdgpu_iv_entry;
  38
  39 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x)              AMDGPU_GET_REG_FIELD(x, 0, 0)
  40 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x)                   AMDGPU_GET_REG_FIELD(x, 1, 1)
  41 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x)        AMDGPU_GET_REG_FIELD(x, 2, 2)
  42 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x)        AMDGPU_GET_REG_FIELD(x, 3, 3)
  43 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x)      AMDGPU_GET_REG_FIELD(x, 4, 4)
  44 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x)      AMDGPU_GET_REG_FIELD(x, 5, 5)
  45 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x)              AMDGPU_GET_REG_FIELD(x, 6, 6)
  46 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x)             AMDGPU_GET_REG_FIELD(x, 7, 7)
  47 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x)                 AMDGPU_GET_REG_FIELD(x, 10, 8)
  48 #define AMDGPU_RAS_GPU_ERR_AID_ID(x)                    AMDGPU_GET_REG_FIELD(x, 12, 11)
  49 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x)                    AMDGPU_GET_REG_FIELD(x, 14, 13)
  50
  51 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT    100
  52 #define AMDGPU_RAS_BOOT_STEADY_STATUS           0xBA
  53 #define AMDGPU_RAS_BOOT_STATUS_MASK             0xFF
  54
  55 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS           (0x1 << 0)
  56 /* position of instance value in sub_block_index of
  57  * ta_ras_trigger_error_input, the sub block uses lower 12 bits
  58  */
  59 #define AMDGPU_RAS_INST_MASK 0xfffff000
  60 #define AMDGPU_RAS_INST_SHIFT 0xc
  61
  62 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29
  63 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000
  64
  65 /* Reserve 8 physical dram row for possible retirement.
  66  * In worst cases, it will lose 8 * 2MB memory in vram domain */
  67 #define AMDGPU_RAS_RESERVED_VRAM_SIZE   (16ULL << 20)
  68 /* The high three bits indicates socketid */
  69 #define AMDGPU_RAS_GET_FEATURES(val)  ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)
  70
  71 #define RAS_EVENT_INVALID_ID            (BIT_ULL(63))
  72 #define RAS_EVENT_ID_IS_VALID(x)        (!((x) & BIT_ULL(63)))
  73
  74 #define RAS_EVENT_LOG(adev, id, fmt, ...)       \
  75         amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__)
  76
  77 #define amdgpu_ras_mark_ras_event(adev, type)   \
  78         (amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0)))
  79
  80 enum amdgpu_ras_block {
  81         AMDGPU_RAS_BLOCK__UMC = 0,
  82         AMDGPU_RAS_BLOCK__SDMA,
  83         AMDGPU_RAS_BLOCK__GFX,
  84         AMDGPU_RAS_BLOCK__MMHUB,
  85         AMDGPU_RAS_BLOCK__ATHUB,
  86         AMDGPU_RAS_BLOCK__PCIE_BIF,
  87         AMDGPU_RAS_BLOCK__HDP,
  88         AMDGPU_RAS_BLOCK__XGMI_WAFL,
  89         AMDGPU_RAS_BLOCK__DF,
  90         AMDGPU_RAS_BLOCK__SMN,
  91         AMDGPU_RAS_BLOCK__SEM,
  92         AMDGPU_RAS_BLOCK__MP0,
  93         AMDGPU_RAS_BLOCK__MP1,
  94         AMDGPU_RAS_BLOCK__FUSE,
  95         AMDGPU_RAS_BLOCK__MCA,
  96         AMDGPU_RAS_BLOCK__VCN,
  97         AMDGPU_RAS_BLOCK__JPEG,
  98         AMDGPU_RAS_BLOCK__IH,
  99         AMDGPU_RAS_BLOCK__MPIO,
 100
 101         AMDGPU_RAS_BLOCK__LAST
 102 };
 103
 104 enum amdgpu_ras_mca_block {
 105         AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
 106         AMDGPU_RAS_MCA_BLOCK__MP1,
 107         AMDGPU_RAS_MCA_BLOCK__MPIO,
 108         AMDGPU_RAS_MCA_BLOCK__IOHC,
 109
 110         AMDGPU_RAS_MCA_BLOCK__LAST
 111 };
 112
 113 #define AMDGPU_RAS_BLOCK_COUNT  AMDGPU_RAS_BLOCK__LAST
 114 #define AMDGPU_RAS_MCA_BLOCK_COUNT      AMDGPU_RAS_MCA_BLOCK__LAST
 115 #define AMDGPU_RAS_BLOCK_MASK   ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
 116
 117 enum amdgpu_ras_gfx_subblock {
 118         /* CPC */
 119         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
 120         AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
 121                 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
 122         AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
 123         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
 124         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
 125         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
 126         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
 127         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
 128         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
 129         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
 130                 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
 131         /* CPF */
 132         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
 133         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
 134                 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
 135         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
 136         AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
 137         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
 138         /* CPG */
 139         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
 140         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
 141                 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
 142         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
 143         AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
 144         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
 145         /* GDS */
 146         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
 147         AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
 148         AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
 149         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
 150         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
 151         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 152         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
 153                 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 154         /* SPI */
 155         AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
 156         /* SQ */
 157         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 158         AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 159         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
 160         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
 161         AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 162         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 163         /* SQC (3 ranges) */
 164         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 165         /* SQC range 0 */
 166         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
 167                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 168         AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 169                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
 170         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 171         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 172         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 173         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 174         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 175         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 176         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
 177                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 178         /* SQC range 1 */
 179         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 180         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 181                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 182         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 183         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 184         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 185         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 186         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 187         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 188         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 189         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 190         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
 191                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 192         /* SQC range 2 */
 193         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 194         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 195                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 196         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 197         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 198         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 199         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 200         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 201         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 202         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 203         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 204         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
 205                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 206         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
 207                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
 208         /* TA */
 209         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 210         AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
 211                 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 212         AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
 213         AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
 214         AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
 215         AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 216         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 217         /* TCA */
 218         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 219         AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
 220                 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 221         AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 222         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
 223                 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 224         /* TCC (5 sub-ranges) */
 225         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 226         /* TCC range 0 */
 227         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
 228                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 229         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
 230                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
 231         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 232         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 233         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 234         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 235         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 236         AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 237         AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 238         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
 239                 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 240         /* TCC range 1 */
 241         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 242         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
 243                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 244         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 245         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
 246                 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 247         /* TCC range 2 */
 248         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 249         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
 250                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 251         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 252         AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 253         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 254         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 255         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 256         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 257         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 258         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
 259                 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 260         /* TCC range 3 */
 261         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 262         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
 263                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 264         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 265         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
 266                 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 267         /* TCC range 4 */
 268         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 269         AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 270                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 271         AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 272         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
 273                 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 274         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
 275                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
 276         /* TCI */
 277         AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 278         /* TCP */
 279         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 280         AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
 281                 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 282         AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 283         AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 284         AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
 285         AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
 286         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 287         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 288         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
 289                 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 290         /* TD */
 291         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 292         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
 293                 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 294         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 295         AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 296         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 297         /* EA (3 sub-ranges) */
 298         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 299         /* EA range 0 */
 300         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
 301                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 302         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
 303                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
 304         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 305         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 306         AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 307         AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 308         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 309         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 310         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 311         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
 312                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 313         /* EA range 1 */
 314         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 315         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
 316                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 317         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 318         AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 319         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 320         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 321         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 322         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 323         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
 324                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 325         /* EA range 2 */
 326         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 327         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
 328                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 329         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 330         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 331         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 332         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
 333                 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 334         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
 335                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
 336         /* UTC VM L2 bank */
 337         AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 338         /* UTC VM walker */
 339         AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
 340         /* UTC ATC L2 2MB cache */
 341         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 342         /* UTC ATC L2 4KB cache */
 343         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 344         AMDGPU_RAS_BLOCK__GFX_MAX
 345 };
 346
 347 enum amdgpu_ras_error_type {
 348         AMDGPU_RAS_ERROR__NONE                                                  = 0,
 349         AMDGPU_RAS_ERROR__PARITY                                                = 1,
 350         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE                                    = 2,
 351         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE                                   = 4,
 352         AMDGPU_RAS_ERROR__POISON                                                = 8,
 353 };
 354
 355 enum amdgpu_ras_ret {
 356         AMDGPU_RAS_SUCCESS = 0,
 357         AMDGPU_RAS_FAIL,
 358         AMDGPU_RAS_UE,
 359         AMDGPU_RAS_CE,
 360         AMDGPU_RAS_PT,
 361 };
 362
 363 enum amdgpu_ras_error_query_mode {
 364         AMDGPU_RAS_INVALID_ERROR_QUERY          = 0,
 365         AMDGPU_RAS_DIRECT_ERROR_QUERY           = 1,
 366         AMDGPU_RAS_FIRMWARE_ERROR_QUERY         = 2,
 367 };
 368
 369 /* ras error status reisger fields */
 370 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT     0x0
 371 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK       0x00000001L
 372 #define ERR_STATUS_LO__MEMORY_ID__SHIFT                 0x18
 373 #define ERR_STATUS_LO__MEMORY_ID_MASK                   0xFF000000L
 374 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT       0x2
 375 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK         0x00000004L
 376 #define ERR_STATUS__ERR_CNT__SHIFT                      0x17
 377 #define ERR_STATUS__ERR_CNT_MASK                        0x03800000L
 378
 379 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
 380         ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
 381
 382 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
 383         (adev->reg_offset[hwip][ip_inst][segment] + (reg))
 384
 385 #define AMDGPU_RAS_ERR_INFO_VALID       (1 << 0)
 386 #define AMDGPU_RAS_ERR_STATUS_VALID     (1 << 1)
 387 #define AMDGPU_RAS_ERR_ADDRESS_VALID    (1 << 2)
 388
 389 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET  (0x1 << 0)
 390 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET  (0x1 << 1)
 391
 392 struct amdgpu_ras_err_status_reg_entry {
 393         uint32_t hwip;
 394         uint32_t ip_inst;
 395         uint32_t seg_lo;
 396         uint32_t reg_lo;
 397         uint32_t seg_hi;
 398         uint32_t reg_hi;
 399         uint32_t reg_inst;
 400         uint32_t flags;
 401         const char *block_name;
 402 };
 403
 404 struct amdgpu_ras_memory_id_entry {
 405         uint32_t memory_id;
 406         const char *name;
 407 };
 408
 409 struct ras_common_if {
 410         enum amdgpu_ras_block block;
 411         enum amdgpu_ras_error_type type;
 412         uint32_t sub_block_index;
 413         char name[32];
 414 };
 415
 416 #define MAX_UMC_CHANNEL_NUM 32
 417
 418 struct ecc_info_per_ch {
 419         uint16_t ce_count_lo_chip;
 420         uint16_t ce_count_hi_chip;
 421         uint64_t mca_umc_status;
 422         uint64_t mca_umc_addr;
 423         uint64_t mca_ceumc_addr;
 424 };
 425
 426 struct umc_ecc_info {
 427         struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
 428
 429         /* Determine smu ecctable whether support
 430          * record correctable error address
 431          */
 432         int record_ce_addr_supported;
 433 };
 434
 435 enum ras_event_type {
 436         RAS_EVENT_TYPE_INVALID = 0,
 437         RAS_EVENT_TYPE_FATAL,
 438         RAS_EVENT_TYPE_POISON_CREATION,
 439         RAS_EVENT_TYPE_POISON_CONSUMPTION,
 440         RAS_EVENT_TYPE_COUNT,
 441 };
 442
 443 struct ras_event_state {
 444         u64 last_seqno;
 445         atomic64_t count;
 446 };
 447
 448 struct ras_event_manager {
 449         atomic64_t seqno;
 450         struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT];
 451 };
 452
 453 struct ras_event_id {
 454         enum ras_event_type type;
 455         u64 event_id;
 456 };
 457
 458 struct ras_query_context {
 459         struct ras_event_id evid;
 460 };
 461
 462 typedef int (*pasid_notify)(struct amdgpu_device *adev,
 463                 uint16_t pasid, void *data);
 464
 465 struct ras_poison_msg {
 466         enum amdgpu_ras_block block;
 467         uint16_t pasid;
 468         uint32_t reset;
 469         pasid_notify pasid_fn;
 470         void *data;
 471 };
 472
 473 struct ras_err_pages {
 474         uint32_t count;
 475         uint64_t *pfn;
 476 };
 477
 478 struct ras_ecc_err {
 479         u64 hash_index;
 480         uint64_t status;
 481         uint64_t ipid;
 482         uint64_t addr;
 483         struct ras_err_pages err_pages;
 484 };
 485
 486 struct ras_ecc_log_info {
 487         struct mutex lock;
 488         siphash_key_t ecc_key;
 489         struct radix_tree_root de_page_tree;
 490         uint64_t        de_queried_count;
 491         uint64_t        prev_de_queried_count;
 492 };
 493
 494 struct amdgpu_ras {
 495         /* ras infrastructure */
 496         /* for ras itself. */
 497         uint32_t features;
 498         uint32_t schema;
 499         struct list_head head;
 500         /* sysfs */
 501         struct device_attribute features_attr;
 502         struct device_attribute version_attr;
 503         struct device_attribute schema_attr;
 504         struct device_attribute event_state_attr;
 505         struct bin_attribute badpages_attr;
 506         struct dentry *de_ras_eeprom_table;
 507         /* block array */
 508         struct ras_manager *objs;
 509
 510         /* gpu recovery */
 511         struct work_struct recovery_work;
 512         atomic_t in_recovery;
 513         struct amdgpu_device *adev;
 514         /* error handler data */
 515         struct ras_err_handler_data *eh_data;
 516         struct mutex recovery_lock;
 517
 518         uint32_t flags;
 519         bool reboot;
 520         struct amdgpu_ras_eeprom_control eeprom_control;
 521
 522         bool error_query_ready;
 523
 524         /* bad page count threshold */
 525         uint32_t bad_page_cnt_threshold;
 526
 527         /* disable ras error count harvest in recovery */
 528         bool disable_ras_err_cnt_harvest;
 529
 530         /* is poison mode supported */
 531         bool poison_supported;
 532
 533         /* RAS count errors delayed work */
 534         struct delayed_work ras_counte_delay_work;
 535         atomic_t ras_ue_count;
 536         atomic_t ras_ce_count;
 537
 538         /* record umc error info queried from smu */
 539         struct umc_ecc_info umc_ecc;
 540
 541         /* Indicates smu whether need update bad channel info */
 542         bool update_channel_flag;
 543         /* Record status of smu mca debug mode */
 544         bool is_aca_debug_mode;
 545         bool is_rma;
 546
 547         /* Record special requirements of gpu reset caller */
 548         uint32_t  gpu_reset_flags;
 549
 550         struct task_struct *page_retirement_thread;
 551         wait_queue_head_t page_retirement_wq;
 552         struct mutex page_retirement_lock;
 553         atomic_t page_retirement_req_cnt;
 554         atomic_t poison_creation_count;
 555         struct mutex page_rsv_lock;
 556         DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128);
 557         struct ras_ecc_log_info  umc_ecc_log;
 558         struct delayed_work page_retirement_dwork;
 559
 560         /* Fatal error detected flag */
 561         atomic_t fed;
 562
 563         /* RAS event manager */
 564         struct ras_event_manager __event_mgr;
 565         struct ras_event_manager *event_mgr;
 566
 567         uint64_t reserved_pages_in_bytes;
 568 };
 569
 570 struct ras_fs_data {
 571         char sysfs_name[48];
 572         char debugfs_name[32];
 573 };
 574
 575 struct ras_err_addr {
 576         struct list_head node;
 577         uint64_t err_status;
 578         uint64_t err_ipid;
 579         uint64_t err_addr;
 580 };
 581
 582 struct ras_err_info {
 583         struct amdgpu_smuio_mcm_config_info mcm_info;
 584         u64 ce_count;
 585         u64 ue_count;
 586         u64 de_count;
 587         struct list_head err_addr_list;
 588 };
 589
 590 struct ras_err_node {
 591         struct list_head node;
 592         struct ras_err_info err_info;
 593 };
 594
 595 struct ras_err_data {
 596         unsigned long ue_count;
 597         unsigned long ce_count;
 598         unsigned long de_count;
 599         unsigned long err_addr_cnt;
 600         struct eeprom_table_record *err_addr;
 601         unsigned long err_addr_len;
 602         u32 err_list_count;
 603         struct list_head err_node_list;
 604 };
 605
 606 #define for_each_ras_error(err_node, err_data) \
 607         list_for_each_entry(err_node, &(err_data)->err_node_list, node)
 608
 609 struct ras_err_handler_data {
 610         /* point to bad page records array */
 611         struct eeprom_table_record *bps;
 612         /* the count of entries */
 613         int count;
 614         /* the space can place new entries */
 615         int space_left;
 616 };
 617
 618 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
 619                 void *err_data,
 620                 struct amdgpu_iv_entry *entry);
 621
 622 struct ras_ih_data {
 623         /* interrupt bottom half */
 624         struct work_struct ih_work;
 625         int inuse;
 626         /* IP callback */
 627         ras_ih_cb cb;
 628         /* full of entries */
 629         unsigned char *ring;
 630         unsigned int ring_size;
 631         unsigned int element_size;
 632         unsigned int aligned_element_size;
 633         unsigned int rptr;
 634         unsigned int wptr;
 635 };
 636
 637 struct ras_manager {
 638         struct ras_common_if head;
 639         /* reference count */
 640         int use;
 641         /* ras block link */
 642         struct list_head node;
 643         /* the device */
 644         struct amdgpu_device *adev;
 645         /* sysfs */
 646         struct device_attribute sysfs_attr;
 647         int attr_inuse;
 648
 649         /* fs node name */
 650         struct ras_fs_data fs_data;
 651
 652         /* IH data */
 653         struct ras_ih_data ih_data;
 654
 655         struct ras_err_data err_data;
 656
 657         struct aca_handle aca_handle;
 658 };
 659
 660 struct ras_badpage {
 661         unsigned int bp;
 662         unsigned int size;
 663         unsigned int flags;
 664 };
 665
 666 /* interfaces for IP */
 667 struct ras_fs_if {
 668         struct ras_common_if head;
 669         const char* sysfs_name;
 670         char debugfs_name[32];
 671 };
 672
 673 struct ras_query_if {
 674         struct ras_common_if head;
 675         unsigned long ue_count;
 676         unsigned long ce_count;
 677         unsigned long de_count;
 678 };
 679
 680 struct ras_inject_if {
 681         struct ras_common_if head;
 682         uint64_t address;
 683         uint64_t value;
 684         uint32_t instance_mask;
 685 };
 686
 687 struct ras_cure_if {
 688         struct ras_common_if head;
 689         uint64_t address;
 690 };
 691
 692 struct ras_ih_if {
 693         struct ras_common_if head;
 694         ras_ih_cb cb;
 695 };
 696
 697 struct ras_dispatch_if {
 698         struct ras_common_if head;
 699         struct amdgpu_iv_entry *entry;
 700 };
 701
 702 struct ras_debug_if {
 703         union {
 704                 struct ras_common_if head;
 705                 struct ras_inject_if inject;
 706         };
 707         int op;
 708 };
 709
 710 struct amdgpu_ras_block_object {
 711         struct ras_common_if  ras_comm;
 712
 713         int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
 714                                 enum amdgpu_ras_block block, uint32_t sub_block_index);
 715         int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 716         void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 717         ras_ih_cb ras_cb;
 718         const struct amdgpu_ras_block_hw_ops *hw_ops;
 719 };
 720
 721 struct amdgpu_ras_block_hw_ops {
 722         int  (*ras_error_inject)(struct amdgpu_device *adev,
 723                         void *inject_if, uint32_t instance_mask);
 724         void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
 725         void (*query_ras_error_status)(struct amdgpu_device *adev);
 726         void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
 727         void (*reset_ras_error_count)(struct amdgpu_device *adev);
 728         void (*reset_ras_error_status)(struct amdgpu_device *adev);
 729         bool (*query_poison_status)(struct amdgpu_device *adev);
 730         bool (*handle_poison_consumption)(struct amdgpu_device *adev);
 731 };
 732
 733 /* work flow
 734  * vbios
 735  * 1: ras feature enable (enabled by default)
 736  * psp
 737  * 2: ras framework init (in ip_init)
 738  * IP
 739  * 3: IH add
 740  * 4: debugfs/sysfs create
 741  * 5: query/inject
 742  * 6: debugfs/sysfs remove
 743  * 7: IH remove
 744  * 8: feature disable
 745  */
 746
 747
 748 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
 749
 750 void amdgpu_ras_resume(struct amdgpu_device *adev);
 751 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 752
 753 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 754                                  unsigned long *ce_count,
 755                                  unsigned long *ue_count,
 756                                  struct ras_query_if *query_info);
 757
 758 /* error handling functions */
 759 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 760                 struct eeprom_table_record *bps, int pages);
 761
 762 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
 763                 unsigned long *new_cnt);
 764
 765 static inline enum ta_ras_block
 766 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
 767         switch (block) {
 768         case AMDGPU_RAS_BLOCK__UMC:
 769                 return TA_RAS_BLOCK__UMC;
 770         case AMDGPU_RAS_BLOCK__SDMA:
 771                 return TA_RAS_BLOCK__SDMA;
 772         case AMDGPU_RAS_BLOCK__GFX:
 773                 return TA_RAS_BLOCK__GFX;
 774         case AMDGPU_RAS_BLOCK__MMHUB:
 775                 return TA_RAS_BLOCK__MMHUB;
 776         case AMDGPU_RAS_BLOCK__ATHUB:
 777                 return TA_RAS_BLOCK__ATHUB;
 778         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 779                 return TA_RAS_BLOCK__PCIE_BIF;
 780         case AMDGPU_RAS_BLOCK__HDP:
 781                 return TA_RAS_BLOCK__HDP;
 782         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 783                 return TA_RAS_BLOCK__XGMI_WAFL;
 784         case AMDGPU_RAS_BLOCK__DF:
 785                 return TA_RAS_BLOCK__DF;
 786         case AMDGPU_RAS_BLOCK__SMN:
 787                 return TA_RAS_BLOCK__SMN;
 788         case AMDGPU_RAS_BLOCK__SEM:
 789                 return TA_RAS_BLOCK__SEM;
 790         case AMDGPU_RAS_BLOCK__MP0:
 791                 return TA_RAS_BLOCK__MP0;
 792         case AMDGPU_RAS_BLOCK__MP1:
 793                 return TA_RAS_BLOCK__MP1;
 794         case AMDGPU_RAS_BLOCK__FUSE:
 795                 return TA_RAS_BLOCK__FUSE;
 796         case AMDGPU_RAS_BLOCK__MCA:
 797                 return TA_RAS_BLOCK__MCA;
 798         case AMDGPU_RAS_BLOCK__VCN:
 799                 return TA_RAS_BLOCK__VCN;
 800         case AMDGPU_RAS_BLOCK__JPEG:
 801                 return TA_RAS_BLOCK__JPEG;
 802         default:
 803                 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
 804                 return TA_RAS_BLOCK__UMC;
 805         }
 806 }
 807
 808 static inline enum ta_ras_error_type
 809 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
 810         switch (error) {
 811         case AMDGPU_RAS_ERROR__NONE:
 812                 return TA_RAS_ERROR__NONE;
 813         case AMDGPU_RAS_ERROR__PARITY:
 814                 return TA_RAS_ERROR__PARITY;
 815         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
 816                 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
 817         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
 818                 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
 819         case AMDGPU_RAS_ERROR__POISON:
 820                 return TA_RAS_ERROR__POISON;
 821         default:
 822                 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
 823                 return TA_RAS_ERROR__NONE;
 824         }
 825 }
 826
 827 /* called in ip_init and ip_fini */
 828 int amdgpu_ras_init(struct amdgpu_device *adev);
 829 int amdgpu_ras_late_init(struct amdgpu_device *adev);
 830 int amdgpu_ras_fini(struct amdgpu_device *adev);
 831 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
 832
 833 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
 834                         struct ras_common_if *ras_block);
 835
 836 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
 837                           struct ras_common_if *ras_block);
 838
 839 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 840                 struct ras_common_if *head, bool enable);
 841
 842 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 843                 struct ras_common_if *head, bool enable);
 844
 845 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
 846                 struct ras_common_if *head);
 847
 848 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
 849                 struct ras_common_if *head);
 850
 851 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 852
 853 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 854                 struct ras_query_if *info);
 855
 856 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
 857                 enum amdgpu_ras_block block);
 858 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 859                 enum amdgpu_ras_block block);
 860
 861 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 862                 struct ras_inject_if *info);
 863
 864 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
 865                 struct ras_common_if *head);
 866
 867 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
 868                 struct ras_common_if *head);
 869
 870 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
 871                 struct ras_dispatch_if *info);
 872
 873 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 874                 struct ras_common_if *head);
 875
 876 extern atomic_t amdgpu_ras_in_intr;
 877
 878 static inline bool amdgpu_ras_intr_triggered(void)
 879 {
 880         return !!atomic_read(&amdgpu_ras_in_intr);
 881 }
 882
 883 static inline void amdgpu_ras_intr_cleared(void)
 884 {
 885         atomic_set(&amdgpu_ras_in_intr, 0);
 886 }
 887
 888 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
 889
 890 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 891
 892 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 893
 894 void amdgpu_release_ras_context(struct amdgpu_device *adev);
 895
 896 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
 897
 898 const char *get_ras_block_str(struct ras_common_if *ras_block);
 899
 900 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
 901
 902 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
 903
 904 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
 905
 906 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
 907
 908 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
 909
 910 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);
 911 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable);
 912 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev);
 913 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
 914                                      unsigned int *mode);
 915
 916 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
 917                                 struct amdgpu_ras_block_object *ras_block_obj);
 918 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
 919 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);
 920 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
 921                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
 922                                          uint32_t instance,
 923                                          uint32_t *memory_id);
 924 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
 925                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
 926                                        uint32_t instance,
 927                                        unsigned long *err_cnt);
 928 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
 929                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
 930                                            uint32_t reg_list_size,
 931                                            const struct amdgpu_ras_memory_id_entry *mem_list,
 932                                            uint32_t mem_list_size,
 933                                            uint32_t instance,
 934                                            uint32_t err_type,
 935                                            unsigned long *err_count);
 936 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
 937                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
 938                                            uint32_t reg_list_size,
 939                                            uint32_t instance);
 940
 941 int amdgpu_ras_error_data_init(struct ras_err_data *err_data);
 942 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data);
 943 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
 944                 struct amdgpu_smuio_mcm_config_info *mcm_info,
 945                 struct ras_err_addr *err_addr, u64 count);
 946 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
 947                 struct amdgpu_smuio_mcm_config_info *mcm_info,
 948                 struct ras_err_addr *err_addr, u64 count);
 949 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,
 950                 struct amdgpu_smuio_mcm_config_info *mcm_info,
 951                 struct ras_err_addr *err_addr, u64 count);
 952 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances);
 953 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
 954                                const struct aca_info *aca_info, void *data);
 955 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk);
 956
 957 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr,
 958                                   struct aca_handle *handle, char *buf, void *data);
 959
 960 void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info,
 961                         struct ras_err_addr *err_addr);
 962
 963 void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info,
 964                 struct ras_err_addr *mca_err_addr);
 965
 966 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status);
 967 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev);
 968
 969 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type);
 970 int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type,
 971                                      const void *caller);
 972
 973 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn);
 974
 975 int amdgpu_ras_put_poison_req(struct amdgpu_device *adev,
 976                 enum amdgpu_ras_block block, uint16_t pasid,
 977                 pasid_notify pasid_fn, void *data, uint32_t reset);
 978
 979 bool amdgpu_ras_in_recovery(struct amdgpu_device *adev);
 980
 981 __printf(3, 4)
 982 void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
 983                                 const char *fmt, ...);
 984
 985 #endif