drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31 #include "amdgpu_xcp.h"
  32 #include "amdgpu_xgmi.h"
  33
  34 /* delay 0.1 second to enable gfx off feature */
  35 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  36
  37 #define GFX_OFF_NO_DELAY 0
  38
  39 /*
  40  * GPU GFX IP block helpers function.
  41  */
  42
  43 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  44                                 int pipe, int queue)
  45 {
  46         int bit = 0;
  47
  48         bit += mec * adev->gfx.mec.num_pipe_per_mec
  49                 * adev->gfx.mec.num_queue_per_pipe;
  50         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  51         bit += queue;
  52
  53         return bit;
  54 }
  55
  56 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  57                                  int *mec, int *pipe, int *queue)
  58 {
  59         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  60         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  61                 % adev->gfx.mec.num_pipe_per_mec;
  62         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  63                / adev->gfx.mec.num_pipe_per_mec;
  64
  65 }
  66
  67 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  68                                      int xcc_id, int mec, int pipe, int queue)
  69 {
  70         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  71                         adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
  72 }
  73
  74 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  75                                int me, int pipe, int queue)
  76 {
  77         int bit = 0;
  78
  79         bit += me * adev->gfx.me.num_pipe_per_me
  80                 * adev->gfx.me.num_queue_per_pipe;
  81         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  82         bit += queue;
  83
  84         return bit;
  85 }
  86
  87 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  88                                 int *me, int *pipe, int *queue)
  89 {
  90         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  91         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  92                 % adev->gfx.me.num_pipe_per_me;
  93         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  94                 / adev->gfx.me.num_pipe_per_me;
  95 }
  96
  97 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  98                                     int me, int pipe, int queue)
  99 {
 100         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
 101                         adev->gfx.me.queue_bitmap);
 102 }
 103
 104 /**
 105  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 106  *
 107  * @mask: array in which the per-shader array disable masks will be stored
 108  * @max_se: number of SEs
 109  * @max_sh: number of SHs
 110  *
 111  * The bitmask of CUs to be disabled in the shader array determined by se and
 112  * sh is stored in mask[se * max_sh + sh].
 113  */
 114 void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsigned int max_sh)
 115 {
 116         unsigned int se, sh, cu;
 117         const char *p;
 118
 119         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 120
 121         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 122                 return;
 123
 124         p = amdgpu_disable_cu;
 125         for (;;) {
 126                 char *next;
 127                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 128
 129                 if (ret < 3) {
 130                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 131                         return;
 132                 }
 133
 134                 if (se < max_se && sh < max_sh && cu < 16) {
 135                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 136                         mask[se * max_sh + sh] |= 1u << cu;
 137                 } else {
 138                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 139                                   se, sh, cu);
 140                 }
 141
 142                 next = strchr(p, ',');
 143                 if (!next)
 144                         break;
 145                 p = next + 1;
 146         }
 147 }
 148
 149 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 150 {
 151         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 152 }
 153
 154 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 155 {
 156         if (amdgpu_compute_multipipe != -1) {
 157                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 158                          amdgpu_compute_multipipe);
 159                 return amdgpu_compute_multipipe == 1;
 160         }
 161
 162         if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0))
 163                 return true;
 164
 165         /* FIXME: spreading the queues across pipes causes perf regressions
 166          * on POLARIS11 compute workloads */
 167         if (adev->asic_type == CHIP_POLARIS11)
 168                 return false;
 169
 170         return adev->gfx.mec.num_mec > 1;
 171 }
 172
 173 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 174                                                 struct amdgpu_ring *ring)
 175 {
 176         int queue = ring->queue;
 177         int pipe = ring->pipe;
 178
 179         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 180          * have more than one gfx pipe.
 181          */
 182         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 183             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 184                 int me = ring->me;
 185                 int bit;
 186
 187                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 188                 if (ring == &adev->gfx.gfx_ring[bit])
 189                         return true;
 190         }
 191
 192         return false;
 193 }
 194
 195 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 196                                                struct amdgpu_ring *ring)
 197 {
 198         /* Policy: use 1st queue as high priority compute queue if we
 199          * have more than one compute queue.
 200          */
 201         if (adev->gfx.num_compute_rings > 1 &&
 202             ring == &adev->gfx.compute_ring[0])
 203                 return true;
 204
 205         return false;
 206 }
 207
 208 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 209 {
 210         int i, j, queue, pipe;
 211         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 212         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 213                                      adev->gfx.mec.num_queue_per_pipe,
 214                                      adev->gfx.num_compute_rings);
 215         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 216
 217         if (multipipe_policy) {
 218                 /* policy: make queues evenly cross all pipes on MEC1 only
 219                  * for multiple xcc, just use the original policy for simplicity */
 220                 for (j = 0; j < num_xcc; j++) {
 221                         for (i = 0; i < max_queues_per_mec; i++) {
 222                                 pipe = i % adev->gfx.mec.num_pipe_per_mec;
 223                                 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 224                                          adev->gfx.mec.num_queue_per_pipe;
 225
 226                                 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 227                                         adev->gfx.mec_bitmap[j].queue_bitmap);
 228                         }
 229                 }
 230         } else {
 231                 /* policy: amdgpu owns all queues in the given pipe */
 232                 for (j = 0; j < num_xcc; j++) {
 233                         for (i = 0; i < max_queues_per_mec; ++i)
 234                                 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
 235                 }
 236         }
 237
 238         for (j = 0; j < num_xcc; j++) {
 239                 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
 240                         bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 241         }
 242 }
 243
 244 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 245 {
 246         int i, queue, pipe;
 247         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 248         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 249                                         adev->gfx.me.num_queue_per_pipe;
 250
 251         if (multipipe_policy) {
 252                 /* policy: amdgpu owns the first queue per pipe at this stage
 253                  * will extend to mulitple queues per pipe later */
 254                 for (i = 0; i < max_queues_per_me; i++) {
 255                         pipe = i % adev->gfx.me.num_pipe_per_me;
 256                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 257                                 adev->gfx.me.num_queue_per_pipe;
 258
 259                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 260                                 adev->gfx.me.queue_bitmap);
 261                 }
 262         } else {
 263                 for (i = 0; i < max_queues_per_me; ++i)
 264                         set_bit(i, adev->gfx.me.queue_bitmap);
 265         }
 266
 267         /* update the number of active graphics rings */
 268         adev->gfx.num_gfx_rings =
 269                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 270 }
 271
 272 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 273                                   struct amdgpu_ring *ring, int xcc_id)
 274 {
 275         int queue_bit;
 276         int mec, pipe, queue;
 277
 278         queue_bit = adev->gfx.mec.num_mec
 279                     * adev->gfx.mec.num_pipe_per_mec
 280                     * adev->gfx.mec.num_queue_per_pipe;
 281
 282         while (--queue_bit >= 0) {
 283                 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 284                         continue;
 285
 286                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 287
 288                 /*
 289                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 290                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 291                  * only can be issued on queue 0.
 292                  */
 293                 if ((mec == 1 && pipe > 1) || queue != 0)
 294                         continue;
 295
 296                 ring->me = mec + 1;
 297                 ring->pipe = pipe;
 298                 ring->queue = queue;
 299
 300                 return 0;
 301         }
 302
 303         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 304         return -EINVAL;
 305 }
 306
 307 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id)
 308 {
 309         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 310         struct amdgpu_irq_src *irq = &kiq->irq;
 311         struct amdgpu_ring *ring = &kiq->ring;
 312         int r = 0;
 313
 314         spin_lock_init(&kiq->ring_lock);
 315
 316         ring->adev = NULL;
 317         ring->ring_obj = NULL;
 318         ring->use_doorbell = true;
 319         ring->xcc_id = xcc_id;
 320         ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
 321         ring->doorbell_index =
 322                 (adev->doorbell_index.kiq +
 323                  xcc_id * adev->doorbell_index.xcc_doorbell_range)
 324                 << 1;
 325
 326         r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id);
 327         if (r)
 328                 return r;
 329
 330         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 331         ring->no_scheduler = true;
 332         snprintf(ring->name, sizeof(ring->name), "kiq_%hhu.%hhu.%hhu.%hhu",
 333                  (unsigned char)xcc_id, (unsigned char)ring->me,
 334                  (unsigned char)ring->pipe, (unsigned char)ring->queue);
 335         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 336                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 337         if (r)
 338                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 339
 340         return r;
 341 }
 342
 343 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 344 {
 345         amdgpu_ring_fini(ring);
 346 }
 347
 348 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id)
 349 {
 350         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 351
 352         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 353 }
 354
 355 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 356                         unsigned int hpd_size, int xcc_id)
 357 {
 358         int r;
 359         u32 *hpd;
 360         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 361
 362         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 363                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 364                                     &kiq->eop_gpu_addr, (void **)&hpd);
 365         if (r) {
 366                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 367                 return r;
 368         }
 369
 370         memset(hpd, 0, hpd_size);
 371
 372         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 373         if (unlikely(r != 0))
 374                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 375         amdgpu_bo_kunmap(kiq->eop_obj);
 376         amdgpu_bo_unreserve(kiq->eop_obj);
 377
 378         return 0;
 379 }
 380
 381 /* create MQD for each compute/gfx queue */
 382 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 383                            unsigned int mqd_size, int xcc_id)
 384 {
 385         int r, i, j;
 386         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 387         struct amdgpu_ring *ring = &kiq->ring;
 388         u32 domain = AMDGPU_GEM_DOMAIN_GTT;
 389
 390 #if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
 391         /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
 392         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0))
 393                 domain |= AMDGPU_GEM_DOMAIN_VRAM;
 394 #endif
 395
 396         /* create MQD for KIQ */
 397         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 398                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 399                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 400                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 401                  * KIQ MQD no matter SRIOV or Bare-metal
 402                  */
 403                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 404                                             AMDGPU_GEM_DOMAIN_VRAM |
 405                                             AMDGPU_GEM_DOMAIN_GTT,
 406                                             &ring->mqd_obj,
 407                                             &ring->mqd_gpu_addr,
 408                                             &ring->mqd_ptr);
 409                 if (r) {
 410                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 411                         return r;
 412                 }
 413
 414                 /* prepare MQD backup */
 415                 kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
 416                 if (!kiq->mqd_backup) {
 417                         dev_warn(adev->dev,
 418                                  "no memory to create MQD backup for ring %s\n", ring->name);
 419                         return -ENOMEM;
 420                 }
 421         }
 422
 423         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 424                 /* create MQD for each KGQ */
 425                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 426                         ring = &adev->gfx.gfx_ring[i];
 427                         if (!ring->mqd_obj) {
 428                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 429                                                             domain, &ring->mqd_obj,
 430                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 431                                 if (r) {
 432                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 433                                         return r;
 434                                 }
 435
 436                                 ring->mqd_size = mqd_size;
 437                                 /* prepare MQD backup */
 438                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 439                                 if (!adev->gfx.me.mqd_backup[i]) {
 440                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 441                                         return -ENOMEM;
 442                                 }
 443                         }
 444                 }
 445         }
 446
 447         /* create MQD for each KCQ */
 448         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 449                 j = i + xcc_id * adev->gfx.num_compute_rings;
 450                 ring = &adev->gfx.compute_ring[j];
 451                 if (!ring->mqd_obj) {
 452                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 453                                                     domain, &ring->mqd_obj,
 454                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 455                         if (r) {
 456                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 457                                 return r;
 458                         }
 459
 460                         ring->mqd_size = mqd_size;
 461                         /* prepare MQD backup */
 462                         adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL);
 463                         if (!adev->gfx.mec.mqd_backup[j]) {
 464                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 465                                 return -ENOMEM;
 466                         }
 467                 }
 468         }
 469
 470         return 0;
 471 }
 472
 473 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id)
 474 {
 475         struct amdgpu_ring *ring = NULL;
 476         int i, j;
 477         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 478
 479         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 480                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 481                         ring = &adev->gfx.gfx_ring[i];
 482                         kfree(adev->gfx.me.mqd_backup[i]);
 483                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 484                                               &ring->mqd_gpu_addr,
 485                                               &ring->mqd_ptr);
 486                 }
 487         }
 488
 489         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 490                 j = i + xcc_id * adev->gfx.num_compute_rings;
 491                 ring = &adev->gfx.compute_ring[j];
 492                 kfree(adev->gfx.mec.mqd_backup[j]);
 493                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 494                                       &ring->mqd_gpu_addr,
 495                                       &ring->mqd_ptr);
 496         }
 497
 498         ring = &kiq->ring;
 499         kfree(kiq->mqd_backup);
 500         amdgpu_bo_free_kernel(&ring->mqd_obj,
 501                               &ring->mqd_gpu_addr,
 502                               &ring->mqd_ptr);
 503 }
 504
 505 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
 506 {
 507         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 508         struct amdgpu_ring *kiq_ring = &kiq->ring;
 509         int i, r = 0;
 510         int j;
 511
 512         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 513                 return -EINVAL;
 514
 515         spin_lock(&kiq->ring_lock);
 516         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 517                                         adev->gfx.num_compute_rings)) {
 518                 spin_unlock(&kiq->ring_lock);
 519                 return -ENOMEM;
 520         }
 521
 522         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 523                 j = i + xcc_id * adev->gfx.num_compute_rings;
 524                 kiq->pmf->kiq_unmap_queues(kiq_ring,
 525                                            &adev->gfx.compute_ring[j],
 526                                            RESET_QUEUES, 0, 0);
 527         }
 528
 529         /**
 530          * This is workaround: only skip kiq_ring test
 531          * during ras recovery in suspend stage for gfx9.4.3
 532          */
 533         if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
 534             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) &&
 535             amdgpu_ras_in_recovery(adev)) {
 536                 spin_unlock(&kiq->ring_lock);
 537                 return 0;
 538         }
 539
 540         if (kiq_ring->sched.ready && !adev->job_hang)
 541                 r = amdgpu_ring_test_helper(kiq_ring);
 542         spin_unlock(&kiq->ring_lock);
 543
 544         return r;
 545 }
 546
 547 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
 548 {
 549         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 550         struct amdgpu_ring *kiq_ring = &kiq->ring;
 551         int i, r = 0;
 552         int j;
 553
 554         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 555                 return -EINVAL;
 556
 557         spin_lock(&kiq->ring_lock);
 558         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 559                 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 560                                                 adev->gfx.num_gfx_rings)) {
 561                         spin_unlock(&kiq->ring_lock);
 562                         return -ENOMEM;
 563                 }
 564
 565                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 566                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 567                         kiq->pmf->kiq_unmap_queues(kiq_ring,
 568                                                    &adev->gfx.gfx_ring[j],
 569                                                    PREEMPT_QUEUES, 0, 0);
 570                 }
 571         }
 572
 573         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 574                 r = amdgpu_ring_test_helper(kiq_ring);
 575         spin_unlock(&kiq->ring_lock);
 576
 577         return r;
 578 }
 579
 580 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 581                                         int queue_bit)
 582 {
 583         int mec, pipe, queue;
 584         int set_resource_bit = 0;
 585
 586         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 587
 588         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 589
 590         return set_resource_bit;
 591 }
 592
 593 static int amdgpu_gfx_mes_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 594 {
 595         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 596         struct amdgpu_ring *kiq_ring = &kiq->ring;
 597         uint64_t queue_mask = ~0ULL;
 598         int r, i, j;
 599
 600         amdgpu_device_flush_hdp(adev, NULL);
 601
 602         if (!adev->enable_uni_mes) {
 603                 spin_lock(&kiq->ring_lock);
 604                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->set_resources_size);
 605                 if (r) {
 606                         dev_err(adev->dev, "Failed to lock KIQ (%d).\n", r);
 607                         spin_unlock(&kiq->ring_lock);
 608                         return r;
 609                 }
 610
 611                 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 612                 r = amdgpu_ring_test_helper(kiq_ring);
 613                 spin_unlock(&kiq->ring_lock);
 614                 if (r)
 615                         dev_err(adev->dev, "KIQ failed to set resources\n");
 616         }
 617
 618         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 619                 j = i + xcc_id * adev->gfx.num_compute_rings;
 620                 r = amdgpu_mes_map_legacy_queue(adev,
 621                                                 &adev->gfx.compute_ring[j]);
 622                 if (r) {
 623                         dev_err(adev->dev, "failed to map compute queue\n");
 624                         return r;
 625                 }
 626         }
 627
 628         return 0;
 629 }
 630
 631 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 632 {
 633         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 634         struct amdgpu_ring *kiq_ring = &kiq->ring;
 635         uint64_t queue_mask = 0;
 636         int r, i, j;
 637
 638         if (adev->enable_mes)
 639                 return amdgpu_gfx_mes_enable_kcq(adev, xcc_id);
 640
 641         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 642                 return -EINVAL;
 643
 644         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 645                 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 646                         continue;
 647
 648                 /* This situation may be hit in the future if a new HW
 649                  * generation exposes more than 64 queues. If so, the
 650                  * definition of queue_mask needs updating */
 651                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 652                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 653                         break;
 654                 }
 655
 656                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 657         }
 658
 659         amdgpu_device_flush_hdp(adev, NULL);
 660
 661         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 662                  kiq_ring->queue);
 663
 664         spin_lock(&kiq->ring_lock);
 665         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 666                                         adev->gfx.num_compute_rings +
 667                                         kiq->pmf->set_resources_size);
 668         if (r) {
 669                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 670                 spin_unlock(&kiq->ring_lock);
 671                 return r;
 672         }
 673
 674         kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 675         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 676                 j = i + xcc_id * adev->gfx.num_compute_rings;
 677                 kiq->pmf->kiq_map_queues(kiq_ring,
 678                                          &adev->gfx.compute_ring[j]);
 679         }
 680
 681         r = amdgpu_ring_test_helper(kiq_ring);
 682         spin_unlock(&kiq->ring_lock);
 683         if (r)
 684                 DRM_ERROR("KCQ enable failed\n");
 685
 686         return r;
 687 }
 688
 689 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
 690 {
 691         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 692         struct amdgpu_ring *kiq_ring = &kiq->ring;
 693         int r, i, j;
 694
 695         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 696                 return -EINVAL;
 697
 698         amdgpu_device_flush_hdp(adev, NULL);
 699
 700         if (adev->enable_mes) {
 701                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 702                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 703                         r = amdgpu_mes_map_legacy_queue(adev,
 704                                                         &adev->gfx.gfx_ring[j]);
 705                         if (r) {
 706                                 DRM_ERROR("failed to map gfx queue\n");
 707                                 return r;
 708                         }
 709                 }
 710
 711                 return 0;
 712         }
 713
 714         spin_lock(&kiq->ring_lock);
 715         /* No need to map kcq on the slave */
 716         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 717                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 718                                                 adev->gfx.num_gfx_rings);
 719                 if (r) {
 720                         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 721                         spin_unlock(&kiq->ring_lock);
 722                         return r;
 723                 }
 724
 725                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 726                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 727                         kiq->pmf->kiq_map_queues(kiq_ring,
 728                                                  &adev->gfx.gfx_ring[j]);
 729                 }
 730         }
 731
 732         r = amdgpu_ring_test_helper(kiq_ring);
 733         spin_unlock(&kiq->ring_lock);
 734         if (r)
 735                 DRM_ERROR("KGQ enable failed\n");
 736
 737         return r;
 738 }
 739
 740 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 741  *
 742  * @adev: amdgpu_device pointer
 743  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 744  *
 745  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 746  * 2. other client can send request to disable gfx off feature, the request should be honored.
 747  * 3. other client can cancel their request of disable gfx off feature
 748  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 749  */
 750
 751 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 752 {
 753         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 754
 755         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 756                 return;
 757
 758         mutex_lock(&adev->gfx.gfx_off_mutex);
 759
 760         if (enable) {
 761                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 762                  * Note that the bug may be in a different caller than the one which triggers the
 763                  * WARN_ON_ONCE.
 764                  */
 765                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 766                         goto unlock;
 767
 768                 adev->gfx.gfx_off_req_count--;
 769
 770                 if (adev->gfx.gfx_off_req_count == 0 &&
 771                     !adev->gfx.gfx_off_state) {
 772                         /* If going to s2idle, no need to wait */
 773                         if (adev->in_s0ix) {
 774                                 if (!amdgpu_dpm_set_powergating_by_smu(adev,
 775                                                 AMD_IP_BLOCK_TYPE_GFX, true))
 776                                         adev->gfx.gfx_off_state = true;
 777                         } else {
 778                                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 779                                               delay);
 780                         }
 781                 }
 782         } else {
 783                 if (adev->gfx.gfx_off_req_count == 0) {
 784                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 785
 786                         if (adev->gfx.gfx_off_state &&
 787                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 788                                 adev->gfx.gfx_off_state = false;
 789
 790                                 if (adev->gfx.funcs->init_spm_golden) {
 791                                         dev_dbg(adev->dev,
 792                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 793                                         amdgpu_gfx_init_spm_golden(adev);
 794                                 }
 795                         }
 796                 }
 797
 798                 adev->gfx.gfx_off_req_count++;
 799         }
 800
 801 unlock:
 802         mutex_unlock(&adev->gfx.gfx_off_mutex);
 803 }
 804
 805 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 806 {
 807         int r = 0;
 808
 809         mutex_lock(&adev->gfx.gfx_off_mutex);
 810
 811         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 812
 813         mutex_unlock(&adev->gfx.gfx_off_mutex);
 814
 815         return r;
 816 }
 817
 818 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 819 {
 820         int r = 0;
 821
 822         mutex_lock(&adev->gfx.gfx_off_mutex);
 823
 824         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 825
 826         mutex_unlock(&adev->gfx.gfx_off_mutex);
 827
 828         return r;
 829 }
 830
 831 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 832 {
 833         int r = 0;
 834
 835         mutex_lock(&adev->gfx.gfx_off_mutex);
 836
 837         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 838
 839         mutex_unlock(&adev->gfx.gfx_off_mutex);
 840
 841         return r;
 842 }
 843
 844 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 845 {
 846
 847         int r = 0;
 848
 849         mutex_lock(&adev->gfx.gfx_off_mutex);
 850
 851         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 852
 853         mutex_unlock(&adev->gfx.gfx_off_mutex);
 854
 855         return r;
 856 }
 857
 858 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 859 {
 860         int r;
 861
 862         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 863                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 864                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 865
 866                 r = amdgpu_ras_block_late_init(adev, ras_block);
 867                 if (r)
 868                         return r;
 869
 870                 if (adev->gfx.cp_ecc_error_irq.funcs) {
 871                         r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 872                         if (r)
 873                                 goto late_fini;
 874                 }
 875         } else {
 876                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 877         }
 878
 879         return 0;
 880 late_fini:
 881         amdgpu_ras_block_late_fini(adev, ras_block);
 882         return r;
 883 }
 884
 885 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 886 {
 887         int err = 0;
 888         struct amdgpu_gfx_ras *ras = NULL;
 889
 890         /* adev->gfx.ras is NULL, which means gfx does not
 891          * support ras function, then do nothing here.
 892          */
 893         if (!adev->gfx.ras)
 894                 return 0;
 895
 896         ras = adev->gfx.ras;
 897
 898         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 899         if (err) {
 900                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 901                 return err;
 902         }
 903
 904         strcpy(ras->ras_block.ras_comm.name, "gfx");
 905         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 906         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 907         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 908
 909         /* If not define special ras_late_init function, use gfx default ras_late_init */
 910         if (!ras->ras_block.ras_late_init)
 911                 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
 912
 913         /* If not defined special ras_cb function, use default ras_cb */
 914         if (!ras->ras_block.ras_cb)
 915                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 916
 917         return 0;
 918 }
 919
 920 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 921                                                 struct amdgpu_iv_entry *entry)
 922 {
 923         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 924                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 925
 926         return 0;
 927 }
 928
 929 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 930                 void *err_data,
 931                 struct amdgpu_iv_entry *entry)
 932 {
 933         /* TODO ue will trigger an interrupt.
 934          *
 935          * When “Full RAS” is enabled, the per-IP interrupt sources should
 936          * be disabled and the driver should only look for the aggregated
 937          * interrupt via sync flood
 938          */
 939         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 940                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 941                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 942                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 943                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 944                 amdgpu_ras_reset_gpu(adev);
 945         }
 946         return AMDGPU_RAS_SUCCESS;
 947 }
 948
 949 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 950                                   struct amdgpu_irq_src *source,
 951                                   struct amdgpu_iv_entry *entry)
 952 {
 953         struct ras_common_if *ras_if = adev->gfx.ras_if;
 954         struct ras_dispatch_if ih_data = {
 955                 .entry = entry,
 956         };
 957
 958         if (!ras_if)
 959                 return 0;
 960
 961         ih_data.head = *ras_if;
 962
 963         DRM_ERROR("CP ECC ERROR IRQ\n");
 964         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 965         return 0;
 966 }
 967
 968 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
 969                 void *ras_error_status,
 970                 void (*func)(struct amdgpu_device *adev, void *ras_error_status,
 971                                 int xcc_id))
 972 {
 973         int i;
 974         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 975         uint32_t xcc_mask = GENMASK(num_xcc - 1, 0);
 976         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 977
 978         if (err_data) {
 979                 err_data->ue_count = 0;
 980                 err_data->ce_count = 0;
 981         }
 982
 983         for_each_inst(i, xcc_mask)
 984                 func(adev, ras_error_status, i);
 985 }
 986
 987 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id)
 988 {
 989         signed long r, cnt = 0;
 990         unsigned long flags;
 991         uint32_t seq, reg_val_offs = 0, value = 0;
 992         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 993         struct amdgpu_ring *ring = &kiq->ring;
 994
 995         if (amdgpu_device_skip_hw_access(adev))
 996                 return 0;
 997
 998         if (adev->mes.ring.sched.ready)
 999                 return amdgpu_mes_rreg(adev, reg);
1000
1001         BUG_ON(!ring->funcs->emit_rreg);
1002
1003         spin_lock_irqsave(&kiq->ring_lock, flags);
1004         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
1005                 pr_err("critical bug! too many kiq readers\n");
1006                 goto failed_unlock;
1007         }
1008         amdgpu_ring_alloc(ring, 32);
1009         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
1010         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
1011         if (r)
1012                 goto failed_undo;
1013
1014         amdgpu_ring_commit(ring);
1015         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1016
1017         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1018
1019         /* don't wait anymore for gpu reset case because this way may
1020          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
1021          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
1022          * never return if we keep waiting in virt_kiq_rreg, which cause
1023          * gpu_recover() hang there.
1024          *
1025          * also don't wait anymore for IRQ context
1026          * */
1027         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
1028                 goto failed_kiq_read;
1029
1030         might_sleep();
1031         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
1032                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
1033                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1034         }
1035
1036         if (cnt > MAX_KIQ_REG_TRY)
1037                 goto failed_kiq_read;
1038
1039         mb();
1040         value = adev->wb.wb[reg_val_offs];
1041         amdgpu_device_wb_free(adev, reg_val_offs);
1042         return value;
1043
1044 failed_undo:
1045         amdgpu_ring_undo(ring);
1046 failed_unlock:
1047         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1048 failed_kiq_read:
1049         if (reg_val_offs)
1050                 amdgpu_device_wb_free(adev, reg_val_offs);
1051         dev_err(adev->dev, "failed to read reg:%x\n", reg);
1052         return ~0;
1053 }
1054
1055 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id)
1056 {
1057         signed long r, cnt = 0;
1058         unsigned long flags;
1059         uint32_t seq;
1060         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
1061         struct amdgpu_ring *ring = &kiq->ring;
1062
1063         BUG_ON(!ring->funcs->emit_wreg);
1064
1065         if (amdgpu_device_skip_hw_access(adev))
1066                 return;
1067
1068         if (adev->mes.ring.sched.ready) {
1069                 amdgpu_mes_wreg(adev, reg, v);
1070                 return;
1071         }
1072
1073         spin_lock_irqsave(&kiq->ring_lock, flags);
1074         amdgpu_ring_alloc(ring, 32);
1075         amdgpu_ring_emit_wreg(ring, reg, v);
1076         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
1077         if (r)
1078                 goto failed_undo;
1079
1080         amdgpu_ring_commit(ring);
1081         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1082
1083         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1084
1085         /* don't wait anymore for gpu reset case because this way may
1086          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
1087          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
1088          * never return if we keep waiting in virt_kiq_rreg, which cause
1089          * gpu_recover() hang there.
1090          *
1091          * also don't wait anymore for IRQ context
1092          * */
1093         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
1094                 goto failed_kiq_write;
1095
1096         might_sleep();
1097         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
1098
1099                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
1100                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1101         }
1102
1103         if (cnt > MAX_KIQ_REG_TRY)
1104                 goto failed_kiq_write;
1105
1106         return;
1107
1108 failed_undo:
1109         amdgpu_ring_undo(ring);
1110         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1111 failed_kiq_write:
1112         dev_err(adev->dev, "failed to write reg:%x\n", reg);
1113 }
1114
1115 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
1116 {
1117         if (amdgpu_num_kcq == -1) {
1118                 return 8;
1119         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
1120                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
1121                 return 8;
1122         }
1123         return amdgpu_num_kcq;
1124 }
1125
1126 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
1127                                   uint32_t ucode_id)
1128 {
1129         const struct gfx_firmware_header_v1_0 *cp_hdr;
1130         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
1131         struct amdgpu_firmware_info *info = NULL;
1132         const struct firmware *ucode_fw;
1133         unsigned int fw_size;
1134
1135         switch (ucode_id) {
1136         case AMDGPU_UCODE_ID_CP_PFP:
1137                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1138                         adev->gfx.pfp_fw->data;
1139                 adev->gfx.pfp_fw_version =
1140                         le32_to_cpu(cp_hdr->header.ucode_version);
1141                 adev->gfx.pfp_feature_version =
1142                         le32_to_cpu(cp_hdr->ucode_feature_version);
1143                 ucode_fw = adev->gfx.pfp_fw;
1144                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1145                 break;
1146         case AMDGPU_UCODE_ID_CP_RS64_PFP:
1147                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1148                         adev->gfx.pfp_fw->data;
1149                 adev->gfx.pfp_fw_version =
1150                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1151                 adev->gfx.pfp_feature_version =
1152                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1153                 ucode_fw = adev->gfx.pfp_fw;
1154                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1155                 break;
1156         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
1157         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
1158                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1159                         adev->gfx.pfp_fw->data;
1160                 ucode_fw = adev->gfx.pfp_fw;
1161                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1162                 break;
1163         case AMDGPU_UCODE_ID_CP_ME:
1164                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1165                         adev->gfx.me_fw->data;
1166                 adev->gfx.me_fw_version =
1167                         le32_to_cpu(cp_hdr->header.ucode_version);
1168                 adev->gfx.me_feature_version =
1169                         le32_to_cpu(cp_hdr->ucode_feature_version);
1170                 ucode_fw = adev->gfx.me_fw;
1171                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1172                 break;
1173         case AMDGPU_UCODE_ID_CP_RS64_ME:
1174                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1175                         adev->gfx.me_fw->data;
1176                 adev->gfx.me_fw_version =
1177                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1178                 adev->gfx.me_feature_version =
1179                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1180                 ucode_fw = adev->gfx.me_fw;
1181                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1182                 break;
1183         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
1184         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
1185                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1186                         adev->gfx.me_fw->data;
1187                 ucode_fw = adev->gfx.me_fw;
1188                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1189                 break;
1190         case AMDGPU_UCODE_ID_CP_CE:
1191                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1192                         adev->gfx.ce_fw->data;
1193                 adev->gfx.ce_fw_version =
1194                         le32_to_cpu(cp_hdr->header.ucode_version);
1195                 adev->gfx.ce_feature_version =
1196                         le32_to_cpu(cp_hdr->ucode_feature_version);
1197                 ucode_fw = adev->gfx.ce_fw;
1198                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1199                 break;
1200         case AMDGPU_UCODE_ID_CP_MEC1:
1201                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1202                         adev->gfx.mec_fw->data;
1203                 adev->gfx.mec_fw_version =
1204                         le32_to_cpu(cp_hdr->header.ucode_version);
1205                 adev->gfx.mec_feature_version =
1206                         le32_to_cpu(cp_hdr->ucode_feature_version);
1207                 ucode_fw = adev->gfx.mec_fw;
1208                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1209                           le32_to_cpu(cp_hdr->jt_size) * 4;
1210                 break;
1211         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1212                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1213                         adev->gfx.mec_fw->data;
1214                 ucode_fw = adev->gfx.mec_fw;
1215                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1216                 break;
1217         case AMDGPU_UCODE_ID_CP_MEC2:
1218                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1219                         adev->gfx.mec2_fw->data;
1220                 adev->gfx.mec2_fw_version =
1221                         le32_to_cpu(cp_hdr->header.ucode_version);
1222                 adev->gfx.mec2_feature_version =
1223                         le32_to_cpu(cp_hdr->ucode_feature_version);
1224                 ucode_fw = adev->gfx.mec2_fw;
1225                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1226                           le32_to_cpu(cp_hdr->jt_size) * 4;
1227                 break;
1228         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1229                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1230                         adev->gfx.mec2_fw->data;
1231                 ucode_fw = adev->gfx.mec2_fw;
1232                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1233                 break;
1234         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1235                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1236                         adev->gfx.mec_fw->data;
1237                 adev->gfx.mec_fw_version =
1238                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1239                 adev->gfx.mec_feature_version =
1240                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1241                 ucode_fw = adev->gfx.mec_fw;
1242                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1243                 break;
1244         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1245         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1246         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1247         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1248                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1249                         adev->gfx.mec_fw->data;
1250                 ucode_fw = adev->gfx.mec_fw;
1251                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1252                 break;
1253         default:
1254                 dev_err(adev->dev, "Invalid ucode id %u\n", ucode_id);
1255                 return;
1256         }
1257
1258         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1259                 info = &adev->firmware.ucode[ucode_id];
1260                 info->ucode_id = ucode_id;
1261                 info->fw = ucode_fw;
1262                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1263         }
1264 }
1265
1266 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
1267 {
1268         return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
1269                         adev->gfx.num_xcc_per_xcp : 1));
1270 }
1271
1272 static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,
1273                                                 struct device_attribute *addr,
1274                                                 char *buf)
1275 {
1276         struct drm_device *ddev = dev_get_drvdata(dev);
1277         struct amdgpu_device *adev = drm_to_adev(ddev);
1278         int mode;
1279
1280         mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
1281                                                AMDGPU_XCP_FL_NONE);
1282
1283         return sysfs_emit(buf, "%s\n", amdgpu_gfx_compute_mode_desc(mode));
1284 }
1285
1286 static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
1287                                                 struct device_attribute *addr,
1288                                                 const char *buf, size_t count)
1289 {
1290         struct drm_device *ddev = dev_get_drvdata(dev);
1291         struct amdgpu_device *adev = drm_to_adev(ddev);
1292         enum amdgpu_gfx_partition mode;
1293         int ret = 0, num_xcc;
1294
1295         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1296         if (num_xcc % 2 != 0)
1297                 return -EINVAL;
1298
1299         if (!strncasecmp("SPX", buf, strlen("SPX"))) {
1300                 mode = AMDGPU_SPX_PARTITION_MODE;
1301         } else if (!strncasecmp("DPX", buf, strlen("DPX"))) {
1302                 /*
1303                  * DPX mode needs AIDs to be in multiple of 2.
1304                  * Each AID connects 2 XCCs.
1305                  */
1306                 if (num_xcc%4)
1307                         return -EINVAL;
1308                 mode = AMDGPU_DPX_PARTITION_MODE;
1309         } else if (!strncasecmp("TPX", buf, strlen("TPX"))) {
1310                 if (num_xcc != 6)
1311                         return -EINVAL;
1312                 mode = AMDGPU_TPX_PARTITION_MODE;
1313         } else if (!strncasecmp("QPX", buf, strlen("QPX"))) {
1314                 if (num_xcc != 8)
1315                         return -EINVAL;
1316                 mode = AMDGPU_QPX_PARTITION_MODE;
1317         } else if (!strncasecmp("CPX", buf, strlen("CPX"))) {
1318                 mode = AMDGPU_CPX_PARTITION_MODE;
1319         } else {
1320                 return -EINVAL;
1321         }
1322
1323         ret = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, mode);
1324
1325         if (ret)
1326                 return ret;
1327
1328         return count;
1329 }
1330
1331 static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,
1332                                                 struct device_attribute *addr,
1333                                                 char *buf)
1334 {
1335         struct drm_device *ddev = dev_get_drvdata(dev);
1336         struct amdgpu_device *adev = drm_to_adev(ddev);
1337         char *supported_partition;
1338
1339         /* TBD */
1340         switch (NUM_XCC(adev->gfx.xcc_mask)) {
1341         case 8:
1342                 supported_partition = "SPX, DPX, QPX, CPX";
1343                 break;
1344         case 6:
1345                 supported_partition = "SPX, TPX, CPX";
1346                 break;
1347         case 4:
1348                 supported_partition = "SPX, DPX, CPX";
1349                 break;
1350         /* this seems only existing in emulation phase */
1351         case 2:
1352                 supported_partition = "SPX, CPX";
1353                 break;
1354         default:
1355                 supported_partition = "Not supported";
1356                 break;
1357         }
1358
1359         return sysfs_emit(buf, "%s\n", supported_partition);
1360 }
1361
1362 static DEVICE_ATTR(current_compute_partition, 0644,
1363                    amdgpu_gfx_get_current_compute_partition,
1364                    amdgpu_gfx_set_compute_partition);
1365
1366 static DEVICE_ATTR(available_compute_partition, 0444,
1367                    amdgpu_gfx_get_available_compute_partition, NULL);
1368
1369 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
1370 {
1371         int r;
1372
1373         r = device_create_file(adev->dev, &dev_attr_current_compute_partition);
1374         if (r)
1375                 return r;
1376
1377         r = device_create_file(adev->dev, &dev_attr_available_compute_partition);
1378
1379         return r;
1380 }
1381
1382 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev)
1383 {
1384         device_remove_file(adev->dev, &dev_attr_current_compute_partition);
1385         device_remove_file(adev->dev, &dev_attr_available_compute_partition);
1386 }