drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30 #include "amdgpu_ras.h"
  31
  32 #include "soc15.h"
  33 #include "gfx_v9_0.h"
  34 #include "gfx_v9_4_3.h"
  35 #include "gmc_v9_0.h"
  36 #include "df_v1_7.h"
  37 #include "df_v3_6.h"
  38 #include "df_v4_3.h"
  39 #include "df_v4_6_2.h"
  40 #include "df_v4_15.h"
  41 #include "nbio_v6_1.h"
  42 #include "nbio_v7_0.h"
  43 #include "nbio_v7_4.h"
  44 #include "nbio_v7_9.h"
  45 #include "nbio_v7_11.h"
  46 #include "hdp_v4_0.h"
  47 #include "vega10_ih.h"
  48 #include "vega20_ih.h"
  49 #include "sdma_v4_0.h"
  50 #include "sdma_v4_4_2.h"
  51 #include "uvd_v7_0.h"
  52 #include "vce_v4_0.h"
  53 #include "vcn_v1_0.h"
  54 #include "vcn_v2_5.h"
  55 #include "jpeg_v2_5.h"
  56 #include "smuio_v9_0.h"
  57 #include "gmc_v10_0.h"
  58 #include "gmc_v11_0.h"
  59 #include "gmc_v12_0.h"
  60 #include "gfxhub_v2_0.h"
  61 #include "mmhub_v2_0.h"
  62 #include "nbio_v2_3.h"
  63 #include "nbio_v4_3.h"
  64 #include "nbio_v7_2.h"
  65 #include "nbio_v7_7.h"
  66 #include "nbif_v6_3_1.h"
  67 #include "hdp_v5_0.h"
  68 #include "hdp_v5_2.h"
  69 #include "hdp_v6_0.h"
  70 #include "hdp_v7_0.h"
  71 #include "nv.h"
  72 #include "soc21.h"
  73 #include "soc24.h"
  74 #include "navi10_ih.h"
  75 #include "ih_v6_0.h"
  76 #include "ih_v6_1.h"
  77 #include "ih_v7_0.h"
  78 #include "gfx_v10_0.h"
  79 #include "gfx_v11_0.h"
  80 #include "gfx_v12_0.h"
  81 #include "sdma_v5_0.h"
  82 #include "sdma_v5_2.h"
  83 #include "sdma_v6_0.h"
  84 #include "sdma_v7_0.h"
  85 #include "lsdma_v6_0.h"
  86 #include "lsdma_v7_0.h"
  87 #include "vcn_v2_0.h"
  88 #include "jpeg_v2_0.h"
  89 #include "vcn_v3_0.h"
  90 #include "jpeg_v3_0.h"
  91 #include "vcn_v4_0.h"
  92 #include "jpeg_v4_0.h"
  93 #include "vcn_v4_0_3.h"
  94 #include "jpeg_v4_0_3.h"
  95 #include "vcn_v4_0_5.h"
  96 #include "jpeg_v4_0_5.h"
  97 #include "amdgpu_vkms.h"
  98 #include "mes_v11_0.h"
  99 #include "mes_v12_0.h"
 100 #include "smuio_v11_0.h"
 101 #include "smuio_v11_0_6.h"
 102 #include "smuio_v13_0.h"
 103 #include "smuio_v13_0_3.h"
 104 #include "smuio_v13_0_6.h"
 105 #include "smuio_v14_0_2.h"
 106 #include "vcn_v5_0_0.h"
 107 #include "jpeg_v5_0_0.h"
 108
 109 #include "amdgpu_vpe.h"
 110 #if defined(CONFIG_DRM_AMD_ISP)
 111 #include "amdgpu_isp.h"
 112 #endif
 113
 114 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
 115 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
 116
 117 #define mmIP_DISCOVERY_VERSION  0x16A00
 118 #define mmRCC_CONFIG_MEMSIZE    0xde3
 119 #define mmMP0_SMN_C2PMSG_33     0x16061
 120 #define mmMM_INDEX              0x0
 121 #define mmMM_INDEX_HI           0x6
 122 #define mmMM_DATA               0x1
 123
 124 static const char *hw_id_names[HW_ID_MAX] = {
 125         [MP1_HWID]              = "MP1",
 126         [MP2_HWID]              = "MP2",
 127         [THM_HWID]              = "THM",
 128         [SMUIO_HWID]            = "SMUIO",
 129         [FUSE_HWID]             = "FUSE",
 130         [CLKA_HWID]             = "CLKA",
 131         [PWR_HWID]              = "PWR",
 132         [GC_HWID]               = "GC",
 133         [UVD_HWID]              = "UVD",
 134         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
 135         [ACP_HWID]              = "ACP",
 136         [DCI_HWID]              = "DCI",
 137         [DMU_HWID]              = "DMU",
 138         [DCO_HWID]              = "DCO",
 139         [DIO_HWID]              = "DIO",
 140         [XDMA_HWID]             = "XDMA",
 141         [DCEAZ_HWID]            = "DCEAZ",
 142         [DAZ_HWID]              = "DAZ",
 143         [SDPMUX_HWID]           = "SDPMUX",
 144         [NTB_HWID]              = "NTB",
 145         [IOHC_HWID]             = "IOHC",
 146         [L2IMU_HWID]            = "L2IMU",
 147         [VCE_HWID]              = "VCE",
 148         [MMHUB_HWID]            = "MMHUB",
 149         [ATHUB_HWID]            = "ATHUB",
 150         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 151         [DFX_HWID]              = "DFX",
 152         [DBGU0_HWID]            = "DBGU0",
 153         [DBGU1_HWID]            = "DBGU1",
 154         [OSSSYS_HWID]           = "OSSSYS",
 155         [HDP_HWID]              = "HDP",
 156         [SDMA0_HWID]            = "SDMA0",
 157         [SDMA1_HWID]            = "SDMA1",
 158         [SDMA2_HWID]            = "SDMA2",
 159         [SDMA3_HWID]            = "SDMA3",
 160         [LSDMA_HWID]            = "LSDMA",
 161         [ISP_HWID]              = "ISP",
 162         [DBGU_IO_HWID]          = "DBGU_IO",
 163         [DF_HWID]               = "DF",
 164         [CLKB_HWID]             = "CLKB",
 165         [FCH_HWID]              = "FCH",
 166         [DFX_DAP_HWID]          = "DFX_DAP",
 167         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 168         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 169         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 170         [L1IMU3_HWID]           = "L1IMU3",
 171         [L1IMU4_HWID]           = "L1IMU4",
 172         [L1IMU5_HWID]           = "L1IMU5",
 173         [L1IMU6_HWID]           = "L1IMU6",
 174         [L1IMU7_HWID]           = "L1IMU7",
 175         [L1IMU8_HWID]           = "L1IMU8",
 176         [L1IMU9_HWID]           = "L1IMU9",
 177         [L1IMU10_HWID]          = "L1IMU10",
 178         [L1IMU11_HWID]          = "L1IMU11",
 179         [L1IMU12_HWID]          = "L1IMU12",
 180         [L1IMU13_HWID]          = "L1IMU13",
 181         [L1IMU14_HWID]          = "L1IMU14",
 182         [L1IMU15_HWID]          = "L1IMU15",
 183         [WAFLC_HWID]            = "WAFLC",
 184         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 185         [PCIE_HWID]             = "PCIE",
 186         [PCS_HWID]              = "PCS",
 187         [DDCL_HWID]             = "DDCL",
 188         [SST_HWID]              = "SST",
 189         [IOAGR_HWID]            = "IOAGR",
 190         [NBIF_HWID]             = "NBIF",
 191         [IOAPIC_HWID]           = "IOAPIC",
 192         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 193         [NTBCCP_HWID]           = "NTBCCP",
 194         [UMC_HWID]              = "UMC",
 195         [SATA_HWID]             = "SATA",
 196         [USB_HWID]              = "USB",
 197         [CCXSEC_HWID]           = "CCXSEC",
 198         [XGMI_HWID]             = "XGMI",
 199         [XGBE_HWID]             = "XGBE",
 200         [MP0_HWID]              = "MP0",
 201         [VPE_HWID]              = "VPE",
 202 };
 203
 204 static int hw_id_map[MAX_HWIP] = {
 205         [GC_HWIP]       = GC_HWID,
 206         [HDP_HWIP]      = HDP_HWID,
 207         [SDMA0_HWIP]    = SDMA0_HWID,
 208         [SDMA1_HWIP]    = SDMA1_HWID,
 209         [SDMA2_HWIP]    = SDMA2_HWID,
 210         [SDMA3_HWIP]    = SDMA3_HWID,
 211         [LSDMA_HWIP]    = LSDMA_HWID,
 212         [MMHUB_HWIP]    = MMHUB_HWID,
 213         [ATHUB_HWIP]    = ATHUB_HWID,
 214         [NBIO_HWIP]     = NBIF_HWID,
 215         [MP0_HWIP]      = MP0_HWID,
 216         [MP1_HWIP]      = MP1_HWID,
 217         [UVD_HWIP]      = UVD_HWID,
 218         [VCE_HWIP]      = VCE_HWID,
 219         [DF_HWIP]       = DF_HWID,
 220         [DCE_HWIP]      = DMU_HWID,
 221         [OSSSYS_HWIP]   = OSSSYS_HWID,
 222         [SMUIO_HWIP]    = SMUIO_HWID,
 223         [PWR_HWIP]      = PWR_HWID,
 224         [NBIF_HWIP]     = NBIF_HWID,
 225         [THM_HWIP]      = THM_HWID,
 226         [CLK_HWIP]      = CLKA_HWID,
 227         [UMC_HWIP]      = UMC_HWID,
 228         [XGMI_HWIP]     = XGMI_HWID,
 229         [DCI_HWIP]      = DCI_HWID,
 230         [PCIE_HWIP]     = PCIE_HWID,
 231         [VPE_HWIP]      = VPE_HWID,
 232         [ISP_HWIP]      = ISP_HWID,
 233 };
 234
 235 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
 236 {
 237         u64 tmr_offset, tmr_size, pos;
 238         void *discv_regn;
 239         int ret;
 240
 241         ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
 242         if (ret)
 243                 return ret;
 244
 245         pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
 246
 247         /* This region is read-only and reserved from system use */
 248         discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC);
 249         if (discv_regn) {
 250                 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size);
 251                 memunmap(discv_regn);
 252                 return 0;
 253         }
 254
 255         return -ENOENT;
 256 }
 257
 258 #define IP_DISCOVERY_V2         2
 259 #define IP_DISCOVERY_V4         4
 260
 261 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
 262                                                  uint8_t *binary)
 263 {
 264         uint64_t vram_size;
 265         u32 msg;
 266         int i, ret = 0;
 267
 268         if (!amdgpu_sriov_vf(adev)) {
 269                 /* It can take up to a second for IFWI init to complete on some dGPUs,
 270                  * but generally it should be in the 60-100ms range.  Normally this starts
 271                  * as soon as the device gets power so by the time the OS loads this has long
 272                  * completed.  However, when a card is hotplugged via e.g., USB4, we need to
 273                  * wait for this to complete.  Once the C2PMSG is updated, we can
 274                  * continue.
 275                  */
 276
 277                 for (i = 0; i < 1000; i++) {
 278                         msg = RREG32(mmMP0_SMN_C2PMSG_33);
 279                         if (msg & 0x80000000)
 280                                 break;
 281                         usleep_range(1000, 1100);
 282                 }
 283         }
 284
 285         vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 286
 287         if (vram_size) {
 288                 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 289                 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 290                                           adev->mman.discovery_tmr_size, false);
 291         } else {
 292                 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
 293         }
 294
 295         return ret;
 296 }
 297
 298 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 299 {
 300         const struct firmware *fw;
 301         const char *fw_name;
 302         int r;
 303
 304         switch (amdgpu_discovery) {
 305         case 2:
 306                 fw_name = FIRMWARE_IP_DISCOVERY;
 307                 break;
 308         default:
 309                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 310                 return -EINVAL;
 311         }
 312
 313         r = request_firmware(&fw, fw_name, adev->dev);
 314         if (r) {
 315                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 316                         fw_name);
 317                 return r;
 318         }
 319
 320         memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
 321         release_firmware(fw);
 322
 323         return 0;
 324 }
 325
 326 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 327 {
 328         uint16_t checksum = 0;
 329         int i;
 330
 331         for (i = 0; i < size; i++)
 332                 checksum += data[i];
 333
 334         return checksum;
 335 }
 336
 337 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 338                                                     uint16_t expected)
 339 {
 340         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 341 }
 342
 343 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 344 {
 345         struct binary_header *bhdr;
 346         bhdr = (struct binary_header *)binary;
 347
 348         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 349 }
 350
 351 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
 352 {
 353         /*
 354          * So far, apply this quirk only on those Navy Flounder boards which
 355          * have a bad harvest table of VCN config.
 356          */
 357         if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&
 358             (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) {
 359                 switch (adev->pdev->revision) {
 360                 case 0xC1:
 361                 case 0xC2:
 362                 case 0xC3:
 363                 case 0xC5:
 364                 case 0xC7:
 365                 case 0xCF:
 366                 case 0xDF:
 367                         adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 368                         adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
 369                         break;
 370                 default:
 371                         break;
 372                 }
 373         }
 374 }
 375
 376 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,
 377                                            struct binary_header *bhdr)
 378 {
 379         struct table_info *info;
 380         uint16_t checksum;
 381         uint16_t offset;
 382
 383         info = &bhdr->table_list[NPS_INFO];
 384         offset = le16_to_cpu(info->offset);
 385         checksum = le16_to_cpu(info->checksum);
 386
 387         struct nps_info_header *nhdr =
 388                 (struct nps_info_header *)(adev->mman.discovery_bin + offset);
 389
 390         if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) {
 391                 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n");
 392                 return -EINVAL;
 393         }
 394
 395         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 396                                               le32_to_cpu(nhdr->size_bytes),
 397                                               checksum)) {
 398                 dev_dbg(adev->dev, "invalid nps info data table checksum\n");
 399                 return -EINVAL;
 400         }
 401
 402         return 0;
 403 }
 404
 405 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 406 {
 407         struct table_info *info;
 408         struct binary_header *bhdr;
 409         uint16_t offset;
 410         uint16_t size;
 411         uint16_t checksum;
 412         int r;
 413
 414         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 415         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 416         if (!adev->mman.discovery_bin)
 417                 return -ENOMEM;
 418
 419         /* Read from file if it is the preferred option */
 420         if (amdgpu_discovery == 2) {
 421                 dev_info(adev->dev, "use ip discovery information from file");
 422                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 423
 424                 if (r) {
 425                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 426                         r = -EINVAL;
 427                         goto out;
 428                 }
 429
 430         } else {
 431                 r = amdgpu_discovery_read_binary_from_mem(
 432                         adev, adev->mman.discovery_bin);
 433                 if (r)
 434                         goto out;
 435         }
 436
 437         /* check the ip discovery binary signature */
 438         if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 439                 dev_err(adev->dev,
 440                         "get invalid ip discovery binary signature\n");
 441                 r = -EINVAL;
 442                 goto out;
 443         }
 444
 445         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 446
 447         offset = offsetof(struct binary_header, binary_checksum) +
 448                 sizeof(bhdr->binary_checksum);
 449         size = le16_to_cpu(bhdr->binary_size) - offset;
 450         checksum = le16_to_cpu(bhdr->binary_checksum);
 451
 452         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 453                                               size, checksum)) {
 454                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 455                 r = -EINVAL;
 456                 goto out;
 457         }
 458
 459         info = &bhdr->table_list[IP_DISCOVERY];
 460         offset = le16_to_cpu(info->offset);
 461         checksum = le16_to_cpu(info->checksum);
 462
 463         if (offset) {
 464                 struct ip_discovery_header *ihdr =
 465                         (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 466                 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 467                         dev_err(adev->dev, "invalid ip discovery data table signature\n");
 468                         r = -EINVAL;
 469                         goto out;
 470                 }
 471
 472                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 473                                                       le16_to_cpu(ihdr->size), checksum)) {
 474                         dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 475                         r = -EINVAL;
 476                         goto out;
 477                 }
 478         }
 479
 480         info = &bhdr->table_list[GC];
 481         offset = le16_to_cpu(info->offset);
 482         checksum = le16_to_cpu(info->checksum);
 483
 484         if (offset) {
 485                 struct gpu_info_header *ghdr =
 486                         (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 487
 488                 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) {
 489                         dev_err(adev->dev, "invalid ip discovery gc table id\n");
 490                         r = -EINVAL;
 491                         goto out;
 492                 }
 493
 494                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 495                                                       le32_to_cpu(ghdr->size), checksum)) {
 496                         dev_err(adev->dev, "invalid gc data table checksum\n");
 497                         r = -EINVAL;
 498                         goto out;
 499                 }
 500         }
 501
 502         info = &bhdr->table_list[HARVEST_INFO];
 503         offset = le16_to_cpu(info->offset);
 504         checksum = le16_to_cpu(info->checksum);
 505
 506         if (offset) {
 507                 struct harvest_info_header *hhdr =
 508                         (struct harvest_info_header *)(adev->mman.discovery_bin + offset);
 509
 510                 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) {
 511                         dev_err(adev->dev, "invalid ip discovery harvest table signature\n");
 512                         r = -EINVAL;
 513                         goto out;
 514                 }
 515
 516                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 517                                                       sizeof(struct harvest_table), checksum)) {
 518                         dev_err(adev->dev, "invalid harvest data table checksum\n");
 519                         r = -EINVAL;
 520                         goto out;
 521                 }
 522         }
 523
 524         info = &bhdr->table_list[VCN_INFO];
 525         offset = le16_to_cpu(info->offset);
 526         checksum = le16_to_cpu(info->checksum);
 527
 528         if (offset) {
 529                 struct vcn_info_header *vhdr =
 530                         (struct vcn_info_header *)(adev->mman.discovery_bin + offset);
 531
 532                 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) {
 533                         dev_err(adev->dev, "invalid ip discovery vcn table id\n");
 534                         r = -EINVAL;
 535                         goto out;
 536                 }
 537
 538                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 539                                                       le32_to_cpu(vhdr->size_bytes), checksum)) {
 540                         dev_err(adev->dev, "invalid vcn data table checksum\n");
 541                         r = -EINVAL;
 542                         goto out;
 543                 }
 544         }
 545
 546         info = &bhdr->table_list[MALL_INFO];
 547         offset = le16_to_cpu(info->offset);
 548         checksum = le16_to_cpu(info->checksum);
 549
 550         if (0 && offset) {
 551                 struct mall_info_header *mhdr =
 552                         (struct mall_info_header *)(adev->mman.discovery_bin + offset);
 553
 554                 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) {
 555                         dev_err(adev->dev, "invalid ip discovery mall table id\n");
 556                         r = -EINVAL;
 557                         goto out;
 558                 }
 559
 560                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 561                                                       le32_to_cpu(mhdr->size_bytes), checksum)) {
 562                         dev_err(adev->dev, "invalid mall data table checksum\n");
 563                         r = -EINVAL;
 564                         goto out;
 565                 }
 566         }
 567
 568         return 0;
 569
 570 out:
 571         kfree(adev->mman.discovery_bin);
 572         adev->mman.discovery_bin = NULL;
 573         if ((amdgpu_discovery != 2) &&
 574             (RREG32(mmIP_DISCOVERY_VERSION) == 4))
 575                 amdgpu_ras_query_boot_status(adev, 4);
 576         return r;
 577 }
 578
 579 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
 580
 581 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 582 {
 583         amdgpu_discovery_sysfs_fini(adev);
 584         kfree(adev->mman.discovery_bin);
 585         adev->mman.discovery_bin = NULL;
 586 }
 587
 588 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip)
 589 {
 590         if (ip->instance_number >= HWIP_MAX_INSTANCE) {
 591                 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n",
 592                           ip->instance_number);
 593                 return -EINVAL;
 594         }
 595         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 596                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 597                           le16_to_cpu(ip->hw_id));
 598                 return -EINVAL;
 599         }
 600
 601         return 0;
 602 }
 603
 604 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
 605                                                 uint32_t *vcn_harvest_count)
 606 {
 607         struct binary_header *bhdr;
 608         struct ip_discovery_header *ihdr;
 609         struct die_header *dhdr;
 610         struct ip_v4 *ip;
 611         uint16_t die_offset, ip_offset, num_dies, num_ips;
 612         int i, j;
 613
 614         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 615         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 616                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 617         num_dies = le16_to_cpu(ihdr->num_dies);
 618
 619         /* scan harvest bit of all IP data structures */
 620         for (i = 0; i < num_dies; i++) {
 621                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 622                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 623                 num_ips = le16_to_cpu(dhdr->num_ips);
 624                 ip_offset = die_offset + sizeof(*dhdr);
 625
 626                 for (j = 0; j < num_ips; j++) {
 627                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
 628
 629                         if (amdgpu_discovery_validate_ip(ip))
 630                                 goto next_ip;
 631
 632                         if (le16_to_cpu(ip->variant) == 1) {
 633                                 switch (le16_to_cpu(ip->hw_id)) {
 634                                 case VCN_HWID:
 635                                         (*vcn_harvest_count)++;
 636                                         if (ip->instance_number == 0) {
 637                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 638                                                 adev->vcn.inst_mask &=
 639                                                         ~AMDGPU_VCN_HARVEST_VCN0;
 640                                                 adev->jpeg.inst_mask &=
 641                                                         ~AMDGPU_VCN_HARVEST_VCN0;
 642                                         } else {
 643                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 644                                                 adev->vcn.inst_mask &=
 645                                                         ~AMDGPU_VCN_HARVEST_VCN1;
 646                                                 adev->jpeg.inst_mask &=
 647                                                         ~AMDGPU_VCN_HARVEST_VCN1;
 648                                         }
 649                                         break;
 650                                 case DMU_HWID:
 651                                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 652                                         break;
 653                                 default:
 654                                         break;
 655                                 }
 656                         }
 657 next_ip:
 658                         if (ihdr->base_addr_64_bit)
 659                                 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
 660                         else
 661                                 ip_offset += struct_size(ip, base_address, ip->num_base_address);
 662                 }
 663         }
 664 }
 665
 666 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
 667                                                      uint32_t *vcn_harvest_count,
 668                                                      uint32_t *umc_harvest_count)
 669 {
 670         struct binary_header *bhdr;
 671         struct harvest_table *harvest_info;
 672         u16 offset;
 673         int i;
 674         uint32_t umc_harvest_config = 0;
 675
 676         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 677         offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
 678
 679         if (!offset) {
 680                 dev_err(adev->dev, "invalid harvest table offset\n");
 681                 return;
 682         }
 683
 684         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset);
 685
 686         for (i = 0; i < 32; i++) {
 687                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
 688                         break;
 689
 690                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
 691                 case VCN_HWID:
 692                         (*vcn_harvest_count)++;
 693                         adev->vcn.harvest_config |=
 694                                 (1 << harvest_info->list[i].number_instance);
 695                         adev->jpeg.harvest_config |=
 696                                 (1 << harvest_info->list[i].number_instance);
 697
 698                         adev->vcn.inst_mask &=
 699                                 ~(1U << harvest_info->list[i].number_instance);
 700                         adev->jpeg.inst_mask &=
 701                                 ~(1U << harvest_info->list[i].number_instance);
 702                         break;
 703                 case DMU_HWID:
 704                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 705                         break;
 706                 case UMC_HWID:
 707                         umc_harvest_config |=
 708                                 1 << (le16_to_cpu(harvest_info->list[i].number_instance));
 709                         (*umc_harvest_count)++;
 710                         break;
 711                 case GC_HWID:
 712                         adev->gfx.xcc_mask &=
 713                                 ~(1U << harvest_info->list[i].number_instance);
 714                         break;
 715                 case SDMA0_HWID:
 716                         adev->sdma.sdma_mask &=
 717                                 ~(1U << harvest_info->list[i].number_instance);
 718                         break;
 719 #if defined(CONFIG_DRM_AMD_ISP)
 720                 case ISP_HWID:
 721                         adev->isp.harvest_config |=
 722                                 ~(1U << harvest_info->list[i].number_instance);
 723                         break;
 724 #endif
 725                 default:
 726                         break;
 727                 }
 728         }
 729
 730         adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &
 731                                 ~umc_harvest_config;
 732 }
 733
 734 /* ================================================== */
 735
 736 struct ip_hw_instance {
 737         struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
 738
 739         int hw_id;
 740         u8  num_instance;
 741         u8  major, minor, revision;
 742         u8  harvest;
 743
 744         int num_base_addresses;
 745         u32 base_addr[] __counted_by(num_base_addresses);
 746 };
 747
 748 struct ip_hw_id {
 749         struct kset hw_id_kset;  /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
 750         int hw_id;
 751 };
 752
 753 struct ip_die_entry {
 754         struct kset ip_kset;     /* ip_discovery/die/#die/, contains ip_hw_id  */
 755         u16 num_ips;
 756 };
 757
 758 /* -------------------------------------------------- */
 759
 760 struct ip_hw_instance_attr {
 761         struct attribute attr;
 762         ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
 763 };
 764
 765 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 766 {
 767         return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
 768 }
 769
 770 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 771 {
 772         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
 773 }
 774
 775 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 776 {
 777         return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
 778 }
 779
 780 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 781 {
 782         return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
 783 }
 784
 785 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 786 {
 787         return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
 788 }
 789
 790 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 791 {
 792         return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
 793 }
 794
 795 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 796 {
 797         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
 798 }
 799
 800 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 801 {
 802         ssize_t res, at;
 803         int ii;
 804
 805         for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
 806                 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
 807                  */
 808                 if (at + 12 > PAGE_SIZE)
 809                         break;
 810                 res = sysfs_emit_at(buf, at, "0x%08X\n",
 811                                     ip_hw_instance->base_addr[ii]);
 812                 if (res <= 0)
 813                         break;
 814                 at += res;
 815         }
 816
 817         return res < 0 ? res : at;
 818 }
 819
 820 static struct ip_hw_instance_attr ip_hw_attr[] = {
 821         __ATTR_RO(hw_id),
 822         __ATTR_RO(num_instance),
 823         __ATTR_RO(major),
 824         __ATTR_RO(minor),
 825         __ATTR_RO(revision),
 826         __ATTR_RO(harvest),
 827         __ATTR_RO(num_base_addresses),
 828         __ATTR_RO(base_addr),
 829 };
 830
 831 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
 832 ATTRIBUTE_GROUPS(ip_hw_instance);
 833
 834 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
 835 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
 836
 837 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
 838                                         struct attribute *attr,
 839                                         char *buf)
 840 {
 841         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 842         struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
 843
 844         if (!ip_hw_attr->show)
 845                 return -EIO;
 846
 847         return ip_hw_attr->show(ip_hw_instance, buf);
 848 }
 849
 850 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
 851         .show = ip_hw_instance_attr_show,
 852 };
 853
 854 static void ip_hw_instance_release(struct kobject *kobj)
 855 {
 856         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 857
 858         kfree(ip_hw_instance);
 859 }
 860
 861 static const struct kobj_type ip_hw_instance_ktype = {
 862         .release = ip_hw_instance_release,
 863         .sysfs_ops = &ip_hw_instance_sysfs_ops,
 864         .default_groups = ip_hw_instance_groups,
 865 };
 866
 867 /* -------------------------------------------------- */
 868
 869 #define to_ip_hw_id(x)  container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
 870
 871 static void ip_hw_id_release(struct kobject *kobj)
 872 {
 873         struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
 874
 875         if (!list_empty(&ip_hw_id->hw_id_kset.list))
 876                 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
 877         kfree(ip_hw_id);
 878 }
 879
 880 static const struct kobj_type ip_hw_id_ktype = {
 881         .release = ip_hw_id_release,
 882         .sysfs_ops = &kobj_sysfs_ops,
 883 };
 884
 885 /* -------------------------------------------------- */
 886
 887 static void die_kobj_release(struct kobject *kobj);
 888 static void ip_disc_release(struct kobject *kobj);
 889
 890 struct ip_die_entry_attribute {
 891         struct attribute attr;
 892         ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
 893 };
 894
 895 #define to_ip_die_entry_attr(x)  container_of(x, struct ip_die_entry_attribute, attr)
 896
 897 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
 898 {
 899         return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
 900 }
 901
 902 /* If there are more ip_die_entry attrs, other than the number of IPs,
 903  * we can make this intro an array of attrs, and then initialize
 904  * ip_die_entry_attrs in a loop.
 905  */
 906 static struct ip_die_entry_attribute num_ips_attr =
 907         __ATTR_RO(num_ips);
 908
 909 static struct attribute *ip_die_entry_attrs[] = {
 910         &num_ips_attr.attr,
 911         NULL,
 912 };
 913 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
 914
 915 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
 916
 917 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
 918                                       struct attribute *attr,
 919                                       char *buf)
 920 {
 921         struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
 922         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 923
 924         if (!ip_die_entry_attr->show)
 925                 return -EIO;
 926
 927         return ip_die_entry_attr->show(ip_die_entry, buf);
 928 }
 929
 930 static void ip_die_entry_release(struct kobject *kobj)
 931 {
 932         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 933
 934         if (!list_empty(&ip_die_entry->ip_kset.list))
 935                 DRM_ERROR("ip_die_entry->ip_kset is not empty");
 936         kfree(ip_die_entry);
 937 }
 938
 939 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
 940         .show = ip_die_entry_attr_show,
 941 };
 942
 943 static const struct kobj_type ip_die_entry_ktype = {
 944         .release = ip_die_entry_release,
 945         .sysfs_ops = &ip_die_entry_sysfs_ops,
 946         .default_groups = ip_die_entry_groups,
 947 };
 948
 949 static const struct kobj_type die_kobj_ktype = {
 950         .release = die_kobj_release,
 951         .sysfs_ops = &kobj_sysfs_ops,
 952 };
 953
 954 static const struct kobj_type ip_discovery_ktype = {
 955         .release = ip_disc_release,
 956         .sysfs_ops = &kobj_sysfs_ops,
 957 };
 958
 959 struct ip_discovery_top {
 960         struct kobject kobj;    /* ip_discovery/ */
 961         struct kset die_kset;   /* ip_discovery/die/, contains ip_die_entry */
 962         struct amdgpu_device *adev;
 963 };
 964
 965 static void die_kobj_release(struct kobject *kobj)
 966 {
 967         struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
 968                                                        struct ip_discovery_top,
 969                                                        die_kset);
 970         if (!list_empty(&ip_top->die_kset.list))
 971                 DRM_ERROR("ip_top->die_kset is not empty");
 972 }
 973
 974 static void ip_disc_release(struct kobject *kobj)
 975 {
 976         struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
 977                                                        kobj);
 978         struct amdgpu_device *adev = ip_top->adev;
 979
 980         adev->ip_top = NULL;
 981         kfree(ip_top);
 982 }
 983
 984 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
 985                                                  uint16_t hw_id, uint8_t inst)
 986 {
 987         uint8_t harvest = 0;
 988
 989         /* Until a uniform way is figured, get mask based on hwid */
 990         switch (hw_id) {
 991         case VCN_HWID:
 992                 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
 993                 break;
 994         case DMU_HWID:
 995                 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
 996                         harvest = 0x1;
 997                 break;
 998         case UMC_HWID:
 999                 /* TODO: It needs another parsing; for now, ignore.*/
1000                 break;
1001         case GC_HWID:
1002                 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
1003                 break;
1004         case SDMA0_HWID:
1005                 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
1006                 break;
1007         default:
1008                 break;
1009         }
1010
1011         return harvest;
1012 }
1013
1014 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
1015                                       struct ip_die_entry *ip_die_entry,
1016                                       const size_t _ip_offset, const int num_ips,
1017                                       bool reg_base_64)
1018 {
1019         int ii, jj, kk, res;
1020
1021         DRM_DEBUG("num_ips:%d", num_ips);
1022
1023         /* Find all IPs of a given HW ID, and add their instance to
1024          * #die/#hw_id/#instance/<attributes>
1025          */
1026         for (ii = 0; ii < HW_ID_MAX; ii++) {
1027                 struct ip_hw_id *ip_hw_id = NULL;
1028                 size_t ip_offset = _ip_offset;
1029
1030                 for (jj = 0; jj < num_ips; jj++) {
1031                         struct ip_v4 *ip;
1032                         struct ip_hw_instance *ip_hw_instance;
1033
1034                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
1035                         if (amdgpu_discovery_validate_ip(ip) ||
1036                             le16_to_cpu(ip->hw_id) != ii)
1037                                 goto next_ip;
1038
1039                         DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
1040
1041                         /* We have a hw_id match; register the hw
1042                          * block if not yet registered.
1043                          */
1044                         if (!ip_hw_id) {
1045                                 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
1046                                 if (!ip_hw_id)
1047                                         return -ENOMEM;
1048                                 ip_hw_id->hw_id = ii;
1049
1050                                 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
1051                                 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
1052                                 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
1053                                 res = kset_register(&ip_hw_id->hw_id_kset);
1054                                 if (res) {
1055                                         DRM_ERROR("Couldn't register ip_hw_id kset");
1056                                         kfree(ip_hw_id);
1057                                         return res;
1058                                 }
1059                                 if (hw_id_names[ii]) {
1060                                         res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
1061                                                                 &ip_hw_id->hw_id_kset.kobj,
1062                                                                 hw_id_names[ii]);
1063                                         if (res) {
1064                                                 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
1065                                                           hw_id_names[ii],
1066                                                           kobject_name(&ip_die_entry->ip_kset.kobj));
1067                                         }
1068                                 }
1069                         }
1070
1071                         /* Now register its instance.
1072                          */
1073                         ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
1074                                                              base_addr,
1075                                                              ip->num_base_address),
1076                                                  GFP_KERNEL);
1077                         if (!ip_hw_instance) {
1078                                 DRM_ERROR("no memory for ip_hw_instance");
1079                                 return -ENOMEM;
1080                         }
1081                         ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
1082                         ip_hw_instance->num_instance = ip->instance_number;
1083                         ip_hw_instance->major = ip->major;
1084                         ip_hw_instance->minor = ip->minor;
1085                         ip_hw_instance->revision = ip->revision;
1086                         ip_hw_instance->harvest =
1087                                 amdgpu_discovery_get_harvest_info(
1088                                         adev, ip_hw_instance->hw_id,
1089                                         ip_hw_instance->num_instance);
1090                         ip_hw_instance->num_base_addresses = ip->num_base_address;
1091
1092                         for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) {
1093                                 if (reg_base_64)
1094                                         ip_hw_instance->base_addr[kk] =
1095                                                 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF;
1096                                 else
1097                                         ip_hw_instance->base_addr[kk] = ip->base_address[kk];
1098                         }
1099
1100                         kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1101                         ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1102                         res = kobject_add(&ip_hw_instance->kobj, NULL,
1103                                           "%d", ip_hw_instance->num_instance);
1104 next_ip:
1105                         if (reg_base_64)
1106                                 ip_offset += struct_size(ip, base_address_64,
1107                                                          ip->num_base_address);
1108                         else
1109                                 ip_offset += struct_size(ip, base_address,
1110                                                          ip->num_base_address);
1111                 }
1112         }
1113
1114         return 0;
1115 }
1116
1117 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
1118 {
1119         struct binary_header *bhdr;
1120         struct ip_discovery_header *ihdr;
1121         struct die_header *dhdr;
1122         struct kset *die_kset = &adev->ip_top->die_kset;
1123         u16 num_dies, die_offset, num_ips;
1124         size_t ip_offset;
1125         int ii, res;
1126
1127         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1128         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1129                                               le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1130         num_dies = le16_to_cpu(ihdr->num_dies);
1131
1132         DRM_DEBUG("number of dies: %d\n", num_dies);
1133
1134         for (ii = 0; ii < num_dies; ii++) {
1135                 struct ip_die_entry *ip_die_entry;
1136
1137                 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1138                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1139                 num_ips = le16_to_cpu(dhdr->num_ips);
1140                 ip_offset = die_offset + sizeof(*dhdr);
1141
1142                 /* Add the die to the kset.
1143                  *
1144                  * dhdr->die_id == ii, which was checked in
1145                  * amdgpu_discovery_reg_base_init().
1146                  */
1147
1148                 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
1149                 if (!ip_die_entry)
1150                         return -ENOMEM;
1151
1152                 ip_die_entry->num_ips = num_ips;
1153
1154                 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1155                 ip_die_entry->ip_kset.kobj.kset = die_kset;
1156                 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1157                 res = kset_register(&ip_die_entry->ip_kset);
1158                 if (res) {
1159                         DRM_ERROR("Couldn't register ip_die_entry kset");
1160                         kfree(ip_die_entry);
1161                         return res;
1162                 }
1163
1164                 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit);
1165         }
1166
1167         return 0;
1168 }
1169
1170 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1171 {
1172         struct kset *die_kset;
1173         int res, ii;
1174
1175         if (!adev->mman.discovery_bin)
1176                 return -EINVAL;
1177
1178         adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
1179         if (!adev->ip_top)
1180                 return -ENOMEM;
1181
1182         adev->ip_top->adev = adev;
1183
1184         res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
1185                                    &adev->dev->kobj, "ip_discovery");
1186         if (res) {
1187                 DRM_ERROR("Couldn't init and add ip_discovery/");
1188                 goto Err;
1189         }
1190
1191         die_kset = &adev->ip_top->die_kset;
1192         kobject_set_name(&die_kset->kobj, "%s", "die");
1193         die_kset->kobj.parent = &adev->ip_top->kobj;
1194         die_kset->kobj.ktype = &die_kobj_ktype;
1195         res = kset_register(&adev->ip_top->die_kset);
1196         if (res) {
1197                 DRM_ERROR("Couldn't register die_kset");
1198                 goto Err;
1199         }
1200
1201         for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1202                 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1203         ip_hw_instance_attrs[ii] = NULL;
1204
1205         res = amdgpu_discovery_sysfs_recurse(adev);
1206
1207         return res;
1208 Err:
1209         kobject_put(&adev->ip_top->kobj);
1210         return res;
1211 }
1212
1213 /* -------------------------------------------------- */
1214
1215 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1216
1217 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1218 {
1219         struct list_head *el, *tmp;
1220         struct kset *hw_id_kset;
1221
1222         hw_id_kset = &ip_hw_id->hw_id_kset;
1223         spin_lock(&hw_id_kset->list_lock);
1224         list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1225                 list_del_init(el);
1226                 spin_unlock(&hw_id_kset->list_lock);
1227                 /* kobject is embedded in ip_hw_instance */
1228                 kobject_put(list_to_kobj(el));
1229                 spin_lock(&hw_id_kset->list_lock);
1230         }
1231         spin_unlock(&hw_id_kset->list_lock);
1232         kobject_put(&ip_hw_id->hw_id_kset.kobj);
1233 }
1234
1235 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1236 {
1237         struct list_head *el, *tmp;
1238         struct kset *ip_kset;
1239
1240         ip_kset = &ip_die_entry->ip_kset;
1241         spin_lock(&ip_kset->list_lock);
1242         list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1243                 list_del_init(el);
1244                 spin_unlock(&ip_kset->list_lock);
1245                 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1246                 spin_lock(&ip_kset->list_lock);
1247         }
1248         spin_unlock(&ip_kset->list_lock);
1249         kobject_put(&ip_die_entry->ip_kset.kobj);
1250 }
1251
1252 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1253 {
1254         struct list_head *el, *tmp;
1255         struct kset *die_kset;
1256
1257         die_kset = &adev->ip_top->die_kset;
1258         spin_lock(&die_kset->list_lock);
1259         list_for_each_prev_safe(el, tmp, &die_kset->list) {
1260                 list_del_init(el);
1261                 spin_unlock(&die_kset->list_lock);
1262                 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1263                 spin_lock(&die_kset->list_lock);
1264         }
1265         spin_unlock(&die_kset->list_lock);
1266         kobject_put(&adev->ip_top->die_kset.kobj);
1267         kobject_put(&adev->ip_top->kobj);
1268 }
1269
1270 /* ================================================== */
1271
1272 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1273 {
1274         uint8_t num_base_address, subrev, variant;
1275         struct binary_header *bhdr;
1276         struct ip_discovery_header *ihdr;
1277         struct die_header *dhdr;
1278         struct ip_v4 *ip;
1279         uint16_t die_offset;
1280         uint16_t ip_offset;
1281         uint16_t num_dies;
1282         uint16_t num_ips;
1283         int hw_ip;
1284         int i, j, k;
1285         int r;
1286
1287         r = amdgpu_discovery_init(adev);
1288         if (r) {
1289                 DRM_ERROR("amdgpu_discovery_init failed\n");
1290                 return r;
1291         }
1292
1293         adev->gfx.xcc_mask = 0;
1294         adev->sdma.sdma_mask = 0;
1295         adev->vcn.inst_mask = 0;
1296         adev->jpeg.inst_mask = 0;
1297         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1298         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1299                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1300         num_dies = le16_to_cpu(ihdr->num_dies);
1301
1302         DRM_DEBUG("number of dies: %d\n", num_dies);
1303
1304         for (i = 0; i < num_dies; i++) {
1305                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1306                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1307                 num_ips = le16_to_cpu(dhdr->num_ips);
1308                 ip_offset = die_offset + sizeof(*dhdr);
1309
1310                 if (le16_to_cpu(dhdr->die_id) != i) {
1311                         DRM_ERROR("invalid die id %d, expected %d\n",
1312                                         le16_to_cpu(dhdr->die_id), i);
1313                         return -EINVAL;
1314                 }
1315
1316                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1317                                 le16_to_cpu(dhdr->die_id), num_ips);
1318
1319                 for (j = 0; j < num_ips; j++) {
1320                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
1321
1322                         if (amdgpu_discovery_validate_ip(ip))
1323                                 goto next_ip;
1324
1325                         num_base_address = ip->num_base_address;
1326
1327                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1328                                   hw_id_names[le16_to_cpu(ip->hw_id)],
1329                                   le16_to_cpu(ip->hw_id),
1330                                   ip->instance_number,
1331                                   ip->major, ip->minor,
1332                                   ip->revision);
1333
1334                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1335                                 /* Bit [5:0]: original revision value
1336                                  * Bit [7:6]: en/decode capability:
1337                                  *     0b00 : VCN function normally
1338                                  *     0b10 : encode is disabled
1339                                  *     0b01 : decode is disabled
1340                                  */
1341                                 if (adev->vcn.num_vcn_inst <
1342                                     AMDGPU_MAX_VCN_INSTANCES) {
1343                                         adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1344                                                 ip->revision & 0xc0;
1345                                         adev->vcn.num_vcn_inst++;
1346                                         adev->vcn.inst_mask |=
1347                                                 (1U << ip->instance_number);
1348                                         adev->jpeg.inst_mask |=
1349                                                 (1U << ip->instance_number);
1350                                 } else {
1351                                         dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1352                                                 adev->vcn.num_vcn_inst + 1,
1353                                                 AMDGPU_MAX_VCN_INSTANCES);
1354                                 }
1355                                 ip->revision &= ~0xc0;
1356                         }
1357                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1358                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1359                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1360                             le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1361                                 if (adev->sdma.num_instances <
1362                                     AMDGPU_MAX_SDMA_INSTANCES) {
1363                                         adev->sdma.num_instances++;
1364                                         adev->sdma.sdma_mask |=
1365                                                 (1U << ip->instance_number);
1366                                 } else {
1367                                         dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1368                                                 adev->sdma.num_instances + 1,
1369                                                 AMDGPU_MAX_SDMA_INSTANCES);
1370                                 }
1371                         }
1372
1373                         if (le16_to_cpu(ip->hw_id) == VPE_HWID) {
1374                                 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES)
1375                                         adev->vpe.num_instances++;
1376                                 else
1377                                         dev_err(adev->dev, "Too many VPE instances: %d vs %d\n",
1378                                                 adev->vpe.num_instances + 1,
1379                                                 AMDGPU_MAX_VPE_INSTANCES);
1380                         }
1381
1382                         if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1383                                 adev->gmc.num_umc++;
1384                                 adev->umc.node_inst_num++;
1385                         }
1386
1387                         if (le16_to_cpu(ip->hw_id) == GC_HWID)
1388                                 adev->gfx.xcc_mask |=
1389                                         (1U << ip->instance_number);
1390
1391                         for (k = 0; k < num_base_address; k++) {
1392                                 /*
1393                                  * convert the endianness of base addresses in place,
1394                                  * so that we don't need to convert them when accessing adev->reg_offset.
1395                                  */
1396                                 if (ihdr->base_addr_64_bit)
1397                                         /* Truncate the 64bit base address from ip discovery
1398                                          * and only store lower 32bit ip base in reg_offset[].
1399                                          * Bits > 32 follows ASIC specific format, thus just
1400                                          * discard them and handle it within specific ASIC.
1401                                          * By this way reg_offset[] and related helpers can
1402                                          * stay unchanged.
1403                                          * The base address is in dwords, thus clear the
1404                                          * highest 2 bits to store.
1405                                          */
1406                                         ip->base_address[k] =
1407                                                 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1408                                 else
1409                                         ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1410                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1411                         }
1412
1413                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1414                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1415                                     hw_id_map[hw_ip] != 0) {
1416                                         DRM_DEBUG("set register base offset for %s\n",
1417                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
1418                                         adev->reg_offset[hw_ip][ip->instance_number] =
1419                                                 ip->base_address;
1420                                         /* Instance support is somewhat inconsistent.
1421                                          * SDMA is a good example.  Sienna cichlid has 4 total
1422                                          * SDMA instances, each enumerated separately (HWIDs
1423                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
1424                                          * but they are enumerated as multiple instances of the
1425                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
1426                                          * example.  On most chips there are multiple instances
1427                                          * with the same HWID.
1428                                          */
1429
1430                                         if (ihdr->version < 3) {
1431                                                 subrev = 0;
1432                                                 variant = 0;
1433                                         } else {
1434                                                 subrev = ip->sub_revision;
1435                                                 variant = ip->variant;
1436                                         }
1437
1438                                         adev->ip_versions[hw_ip]
1439                                                          [ip->instance_number] =
1440                                                 IP_VERSION_FULL(ip->major,
1441                                                                 ip->minor,
1442                                                                 ip->revision,
1443                                                                 variant,
1444                                                                 subrev);
1445                                 }
1446                         }
1447
1448 next_ip:
1449                         if (ihdr->base_addr_64_bit)
1450                                 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1451                         else
1452                                 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1453                 }
1454         }
1455
1456         return 0;
1457 }
1458
1459 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1460 {
1461         int vcn_harvest_count = 0;
1462         int umc_harvest_count = 0;
1463
1464         /*
1465          * Harvest table does not fit Navi1x and legacy GPUs,
1466          * so read harvest bit per IP data structure to set
1467          * harvest configuration.
1468          */
1469         if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) &&
1470             amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) &&
1471             amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) {
1472                 if ((adev->pdev->device == 0x731E &&
1473                         (adev->pdev->revision == 0xC6 ||
1474                          adev->pdev->revision == 0xC7)) ||
1475                         (adev->pdev->device == 0x7340 &&
1476                          adev->pdev->revision == 0xC9) ||
1477                         (adev->pdev->device == 0x7360 &&
1478                          adev->pdev->revision == 0xC7))
1479                         amdgpu_discovery_read_harvest_bit_per_ip(adev,
1480                                 &vcn_harvest_count);
1481         } else {
1482                 amdgpu_discovery_read_from_harvest_table(adev,
1483                                                          &vcn_harvest_count,
1484                                                          &umc_harvest_count);
1485         }
1486
1487         amdgpu_discovery_harvest_config_quirk(adev);
1488
1489         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1490                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1491                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1492         }
1493
1494         if (umc_harvest_count < adev->gmc.num_umc) {
1495                 adev->gmc.num_umc -= umc_harvest_count;
1496         }
1497 }
1498
1499 union gc_info {
1500         struct gc_info_v1_0 v1;
1501         struct gc_info_v1_1 v1_1;
1502         struct gc_info_v1_2 v1_2;
1503         struct gc_info_v2_0 v2;
1504         struct gc_info_v2_1 v2_1;
1505 };
1506
1507 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1508 {
1509         struct binary_header *bhdr;
1510         union gc_info *gc_info;
1511         u16 offset;
1512
1513         if (!adev->mman.discovery_bin) {
1514                 DRM_ERROR("ip discovery uninitialized\n");
1515                 return -EINVAL;
1516         }
1517
1518         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1519         offset = le16_to_cpu(bhdr->table_list[GC].offset);
1520
1521         if (!offset)
1522                 return 0;
1523
1524         gc_info = (union gc_info *)(adev->mman.discovery_bin + offset);
1525
1526         switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1527         case 1:
1528                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1529                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1530                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1531                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1532                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1533                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1534                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1535                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1536                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1537                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1538                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1539                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1540                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1541                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1542                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1543                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1544                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1545                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1546                 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) {
1547                         adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1548                         adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1549                         adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1550                 }
1551                 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) {
1552                         adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1553                         adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1554                         adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1555                         adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1556                         adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1557                         adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1558                         adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1559                         adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1560                 }
1561                 break;
1562         case 2:
1563                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1564                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1565                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1566                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1567                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1568                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1569                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1570                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1571                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1572                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1573                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1574                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1575                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1576                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1577                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1578                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1579                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1580                 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) {
1581                         adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh);
1582                         adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu);
1583                         adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */
1584                         adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc);
1585                         adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc);
1586                         adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc);
1587                         adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */
1588                 }
1589                 break;
1590         default:
1591                 dev_err(adev->dev,
1592                         "Unhandled GC info table %d.%d\n",
1593                         le16_to_cpu(gc_info->v1.header.version_major),
1594                         le16_to_cpu(gc_info->v1.header.version_minor));
1595                 return -EINVAL;
1596         }
1597         return 0;
1598 }
1599
1600 union mall_info {
1601         struct mall_info_v1_0 v1;
1602         struct mall_info_v2_0 v2;
1603 };
1604
1605 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
1606 {
1607         struct binary_header *bhdr;
1608         union mall_info *mall_info;
1609         u32 u, mall_size_per_umc, m_s_present, half_use;
1610         u64 mall_size;
1611         u16 offset;
1612
1613         if (!adev->mman.discovery_bin) {
1614                 DRM_ERROR("ip discovery uninitialized\n");
1615                 return -EINVAL;
1616         }
1617
1618         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1619         offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset);
1620
1621         if (!offset)
1622                 return 0;
1623
1624         mall_info = (union mall_info *)(adev->mman.discovery_bin + offset);
1625
1626         switch (le16_to_cpu(mall_info->v1.header.version_major)) {
1627         case 1:
1628                 mall_size = 0;
1629                 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
1630                 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
1631                 half_use = le32_to_cpu(mall_info->v1.m_half_use);
1632                 for (u = 0; u < adev->gmc.num_umc; u++) {
1633                         if (m_s_present & (1 << u))
1634                                 mall_size += mall_size_per_umc * 2;
1635                         else if (half_use & (1 << u))
1636                                 mall_size += mall_size_per_umc / 2;
1637                         else
1638                                 mall_size += mall_size_per_umc;
1639                 }
1640                 adev->gmc.mall_size = mall_size;
1641                 adev->gmc.m_half_use = half_use;
1642                 break;
1643         case 2:
1644                 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc);
1645                 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc;
1646                 break;
1647         default:
1648                 dev_err(adev->dev,
1649                         "Unhandled MALL info table %d.%d\n",
1650                         le16_to_cpu(mall_info->v1.header.version_major),
1651                         le16_to_cpu(mall_info->v1.header.version_minor));
1652                 return -EINVAL;
1653         }
1654         return 0;
1655 }
1656
1657 union vcn_info {
1658         struct vcn_info_v1_0 v1;
1659 };
1660
1661 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
1662 {
1663         struct binary_header *bhdr;
1664         union vcn_info *vcn_info;
1665         u16 offset;
1666         int v;
1667
1668         if (!adev->mman.discovery_bin) {
1669                 DRM_ERROR("ip discovery uninitialized\n");
1670                 return -EINVAL;
1671         }
1672
1673         /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1674          * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
1675          * but that may change in the future with new GPUs so keep this
1676          * check for defensive purposes.
1677          */
1678         if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
1679                 dev_err(adev->dev, "invalid vcn instances\n");
1680                 return -EINVAL;
1681         }
1682
1683         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1684         offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset);
1685
1686         if (!offset)
1687                 return 0;
1688
1689         vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset);
1690
1691         switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
1692         case 1:
1693                 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1694                  * so this won't overflow.
1695                  */
1696                 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
1697                         adev->vcn.vcn_codec_disable_mask[v] =
1698                                 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
1699                 }
1700                 break;
1701         default:
1702                 dev_err(adev->dev,
1703                         "Unhandled VCN info table %d.%d\n",
1704                         le16_to_cpu(vcn_info->v1.header.version_major),
1705                         le16_to_cpu(vcn_info->v1.header.version_minor));
1706                 return -EINVAL;
1707         }
1708         return 0;
1709 }
1710
1711 union nps_info {
1712         struct nps_info_v1_0 v1;
1713 };
1714
1715 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
1716                                   uint32_t *nps_type,
1717                                   struct amdgpu_gmc_memrange **ranges,
1718                                   int *range_cnt)
1719 {
1720         struct amdgpu_gmc_memrange *mem_ranges;
1721         struct binary_header *bhdr;
1722         union nps_info *nps_info;
1723         u16 offset;
1724         int i;
1725
1726         if (!nps_type || !range_cnt || !ranges)
1727                 return -EINVAL;
1728
1729         if (!adev->mman.discovery_bin) {
1730                 dev_err(adev->dev,
1731                         "fetch mem range failed, ip discovery uninitialized\n");
1732                 return -EINVAL;
1733         }
1734
1735         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1736         offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset);
1737
1738         if (!offset)
1739                 return -ENOENT;
1740
1741         /* If verification fails, return as if NPS table doesn't exist */
1742         if (amdgpu_discovery_verify_npsinfo(adev, bhdr))
1743                 return -ENOENT;
1744
1745         nps_info = (union nps_info *)(adev->mman.discovery_bin + offset);
1746
1747         switch (le16_to_cpu(nps_info->v1.header.version_major)) {
1748         case 1:
1749                 *nps_type = nps_info->v1.nps_type;
1750                 *range_cnt = nps_info->v1.count;
1751                 mem_ranges = kvzalloc(
1752                         *range_cnt * sizeof(struct amdgpu_gmc_memrange),
1753                         GFP_KERNEL);
1754                 for (i = 0; i < *range_cnt; i++) {
1755                         mem_ranges[i].base_address =
1756                                 nps_info->v1.instance_info[i].base_address;
1757                         mem_ranges[i].limit_address =
1758                                 nps_info->v1.instance_info[i].limit_address;
1759                         mem_ranges[i].nid_mask = -1;
1760                         mem_ranges[i].flags = 0;
1761                 }
1762                 *ranges = mem_ranges;
1763                 break;
1764         default:
1765                 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n",
1766                         le16_to_cpu(nps_info->v1.header.version_major),
1767                         le16_to_cpu(nps_info->v1.header.version_minor));
1768                 return -EINVAL;
1769         }
1770
1771         return 0;
1772 }
1773
1774 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1775 {
1776         /* what IP to use for this? */
1777         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1778         case IP_VERSION(9, 0, 1):
1779         case IP_VERSION(9, 1, 0):
1780         case IP_VERSION(9, 2, 1):
1781         case IP_VERSION(9, 2, 2):
1782         case IP_VERSION(9, 3, 0):
1783         case IP_VERSION(9, 4, 0):
1784         case IP_VERSION(9, 4, 1):
1785         case IP_VERSION(9, 4, 2):
1786         case IP_VERSION(9, 4, 3):
1787         case IP_VERSION(9, 4, 4):
1788                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1789                 break;
1790         case IP_VERSION(10, 1, 10):
1791         case IP_VERSION(10, 1, 1):
1792         case IP_VERSION(10, 1, 2):
1793         case IP_VERSION(10, 1, 3):
1794         case IP_VERSION(10, 1, 4):
1795         case IP_VERSION(10, 3, 0):
1796         case IP_VERSION(10, 3, 1):
1797         case IP_VERSION(10, 3, 2):
1798         case IP_VERSION(10, 3, 3):
1799         case IP_VERSION(10, 3, 4):
1800         case IP_VERSION(10, 3, 5):
1801         case IP_VERSION(10, 3, 6):
1802         case IP_VERSION(10, 3, 7):
1803                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1804                 break;
1805         case IP_VERSION(11, 0, 0):
1806         case IP_VERSION(11, 0, 1):
1807         case IP_VERSION(11, 0, 2):
1808         case IP_VERSION(11, 0, 3):
1809         case IP_VERSION(11, 0, 4):
1810         case IP_VERSION(11, 5, 0):
1811         case IP_VERSION(11, 5, 1):
1812         case IP_VERSION(11, 5, 2):
1813                 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
1814                 break;
1815         case IP_VERSION(12, 0, 0):
1816         case IP_VERSION(12, 0, 1):
1817                 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block);
1818                 break;
1819         default:
1820                 dev_err(adev->dev,
1821                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
1822                         amdgpu_ip_version(adev, GC_HWIP, 0));
1823                 return -EINVAL;
1824         }
1825         return 0;
1826 }
1827
1828 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1829 {
1830         /* use GC or MMHUB IP version */
1831         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1832         case IP_VERSION(9, 0, 1):
1833         case IP_VERSION(9, 1, 0):
1834         case IP_VERSION(9, 2, 1):
1835         case IP_VERSION(9, 2, 2):
1836         case IP_VERSION(9, 3, 0):
1837         case IP_VERSION(9, 4, 0):
1838         case IP_VERSION(9, 4, 1):
1839         case IP_VERSION(9, 4, 2):
1840         case IP_VERSION(9, 4, 3):
1841         case IP_VERSION(9, 4, 4):
1842                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1843                 break;
1844         case IP_VERSION(10, 1, 10):
1845         case IP_VERSION(10, 1, 1):
1846         case IP_VERSION(10, 1, 2):
1847         case IP_VERSION(10, 1, 3):
1848         case IP_VERSION(10, 1, 4):
1849         case IP_VERSION(10, 3, 0):
1850         case IP_VERSION(10, 3, 1):
1851         case IP_VERSION(10, 3, 2):
1852         case IP_VERSION(10, 3, 3):
1853         case IP_VERSION(10, 3, 4):
1854         case IP_VERSION(10, 3, 5):
1855         case IP_VERSION(10, 3, 6):
1856         case IP_VERSION(10, 3, 7):
1857                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1858                 break;
1859         case IP_VERSION(11, 0, 0):
1860         case IP_VERSION(11, 0, 1):
1861         case IP_VERSION(11, 0, 2):
1862         case IP_VERSION(11, 0, 3):
1863         case IP_VERSION(11, 0, 4):
1864         case IP_VERSION(11, 5, 0):
1865         case IP_VERSION(11, 5, 1):
1866         case IP_VERSION(11, 5, 2):
1867                 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
1868                 break;
1869         case IP_VERSION(12, 0, 0):
1870         case IP_VERSION(12, 0, 1):
1871                 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block);
1872                 break;
1873         default:
1874                 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1875                         amdgpu_ip_version(adev, GC_HWIP, 0));
1876                 return -EINVAL;
1877         }
1878         return 0;
1879 }
1880
1881 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1882 {
1883         switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) {
1884         case IP_VERSION(4, 0, 0):
1885         case IP_VERSION(4, 0, 1):
1886         case IP_VERSION(4, 1, 0):
1887         case IP_VERSION(4, 1, 1):
1888         case IP_VERSION(4, 3, 0):
1889                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1890                 break;
1891         case IP_VERSION(4, 2, 0):
1892         case IP_VERSION(4, 2, 1):
1893         case IP_VERSION(4, 4, 0):
1894         case IP_VERSION(4, 4, 2):
1895         case IP_VERSION(4, 4, 5):
1896                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1897                 break;
1898         case IP_VERSION(5, 0, 0):
1899         case IP_VERSION(5, 0, 1):
1900         case IP_VERSION(5, 0, 2):
1901         case IP_VERSION(5, 0, 3):
1902         case IP_VERSION(5, 2, 0):
1903         case IP_VERSION(5, 2, 1):
1904                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1905                 break;
1906         case IP_VERSION(6, 0, 0):
1907         case IP_VERSION(6, 0, 1):
1908         case IP_VERSION(6, 0, 2):
1909                 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
1910                 break;
1911         case IP_VERSION(6, 1, 0):
1912                 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block);
1913                 break;
1914         case IP_VERSION(7, 0, 0):
1915                 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block);
1916                 break;
1917         default:
1918                 dev_err(adev->dev,
1919                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1920                         amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
1921                 return -EINVAL;
1922         }
1923         return 0;
1924 }
1925
1926 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1927 {
1928         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
1929         case IP_VERSION(9, 0, 0):
1930                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1931                 break;
1932         case IP_VERSION(10, 0, 0):
1933         case IP_VERSION(10, 0, 1):
1934                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1935                 break;
1936         case IP_VERSION(11, 0, 0):
1937         case IP_VERSION(11, 0, 2):
1938         case IP_VERSION(11, 0, 4):
1939         case IP_VERSION(11, 0, 5):
1940         case IP_VERSION(11, 0, 9):
1941         case IP_VERSION(11, 0, 7):
1942         case IP_VERSION(11, 0, 11):
1943         case IP_VERSION(11, 0, 12):
1944         case IP_VERSION(11, 0, 13):
1945         case IP_VERSION(11, 5, 0):
1946                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1947                 break;
1948         case IP_VERSION(11, 0, 8):
1949                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1950                 break;
1951         case IP_VERSION(11, 0, 3):
1952         case IP_VERSION(12, 0, 1):
1953                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1954                 break;
1955         case IP_VERSION(13, 0, 0):
1956         case IP_VERSION(13, 0, 1):
1957         case IP_VERSION(13, 0, 2):
1958         case IP_VERSION(13, 0, 3):
1959         case IP_VERSION(13, 0, 5):
1960         case IP_VERSION(13, 0, 6):
1961         case IP_VERSION(13, 0, 7):
1962         case IP_VERSION(13, 0, 8):
1963         case IP_VERSION(13, 0, 10):
1964         case IP_VERSION(13, 0, 11):
1965         case IP_VERSION(13, 0, 14):
1966         case IP_VERSION(14, 0, 0):
1967         case IP_VERSION(14, 0, 1):
1968         case IP_VERSION(14, 0, 4):
1969                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1970                 break;
1971         case IP_VERSION(13, 0, 4):
1972                 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
1973                 break;
1974         case IP_VERSION(14, 0, 2):
1975         case IP_VERSION(14, 0, 3):
1976                 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block);
1977                 break;
1978         default:
1979                 dev_err(adev->dev,
1980                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1981                         amdgpu_ip_version(adev, MP0_HWIP, 0));
1982                 return -EINVAL;
1983         }
1984         return 0;
1985 }
1986
1987 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1988 {
1989         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1990         case IP_VERSION(9, 0, 0):
1991         case IP_VERSION(10, 0, 0):
1992         case IP_VERSION(10, 0, 1):
1993         case IP_VERSION(11, 0, 2):
1994                 if (adev->asic_type == CHIP_ARCTURUS)
1995                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1996                 else
1997                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1998                 break;
1999         case IP_VERSION(11, 0, 0):
2000         case IP_VERSION(11, 0, 5):
2001         case IP_VERSION(11, 0, 9):
2002         case IP_VERSION(11, 0, 7):
2003         case IP_VERSION(11, 0, 8):
2004         case IP_VERSION(11, 0, 11):
2005         case IP_VERSION(11, 0, 12):
2006         case IP_VERSION(11, 0, 13):
2007         case IP_VERSION(11, 5, 0):
2008                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2009                 break;
2010         case IP_VERSION(12, 0, 0):
2011         case IP_VERSION(12, 0, 1):
2012                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
2013                 break;
2014         case IP_VERSION(13, 0, 0):
2015         case IP_VERSION(13, 0, 1):
2016         case IP_VERSION(13, 0, 2):
2017         case IP_VERSION(13, 0, 3):
2018         case IP_VERSION(13, 0, 4):
2019         case IP_VERSION(13, 0, 5):
2020         case IP_VERSION(13, 0, 6):
2021         case IP_VERSION(13, 0, 7):
2022         case IP_VERSION(13, 0, 8):
2023         case IP_VERSION(13, 0, 10):
2024         case IP_VERSION(13, 0, 11):
2025         case IP_VERSION(13, 0, 14):
2026                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
2027                 break;
2028         case IP_VERSION(14, 0, 0):
2029         case IP_VERSION(14, 0, 1):
2030         case IP_VERSION(14, 0, 2):
2031         case IP_VERSION(14, 0, 3):
2032         case IP_VERSION(14, 0, 4):
2033                 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
2034                 break;
2035         default:
2036                 dev_err(adev->dev,
2037                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
2038                         amdgpu_ip_version(adev, MP1_HWIP, 0));
2039                 return -EINVAL;
2040         }
2041         return 0;
2042 }
2043
2044 #if defined(CONFIG_DRM_AMD_DC)
2045 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
2046 {
2047         amdgpu_device_set_sriov_virtual_display(adev);
2048         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2049 }
2050 #endif
2051
2052 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
2053 {
2054         if (adev->enable_virtual_display) {
2055                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2056                 return 0;
2057         }
2058
2059         if (!amdgpu_device_has_dc_support(adev))
2060                 return 0;
2061
2062 #if defined(CONFIG_DRM_AMD_DC)
2063         if (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2064                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2065                 case IP_VERSION(1, 0, 0):
2066                 case IP_VERSION(1, 0, 1):
2067                 case IP_VERSION(2, 0, 2):
2068                 case IP_VERSION(2, 0, 0):
2069                 case IP_VERSION(2, 0, 3):
2070                 case IP_VERSION(2, 1, 0):
2071                 case IP_VERSION(3, 0, 0):
2072                 case IP_VERSION(3, 0, 2):
2073                 case IP_VERSION(3, 0, 3):
2074                 case IP_VERSION(3, 0, 1):
2075                 case IP_VERSION(3, 1, 2):
2076                 case IP_VERSION(3, 1, 3):
2077                 case IP_VERSION(3, 1, 4):
2078                 case IP_VERSION(3, 1, 5):
2079                 case IP_VERSION(3, 1, 6):
2080                 case IP_VERSION(3, 2, 0):
2081                 case IP_VERSION(3, 2, 1):
2082                 case IP_VERSION(3, 5, 0):
2083                 case IP_VERSION(3, 5, 1):
2084                 case IP_VERSION(4, 1, 0):
2085                         /* TODO: Fix IP version. DC code expects version 4.0.1 */
2086                         if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0))
2087                                 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1);
2088
2089                         if (amdgpu_sriov_vf(adev))
2090                                 amdgpu_discovery_set_sriov_display(adev);
2091                         else
2092                                 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2093                         break;
2094                 default:
2095                         dev_err(adev->dev,
2096                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
2097                                 amdgpu_ip_version(adev, DCE_HWIP, 0));
2098                         return -EINVAL;
2099                 }
2100         } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2101                 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2102                 case IP_VERSION(12, 0, 0):
2103                 case IP_VERSION(12, 0, 1):
2104                 case IP_VERSION(12, 1, 0):
2105                         if (amdgpu_sriov_vf(adev))
2106                                 amdgpu_discovery_set_sriov_display(adev);
2107                         else
2108                                 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2109                         break;
2110                 default:
2111                         dev_err(adev->dev,
2112                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
2113                                 amdgpu_ip_version(adev, DCI_HWIP, 0));
2114                         return -EINVAL;
2115                 }
2116         }
2117 #endif
2118         return 0;
2119 }
2120
2121 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
2122 {
2123         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2124         case IP_VERSION(9, 0, 1):
2125         case IP_VERSION(9, 1, 0):
2126         case IP_VERSION(9, 2, 1):
2127         case IP_VERSION(9, 2, 2):
2128         case IP_VERSION(9, 3, 0):
2129         case IP_VERSION(9, 4, 0):
2130         case IP_VERSION(9, 4, 1):
2131         case IP_VERSION(9, 4, 2):
2132                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
2133                 break;
2134         case IP_VERSION(9, 4, 3):
2135         case IP_VERSION(9, 4, 4):
2136                 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
2137                 break;
2138         case IP_VERSION(10, 1, 10):
2139         case IP_VERSION(10, 1, 2):
2140         case IP_VERSION(10, 1, 1):
2141         case IP_VERSION(10, 1, 3):
2142         case IP_VERSION(10, 1, 4):
2143         case IP_VERSION(10, 3, 0):
2144         case IP_VERSION(10, 3, 2):
2145         case IP_VERSION(10, 3, 1):
2146         case IP_VERSION(10, 3, 4):
2147         case IP_VERSION(10, 3, 5):
2148         case IP_VERSION(10, 3, 6):
2149         case IP_VERSION(10, 3, 3):
2150         case IP_VERSION(10, 3, 7):
2151                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
2152                 break;
2153         case IP_VERSION(11, 0, 0):
2154         case IP_VERSION(11, 0, 1):
2155         case IP_VERSION(11, 0, 2):
2156         case IP_VERSION(11, 0, 3):
2157         case IP_VERSION(11, 0, 4):
2158         case IP_VERSION(11, 5, 0):
2159         case IP_VERSION(11, 5, 1):
2160         case IP_VERSION(11, 5, 2):
2161                 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
2162                 break;
2163         case IP_VERSION(12, 0, 0):
2164         case IP_VERSION(12, 0, 1):
2165                 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block);
2166                 break;
2167         default:
2168                 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
2169                         amdgpu_ip_version(adev, GC_HWIP, 0));
2170                 return -EINVAL;
2171         }
2172         return 0;
2173 }
2174
2175 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
2176 {
2177         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
2178         case IP_VERSION(4, 0, 0):
2179         case IP_VERSION(4, 0, 1):
2180         case IP_VERSION(4, 1, 0):
2181         case IP_VERSION(4, 1, 1):
2182         case IP_VERSION(4, 1, 2):
2183         case IP_VERSION(4, 2, 0):
2184         case IP_VERSION(4, 2, 2):
2185         case IP_VERSION(4, 4, 0):
2186                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2187                 break;
2188         case IP_VERSION(4, 4, 2):
2189         case IP_VERSION(4, 4, 5):
2190                 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
2191                 break;
2192         case IP_VERSION(5, 0, 0):
2193         case IP_VERSION(5, 0, 1):
2194         case IP_VERSION(5, 0, 2):
2195         case IP_VERSION(5, 0, 5):
2196                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
2197                 break;
2198         case IP_VERSION(5, 2, 0):
2199         case IP_VERSION(5, 2, 2):
2200         case IP_VERSION(5, 2, 4):
2201         case IP_VERSION(5, 2, 5):
2202         case IP_VERSION(5, 2, 6):
2203         case IP_VERSION(5, 2, 3):
2204         case IP_VERSION(5, 2, 1):
2205         case IP_VERSION(5, 2, 7):
2206                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
2207                 break;
2208         case IP_VERSION(6, 0, 0):
2209         case IP_VERSION(6, 0, 1):
2210         case IP_VERSION(6, 0, 2):
2211         case IP_VERSION(6, 0, 3):
2212         case IP_VERSION(6, 1, 0):
2213         case IP_VERSION(6, 1, 1):
2214         case IP_VERSION(6, 1, 2):
2215                 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
2216                 break;
2217         case IP_VERSION(7, 0, 0):
2218         case IP_VERSION(7, 0, 1):
2219                 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block);
2220                 break;
2221         default:
2222                 dev_err(adev->dev,
2223                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
2224                         amdgpu_ip_version(adev, SDMA0_HWIP, 0));
2225                 return -EINVAL;
2226         }
2227         return 0;
2228 }
2229
2230 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
2231 {
2232         if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2233                 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2234                 case IP_VERSION(7, 0, 0):
2235                 case IP_VERSION(7, 2, 0):
2236                         /* UVD is not supported on vega20 SR-IOV */
2237                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2238                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
2239                         break;
2240                 default:
2241                         dev_err(adev->dev,
2242                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
2243                                 amdgpu_ip_version(adev, UVD_HWIP, 0));
2244                         return -EINVAL;
2245                 }
2246                 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2247                 case IP_VERSION(4, 0, 0):
2248                 case IP_VERSION(4, 1, 0):
2249                         /* VCE is not supported on vega20 SR-IOV */
2250                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2251                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
2252                         break;
2253                 default:
2254                         dev_err(adev->dev,
2255                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2256                                 amdgpu_ip_version(adev, VCE_HWIP, 0));
2257                         return -EINVAL;
2258                 }
2259         } else {
2260                 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2261                 case IP_VERSION(1, 0, 0):
2262                 case IP_VERSION(1, 0, 1):
2263                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2264                         break;
2265                 case IP_VERSION(2, 0, 0):
2266                 case IP_VERSION(2, 0, 2):
2267                 case IP_VERSION(2, 2, 0):
2268                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2269                         if (!amdgpu_sriov_vf(adev))
2270                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2271                         break;
2272                 case IP_VERSION(2, 0, 3):
2273                         break;
2274                 case IP_VERSION(2, 5, 0):
2275                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2276                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2277                         break;
2278                 case IP_VERSION(2, 6, 0):
2279                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2280                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2281                         break;
2282                 case IP_VERSION(3, 0, 0):
2283                 case IP_VERSION(3, 0, 16):
2284                 case IP_VERSION(3, 1, 1):
2285                 case IP_VERSION(3, 1, 2):
2286                 case IP_VERSION(3, 0, 2):
2287                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2288                         if (!amdgpu_sriov_vf(adev))
2289                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2290                         break;
2291                 case IP_VERSION(3, 0, 33):
2292                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2293                         break;
2294                 case IP_VERSION(4, 0, 0):
2295                 case IP_VERSION(4, 0, 2):
2296                 case IP_VERSION(4, 0, 4):
2297                         amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2298                         amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2299                         break;
2300                 case IP_VERSION(4, 0, 3):
2301                         amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2302                         amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2303                         break;
2304                 case IP_VERSION(4, 0, 5):
2305                 case IP_VERSION(4, 0, 6):
2306                         amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
2307                         amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
2308                         break;
2309                 case IP_VERSION(5, 0, 0):
2310                         amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2311                         amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
2312                         break;
2313                 default:
2314                         dev_err(adev->dev,
2315                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2316                                 amdgpu_ip_version(adev, UVD_HWIP, 0));
2317                         return -EINVAL;
2318                 }
2319         }
2320         return 0;
2321 }
2322
2323 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2324 {
2325         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2326         case IP_VERSION(11, 0, 0):
2327         case IP_VERSION(11, 0, 1):
2328         case IP_VERSION(11, 0, 2):
2329         case IP_VERSION(11, 0, 3):
2330         case IP_VERSION(11, 0, 4):
2331         case IP_VERSION(11, 5, 0):
2332         case IP_VERSION(11, 5, 1):
2333         case IP_VERSION(11, 5, 2):
2334                 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2335                 adev->enable_mes = true;
2336                 adev->enable_mes_kiq = true;
2337                 break;
2338         case IP_VERSION(12, 0, 0):
2339         case IP_VERSION(12, 0, 1):
2340                 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block);
2341                 adev->enable_mes = true;
2342                 adev->enable_mes_kiq = true;
2343                 if (amdgpu_uni_mes)
2344                         adev->enable_uni_mes = true;
2345                 break;
2346         default:
2347                 break;
2348         }
2349         return 0;
2350 }
2351
2352 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
2353 {
2354         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2355         case IP_VERSION(9, 4, 3):
2356         case IP_VERSION(9, 4, 4):
2357                 aqua_vanjaram_init_soc_config(adev);
2358                 break;
2359         default:
2360                 break;
2361         }
2362 }
2363
2364 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)
2365 {
2366         switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
2367         case IP_VERSION(6, 1, 0):
2368         case IP_VERSION(6, 1, 1):
2369         case IP_VERSION(6, 1, 3):
2370                 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);
2371                 break;
2372         default:
2373                 break;
2374         }
2375
2376         return 0;
2377 }
2378
2379 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
2380 {
2381         switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
2382         case IP_VERSION(4, 0, 5):
2383         case IP_VERSION(4, 0, 6):
2384                 if (amdgpu_umsch_mm & 0x1) {
2385                         amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block);
2386                         adev->enable_umsch_mm = true;
2387                 }
2388                 break;
2389         default:
2390                 break;
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev)
2397 {
2398 #if defined(CONFIG_DRM_AMD_ISP)
2399         switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {
2400         case IP_VERSION(4, 1, 0):
2401                 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block);
2402                 break;
2403         case IP_VERSION(4, 1, 1):
2404                 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block);
2405                 break;
2406         default:
2407                 break;
2408         }
2409 #endif
2410
2411         return 0;
2412 }
2413
2414 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
2415 {
2416         int r;
2417
2418         switch (adev->asic_type) {
2419         case CHIP_VEGA10:
2420                 vega10_reg_base_init(adev);
2421                 adev->sdma.num_instances = 2;
2422                 adev->gmc.num_umc = 4;
2423                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2424                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2425                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
2426                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
2427                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
2428                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
2429                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2430                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
2431                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
2432                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2433                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2434                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2435                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
2436                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
2437                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2438                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2439                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
2440                 break;
2441         case CHIP_VEGA12:
2442                 vega10_reg_base_init(adev);
2443                 adev->sdma.num_instances = 2;
2444                 adev->gmc.num_umc = 4;
2445                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2446                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2447                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
2448                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
2449                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
2450                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
2451                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
2452                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
2453                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
2454                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2455                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2456                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2457                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
2458                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
2459                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2460                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2461                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
2462                 break;
2463         case CHIP_RAVEN:
2464                 vega10_reg_base_init(adev);
2465                 adev->sdma.num_instances = 1;
2466                 adev->vcn.num_vcn_inst = 1;
2467                 adev->gmc.num_umc = 2;
2468                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
2469                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2470                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2471                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
2472                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
2473                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
2474                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
2475                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
2476                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
2477                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
2478                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
2479                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
2480                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
2481                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
2482                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
2483                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
2484                 } else {
2485                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2486                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2487                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
2488                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
2489                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
2490                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2491                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
2492                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
2493                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
2494                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
2495                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
2496                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
2497                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
2498                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
2499                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2500                 }
2501                 break;
2502         case CHIP_VEGA20:
2503                 vega20_reg_base_init(adev);
2504                 adev->sdma.num_instances = 2;
2505                 adev->gmc.num_umc = 8;
2506                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2507                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2508                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
2509                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
2510                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
2511                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
2512                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
2513                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
2514                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
2515                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
2516                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2517                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
2518                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
2519                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
2520                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
2521                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
2522                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
2523                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
2524                 break;
2525         case CHIP_ARCTURUS:
2526                 arct_reg_base_init(adev);
2527                 adev->sdma.num_instances = 8;
2528                 adev->vcn.num_vcn_inst = 2;
2529                 adev->gmc.num_umc = 8;
2530                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2531                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2532                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
2533                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
2534                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
2535                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
2536                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
2537                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
2538                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
2539                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
2540                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
2541                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
2542                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
2543                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
2544                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
2545                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
2546                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2547                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
2548                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
2549                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
2550                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
2551                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
2552                 break;
2553         case CHIP_ALDEBARAN:
2554                 aldebaran_reg_base_init(adev);
2555                 adev->sdma.num_instances = 5;
2556                 adev->vcn.num_vcn_inst = 2;
2557                 adev->gmc.num_umc = 4;
2558                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2559                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2560                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
2561                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
2562                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
2563                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
2564                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
2565                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
2566                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
2567                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
2568                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
2569                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
2570                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
2571                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
2572                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
2573                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
2574                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
2575                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
2576                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
2577                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
2578                 break;
2579         default:
2580                 r = amdgpu_discovery_reg_base_init(adev);
2581                 if (r)
2582                         return -EINVAL;
2583
2584                 amdgpu_discovery_harvest_ip(adev);
2585                 amdgpu_discovery_get_gfx_info(adev);
2586                 amdgpu_discovery_get_mall_info(adev);
2587                 amdgpu_discovery_get_vcn_info(adev);
2588                 break;
2589         }
2590
2591         amdgpu_discovery_init_soc_config(adev);
2592         amdgpu_discovery_sysfs_init(adev);
2593
2594         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2595         case IP_VERSION(9, 0, 1):
2596         case IP_VERSION(9, 2, 1):
2597         case IP_VERSION(9, 4, 0):
2598         case IP_VERSION(9, 4, 1):
2599         case IP_VERSION(9, 4, 2):
2600         case IP_VERSION(9, 4, 3):
2601         case IP_VERSION(9, 4, 4):
2602                 adev->family = AMDGPU_FAMILY_AI;
2603                 break;
2604         case IP_VERSION(9, 1, 0):
2605         case IP_VERSION(9, 2, 2):
2606         case IP_VERSION(9, 3, 0):
2607                 adev->family = AMDGPU_FAMILY_RV;
2608                 break;
2609         case IP_VERSION(10, 1, 10):
2610         case IP_VERSION(10, 1, 1):
2611         case IP_VERSION(10, 1, 2):
2612         case IP_VERSION(10, 1, 3):
2613         case IP_VERSION(10, 1, 4):
2614         case IP_VERSION(10, 3, 0):
2615         case IP_VERSION(10, 3, 2):
2616         case IP_VERSION(10, 3, 4):
2617         case IP_VERSION(10, 3, 5):
2618                 adev->family = AMDGPU_FAMILY_NV;
2619                 break;
2620         case IP_VERSION(10, 3, 1):
2621                 adev->family = AMDGPU_FAMILY_VGH;
2622                 adev->apu_flags |= AMD_APU_IS_VANGOGH;
2623                 break;
2624         case IP_VERSION(10, 3, 3):
2625                 adev->family = AMDGPU_FAMILY_YC;
2626                 break;
2627         case IP_VERSION(10, 3, 6):
2628                 adev->family = AMDGPU_FAMILY_GC_10_3_6;
2629                 break;
2630         case IP_VERSION(10, 3, 7):
2631                 adev->family = AMDGPU_FAMILY_GC_10_3_7;
2632                 break;
2633         case IP_VERSION(11, 0, 0):
2634         case IP_VERSION(11, 0, 2):
2635         case IP_VERSION(11, 0, 3):
2636                 adev->family = AMDGPU_FAMILY_GC_11_0_0;
2637                 break;
2638         case IP_VERSION(11, 0, 1):
2639         case IP_VERSION(11, 0, 4):
2640                 adev->family = AMDGPU_FAMILY_GC_11_0_1;
2641                 break;
2642         case IP_VERSION(11, 5, 0):
2643         case IP_VERSION(11, 5, 1):
2644         case IP_VERSION(11, 5, 2):
2645                 adev->family = AMDGPU_FAMILY_GC_11_5_0;
2646                 break;
2647         case IP_VERSION(12, 0, 0):
2648         case IP_VERSION(12, 0, 1):
2649                 adev->family = AMDGPU_FAMILY_GC_12_0_0;
2650                 break;
2651         default:
2652                 return -EINVAL;
2653         }
2654
2655         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2656         case IP_VERSION(9, 1, 0):
2657         case IP_VERSION(9, 2, 2):
2658         case IP_VERSION(9, 3, 0):
2659         case IP_VERSION(10, 1, 3):
2660         case IP_VERSION(10, 1, 4):
2661         case IP_VERSION(10, 3, 1):
2662         case IP_VERSION(10, 3, 3):
2663         case IP_VERSION(10, 3, 6):
2664         case IP_VERSION(10, 3, 7):
2665         case IP_VERSION(11, 0, 1):
2666         case IP_VERSION(11, 0, 4):
2667         case IP_VERSION(11, 5, 0):
2668         case IP_VERSION(11, 5, 1):
2669         case IP_VERSION(11, 5, 2):
2670                 adev->flags |= AMD_IS_APU;
2671                 break;
2672         default:
2673                 break;
2674         }
2675
2676         if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0))
2677                 adev->gmc.xgmi.supported = true;
2678
2679         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
2680             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4))
2681                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0);
2682
2683         /* set NBIO version */
2684         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2685         case IP_VERSION(6, 1, 0):
2686         case IP_VERSION(6, 2, 0):
2687                 adev->nbio.funcs = &nbio_v6_1_funcs;
2688                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
2689                 break;
2690         case IP_VERSION(7, 0, 0):
2691         case IP_VERSION(7, 0, 1):
2692         case IP_VERSION(2, 5, 0):
2693                 adev->nbio.funcs = &nbio_v7_0_funcs;
2694                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
2695                 break;
2696         case IP_VERSION(7, 4, 0):
2697         case IP_VERSION(7, 4, 1):
2698         case IP_VERSION(7, 4, 4):
2699                 adev->nbio.funcs = &nbio_v7_4_funcs;
2700                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
2701                 break;
2702         case IP_VERSION(7, 9, 0):
2703                 adev->nbio.funcs = &nbio_v7_9_funcs;
2704                 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
2705                 break;
2706         case IP_VERSION(7, 11, 0):
2707         case IP_VERSION(7, 11, 1):
2708         case IP_VERSION(7, 11, 3):
2709                 adev->nbio.funcs = &nbio_v7_11_funcs;
2710                 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;
2711                 break;
2712         case IP_VERSION(7, 2, 0):
2713         case IP_VERSION(7, 2, 1):
2714         case IP_VERSION(7, 3, 0):
2715         case IP_VERSION(7, 5, 0):
2716         case IP_VERSION(7, 5, 1):
2717                 adev->nbio.funcs = &nbio_v7_2_funcs;
2718                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
2719                 break;
2720         case IP_VERSION(2, 1, 1):
2721         case IP_VERSION(2, 3, 0):
2722         case IP_VERSION(2, 3, 1):
2723         case IP_VERSION(2, 3, 2):
2724         case IP_VERSION(3, 3, 0):
2725         case IP_VERSION(3, 3, 1):
2726         case IP_VERSION(3, 3, 2):
2727         case IP_VERSION(3, 3, 3):
2728                 adev->nbio.funcs = &nbio_v2_3_funcs;
2729                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
2730                 break;
2731         case IP_VERSION(4, 3, 0):
2732         case IP_VERSION(4, 3, 1):
2733                 if (amdgpu_sriov_vf(adev))
2734                         adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
2735                 else
2736                         adev->nbio.funcs = &nbio_v4_3_funcs;
2737                 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
2738                 break;
2739         case IP_VERSION(7, 7, 0):
2740         case IP_VERSION(7, 7, 1):
2741                 adev->nbio.funcs = &nbio_v7_7_funcs;
2742                 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
2743                 break;
2744         case IP_VERSION(6, 3, 1):
2745                 adev->nbio.funcs = &nbif_v6_3_1_funcs;
2746                 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
2747                 break;
2748         default:
2749                 break;
2750         }
2751
2752         switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
2753         case IP_VERSION(4, 0, 0):
2754         case IP_VERSION(4, 0, 1):
2755         case IP_VERSION(4, 1, 0):
2756         case IP_VERSION(4, 1, 1):
2757         case IP_VERSION(4, 1, 2):
2758         case IP_VERSION(4, 2, 0):
2759         case IP_VERSION(4, 2, 1):
2760         case IP_VERSION(4, 4, 0):
2761         case IP_VERSION(4, 4, 2):
2762         case IP_VERSION(4, 4, 5):
2763                 adev->hdp.funcs = &hdp_v4_0_funcs;
2764                 break;
2765         case IP_VERSION(5, 0, 0):
2766         case IP_VERSION(5, 0, 1):
2767         case IP_VERSION(5, 0, 2):
2768         case IP_VERSION(5, 0, 3):
2769         case IP_VERSION(5, 0, 4):
2770         case IP_VERSION(5, 2, 0):
2771                 adev->hdp.funcs = &hdp_v5_0_funcs;
2772                 break;
2773         case IP_VERSION(5, 2, 1):
2774                 adev->hdp.funcs = &hdp_v5_2_funcs;
2775                 break;
2776         case IP_VERSION(6, 0, 0):
2777         case IP_VERSION(6, 0, 1):
2778         case IP_VERSION(6, 1, 0):
2779                 adev->hdp.funcs = &hdp_v6_0_funcs;
2780                 break;
2781         case IP_VERSION(7, 0, 0):
2782                 adev->hdp.funcs = &hdp_v7_0_funcs;
2783                 break;
2784         default:
2785                 break;
2786         }
2787
2788         switch (amdgpu_ip_version(adev, DF_HWIP, 0)) {
2789         case IP_VERSION(3, 6, 0):
2790         case IP_VERSION(3, 6, 1):
2791         case IP_VERSION(3, 6, 2):
2792                 adev->df.funcs = &df_v3_6_funcs;
2793                 break;
2794         case IP_VERSION(2, 1, 0):
2795         case IP_VERSION(2, 1, 1):
2796         case IP_VERSION(2, 5, 0):
2797         case IP_VERSION(3, 5, 1):
2798         case IP_VERSION(3, 5, 2):
2799                 adev->df.funcs = &df_v1_7_funcs;
2800                 break;
2801         case IP_VERSION(4, 3, 0):
2802                 adev->df.funcs = &df_v4_3_funcs;
2803                 break;
2804         case IP_VERSION(4, 6, 2):
2805                 adev->df.funcs = &df_v4_6_2_funcs;
2806                 break;
2807         case IP_VERSION(4, 15, 0):
2808         case IP_VERSION(4, 15, 1):
2809                 adev->df.funcs = &df_v4_15_funcs;
2810                 break;
2811         default:
2812                 break;
2813         }
2814
2815         switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) {
2816         case IP_VERSION(9, 0, 0):
2817         case IP_VERSION(9, 0, 1):
2818         case IP_VERSION(10, 0, 0):
2819         case IP_VERSION(10, 0, 1):
2820         case IP_VERSION(10, 0, 2):
2821                 adev->smuio.funcs = &smuio_v9_0_funcs;
2822                 break;
2823         case IP_VERSION(11, 0, 0):
2824         case IP_VERSION(11, 0, 2):
2825         case IP_VERSION(11, 0, 3):
2826         case IP_VERSION(11, 0, 4):
2827         case IP_VERSION(11, 0, 7):
2828         case IP_VERSION(11, 0, 8):
2829                 adev->smuio.funcs = &smuio_v11_0_funcs;
2830                 break;
2831         case IP_VERSION(11, 0, 6):
2832         case IP_VERSION(11, 0, 10):
2833         case IP_VERSION(11, 0, 11):
2834         case IP_VERSION(11, 5, 0):
2835         case IP_VERSION(13, 0, 1):
2836         case IP_VERSION(13, 0, 9):
2837         case IP_VERSION(13, 0, 10):
2838                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2839                 break;
2840         case IP_VERSION(13, 0, 2):
2841                 adev->smuio.funcs = &smuio_v13_0_funcs;
2842                 break;
2843         case IP_VERSION(13, 0, 3):
2844                 adev->smuio.funcs = &smuio_v13_0_3_funcs;
2845                 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {
2846                         adev->flags |= AMD_IS_APU;
2847                 }
2848                 break;
2849         case IP_VERSION(13, 0, 6):
2850         case IP_VERSION(13, 0, 8):
2851         case IP_VERSION(14, 0, 0):
2852         case IP_VERSION(14, 0, 1):
2853                 adev->smuio.funcs = &smuio_v13_0_6_funcs;
2854                 break;
2855         case IP_VERSION(14, 0, 2):
2856                 adev->smuio.funcs = &smuio_v14_0_2_funcs;
2857                 break;
2858         default:
2859                 break;
2860         }
2861
2862         switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
2863         case IP_VERSION(6, 0, 0):
2864         case IP_VERSION(6, 0, 1):
2865         case IP_VERSION(6, 0, 2):
2866         case IP_VERSION(6, 0, 3):
2867                 adev->lsdma.funcs = &lsdma_v6_0_funcs;
2868                 break;
2869         case IP_VERSION(7, 0, 0):
2870         case IP_VERSION(7, 0, 1):
2871                 adev->lsdma.funcs = &lsdma_v7_0_funcs;
2872                 break;
2873         default:
2874                 break;
2875         }
2876
2877         r = amdgpu_discovery_set_common_ip_blocks(adev);
2878         if (r)
2879                 return r;
2880
2881         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
2882         if (r)
2883                 return r;
2884
2885         /* For SR-IOV, PSP needs to be initialized before IH */
2886         if (amdgpu_sriov_vf(adev)) {
2887                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2888                 if (r)
2889                         return r;
2890                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2891                 if (r)
2892                         return r;
2893         } else {
2894                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2895                 if (r)
2896                         return r;
2897
2898                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2899                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
2900                         if (r)
2901                                 return r;
2902                 }
2903         }
2904
2905         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2906                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2907                 if (r)
2908                         return r;
2909         }
2910
2911         r = amdgpu_discovery_set_display_ip_blocks(adev);
2912         if (r)
2913                 return r;
2914
2915         r = amdgpu_discovery_set_gc_ip_blocks(adev);
2916         if (r)
2917                 return r;
2918
2919         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2920         if (r)
2921                 return r;
2922
2923         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2924              !amdgpu_sriov_vf(adev)) ||
2925             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
2926                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2927                 if (r)
2928                         return r;
2929         }
2930
2931         r = amdgpu_discovery_set_mm_ip_blocks(adev);
2932         if (r)
2933                 return r;
2934
2935         r = amdgpu_discovery_set_mes_ip_blocks(adev);
2936         if (r)
2937                 return r;
2938
2939         r = amdgpu_discovery_set_vpe_ip_blocks(adev);
2940         if (r)
2941                 return r;
2942
2943         r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev);
2944         if (r)
2945                 return r;
2946
2947         r = amdgpu_discovery_set_isp_ip_blocks(adev);
2948         if (r)
2949                 return r;
2950         return 0;
2951 }
2952