drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.ac_power = true;
  72                 else
  73                         adev->pm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 /**
  81  * DOC: power_dpm_state
  82  *
  83  * The power_dpm_state file is a legacy interface and is only provided for
  84  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  85  * certain power related parameters.  The file power_dpm_state is used for this.
  86  * It accepts the following arguments:
  87  *
  88  * - battery
  89  *
  90  * - balanced
  91  *
  92  * - performance
  93  *
  94  * battery
  95  *
  96  * On older GPUs, the vbios provided a special power state for battery
  97  * operation.  Selecting battery switched to this state.  This is no
  98  * longer provided on newer GPUs so the option does nothing in that case.
  99  *
 100  * balanced
 101  *
 102  * On older GPUs, the vbios provided a special power state for balanced
 103  * operation.  Selecting balanced switched to this state.  This is no
 104  * longer provided on newer GPUs so the option does nothing in that case.
 105  *
 106  * performance
 107  *
 108  * On older GPUs, the vbios provided a special power state for performance
 109  * operation.  Selecting performance switched to this state.  This is no
 110  * longer provided on newer GPUs so the option does nothing in that case.
 111  *
 112  */
 113
 114 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 115                                     struct device_attribute *attr,
 116                                     char *buf)
 117 {
 118         struct drm_device *ddev = dev_get_drvdata(dev);
 119         struct amdgpu_device *adev = ddev->dev_private;
 120         enum amd_pm_state_type pm;
 121
 122         if (adev->powerplay.pp_funcs->get_current_power_state)
 123                 pm = amdgpu_dpm_get_current_power_state(adev);
 124         else
 125                 pm = adev->pm.dpm.user_state;
 126
 127         return snprintf(buf, PAGE_SIZE, "%s\n",
 128                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 129                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 130 }
 131
 132 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 133                                     struct device_attribute *attr,
 134                                     const char *buf,
 135                                     size_t count)
 136 {
 137         struct drm_device *ddev = dev_get_drvdata(dev);
 138         struct amdgpu_device *adev = ddev->dev_private;
 139         enum amd_pm_state_type  state;
 140
 141         if (strncmp("battery", buf, strlen("battery")) == 0)
 142                 state = POWER_STATE_TYPE_BATTERY;
 143         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 144                 state = POWER_STATE_TYPE_BALANCED;
 145         else if (strncmp("performance", buf, strlen("performance")) == 0)
 146                 state = POWER_STATE_TYPE_PERFORMANCE;
 147         else {
 148                 count = -EINVAL;
 149                 goto fail;
 150         }
 151
 152         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 153                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 154         } else {
 155                 mutex_lock(&adev->pm.mutex);
 156                 adev->pm.dpm.user_state = state;
 157                 mutex_unlock(&adev->pm.mutex);
 158
 159                 /* Can't set dpm state when the card is off */
 160                 if (!(adev->flags & AMD_IS_PX) ||
 161                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 162                         amdgpu_pm_compute_clocks(adev);
 163         }
 164 fail:
 165         return count;
 166 }
 167
 168
 169 /**
 170  * DOC: power_dpm_force_performance_level
 171  *
 172  * The amdgpu driver provides a sysfs API for adjusting certain power
 173  * related parameters.  The file power_dpm_force_performance_level is
 174  * used for this.  It accepts the following arguments:
 175  *
 176  * - auto
 177  *
 178  * - low
 179  *
 180  * - high
 181  *
 182  * - manual
 183  *
 184  * - profile_standard
 185  *
 186  * - profile_min_sclk
 187  *
 188  * - profile_min_mclk
 189  *
 190  * - profile_peak
 191  *
 192  * auto
 193  *
 194  * When auto is selected, the driver will attempt to dynamically select
 195  * the optimal power profile for current conditions in the driver.
 196  *
 197  * low
 198  *
 199  * When low is selected, the clocks are forced to the lowest power state.
 200  *
 201  * high
 202  *
 203  * When high is selected, the clocks are forced to the highest power state.
 204  *
 205  * manual
 206  *
 207  * When manual is selected, the user can manually adjust which power states
 208  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 209  * and pp_dpm_pcie files and adjust the power state transition heuristics
 210  * via the pp_power_profile_mode sysfs file.
 211  *
 212  * profile_standard
 213  * profile_min_sclk
 214  * profile_min_mclk
 215  * profile_peak
 216  *
 217  * When the profiling modes are selected, clock and power gating are
 218  * disabled and the clocks are set for different profiling cases. This
 219  * mode is recommended for profiling specific work loads where you do
 220  * not want clock or power gating for clock fluctuation to interfere
 221  * with your results. profile_standard sets the clocks to a fixed clock
 222  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 223  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 224  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 225  *
 226  */
 227
 228 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 229                                                 struct device_attribute *attr,
 230                                                                 char *buf)
 231 {
 232         struct drm_device *ddev = dev_get_drvdata(dev);
 233         struct amdgpu_device *adev = ddev->dev_private;
 234         enum amd_dpm_forced_level level = 0xff;
 235
 236         if  ((adev->flags & AMD_IS_PX) &&
 237              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 238                 return snprintf(buf, PAGE_SIZE, "off\n");
 239
 240         if (adev->powerplay.pp_funcs->get_performance_level)
 241                 level = amdgpu_dpm_get_performance_level(adev);
 242         else
 243                 level = adev->pm.dpm.forced_level;
 244
 245         return snprintf(buf, PAGE_SIZE, "%s\n",
 246                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 247                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 248                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 249                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 250                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 251                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 252                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 253                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 254                         "unknown");
 255 }
 256
 257 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 258                                                        struct device_attribute *attr,
 259                                                        const char *buf,
 260                                                        size_t count)
 261 {
 262         struct drm_device *ddev = dev_get_drvdata(dev);
 263         struct amdgpu_device *adev = ddev->dev_private;
 264         enum amd_dpm_forced_level level;
 265         enum amd_dpm_forced_level current_level = 0xff;
 266         int ret = 0;
 267
 268         /* Can't force performance level when the card is off */
 269         if  ((adev->flags & AMD_IS_PX) &&
 270              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 271                 return -EINVAL;
 272
 273         if (adev->powerplay.pp_funcs->get_performance_level)
 274                 current_level = amdgpu_dpm_get_performance_level(adev);
 275
 276         if (strncmp("low", buf, strlen("low")) == 0) {
 277                 level = AMD_DPM_FORCED_LEVEL_LOW;
 278         } else if (strncmp("high", buf, strlen("high")) == 0) {
 279                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 280         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 281                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 282         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 283                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 284         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 285                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 286         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 287                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 288         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 289                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 290         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 291                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 292         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 293                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 294         }  else {
 295                 count = -EINVAL;
 296                 goto fail;
 297         }
 298
 299         if (current_level == level)
 300                 return count;
 301
 302         if (adev->powerplay.pp_funcs->force_performance_level) {
 303                 mutex_lock(&adev->pm.mutex);
 304                 if (adev->pm.dpm.thermal_active) {
 305                         count = -EINVAL;
 306                         mutex_unlock(&adev->pm.mutex);
 307                         goto fail;
 308                 }
 309                 ret = amdgpu_dpm_force_performance_level(adev, level);
 310                 if (ret)
 311                         count = -EINVAL;
 312                 else
 313                         adev->pm.dpm.forced_level = level;
 314                 mutex_unlock(&adev->pm.mutex);
 315         }
 316
 317 fail:
 318         return count;
 319 }
 320
 321 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 322                 struct device_attribute *attr,
 323                 char *buf)
 324 {
 325         struct drm_device *ddev = dev_get_drvdata(dev);
 326         struct amdgpu_device *adev = ddev->dev_private;
 327         struct pp_states_info data;
 328         int i, buf_len;
 329
 330         if (adev->powerplay.pp_funcs->get_pp_num_states)
 331                 amdgpu_dpm_get_pp_num_states(adev, &data);
 332
 333         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 334         for (i = 0; i < data.nums; i++)
 335                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 336                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 337                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 338                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 339                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 340
 341         return buf_len;
 342 }
 343
 344 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 345                 struct device_attribute *attr,
 346                 char *buf)
 347 {
 348         struct drm_device *ddev = dev_get_drvdata(dev);
 349         struct amdgpu_device *adev = ddev->dev_private;
 350         struct pp_states_info data;
 351         enum amd_pm_state_type pm = 0;
 352         int i = 0;
 353
 354         if (adev->powerplay.pp_funcs->get_current_power_state
 355                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 356                 pm = amdgpu_dpm_get_current_power_state(adev);
 357                 amdgpu_dpm_get_pp_num_states(adev, &data);
 358
 359                 for (i = 0; i < data.nums; i++) {
 360                         if (pm == data.states[i])
 361                                 break;
 362                 }
 363
 364                 if (i == data.nums)
 365                         i = -EINVAL;
 366         }
 367
 368         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 369 }
 370
 371 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 372                 struct device_attribute *attr,
 373                 char *buf)
 374 {
 375         struct drm_device *ddev = dev_get_drvdata(dev);
 376         struct amdgpu_device *adev = ddev->dev_private;
 377
 378         if (adev->pp_force_state_enabled)
 379                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 380         else
 381                 return snprintf(buf, PAGE_SIZE, "\n");
 382 }
 383
 384 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 385                 struct device_attribute *attr,
 386                 const char *buf,
 387                 size_t count)
 388 {
 389         struct drm_device *ddev = dev_get_drvdata(dev);
 390         struct amdgpu_device *adev = ddev->dev_private;
 391         enum amd_pm_state_type state = 0;
 392         unsigned long idx;
 393         int ret;
 394
 395         if (strlen(buf) == 1)
 396                 adev->pp_force_state_enabled = false;
 397         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 398                         adev->powerplay.pp_funcs->get_pp_num_states) {
 399                 struct pp_states_info data;
 400
 401                 ret = kstrtoul(buf, 0, &idx);
 402                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 403                         count = -EINVAL;
 404                         goto fail;
 405                 }
 406
 407                 amdgpu_dpm_get_pp_num_states(adev, &data);
 408                 state = data.states[idx];
 409                 /* only set user selected power states */
 410                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 411                     state != POWER_STATE_TYPE_DEFAULT) {
 412                         amdgpu_dpm_dispatch_task(adev,
 413                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 414                         adev->pp_force_state_enabled = true;
 415                 }
 416         }
 417 fail:
 418         return count;
 419 }
 420
 421 /**
 422  * DOC: pp_table
 423  *
 424  * The amdgpu driver provides a sysfs API for uploading new powerplay
 425  * tables.  The file pp_table is used for this.  Reading the file
 426  * will dump the current power play table.  Writing to the file
 427  * will attempt to upload a new powerplay table and re-initialize
 428  * powerplay using that new table.
 429  *
 430  */
 431
 432 static ssize_t amdgpu_get_pp_table(struct device *dev,
 433                 struct device_attribute *attr,
 434                 char *buf)
 435 {
 436         struct drm_device *ddev = dev_get_drvdata(dev);
 437         struct amdgpu_device *adev = ddev->dev_private;
 438         char *table = NULL;
 439         int size;
 440
 441         if (adev->powerplay.pp_funcs->get_pp_table)
 442                 size = amdgpu_dpm_get_pp_table(adev, &table);
 443         else
 444                 return 0;
 445
 446         if (size >= PAGE_SIZE)
 447                 size = PAGE_SIZE - 1;
 448
 449         memcpy(buf, table, size);
 450
 451         return size;
 452 }
 453
 454 static ssize_t amdgpu_set_pp_table(struct device *dev,
 455                 struct device_attribute *attr,
 456                 const char *buf,
 457                 size_t count)
 458 {
 459         struct drm_device *ddev = dev_get_drvdata(dev);
 460         struct amdgpu_device *adev = ddev->dev_private;
 461
 462         if (adev->powerplay.pp_funcs->set_pp_table)
 463                 amdgpu_dpm_set_pp_table(adev, buf, count);
 464
 465         return count;
 466 }
 467
 468 /**
 469  * DOC: pp_od_clk_voltage
 470  *
 471  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 472  * in each power level within a power state.  The pp_od_clk_voltage is used for
 473  * this.
 474  *
 475  * Reading the file will display:
 476  *
 477  * - a list of engine clock levels and voltages labeled OD_SCLK
 478  *
 479  * - a list of memory clock levels and voltages labeled OD_MCLK
 480  *
 481  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 482  *
 483  * To manually adjust these settings, first select manual using
 484  * power_dpm_force_performance_level. Enter a new value for each
 485  * level by writing a string that contains "s/m level clock voltage" to
 486  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 487  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 488  * 810 mV.  When you have edited all of the states as needed, write
 489  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 490  * default power levels, write "r" (reset) to the file to reset them.
 491  *
 492  */
 493
 494 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 495                 struct device_attribute *attr,
 496                 const char *buf,
 497                 size_t count)
 498 {
 499         struct drm_device *ddev = dev_get_drvdata(dev);
 500         struct amdgpu_device *adev = ddev->dev_private;
 501         int ret;
 502         uint32_t parameter_size = 0;
 503         long parameter[64];
 504         char buf_cpy[128];
 505         char *tmp_str;
 506         char *sub_str;
 507         const char delimiter[3] = {' ', '\n', '\0'};
 508         uint32_t type;
 509
 510         if (count > 127)
 511                 return -EINVAL;
 512
 513         if (*buf == 's')
 514                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 515         else if (*buf == 'm')
 516                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 517         else if(*buf == 'r')
 518                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 519         else if (*buf == 'c')
 520                 type = PP_OD_COMMIT_DPM_TABLE;
 521         else
 522                 return -EINVAL;
 523
 524         memcpy(buf_cpy, buf, count+1);
 525
 526         tmp_str = buf_cpy;
 527
 528         while (isspace(*++tmp_str));
 529
 530         while (tmp_str[0]) {
 531                 sub_str = strsep(&tmp_str, delimiter);
 532                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 533                 if (ret)
 534                         return -EINVAL;
 535                 parameter_size++;
 536
 537                 while (isspace(*tmp_str))
 538                         tmp_str++;
 539         }
 540
 541         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 542                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 543                                                 parameter, parameter_size);
 544
 545         if (ret)
 546                 return -EINVAL;
 547
 548         if (type == PP_OD_COMMIT_DPM_TABLE) {
 549                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 550                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 551                         return count;
 552                 } else {
 553                         return -EINVAL;
 554                 }
 555         }
 556
 557         return count;
 558 }
 559
 560 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 561                 struct device_attribute *attr,
 562                 char *buf)
 563 {
 564         struct drm_device *ddev = dev_get_drvdata(dev);
 565         struct amdgpu_device *adev = ddev->dev_private;
 566         uint32_t size = 0;
 567
 568         if (adev->powerplay.pp_funcs->print_clock_levels) {
 569                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 570                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 571                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 572                 return size;
 573         } else {
 574                 return snprintf(buf, PAGE_SIZE, "\n");
 575         }
 576
 577 }
 578
 579 /**
 580  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
 581  *
 582  * The amdgpu driver provides a sysfs API for adjusting what power levels
 583  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 584  * and pp_dpm_pcie are used for this.
 585  *
 586  * Reading back the files will show you the available power levels within
 587  * the power state and the clock information for those levels.
 588  *
 589  * To manually adjust these states, first select manual using
 590  * power_dpm_force_performance_level.
 591  * Secondly,Enter a new value for each level by inputing a string that
 592  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 593  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 594  */
 595
 596 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 597                 struct device_attribute *attr,
 598                 char *buf)
 599 {
 600         struct drm_device *ddev = dev_get_drvdata(dev);
 601         struct amdgpu_device *adev = ddev->dev_private;
 602
 603         if (adev->powerplay.pp_funcs->print_clock_levels)
 604                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 605         else
 606                 return snprintf(buf, PAGE_SIZE, "\n");
 607 }
 608
 609 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 610                 struct device_attribute *attr,
 611                 const char *buf,
 612                 size_t count)
 613 {
 614         struct drm_device *ddev = dev_get_drvdata(dev);
 615         struct amdgpu_device *adev = ddev->dev_private;
 616         int ret;
 617         long level;
 618         uint32_t mask = 0;
 619         char *sub_str = NULL;
 620         char *tmp;
 621         char buf_cpy[count];
 622         const char delimiter[3] = {' ', '\n', '\0'};
 623
 624         memcpy(buf_cpy, buf, count+1);
 625         tmp = buf_cpy;
 626         while (tmp[0]) {
 627                 sub_str =  strsep(&tmp, delimiter);
 628                 if (strlen(sub_str)) {
 629                         ret = kstrtol(sub_str, 0, &level);
 630
 631                         if (ret) {
 632                                 count = -EINVAL;
 633                                 goto fail;
 634                         }
 635                         mask |= 1 << level;
 636                 } else
 637                         break;
 638         }
 639         if (adev->powerplay.pp_funcs->force_clock_level)
 640                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 641
 642 fail:
 643         return count;
 644 }
 645
 646 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 647                 struct device_attribute *attr,
 648                 char *buf)
 649 {
 650         struct drm_device *ddev = dev_get_drvdata(dev);
 651         struct amdgpu_device *adev = ddev->dev_private;
 652
 653         if (adev->powerplay.pp_funcs->print_clock_levels)
 654                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 655         else
 656                 return snprintf(buf, PAGE_SIZE, "\n");
 657 }
 658
 659 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 660                 struct device_attribute *attr,
 661                 const char *buf,
 662                 size_t count)
 663 {
 664         struct drm_device *ddev = dev_get_drvdata(dev);
 665         struct amdgpu_device *adev = ddev->dev_private;
 666         int ret;
 667         long level;
 668         uint32_t mask = 0;
 669         char *sub_str = NULL;
 670         char *tmp;
 671         char buf_cpy[count];
 672         const char delimiter[3] = {' ', '\n', '\0'};
 673
 674         memcpy(buf_cpy, buf, count+1);
 675         tmp = buf_cpy;
 676         while (tmp[0]) {
 677                 sub_str =  strsep(&tmp, delimiter);
 678                 if (strlen(sub_str)) {
 679                         ret = kstrtol(sub_str, 0, &level);
 680
 681                         if (ret) {
 682                                 count = -EINVAL;
 683                                 goto fail;
 684                         }
 685                         mask |= 1 << level;
 686                 } else
 687                         break;
 688         }
 689         if (adev->powerplay.pp_funcs->force_clock_level)
 690                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 691
 692 fail:
 693         return count;
 694 }
 695
 696 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 697                 struct device_attribute *attr,
 698                 char *buf)
 699 {
 700         struct drm_device *ddev = dev_get_drvdata(dev);
 701         struct amdgpu_device *adev = ddev->dev_private;
 702
 703         if (adev->powerplay.pp_funcs->print_clock_levels)
 704                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 705         else
 706                 return snprintf(buf, PAGE_SIZE, "\n");
 707 }
 708
 709 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 710                 struct device_attribute *attr,
 711                 const char *buf,
 712                 size_t count)
 713 {
 714         struct drm_device *ddev = dev_get_drvdata(dev);
 715         struct amdgpu_device *adev = ddev->dev_private;
 716         int ret;
 717         long level;
 718         uint32_t mask = 0;
 719         char *sub_str = NULL;
 720         char *tmp;
 721         char buf_cpy[count];
 722         const char delimiter[3] = {' ', '\n', '\0'};
 723
 724         memcpy(buf_cpy, buf, count+1);
 725         tmp = buf_cpy;
 726
 727         while (tmp[0]) {
 728                 sub_str =  strsep(&tmp, delimiter);
 729                 if (strlen(sub_str)) {
 730                         ret = kstrtol(sub_str, 0, &level);
 731
 732                         if (ret) {
 733                                 count = -EINVAL;
 734                                 goto fail;
 735                         }
 736                         mask |= 1 << level;
 737                 } else
 738                         break;
 739         }
 740         if (adev->powerplay.pp_funcs->force_clock_level)
 741                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 742
 743 fail:
 744         return count;
 745 }
 746
 747 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 748                 struct device_attribute *attr,
 749                 char *buf)
 750 {
 751         struct drm_device *ddev = dev_get_drvdata(dev);
 752         struct amdgpu_device *adev = ddev->dev_private;
 753         uint32_t value = 0;
 754
 755         if (adev->powerplay.pp_funcs->get_sclk_od)
 756                 value = amdgpu_dpm_get_sclk_od(adev);
 757
 758         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 759 }
 760
 761 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 762                 struct device_attribute *attr,
 763                 const char *buf,
 764                 size_t count)
 765 {
 766         struct drm_device *ddev = dev_get_drvdata(dev);
 767         struct amdgpu_device *adev = ddev->dev_private;
 768         int ret;
 769         long int value;
 770
 771         ret = kstrtol(buf, 0, &value);
 772
 773         if (ret) {
 774                 count = -EINVAL;
 775                 goto fail;
 776         }
 777         if (adev->powerplay.pp_funcs->set_sclk_od)
 778                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 779
 780         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 781                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 782         } else {
 783                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 784                 amdgpu_pm_compute_clocks(adev);
 785         }
 786
 787 fail:
 788         return count;
 789 }
 790
 791 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 792                 struct device_attribute *attr,
 793                 char *buf)
 794 {
 795         struct drm_device *ddev = dev_get_drvdata(dev);
 796         struct amdgpu_device *adev = ddev->dev_private;
 797         uint32_t value = 0;
 798
 799         if (adev->powerplay.pp_funcs->get_mclk_od)
 800                 value = amdgpu_dpm_get_mclk_od(adev);
 801
 802         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 803 }
 804
 805 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 806                 struct device_attribute *attr,
 807                 const char *buf,
 808                 size_t count)
 809 {
 810         struct drm_device *ddev = dev_get_drvdata(dev);
 811         struct amdgpu_device *adev = ddev->dev_private;
 812         int ret;
 813         long int value;
 814
 815         ret = kstrtol(buf, 0, &value);
 816
 817         if (ret) {
 818                 count = -EINVAL;
 819                 goto fail;
 820         }
 821         if (adev->powerplay.pp_funcs->set_mclk_od)
 822                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 823
 824         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 825                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 826         } else {
 827                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 828                 amdgpu_pm_compute_clocks(adev);
 829         }
 830
 831 fail:
 832         return count;
 833 }
 834
 835 /**
 836  * DOC: pp_power_profile_mode
 837  *
 838  * The amdgpu driver provides a sysfs API for adjusting the heuristics
 839  * related to switching between power levels in a power state.  The file
 840  * pp_power_profile_mode is used for this.
 841  *
 842  * Reading this file outputs a list of all of the predefined power profiles
 843  * and the relevant heuristics settings for that profile.
 844  *
 845  * To select a profile or create a custom profile, first select manual using
 846  * power_dpm_force_performance_level.  Writing the number of a predefined
 847  * profile to pp_power_profile_mode will enable those heuristics.  To
 848  * create a custom set of heuristics, write a string of numbers to the file
 849  * starting with the number of the custom profile along with a setting
 850  * for each heuristic parameter.  Due to differences across asic families
 851  * the heuristic parameters vary from family to family.
 852  *
 853  */
 854
 855 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 856                 struct device_attribute *attr,
 857                 char *buf)
 858 {
 859         struct drm_device *ddev = dev_get_drvdata(dev);
 860         struct amdgpu_device *adev = ddev->dev_private;
 861
 862         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 863                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 864
 865         return snprintf(buf, PAGE_SIZE, "\n");
 866 }
 867
 868
 869 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 870                 struct device_attribute *attr,
 871                 const char *buf,
 872                 size_t count)
 873 {
 874         int ret = 0xff;
 875         struct drm_device *ddev = dev_get_drvdata(dev);
 876         struct amdgpu_device *adev = ddev->dev_private;
 877         uint32_t parameter_size = 0;
 878         long parameter[64];
 879         char *sub_str, buf_cpy[128];
 880         char *tmp_str;
 881         uint32_t i = 0;
 882         char tmp[2];
 883         long int profile_mode = 0;
 884         const char delimiter[3] = {' ', '\n', '\0'};
 885
 886         tmp[0] = *(buf);
 887         tmp[1] = '\0';
 888         ret = kstrtol(tmp, 0, &profile_mode);
 889         if (ret)
 890                 goto fail;
 891
 892         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 893                 if (count < 2 || count > 127)
 894                         return -EINVAL;
 895                 while (isspace(*++buf))
 896                         i++;
 897                 memcpy(buf_cpy, buf, count-i);
 898                 tmp_str = buf_cpy;
 899                 while (tmp_str[0]) {
 900                         sub_str = strsep(&tmp_str, delimiter);
 901                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 902                         if (ret) {
 903                                 count = -EINVAL;
 904                                 goto fail;
 905                         }
 906                         parameter_size++;
 907                         while (isspace(*tmp_str))
 908                                 tmp_str++;
 909                 }
 910         }
 911         parameter[parameter_size] = profile_mode;
 912         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 913                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 914
 915         if (!ret)
 916                 return count;
 917 fail:
 918         return -EINVAL;
 919 }
 920
 921 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 922 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 923                    amdgpu_get_dpm_forced_performance_level,
 924                    amdgpu_set_dpm_forced_performance_level);
 925 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 926 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 927 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 928                 amdgpu_get_pp_force_state,
 929                 amdgpu_set_pp_force_state);
 930 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 931                 amdgpu_get_pp_table,
 932                 amdgpu_set_pp_table);
 933 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 934                 amdgpu_get_pp_dpm_sclk,
 935                 amdgpu_set_pp_dpm_sclk);
 936 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 937                 amdgpu_get_pp_dpm_mclk,
 938                 amdgpu_set_pp_dpm_mclk);
 939 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 940                 amdgpu_get_pp_dpm_pcie,
 941                 amdgpu_set_pp_dpm_pcie);
 942 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 943                 amdgpu_get_pp_sclk_od,
 944                 amdgpu_set_pp_sclk_od);
 945 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 946                 amdgpu_get_pp_mclk_od,
 947                 amdgpu_set_pp_mclk_od);
 948 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 949                 amdgpu_get_pp_power_profile_mode,
 950                 amdgpu_set_pp_power_profile_mode);
 951 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 952                 amdgpu_get_pp_od_clk_voltage,
 953                 amdgpu_set_pp_od_clk_voltage);
 954
 955 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 956                                       struct device_attribute *attr,
 957                                       char *buf)
 958 {
 959         struct amdgpu_device *adev = dev_get_drvdata(dev);
 960         struct drm_device *ddev = adev->ddev;
 961         int r, temp, size = sizeof(temp);
 962
 963         /* Can't get temperature when the card is off */
 964         if  ((adev->flags & AMD_IS_PX) &&
 965              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 966                 return -EINVAL;
 967
 968         /* sanity check PP is enabled */
 969         if (!(adev->powerplay.pp_funcs &&
 970               adev->powerplay.pp_funcs->read_sensor))
 971                 return -EINVAL;
 972
 973         /* get the temperature */
 974         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 975                                    (void *)&temp, &size);
 976         if (r)
 977                 return r;
 978
 979         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 980 }
 981
 982 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 983                                              struct device_attribute *attr,
 984                                              char *buf)
 985 {
 986         struct amdgpu_device *adev = dev_get_drvdata(dev);
 987         int hyst = to_sensor_dev_attr(attr)->index;
 988         int temp;
 989
 990         if (hyst)
 991                 temp = adev->pm.dpm.thermal.min_temp;
 992         else
 993                 temp = adev->pm.dpm.thermal.max_temp;
 994
 995         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 996 }
 997
 998 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 999                                             struct device_attribute *attr,
1000                                             char *buf)
1001 {
1002         struct amdgpu_device *adev = dev_get_drvdata(dev);
1003         u32 pwm_mode = 0;
1004
1005         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1006                 return -EINVAL;
1007
1008         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1009
1010         return sprintf(buf, "%i\n", pwm_mode);
1011 }
1012
1013 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1014                                             struct device_attribute *attr,
1015                                             const char *buf,
1016                                             size_t count)
1017 {
1018         struct amdgpu_device *adev = dev_get_drvdata(dev);
1019         int err;
1020         int value;
1021
1022         /* Can't adjust fan when the card is off */
1023         if  ((adev->flags & AMD_IS_PX) &&
1024              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1025                 return -EINVAL;
1026
1027         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1028                 return -EINVAL;
1029
1030         err = kstrtoint(buf, 10, &value);
1031         if (err)
1032                 return err;
1033
1034         amdgpu_dpm_set_fan_control_mode(adev, value);
1035
1036         return count;
1037 }
1038
1039 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1040                                          struct device_attribute *attr,
1041                                          char *buf)
1042 {
1043         return sprintf(buf, "%i\n", 0);
1044 }
1045
1046 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1047                                          struct device_attribute *attr,
1048                                          char *buf)
1049 {
1050         return sprintf(buf, "%i\n", 255);
1051 }
1052
1053 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1054                                      struct device_attribute *attr,
1055                                      const char *buf, size_t count)
1056 {
1057         struct amdgpu_device *adev = dev_get_drvdata(dev);
1058         int err;
1059         u32 value;
1060
1061         /* Can't adjust fan when the card is off */
1062         if  ((adev->flags & AMD_IS_PX) &&
1063              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1064                 return -EINVAL;
1065
1066         err = kstrtou32(buf, 10, &value);
1067         if (err)
1068                 return err;
1069
1070         value = (value * 100) / 255;
1071
1072         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1073                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1074                 if (err)
1075                         return err;
1076         }
1077
1078         return count;
1079 }
1080
1081 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1082                                      struct device_attribute *attr,
1083                                      char *buf)
1084 {
1085         struct amdgpu_device *adev = dev_get_drvdata(dev);
1086         int err;
1087         u32 speed = 0;
1088
1089         /* Can't adjust fan when the card is off */
1090         if  ((adev->flags & AMD_IS_PX) &&
1091              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1092                 return -EINVAL;
1093
1094         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1095                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1096                 if (err)
1097                         return err;
1098         }
1099
1100         speed = (speed * 255) / 100;
1101
1102         return sprintf(buf, "%i\n", speed);
1103 }
1104
1105 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1106                                            struct device_attribute *attr,
1107                                            char *buf)
1108 {
1109         struct amdgpu_device *adev = dev_get_drvdata(dev);
1110         int err;
1111         u32 speed = 0;
1112
1113         /* Can't adjust fan when the card is off */
1114         if  ((adev->flags & AMD_IS_PX) &&
1115              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1116                 return -EINVAL;
1117
1118         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1119                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1120                 if (err)
1121                         return err;
1122         }
1123
1124         return sprintf(buf, "%i\n", speed);
1125 }
1126
1127 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1128                                         struct device_attribute *attr,
1129                                         char *buf)
1130 {
1131         struct amdgpu_device *adev = dev_get_drvdata(dev);
1132         struct drm_device *ddev = adev->ddev;
1133         u32 vddgfx;
1134         int r, size = sizeof(vddgfx);
1135
1136         /* Can't get voltage when the card is off */
1137         if  ((adev->flags & AMD_IS_PX) &&
1138              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1139                 return -EINVAL;
1140
1141         /* sanity check PP is enabled */
1142         if (!(adev->powerplay.pp_funcs &&
1143               adev->powerplay.pp_funcs->read_sensor))
1144               return -EINVAL;
1145
1146         /* get the voltage */
1147         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1148                                    (void *)&vddgfx, &size);
1149         if (r)
1150                 return r;
1151
1152         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1153 }
1154
1155 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1156                                               struct device_attribute *attr,
1157                                               char *buf)
1158 {
1159         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1160 }
1161
1162 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1163                                        struct device_attribute *attr,
1164                                        char *buf)
1165 {
1166         struct amdgpu_device *adev = dev_get_drvdata(dev);
1167         struct drm_device *ddev = adev->ddev;
1168         u32 vddnb;
1169         int r, size = sizeof(vddnb);
1170
1171         /* only APUs have vddnb */
1172         if  (adev->flags & AMD_IS_APU)
1173                 return -EINVAL;
1174
1175         /* Can't get voltage when the card is off */
1176         if  ((adev->flags & AMD_IS_PX) &&
1177              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1178                 return -EINVAL;
1179
1180         /* sanity check PP is enabled */
1181         if (!(adev->powerplay.pp_funcs &&
1182               adev->powerplay.pp_funcs->read_sensor))
1183               return -EINVAL;
1184
1185         /* get the voltage */
1186         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1187                                    (void *)&vddnb, &size);
1188         if (r)
1189                 return r;
1190
1191         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1192 }
1193
1194 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1195                                               struct device_attribute *attr,
1196                                               char *buf)
1197 {
1198         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1199 }
1200
1201 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1202                                            struct device_attribute *attr,
1203                                            char *buf)
1204 {
1205         struct amdgpu_device *adev = dev_get_drvdata(dev);
1206         struct drm_device *ddev = adev->ddev;
1207         u32 query = 0;
1208         int r, size = sizeof(u32);
1209         unsigned uw;
1210
1211         /* Can't get power when the card is off */
1212         if  ((adev->flags & AMD_IS_PX) &&
1213              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1214                 return -EINVAL;
1215
1216         /* sanity check PP is enabled */
1217         if (!(adev->powerplay.pp_funcs &&
1218               adev->powerplay.pp_funcs->read_sensor))
1219               return -EINVAL;
1220
1221         /* get the voltage */
1222         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1223                                    (void *)&query, &size);
1224         if (r)
1225                 return r;
1226
1227         /* convert to microwatts */
1228         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1229
1230         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1231 }
1232
1233 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1234                                          struct device_attribute *attr,
1235                                          char *buf)
1236 {
1237         return sprintf(buf, "%i\n", 0);
1238 }
1239
1240 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1241                                          struct device_attribute *attr,
1242                                          char *buf)
1243 {
1244         struct amdgpu_device *adev = dev_get_drvdata(dev);
1245         uint32_t limit = 0;
1246
1247         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1248                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1249                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1250         } else {
1251                 return snprintf(buf, PAGE_SIZE, "\n");
1252         }
1253 }
1254
1255 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1256                                          struct device_attribute *attr,
1257                                          char *buf)
1258 {
1259         struct amdgpu_device *adev = dev_get_drvdata(dev);
1260         uint32_t limit = 0;
1261
1262         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1263                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1264                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1265         } else {
1266                 return snprintf(buf, PAGE_SIZE, "\n");
1267         }
1268 }
1269
1270
1271 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1272                 struct device_attribute *attr,
1273                 const char *buf,
1274                 size_t count)
1275 {
1276         struct amdgpu_device *adev = dev_get_drvdata(dev);
1277         int err;
1278         u32 value;
1279
1280         err = kstrtou32(buf, 10, &value);
1281         if (err)
1282                 return err;
1283
1284         value = value / 1000000; /* convert to Watt */
1285         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1286                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1287                 if (err)
1288                         return err;
1289         } else {
1290                 return -EINVAL;
1291         }
1292
1293         return count;
1294 }
1295
1296
1297 /**
1298  * DOC: hwmon
1299  *
1300  * The amdgpu driver exposes the following sensor interfaces:
1301  *
1302  * - GPU temperature (via the on-die sensor)
1303  *
1304  * - GPU voltage
1305  *
1306  * - Northbridge voltage (APUs only)
1307  *
1308  * - GPU power
1309  *
1310  * - GPU fan
1311  *
1312  * hwmon interfaces for GPU temperature:
1313  *
1314  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1315  *
1316  * - temp1_crit: temperature critical max value in millidegrees Celsius
1317  *
1318  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1319  *
1320  * hwmon interfaces for GPU voltage:
1321  *
1322  * - in0_input: the voltage on the GPU in millivolts
1323  *
1324  * - in1_input: the voltage on the Northbridge in millivolts
1325  *
1326  * hwmon interfaces for GPU power:
1327  *
1328  * - power1_average: average power used by the GPU in microWatts
1329  *
1330  * - power1_cap_min: minimum cap supported in microWatts
1331  *
1332  * - power1_cap_max: maximum cap supported in microWatts
1333  *
1334  * - power1_cap: selected power cap in microWatts
1335  *
1336  * hwmon interfaces for GPU fan:
1337  *
1338  * - pwm1: pulse width modulation fan level (0-255)
1339  *
1340  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1341  *
1342  * - pwm1_min: pulse width modulation fan control minimum level (0)
1343  *
1344  * - pwm1_max: pulse width modulation fan control maximum level (255)
1345  *
1346  * - fan1_input: fan speed in RPM
1347  *
1348  * You can use hwmon tools like sensors to view this information on your system.
1349  *
1350  */
1351
1352 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1353 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1354 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1355 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1356 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1357 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1358 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1359 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1360 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1361 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1362 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1363 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1364 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1365 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1366 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1367 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1368
1369 static struct attribute *hwmon_attributes[] = {
1370         &sensor_dev_attr_temp1_input.dev_attr.attr,
1371         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1372         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1373         &sensor_dev_attr_pwm1.dev_attr.attr,
1374         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1375         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1376         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1377         &sensor_dev_attr_fan1_input.dev_attr.attr,
1378         &sensor_dev_attr_in0_input.dev_attr.attr,
1379         &sensor_dev_attr_in0_label.dev_attr.attr,
1380         &sensor_dev_attr_in1_input.dev_attr.attr,
1381         &sensor_dev_attr_in1_label.dev_attr.attr,
1382         &sensor_dev_attr_power1_average.dev_attr.attr,
1383         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1384         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1385         &sensor_dev_attr_power1_cap.dev_attr.attr,
1386         NULL
1387 };
1388
1389 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1390                                         struct attribute *attr, int index)
1391 {
1392         struct device *dev = kobj_to_dev(kobj);
1393         struct amdgpu_device *adev = dev_get_drvdata(dev);
1394         umode_t effective_mode = attr->mode;
1395
1396
1397         /* Skip fan attributes if fan is not present */
1398         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1399             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1400             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1401             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1402             attr == &sensor_dev_attr_fan1_input.dev_attr.attr))
1403                 return 0;
1404
1405         /* Skip limit attributes if DPM is not enabled */
1406         if (!adev->pm.dpm_enabled &&
1407             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1408              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1409              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1410              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1411              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1412              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1413                 return 0;
1414
1415         /* mask fan attributes if we have no bindings for this asic to expose */
1416         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1417              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1418             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1419              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1420                 effective_mode &= ~S_IRUGO;
1421
1422         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1423              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1424             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1425              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1426                 effective_mode &= ~S_IWUSR;
1427
1428         if ((adev->flags & AMD_IS_APU) &&
1429             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1430              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1431              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1432                 return 0;
1433
1434         /* hide max/min values if we can't both query and manage the fan */
1435         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1436              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1437             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1438              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1439                 return 0;
1440
1441         /* only APUs have vddnb */
1442         if (!(adev->flags & AMD_IS_APU) &&
1443             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1444              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1445                 return 0;
1446
1447         return effective_mode;
1448 }
1449
1450 static const struct attribute_group hwmon_attrgroup = {
1451         .attrs = hwmon_attributes,
1452         .is_visible = hwmon_attributes_visible,
1453 };
1454
1455 static const struct attribute_group *hwmon_groups[] = {
1456         &hwmon_attrgroup,
1457         NULL
1458 };
1459
1460 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1461 {
1462         struct amdgpu_device *adev =
1463                 container_of(work, struct amdgpu_device,
1464                              pm.dpm.thermal.work);
1465         /* switch to the thermal state */
1466         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1467         int temp, size = sizeof(temp);
1468
1469         if (!adev->pm.dpm_enabled)
1470                 return;
1471
1472         if (adev->powerplay.pp_funcs &&
1473             adev->powerplay.pp_funcs->read_sensor &&
1474             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1475                                     (void *)&temp, &size)) {
1476                 if (temp < adev->pm.dpm.thermal.min_temp)
1477                         /* switch back the user state */
1478                         dpm_state = adev->pm.dpm.user_state;
1479         } else {
1480                 if (adev->pm.dpm.thermal.high_to_low)
1481                         /* switch back the user state */
1482                         dpm_state = adev->pm.dpm.user_state;
1483         }
1484         mutex_lock(&adev->pm.mutex);
1485         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1486                 adev->pm.dpm.thermal_active = true;
1487         else
1488                 adev->pm.dpm.thermal_active = false;
1489         adev->pm.dpm.state = dpm_state;
1490         mutex_unlock(&adev->pm.mutex);
1491
1492         amdgpu_pm_compute_clocks(adev);
1493 }
1494
1495 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1496                                                      enum amd_pm_state_type dpm_state)
1497 {
1498         int i;
1499         struct amdgpu_ps *ps;
1500         u32 ui_class;
1501         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1502                 true : false;
1503
1504         /* check if the vblank period is too short to adjust the mclk */
1505         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1506                 if (amdgpu_dpm_vblank_too_short(adev))
1507                         single_display = false;
1508         }
1509
1510         /* certain older asics have a separare 3D performance state,
1511          * so try that first if the user selected performance
1512          */
1513         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1514                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1515         /* balanced states don't exist at the moment */
1516         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1517                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1518
1519 restart_search:
1520         /* Pick the best power state based on current conditions */
1521         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1522                 ps = &adev->pm.dpm.ps[i];
1523                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1524                 switch (dpm_state) {
1525                 /* user states */
1526                 case POWER_STATE_TYPE_BATTERY:
1527                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1528                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1529                                         if (single_display)
1530                                                 return ps;
1531                                 } else
1532                                         return ps;
1533                         }
1534                         break;
1535                 case POWER_STATE_TYPE_BALANCED:
1536                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1537                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1538                                         if (single_display)
1539                                                 return ps;
1540                                 } else
1541                                         return ps;
1542                         }
1543                         break;
1544                 case POWER_STATE_TYPE_PERFORMANCE:
1545                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1546                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1547                                         if (single_display)
1548                                                 return ps;
1549                                 } else
1550                                         return ps;
1551                         }
1552                         break;
1553                 /* internal states */
1554                 case POWER_STATE_TYPE_INTERNAL_UVD:
1555                         if (adev->pm.dpm.uvd_ps)
1556                                 return adev->pm.dpm.uvd_ps;
1557                         else
1558                                 break;
1559                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1560                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1561                                 return ps;
1562                         break;
1563                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1564                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1565                                 return ps;
1566                         break;
1567                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1568                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1569                                 return ps;
1570                         break;
1571                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1572                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1573                                 return ps;
1574                         break;
1575                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1576                         return adev->pm.dpm.boot_ps;
1577                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1578                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1579                                 return ps;
1580                         break;
1581                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1582                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1583                                 return ps;
1584                         break;
1585                 case POWER_STATE_TYPE_INTERNAL_ULV:
1586                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1587                                 return ps;
1588                         break;
1589                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1590                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1591                                 return ps;
1592                         break;
1593                 default:
1594                         break;
1595                 }
1596         }
1597         /* use a fallback state if we didn't match */
1598         switch (dpm_state) {
1599         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1600                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1601                 goto restart_search;
1602         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1603         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1604         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1605                 if (adev->pm.dpm.uvd_ps) {
1606                         return adev->pm.dpm.uvd_ps;
1607                 } else {
1608                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1609                         goto restart_search;
1610                 }
1611         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1612                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1613                 goto restart_search;
1614         case POWER_STATE_TYPE_INTERNAL_ACPI:
1615                 dpm_state = POWER_STATE_TYPE_BATTERY;
1616                 goto restart_search;
1617         case POWER_STATE_TYPE_BATTERY:
1618         case POWER_STATE_TYPE_BALANCED:
1619         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1620                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1621                 goto restart_search;
1622         default:
1623                 break;
1624         }
1625
1626         return NULL;
1627 }
1628
1629 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1630 {
1631         struct amdgpu_ps *ps;
1632         enum amd_pm_state_type dpm_state;
1633         int ret;
1634         bool equal = false;
1635
1636         /* if dpm init failed */
1637         if (!adev->pm.dpm_enabled)
1638                 return;
1639
1640         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1641                 /* add other state override checks here */
1642                 if ((!adev->pm.dpm.thermal_active) &&
1643                     (!adev->pm.dpm.uvd_active))
1644                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1645         }
1646         dpm_state = adev->pm.dpm.state;
1647
1648         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1649         if (ps)
1650                 adev->pm.dpm.requested_ps = ps;
1651         else
1652                 return;
1653
1654         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1655                 printk("switching from power state:\n");
1656                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1657                 printk("switching to power state:\n");
1658                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1659         }
1660
1661         /* update whether vce is active */
1662         ps->vce_active = adev->pm.dpm.vce_active;
1663         if (adev->powerplay.pp_funcs->display_configuration_changed)
1664                 amdgpu_dpm_display_configuration_changed(adev);
1665
1666         ret = amdgpu_dpm_pre_set_power_state(adev);
1667         if (ret)
1668                 return;
1669
1670         if (adev->powerplay.pp_funcs->check_state_equal) {
1671                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1672                         equal = false;
1673         }
1674
1675         if (equal)
1676                 return;
1677
1678         amdgpu_dpm_set_power_state(adev);
1679         amdgpu_dpm_post_set_power_state(adev);
1680
1681         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1682         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1683
1684         if (adev->powerplay.pp_funcs->force_performance_level) {
1685                 if (adev->pm.dpm.thermal_active) {
1686                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1687                         /* force low perf level for thermal */
1688                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1689                         /* save the user's level */
1690                         adev->pm.dpm.forced_level = level;
1691                 } else {
1692                         /* otherwise, user selected level */
1693                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1694                 }
1695         }
1696 }
1697
1698 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1699 {
1700         if (adev->powerplay.pp_funcs->powergate_uvd) {
1701                 /* enable/disable UVD */
1702                 mutex_lock(&adev->pm.mutex);
1703                 amdgpu_dpm_powergate_uvd(adev, !enable);
1704                 mutex_unlock(&adev->pm.mutex);
1705         } else {
1706                 if (enable) {
1707                         mutex_lock(&adev->pm.mutex);
1708                         adev->pm.dpm.uvd_active = true;
1709                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1710                         mutex_unlock(&adev->pm.mutex);
1711                 } else {
1712                         mutex_lock(&adev->pm.mutex);
1713                         adev->pm.dpm.uvd_active = false;
1714                         mutex_unlock(&adev->pm.mutex);
1715                 }
1716                 amdgpu_pm_compute_clocks(adev);
1717         }
1718 }
1719
1720 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1721 {
1722         if (adev->powerplay.pp_funcs->powergate_vce) {
1723                 /* enable/disable VCE */
1724                 mutex_lock(&adev->pm.mutex);
1725                 amdgpu_dpm_powergate_vce(adev, !enable);
1726                 mutex_unlock(&adev->pm.mutex);
1727         } else {
1728                 if (enable) {
1729                         mutex_lock(&adev->pm.mutex);
1730                         adev->pm.dpm.vce_active = true;
1731                         /* XXX select vce level based on ring/task */
1732                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1733                         mutex_unlock(&adev->pm.mutex);
1734                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1735                                                                AMD_CG_STATE_UNGATE);
1736                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1737                                                                AMD_PG_STATE_UNGATE);
1738                         amdgpu_pm_compute_clocks(adev);
1739                 } else {
1740                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1741                                                                AMD_PG_STATE_GATE);
1742                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1743                                                                AMD_CG_STATE_GATE);
1744                         mutex_lock(&adev->pm.mutex);
1745                         adev->pm.dpm.vce_active = false;
1746                         mutex_unlock(&adev->pm.mutex);
1747                         amdgpu_pm_compute_clocks(adev);
1748                 }
1749
1750         }
1751 }
1752
1753 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1754 {
1755         int i;
1756
1757         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1758                 return;
1759
1760         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1761                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1762
1763 }
1764
1765 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1766 {
1767         int ret;
1768
1769         if (adev->pm.sysfs_initialized)
1770                 return 0;
1771
1772         if (adev->pm.dpm_enabled == 0)
1773                 return 0;
1774
1775         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1776                                                                    DRIVER_NAME, adev,
1777                                                                    hwmon_groups);
1778         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1779                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1780                 dev_err(adev->dev,
1781                         "Unable to register hwmon device: %d\n", ret);
1782                 return ret;
1783         }
1784
1785         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1786         if (ret) {
1787                 DRM_ERROR("failed to create device file for dpm state\n");
1788                 return ret;
1789         }
1790         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1791         if (ret) {
1792                 DRM_ERROR("failed to create device file for dpm state\n");
1793                 return ret;
1794         }
1795
1796
1797         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1798         if (ret) {
1799                 DRM_ERROR("failed to create device file pp_num_states\n");
1800                 return ret;
1801         }
1802         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1803         if (ret) {
1804                 DRM_ERROR("failed to create device file pp_cur_state\n");
1805                 return ret;
1806         }
1807         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1808         if (ret) {
1809                 DRM_ERROR("failed to create device file pp_force_state\n");
1810                 return ret;
1811         }
1812         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1813         if (ret) {
1814                 DRM_ERROR("failed to create device file pp_table\n");
1815                 return ret;
1816         }
1817
1818         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1819         if (ret) {
1820                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1821                 return ret;
1822         }
1823         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1824         if (ret) {
1825                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1826                 return ret;
1827         }
1828         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1829         if (ret) {
1830                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1831                 return ret;
1832         }
1833         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1834         if (ret) {
1835                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1836                 return ret;
1837         }
1838         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1839         if (ret) {
1840                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1841                 return ret;
1842         }
1843         ret = device_create_file(adev->dev,
1844                         &dev_attr_pp_power_profile_mode);
1845         if (ret) {
1846                 DRM_ERROR("failed to create device file "
1847                                 "pp_power_profile_mode\n");
1848                 return ret;
1849         }
1850         ret = device_create_file(adev->dev,
1851                         &dev_attr_pp_od_clk_voltage);
1852         if (ret) {
1853                 DRM_ERROR("failed to create device file "
1854                                 "pp_od_clk_voltage\n");
1855                 return ret;
1856         }
1857         ret = amdgpu_debugfs_pm_init(adev);
1858         if (ret) {
1859                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1860                 return ret;
1861         }
1862
1863         adev->pm.sysfs_initialized = true;
1864
1865         return 0;
1866 }
1867
1868 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1869 {
1870         if (adev->pm.dpm_enabled == 0)
1871                 return;
1872
1873         if (adev->pm.int_hwmon_dev)
1874                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1875         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1876         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1877
1878         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1879         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1880         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1881         device_remove_file(adev->dev, &dev_attr_pp_table);
1882
1883         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1884         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1885         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1886         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1887         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1888         device_remove_file(adev->dev,
1889                         &dev_attr_pp_power_profile_mode);
1890         device_remove_file(adev->dev,
1891                         &dev_attr_pp_od_clk_voltage);
1892 }
1893
1894 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1895 {
1896         int i = 0;
1897
1898         if (!adev->pm.dpm_enabled)
1899                 return;
1900
1901         if (adev->mode_info.num_crtc)
1902                 amdgpu_display_bandwidth_update(adev);
1903
1904         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1905                 struct amdgpu_ring *ring = adev->rings[i];
1906                 if (ring && ring->ready)
1907                         amdgpu_fence_wait_empty(ring);
1908         }
1909
1910         mutex_lock(&adev->pm.mutex);
1911         /* update battery/ac status */
1912         if (power_supply_is_system_supplied() > 0)
1913                 adev->pm.ac_power = true;
1914         else
1915                 adev->pm.ac_power = false;
1916         mutex_unlock(&adev->pm.mutex);
1917
1918         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1919                 if (!amdgpu_device_has_dc_support(adev)) {
1920                         mutex_lock(&adev->pm.mutex);
1921                         amdgpu_dpm_get_active_displays(adev);
1922                         adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
1923                         adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1924                         adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1925                         /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1926                         if (adev->pm.pm_display_cfg.vrefresh > 120)
1927                                 adev->pm.pm_display_cfg.min_vblank_time = 0;
1928                         if (adev->powerplay.pp_funcs->display_configuration_change)
1929                                 adev->powerplay.pp_funcs->display_configuration_change(
1930                                                                 adev->powerplay.pp_handle,
1931                                                                 &adev->pm.pm_display_cfg);
1932                         mutex_unlock(&adev->pm.mutex);
1933                 }
1934                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1935         } else {
1936                 mutex_lock(&adev->pm.mutex);
1937                 amdgpu_dpm_get_active_displays(adev);
1938                 amdgpu_dpm_change_power_state_locked(adev);
1939                 mutex_unlock(&adev->pm.mutex);
1940         }
1941 }
1942
1943 /*
1944  * Debugfs info
1945  */
1946 #if defined(CONFIG_DEBUG_FS)
1947
1948 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1949 {
1950         uint32_t value;
1951         uint32_t query = 0;
1952         int size;
1953
1954         /* sanity check PP is enabled */
1955         if (!(adev->powerplay.pp_funcs &&
1956               adev->powerplay.pp_funcs->read_sensor))
1957               return -EINVAL;
1958
1959         /* GPU Clocks */
1960         size = sizeof(value);
1961         seq_printf(m, "GFX Clocks and Power:\n");
1962         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1963                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1964         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1965                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1966         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1967                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1968         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1969                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1970         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1971                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1972         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1973                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1974         size = sizeof(uint32_t);
1975         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1976                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
1977         size = sizeof(value);
1978         seq_printf(m, "\n");
1979
1980         /* GPU Temp */
1981         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1982                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1983
1984         /* GPU Load */
1985         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1986                 seq_printf(m, "GPU Load: %u %%\n", value);
1987         seq_printf(m, "\n");
1988
1989         /* UVD clocks */
1990         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1991                 if (!value) {
1992                         seq_printf(m, "UVD: Disabled\n");
1993                 } else {
1994                         seq_printf(m, "UVD: Enabled\n");
1995                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1996                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1997                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1998                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1999                 }
2000         }
2001         seq_printf(m, "\n");
2002
2003         /* VCE clocks */
2004         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2005                 if (!value) {
2006                         seq_printf(m, "VCE: Disabled\n");
2007                 } else {
2008                         seq_printf(m, "VCE: Enabled\n");
2009                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2010                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2011                 }
2012         }
2013
2014         return 0;
2015 }
2016
2017 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2018 {
2019         int i;
2020
2021         for (i = 0; clocks[i].flag; i++)
2022                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2023                            (flags & clocks[i].flag) ? "On" : "Off");
2024 }
2025
2026 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2027 {
2028         struct drm_info_node *node = (struct drm_info_node *) m->private;
2029         struct drm_device *dev = node->minor->dev;
2030         struct amdgpu_device *adev = dev->dev_private;
2031         struct drm_device *ddev = adev->ddev;
2032         u32 flags = 0;
2033
2034         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2035         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2036         amdgpu_parse_cg_state(m, flags);
2037         seq_printf(m, "\n");
2038
2039         if (!adev->pm.dpm_enabled) {
2040                 seq_printf(m, "dpm not enabled\n");
2041                 return 0;
2042         }
2043         if  ((adev->flags & AMD_IS_PX) &&
2044              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2045                 seq_printf(m, "PX asic powered off\n");
2046         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2047                 mutex_lock(&adev->pm.mutex);
2048                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2049                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2050                 else
2051                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2052                 mutex_unlock(&adev->pm.mutex);
2053         } else {
2054                 return amdgpu_debugfs_pm_info_pp(m, adev);
2055         }
2056
2057         return 0;
2058 }
2059
2060 static const struct drm_info_list amdgpu_pm_info_list[] = {
2061         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2062 };
2063 #endif
2064
2065 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2066 {
2067 #if defined(CONFIG_DEBUG_FS)
2068         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2069 #else
2070         return 0;
2071 #endif
2072 }