drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <[email protected]>,
   8  *          Sebastian Andrzej Siewior <[email protected]>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81
  82                 /*
  83                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  84                  * mode. If the controller supports DRD but the dr_mode is not
  85                  * specified or set to OTG, then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG &&
  88                     dwc->revision >= DWC3_REVISION_330A)
  89                         mode = USB_DR_MODE_PERIPHERAL;
  90         }
  91
  92         if (mode != dwc->dr_mode) {
  93                 dev_warn(dev,
  94                          "Configuration mismatch. dr_mode forced to %s\n",
  95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  96
  97                 dwc->dr_mode = mode;
  98         }
  99
 100         return 0;
 101 }
 102
 103 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 104 {
 105         u32 reg;
 106
 107         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 108         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 109         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 110         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 111
 112         dwc->current_dr_role = mode;
 113 }
 114
 115 static void __dwc3_set_mode(struct work_struct *work)
 116 {
 117         struct dwc3 *dwc = work_to_dwc(work);
 118         unsigned long flags;
 119         int ret;
 120
 121         if (dwc->dr_mode != USB_DR_MODE_OTG)
 122                 return;
 123
 124         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 125                 dwc3_otg_update(dwc, 0);
 126
 127         if (!dwc->desired_dr_role)
 128                 return;
 129
 130         if (dwc->desired_dr_role == dwc->current_dr_role)
 131                 return;
 132
 133         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 134                 return;
 135
 136         switch (dwc->current_dr_role) {
 137         case DWC3_GCTL_PRTCAP_HOST:
 138                 dwc3_host_exit(dwc);
 139                 break;
 140         case DWC3_GCTL_PRTCAP_DEVICE:
 141                 dwc3_gadget_exit(dwc);
 142                 dwc3_event_buffers_cleanup(dwc);
 143                 break;
 144         case DWC3_GCTL_PRTCAP_OTG:
 145                 dwc3_otg_exit(dwc);
 146                 spin_lock_irqsave(&dwc->lock, flags);
 147                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 148                 spin_unlock_irqrestore(&dwc->lock, flags);
 149                 dwc3_otg_update(dwc, 1);
 150                 break;
 151         default:
 152                 break;
 153         }
 154
 155         spin_lock_irqsave(&dwc->lock, flags);
 156
 157         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 158
 159         spin_unlock_irqrestore(&dwc->lock, flags);
 160
 161         switch (dwc->desired_dr_role) {
 162         case DWC3_GCTL_PRTCAP_HOST:
 163                 ret = dwc3_host_init(dwc);
 164                 if (ret) {
 165                         dev_err(dwc->dev, "failed to initialize host\n");
 166                 } else {
 167                         if (dwc->usb2_phy)
 168                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 169                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 170                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 171                 }
 172                 break;
 173         case DWC3_GCTL_PRTCAP_DEVICE:
 174                 dwc3_event_buffers_setup(dwc);
 175
 176                 if (dwc->usb2_phy)
 177                         otg_set_vbus(dwc->usb2_phy->otg, false);
 178                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 179                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 180
 181                 ret = dwc3_gadget_init(dwc);
 182                 if (ret)
 183                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 184                 break;
 185         case DWC3_GCTL_PRTCAP_OTG:
 186                 dwc3_otg_init(dwc);
 187                 dwc3_otg_update(dwc, 0);
 188                 break;
 189         default:
 190                 break;
 191         }
 192
 193 }
 194
 195 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 196 {
 197         unsigned long flags;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         dwc->desired_dr_role = mode;
 201         spin_unlock_irqrestore(&dwc->lock, flags);
 202
 203         queue_work(system_freezable_wq, &dwc->drd_work);
 204 }
 205
 206 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 207 {
 208         struct dwc3             *dwc = dep->dwc;
 209         u32                     reg;
 210
 211         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 212                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 213                         DWC3_GDBGFIFOSPACE_TYPE(type));
 214
 215         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 216
 217         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 218 }
 219
 220 /**
 221  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 222  * @dwc: pointer to our context structure
 223  */
 224 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 225 {
 226         u32             reg;
 227         int             retries = 1000;
 228         int             ret;
 229
 230         usb_phy_init(dwc->usb2_phy);
 231         usb_phy_init(dwc->usb3_phy);
 232         ret = phy_init(dwc->usb2_generic_phy);
 233         if (ret < 0)
 234                 return ret;
 235
 236         ret = phy_init(dwc->usb3_generic_phy);
 237         if (ret < 0) {
 238                 phy_exit(dwc->usb2_generic_phy);
 239                 return ret;
 240         }
 241
 242         /*
 243          * We're resetting only the device side because, if we're in host mode,
 244          * XHCI driver will reset the host block. If dwc3 was configured for
 245          * host-only mode, then we can return early.
 246          */
 247         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 248                 return 0;
 249
 250         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 251         reg |= DWC3_DCTL_CSFTRST;
 252         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 253
 254         /*
 255          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 256          * is cleared only after all the clocks are synchronized. This can
 257          * take a little more than 50ms. Set the polling rate at 20ms
 258          * for 10 times instead.
 259          */
 260         if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
 261                 retries = 10;
 262
 263         do {
 264                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 265                 if (!(reg & DWC3_DCTL_CSFTRST))
 266                         goto done;
 267
 268                 if (dwc3_is_usb31(dwc) &&
 269                     dwc->revision >= DWC3_USB31_REVISION_190A)
 270                         msleep(20);
 271                 else
 272                         udelay(1);
 273         } while (--retries);
 274
 275         phy_exit(dwc->usb3_generic_phy);
 276         phy_exit(dwc->usb2_generic_phy);
 277
 278         return -ETIMEDOUT;
 279
 280 done:
 281         /*
 282          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 283          * is cleared, we must wait at least 50ms before accessing the PHY
 284          * domain (synchronization delay).
 285          */
 286         if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
 287                 msleep(50);
 288
 289         return 0;
 290 }
 291
 292 static const struct clk_bulk_data dwc3_core_clks[] = {
 293         { .id = "ref" },
 294         { .id = "bus_early" },
 295         { .id = "suspend" },
 296 };
 297
 298 /*
 299  * dwc3_frame_length_adjustment - Adjusts frame length if required
 300  * @dwc3: Pointer to our controller context structure
 301  */
 302 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 303 {
 304         u32 reg;
 305         u32 dft;
 306
 307         if (dwc->revision < DWC3_REVISION_250A)
 308                 return;
 309
 310         if (dwc->fladj == 0)
 311                 return;
 312
 313         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 314         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 315         if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
 316             "request value same as default, ignoring\n")) {
 317                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 318                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 319                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 320         }
 321 }
 322
 323 /**
 324  * dwc3_free_one_event_buffer - Frees one event buffer
 325  * @dwc: Pointer to our controller context structure
 326  * @evt: Pointer to event buffer to be freed
 327  */
 328 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 329                 struct dwc3_event_buffer *evt)
 330 {
 331         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 332 }
 333
 334 /**
 335  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 336  * @dwc: Pointer to our controller context structure
 337  * @length: size of the event buffer
 338  *
 339  * Returns a pointer to the allocated event buffer structure on success
 340  * otherwise ERR_PTR(errno).
 341  */
 342 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 343                 unsigned length)
 344 {
 345         struct dwc3_event_buffer        *evt;
 346
 347         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 348         if (!evt)
 349                 return ERR_PTR(-ENOMEM);
 350
 351         evt->dwc        = dwc;
 352         evt->length     = length;
 353         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 354         if (!evt->cache)
 355                 return ERR_PTR(-ENOMEM);
 356
 357         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 358                         &evt->dma, GFP_KERNEL);
 359         if (!evt->buf)
 360                 return ERR_PTR(-ENOMEM);
 361
 362         return evt;
 363 }
 364
 365 /**
 366  * dwc3_free_event_buffers - frees all allocated event buffers
 367  * @dwc: Pointer to our controller context structure
 368  */
 369 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 370 {
 371         struct dwc3_event_buffer        *evt;
 372
 373         evt = dwc->ev_buf;
 374         if (evt)
 375                 dwc3_free_one_event_buffer(dwc, evt);
 376 }
 377
 378 /**
 379  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 380  * @dwc: pointer to our controller context structure
 381  * @length: size of event buffer
 382  *
 383  * Returns 0 on success otherwise negative errno. In the error case, dwc
 384  * may contain some buffers allocated but not all which were requested.
 385  */
 386 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 387 {
 388         struct dwc3_event_buffer *evt;
 389
 390         evt = dwc3_alloc_one_event_buffer(dwc, length);
 391         if (IS_ERR(evt)) {
 392                 dev_err(dwc->dev, "can't allocate event buffer\n");
 393                 return PTR_ERR(evt);
 394         }
 395         dwc->ev_buf = evt;
 396
 397         return 0;
 398 }
 399
 400 /**
 401  * dwc3_event_buffers_setup - setup our allocated event buffers
 402  * @dwc: pointer to our controller context structure
 403  *
 404  * Returns 0 on success otherwise negative errno.
 405  */
 406 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 407 {
 408         struct dwc3_event_buffer        *evt;
 409
 410         evt = dwc->ev_buf;
 411         evt->lpos = 0;
 412         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 413                         lower_32_bits(evt->dma));
 414         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 415                         upper_32_bits(evt->dma));
 416         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 417                         DWC3_GEVNTSIZ_SIZE(evt->length));
 418         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 419
 420         return 0;
 421 }
 422
 423 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 424 {
 425         struct dwc3_event_buffer        *evt;
 426
 427         evt = dwc->ev_buf;
 428
 429         evt->lpos = 0;
 430
 431         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 432         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 433         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 434                         | DWC3_GEVNTSIZ_SIZE(0));
 435         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 436 }
 437
 438 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 439 {
 440         if (!dwc->has_hibernation)
 441                 return 0;
 442
 443         if (!dwc->nr_scratch)
 444                 return 0;
 445
 446         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 447                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 448         if (!dwc->scratchbuf)
 449                 return -ENOMEM;
 450
 451         return 0;
 452 }
 453
 454 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 455 {
 456         dma_addr_t scratch_addr;
 457         u32 param;
 458         int ret;
 459
 460         if (!dwc->has_hibernation)
 461                 return 0;
 462
 463         if (!dwc->nr_scratch)
 464                 return 0;
 465
 466          /* should never fall here */
 467         if (!WARN_ON(dwc->scratchbuf))
 468                 return 0;
 469
 470         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 471                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 472                         DMA_BIDIRECTIONAL);
 473         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 474                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 475                 ret = -EFAULT;
 476                 goto err0;
 477         }
 478
 479         dwc->scratch_addr = scratch_addr;
 480
 481         param = lower_32_bits(scratch_addr);
 482
 483         ret = dwc3_send_gadget_generic_command(dwc,
 484                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 485         if (ret < 0)
 486                 goto err1;
 487
 488         param = upper_32_bits(scratch_addr);
 489
 490         ret = dwc3_send_gadget_generic_command(dwc,
 491                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 492         if (ret < 0)
 493                 goto err1;
 494
 495         return 0;
 496
 497 err1:
 498         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 499                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 500
 501 err0:
 502         return ret;
 503 }
 504
 505 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 506 {
 507         if (!dwc->has_hibernation)
 508                 return;
 509
 510         if (!dwc->nr_scratch)
 511                 return;
 512
 513          /* should never fall here */
 514         if (!WARN_ON(dwc->scratchbuf))
 515                 return;
 516
 517         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 518                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 519         kfree(dwc->scratchbuf);
 520 }
 521
 522 static void dwc3_core_num_eps(struct dwc3 *dwc)
 523 {
 524         struct dwc3_hwparams    *parms = &dwc->hwparams;
 525
 526         dwc->num_eps = DWC3_NUM_EPS(parms);
 527 }
 528
 529 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 530 {
 531         struct dwc3_hwparams    *parms = &dwc->hwparams;
 532
 533         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 534         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 535         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 536         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 537         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 538         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 539         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 540         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 541         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 542 }
 543
 544 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 545 {
 546         int intf;
 547         int ret = 0;
 548
 549         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 550
 551         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 552             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 553              dwc->hsphy_interface &&
 554              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 555                 ret = dwc3_ulpi_init(dwc);
 556
 557         return ret;
 558 }
 559
 560 /**
 561  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 562  * @dwc: Pointer to our controller context structure
 563  *
 564  * Returns 0 on success. The USB PHY interfaces are configured but not
 565  * initialized. The PHY interfaces and the PHYs get initialized together with
 566  * the core in dwc3_core_init.
 567  */
 568 static int dwc3_phy_setup(struct dwc3 *dwc)
 569 {
 570         u32 reg;
 571
 572         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 573
 574         /*
 575          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 576          * PHYs. Also, this bit is not supposed to be used in normal operation.
 577          */
 578         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 579
 580         /*
 581          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 582          * to '0' during coreConsultant configuration. So default value
 583          * will be '0' when the core is reset. Application needs to set it
 584          * to '1' after the core initialization is completed.
 585          */
 586         if (dwc->revision > DWC3_REVISION_194A)
 587                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 588
 589         if (dwc->u2ss_inp3_quirk)
 590                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 591
 592         if (dwc->dis_rxdet_inp3_quirk)
 593                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 594
 595         if (dwc->req_p1p2p3_quirk)
 596                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 597
 598         if (dwc->del_p1p2p3_quirk)
 599                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 600
 601         if (dwc->del_phy_power_chg_quirk)
 602                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 603
 604         if (dwc->lfps_filter_quirk)
 605                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 606
 607         if (dwc->rx_detect_poll_quirk)
 608                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 609
 610         if (dwc->tx_de_emphasis_quirk)
 611                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 612
 613         if (dwc->dis_u3_susphy_quirk)
 614                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 615
 616         if (dwc->dis_del_phy_power_chg_quirk)
 617                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 618
 619         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 620
 621         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 622
 623         /* Select the HS PHY interface */
 624         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 625         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 626                 if (dwc->hsphy_interface &&
 627                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 628                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 629                         break;
 630                 } else if (dwc->hsphy_interface &&
 631                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 632                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 633                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 634                 } else {
 635                         /* Relying on default value. */
 636                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 637                                 break;
 638                 }
 639                 /* FALLTHROUGH */
 640         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 641                 /* FALLTHROUGH */
 642         default:
 643                 break;
 644         }
 645
 646         switch (dwc->hsphy_mode) {
 647         case USBPHY_INTERFACE_MODE_UTMI:
 648                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 649                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 650                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 651                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 652                 break;
 653         case USBPHY_INTERFACE_MODE_UTMIW:
 654                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 655                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 656                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 657                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 658                 break;
 659         default:
 660                 break;
 661         }
 662
 663         /*
 664          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 665          * '0' during coreConsultant configuration. So default value will
 666          * be '0' when the core is reset. Application needs to set it to
 667          * '1' after the core initialization is completed.
 668          */
 669         if (dwc->revision > DWC3_REVISION_194A)
 670                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 671
 672         if (dwc->dis_u2_susphy_quirk)
 673                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 674
 675         if (dwc->dis_enblslpm_quirk)
 676                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 677         else
 678                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 679
 680         if (dwc->dis_u2_freeclk_exists_quirk)
 681                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 682
 683         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 684
 685         return 0;
 686 }
 687
 688 static void dwc3_core_exit(struct dwc3 *dwc)
 689 {
 690         dwc3_event_buffers_cleanup(dwc);
 691
 692         usb_phy_shutdown(dwc->usb2_phy);
 693         usb_phy_shutdown(dwc->usb3_phy);
 694         phy_exit(dwc->usb2_generic_phy);
 695         phy_exit(dwc->usb3_generic_phy);
 696
 697         usb_phy_set_suspend(dwc->usb2_phy, 1);
 698         usb_phy_set_suspend(dwc->usb3_phy, 1);
 699         phy_power_off(dwc->usb2_generic_phy);
 700         phy_power_off(dwc->usb3_generic_phy);
 701         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
 702         reset_control_assert(dwc->reset);
 703 }
 704
 705 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 706 {
 707         u32 reg;
 708
 709         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 710
 711         /* This should read as U3 followed by revision number */
 712         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 713                 /* Detected DWC_usb3 IP */
 714                 dwc->revision = reg;
 715         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 716                 /* Detected DWC_usb31 IP */
 717                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 718                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 719                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 720         } else {
 721                 return false;
 722         }
 723
 724         return true;
 725 }
 726
 727 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 728 {
 729         u32 hwparams4 = dwc->hwparams.hwparams4;
 730         u32 reg;
 731
 732         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 733         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 734
 735         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 736         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 737                 /**
 738                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 739                  * issue which would cause xHCI compliance tests to fail.
 740                  *
 741                  * Because of that we cannot enable clock gating on such
 742                  * configurations.
 743                  *
 744                  * Refers to:
 745                  *
 746                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 747                  * SOF/ITP Mode Used
 748                  */
 749                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 750                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 751                                 (dwc->revision >= DWC3_REVISION_210A &&
 752                                 dwc->revision <= DWC3_REVISION_250A))
 753                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 754                 else
 755                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 756                 break;
 757         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 758                 /* enable hibernation here */
 759                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 760
 761                 /*
 762                  * REVISIT Enabling this bit so that host-mode hibernation
 763                  * will work. Device-mode hibernation is not yet implemented.
 764                  */
 765                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 766                 break;
 767         default:
 768                 /* nothing */
 769                 break;
 770         }
 771
 772         /* check if current dwc3 is on simulation board */
 773         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 774                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 775                 dwc->is_fpga = true;
 776         }
 777
 778         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 779                         "disable_scramble cannot be used on non-FPGA builds\n");
 780
 781         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 782                 reg |= DWC3_GCTL_DISSCRAMBLE;
 783         else
 784                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 785
 786         if (dwc->u2exit_lfps_quirk)
 787                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 788
 789         /*
 790          * WORKAROUND: DWC3 revisions <1.90a have a bug
 791          * where the device can fail to connect at SuperSpeed
 792          * and falls back to high-speed mode which causes
 793          * the device to enter a Connect/Disconnect loop
 794          */
 795         if (dwc->revision < DWC3_REVISION_190A)
 796                 reg |= DWC3_GCTL_U2RSTECN;
 797
 798         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 799 }
 800
 801 static int dwc3_core_get_phy(struct dwc3 *dwc);
 802 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 803
 804 /* set global incr burst type configuration registers */
 805 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 806 {
 807         struct device *dev = dwc->dev;
 808         /* incrx_mode : for INCR burst type. */
 809         bool incrx_mode;
 810         /* incrx_size : for size of INCRX burst. */
 811         u32 incrx_size;
 812         u32 *vals;
 813         u32 cfg;
 814         int ntype;
 815         int ret;
 816         int i;
 817
 818         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 819
 820         /*
 821          * Handle property "snps,incr-burst-type-adjustment".
 822          * Get the number of value from this property:
 823          * result <= 0, means this property is not supported.
 824          * result = 1, means INCRx burst mode supported.
 825          * result > 1, means undefined length burst mode supported.
 826          */
 827         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 828         if (ntype <= 0)
 829                 return;
 830
 831         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 832         if (!vals) {
 833                 dev_err(dev, "Error to get memory\n");
 834                 return;
 835         }
 836
 837         /* Get INCR burst type, and parse it */
 838         ret = device_property_read_u32_array(dev,
 839                         "snps,incr-burst-type-adjustment", vals, ntype);
 840         if (ret) {
 841                 kfree(vals);
 842                 dev_err(dev, "Error to get property\n");
 843                 return;
 844         }
 845
 846         incrx_size = *vals;
 847
 848         if (ntype > 1) {
 849                 /* INCRX (undefined length) burst mode */
 850                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 851                 for (i = 1; i < ntype; i++) {
 852                         if (vals[i] > incrx_size)
 853                                 incrx_size = vals[i];
 854                 }
 855         } else {
 856                 /* INCRX burst mode */
 857                 incrx_mode = INCRX_BURST_MODE;
 858         }
 859
 860         kfree(vals);
 861
 862         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 863         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 864         if (incrx_mode)
 865                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 866         switch (incrx_size) {
 867         case 256:
 868                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 869                 break;
 870         case 128:
 871                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 872                 break;
 873         case 64:
 874                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 875                 break;
 876         case 32:
 877                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 878                 break;
 879         case 16:
 880                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 881                 break;
 882         case 8:
 883                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 884                 break;
 885         case 4:
 886                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 887                 break;
 888         case 1:
 889                 break;
 890         default:
 891                 dev_err(dev, "Invalid property\n");
 892                 break;
 893         }
 894
 895         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 896 }
 897
 898 /**
 899  * dwc3_core_init - Low-level initialization of DWC3 Core
 900  * @dwc: Pointer to our controller context structure
 901  *
 902  * Returns 0 on success otherwise negative errno.
 903  */
 904 static int dwc3_core_init(struct dwc3 *dwc)
 905 {
 906         u32                     reg;
 907         int                     ret;
 908
 909         /*
 910          * Write Linux Version Code to our GUID register so it's easy to figure
 911          * out which kernel version a bug was found.
 912          */
 913         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 914
 915         /* Handle USB2.0-only core configuration */
 916         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 917                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 918                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 919                         dwc->maximum_speed = USB_SPEED_HIGH;
 920         }
 921
 922         ret = dwc3_phy_setup(dwc);
 923         if (ret)
 924                 goto err0;
 925
 926         if (!dwc->ulpi_ready) {
 927                 ret = dwc3_core_ulpi_init(dwc);
 928                 if (ret)
 929                         goto err0;
 930                 dwc->ulpi_ready = true;
 931         }
 932
 933         if (!dwc->phys_ready) {
 934                 ret = dwc3_core_get_phy(dwc);
 935                 if (ret)
 936                         goto err0a;
 937                 dwc->phys_ready = true;
 938         }
 939
 940         ret = dwc3_core_soft_reset(dwc);
 941         if (ret)
 942                 goto err0a;
 943
 944         dwc3_core_setup_global_control(dwc);
 945         dwc3_core_num_eps(dwc);
 946
 947         ret = dwc3_setup_scratch_buffers(dwc);
 948         if (ret)
 949                 goto err1;
 950
 951         /* Adjust Frame Length */
 952         dwc3_frame_length_adjustment(dwc);
 953
 954         dwc3_set_incr_burst_type(dwc);
 955
 956         usb_phy_set_suspend(dwc->usb2_phy, 0);
 957         usb_phy_set_suspend(dwc->usb3_phy, 0);
 958         ret = phy_power_on(dwc->usb2_generic_phy);
 959         if (ret < 0)
 960                 goto err2;
 961
 962         ret = phy_power_on(dwc->usb3_generic_phy);
 963         if (ret < 0)
 964                 goto err3;
 965
 966         ret = dwc3_event_buffers_setup(dwc);
 967         if (ret) {
 968                 dev_err(dwc->dev, "failed to setup event buffers\n");
 969                 goto err4;
 970         }
 971
 972         /*
 973          * ENDXFER polling is available on version 3.10a and later of
 974          * the DWC_usb3 controller. It is NOT available in the
 975          * DWC_usb31 controller.
 976          */
 977         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 978                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 979                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 980                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 981         }
 982
 983         if (dwc->revision >= DWC3_REVISION_250A) {
 984                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
 985
 986                 /*
 987                  * Enable hardware control of sending remote wakeup
 988                  * in HS when the device is in the L1 state.
 989                  */
 990                 if (dwc->revision >= DWC3_REVISION_290A)
 991                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
 992
 993                 if (dwc->dis_tx_ipgap_linecheck_quirk)
 994                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 995
 996                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 997         }
 998
 999         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1000             dwc->dr_mode == USB_DR_MODE_OTG) {
1001                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1002
1003                 /*
1004                  * Enable Auto retry Feature to make the controller operating in
1005                  * Host mode on seeing transaction errors(CRC errors or internal
1006                  * overrun scenerios) on IN transfers to reply to the device
1007                  * with a non-terminating retry ACK (i.e, an ACK transcation
1008                  * packet with Retry=1 & Nump != 0)
1009                  */
1010                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1011
1012                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1013         }
1014
1015         /*
1016          * Must config both number of packets and max burst settings to enable
1017          * RX and/or TX threshold.
1018          */
1019         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1020                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1021                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1022                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1023                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1024
1025                 if (rx_thr_num && rx_maxburst) {
1026                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1027                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1028
1029                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1030                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1031
1032                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1033                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1034
1035                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1036                 }
1037
1038                 if (tx_thr_num && tx_maxburst) {
1039                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1040                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1041
1042                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1043                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1044
1045                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1046                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1047
1048                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1049                 }
1050         }
1051
1052         return 0;
1053
1054 err4:
1055         phy_power_off(dwc->usb3_generic_phy);
1056
1057 err3:
1058         phy_power_off(dwc->usb2_generic_phy);
1059
1060 err2:
1061         usb_phy_set_suspend(dwc->usb2_phy, 1);
1062         usb_phy_set_suspend(dwc->usb3_phy, 1);
1063
1064 err1:
1065         usb_phy_shutdown(dwc->usb2_phy);
1066         usb_phy_shutdown(dwc->usb3_phy);
1067         phy_exit(dwc->usb2_generic_phy);
1068         phy_exit(dwc->usb3_generic_phy);
1069
1070 err0a:
1071         dwc3_ulpi_exit(dwc);
1072
1073 err0:
1074         return ret;
1075 }
1076
1077 static int dwc3_core_get_phy(struct dwc3 *dwc)
1078 {
1079         struct device           *dev = dwc->dev;
1080         struct device_node      *node = dev->of_node;
1081         int ret;
1082
1083         if (node) {
1084                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1085                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1086         } else {
1087                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1088                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1089         }
1090
1091         if (IS_ERR(dwc->usb2_phy)) {
1092                 ret = PTR_ERR(dwc->usb2_phy);
1093                 if (ret == -ENXIO || ret == -ENODEV) {
1094                         dwc->usb2_phy = NULL;
1095                 } else if (ret == -EPROBE_DEFER) {
1096                         return ret;
1097                 } else {
1098                         dev_err(dev, "no usb2 phy configured\n");
1099                         return ret;
1100                 }
1101         }
1102
1103         if (IS_ERR(dwc->usb3_phy)) {
1104                 ret = PTR_ERR(dwc->usb3_phy);
1105                 if (ret == -ENXIO || ret == -ENODEV) {
1106                         dwc->usb3_phy = NULL;
1107                 } else if (ret == -EPROBE_DEFER) {
1108                         return ret;
1109                 } else {
1110                         dev_err(dev, "no usb3 phy configured\n");
1111                         return ret;
1112                 }
1113         }
1114
1115         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1116         if (IS_ERR(dwc->usb2_generic_phy)) {
1117                 ret = PTR_ERR(dwc->usb2_generic_phy);
1118                 if (ret == -ENOSYS || ret == -ENODEV) {
1119                         dwc->usb2_generic_phy = NULL;
1120                 } else if (ret == -EPROBE_DEFER) {
1121                         return ret;
1122                 } else {
1123                         dev_err(dev, "no usb2 phy configured\n");
1124                         return ret;
1125                 }
1126         }
1127
1128         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1129         if (IS_ERR(dwc->usb3_generic_phy)) {
1130                 ret = PTR_ERR(dwc->usb3_generic_phy);
1131                 if (ret == -ENOSYS || ret == -ENODEV) {
1132                         dwc->usb3_generic_phy = NULL;
1133                 } else if (ret == -EPROBE_DEFER) {
1134                         return ret;
1135                 } else {
1136                         dev_err(dev, "no usb3 phy configured\n");
1137                         return ret;
1138                 }
1139         }
1140
1141         return 0;
1142 }
1143
1144 static int dwc3_core_init_mode(struct dwc3 *dwc)
1145 {
1146         struct device *dev = dwc->dev;
1147         int ret;
1148
1149         switch (dwc->dr_mode) {
1150         case USB_DR_MODE_PERIPHERAL:
1151                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1152
1153                 if (dwc->usb2_phy)
1154                         otg_set_vbus(dwc->usb2_phy->otg, false);
1155                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1156                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1157
1158                 ret = dwc3_gadget_init(dwc);
1159                 if (ret) {
1160                         if (ret != -EPROBE_DEFER)
1161                                 dev_err(dev, "failed to initialize gadget\n");
1162                         return ret;
1163                 }
1164                 break;
1165         case USB_DR_MODE_HOST:
1166                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1167
1168                 if (dwc->usb2_phy)
1169                         otg_set_vbus(dwc->usb2_phy->otg, true);
1170                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1171                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1172
1173                 ret = dwc3_host_init(dwc);
1174                 if (ret) {
1175                         if (ret != -EPROBE_DEFER)
1176                                 dev_err(dev, "failed to initialize host\n");
1177                         return ret;
1178                 }
1179                 break;
1180         case USB_DR_MODE_OTG:
1181                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1182                 ret = dwc3_drd_init(dwc);
1183                 if (ret) {
1184                         if (ret != -EPROBE_DEFER)
1185                                 dev_err(dev, "failed to initialize dual-role\n");
1186                         return ret;
1187                 }
1188                 break;
1189         default:
1190                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1191                 return -EINVAL;
1192         }
1193
1194         return 0;
1195 }
1196
1197 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1198 {
1199         switch (dwc->dr_mode) {
1200         case USB_DR_MODE_PERIPHERAL:
1201                 dwc3_gadget_exit(dwc);
1202                 break;
1203         case USB_DR_MODE_HOST:
1204                 dwc3_host_exit(dwc);
1205                 break;
1206         case USB_DR_MODE_OTG:
1207                 dwc3_drd_exit(dwc);
1208                 break;
1209         default:
1210                 /* do nothing */
1211                 break;
1212         }
1213 }
1214
1215 static void dwc3_get_properties(struct dwc3 *dwc)
1216 {
1217         struct device           *dev = dwc->dev;
1218         u8                      lpm_nyet_threshold;
1219         u8                      tx_de_emphasis;
1220         u8                      hird_threshold;
1221         u8                      rx_thr_num_pkt_prd;
1222         u8                      rx_max_burst_prd;
1223         u8                      tx_thr_num_pkt_prd;
1224         u8                      tx_max_burst_prd;
1225
1226         /* default to highest possible threshold */
1227         lpm_nyet_threshold = 0xf;
1228
1229         /* default to -3.5dB de-emphasis */
1230         tx_de_emphasis = 1;
1231
1232         /*
1233          * default to assert utmi_sleep_n and use maximum allowed HIRD
1234          * threshold value of 0b1100
1235          */
1236         hird_threshold = 12;
1237
1238         dwc->maximum_speed = usb_get_maximum_speed(dev);
1239         dwc->dr_mode = usb_get_dr_mode(dev);
1240         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1241
1242         dwc->sysdev_is_parent = device_property_read_bool(dev,
1243                                 "linux,sysdev_is_parent");
1244         if (dwc->sysdev_is_parent)
1245                 dwc->sysdev = dwc->dev->parent;
1246         else
1247                 dwc->sysdev = dwc->dev;
1248
1249         dwc->has_lpm_erratum = device_property_read_bool(dev,
1250                                 "snps,has-lpm-erratum");
1251         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1252                                 &lpm_nyet_threshold);
1253         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1254                                 "snps,is-utmi-l1-suspend");
1255         device_property_read_u8(dev, "snps,hird-threshold",
1256                                 &hird_threshold);
1257         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1258                                 "snps,dis-start-transfer-quirk");
1259         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1260                                 "snps,usb3_lpm_capable");
1261         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1262                                 "snps,usb2-lpm-disable");
1263         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1264                                 &rx_thr_num_pkt_prd);
1265         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1266                                 &rx_max_burst_prd);
1267         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1268                                 &tx_thr_num_pkt_prd);
1269         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1270                                 &tx_max_burst_prd);
1271
1272         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1273                                 "snps,disable_scramble_quirk");
1274         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1275                                 "snps,u2exit_lfps_quirk");
1276         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1277                                 "snps,u2ss_inp3_quirk");
1278         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1279                                 "snps,req_p1p2p3_quirk");
1280         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1281                                 "snps,del_p1p2p3_quirk");
1282         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1283                                 "snps,del_phy_power_chg_quirk");
1284         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1285                                 "snps,lfps_filter_quirk");
1286         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1287                                 "snps,rx_detect_poll_quirk");
1288         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1289                                 "snps,dis_u3_susphy_quirk");
1290         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1291                                 "snps,dis_u2_susphy_quirk");
1292         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1293                                 "snps,dis_enblslpm_quirk");
1294         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1295                                 "snps,dis-u1-entry-quirk");
1296         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1297                                 "snps,dis-u2-entry-quirk");
1298         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1299                                 "snps,dis_rxdet_inp3_quirk");
1300         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1301                                 "snps,dis-u2-freeclk-exists-quirk");
1302         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1303                                 "snps,dis-del-phy-power-chg-quirk");
1304         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1305                                 "snps,dis-tx-ipgap-linecheck-quirk");
1306
1307         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1308                                 "snps,tx_de_emphasis_quirk");
1309         device_property_read_u8(dev, "snps,tx_de_emphasis",
1310                                 &tx_de_emphasis);
1311         device_property_read_string(dev, "snps,hsphy_interface",
1312                                     &dwc->hsphy_interface);
1313         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1314                                  &dwc->fladj);
1315
1316         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1317                                 "snps,dis_metastability_quirk");
1318
1319         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1320         dwc->tx_de_emphasis = tx_de_emphasis;
1321
1322         dwc->hird_threshold = hird_threshold;
1323
1324         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1325         dwc->rx_max_burst_prd = rx_max_burst_prd;
1326
1327         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1328         dwc->tx_max_burst_prd = tx_max_burst_prd;
1329
1330         dwc->imod_interval = 0;
1331 }
1332
1333 /* check whether the core supports IMOD */
1334 bool dwc3_has_imod(struct dwc3 *dwc)
1335 {
1336         return ((dwc3_is_usb3(dwc) &&
1337                  dwc->revision >= DWC3_REVISION_300A) ||
1338                 (dwc3_is_usb31(dwc) &&
1339                  dwc->revision >= DWC3_USB31_REVISION_120A));
1340 }
1341
1342 static void dwc3_check_params(struct dwc3 *dwc)
1343 {
1344         struct device *dev = dwc->dev;
1345
1346         /* Check for proper value of imod_interval */
1347         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1348                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1349                 dwc->imod_interval = 0;
1350         }
1351
1352         /*
1353          * Workaround for STAR 9000961433 which affects only version
1354          * 3.00a of the DWC_usb3 core. This prevents the controller
1355          * interrupt from being masked while handling events. IMOD
1356          * allows us to work around this issue. Enable it for the
1357          * affected version.
1358          */
1359         if (!dwc->imod_interval &&
1360             (dwc->revision == DWC3_REVISION_300A))
1361                 dwc->imod_interval = 1;
1362
1363         /* Check the maximum_speed parameter */
1364         switch (dwc->maximum_speed) {
1365         case USB_SPEED_LOW:
1366         case USB_SPEED_FULL:
1367         case USB_SPEED_HIGH:
1368         case USB_SPEED_SUPER:
1369         case USB_SPEED_SUPER_PLUS:
1370                 break;
1371         default:
1372                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1373                         dwc->maximum_speed);
1374                 /* fall through */
1375         case USB_SPEED_UNKNOWN:
1376                 /* default to superspeed */
1377                 dwc->maximum_speed = USB_SPEED_SUPER;
1378
1379                 /*
1380                  * default to superspeed plus if we are capable.
1381                  */
1382                 if (dwc3_is_usb31(dwc) &&
1383                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1384                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1385                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1386
1387                 break;
1388         }
1389 }
1390
1391 static int dwc3_probe(struct platform_device *pdev)
1392 {
1393         struct device           *dev = &pdev->dev;
1394         struct resource         *res, dwc_res;
1395         struct dwc3             *dwc;
1396
1397         int                     ret;
1398
1399         void __iomem            *regs;
1400
1401         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1402         if (!dwc)
1403                 return -ENOMEM;
1404
1405         dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1406                                  GFP_KERNEL);
1407         if (!dwc->clks)
1408                 return -ENOMEM;
1409
1410         dwc->dev = dev;
1411
1412         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1413         if (!res) {
1414                 dev_err(dev, "missing memory resource\n");
1415                 return -ENODEV;
1416         }
1417
1418         dwc->xhci_resources[0].start = res->start;
1419         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1420                                         DWC3_XHCI_REGS_END;
1421         dwc->xhci_resources[0].flags = res->flags;
1422         dwc->xhci_resources[0].name = res->name;
1423
1424         /*
1425          * Request memory region but exclude xHCI regs,
1426          * since it will be requested by the xhci-plat driver.
1427          */
1428         dwc_res = *res;
1429         dwc_res.start += DWC3_GLOBALS_REGS_START;
1430
1431         regs = devm_ioremap_resource(dev, &dwc_res);
1432         if (IS_ERR(regs))
1433                 return PTR_ERR(regs);
1434
1435         dwc->regs       = regs;
1436         dwc->regs_size  = resource_size(&dwc_res);
1437
1438         dwc3_get_properties(dwc);
1439
1440         dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1441         if (IS_ERR(dwc->reset))
1442                 return PTR_ERR(dwc->reset);
1443
1444         if (dev->of_node) {
1445                 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1446
1447                 ret = devm_clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1448                 if (ret == -EPROBE_DEFER)
1449                         return ret;
1450                 /*
1451                  * Clocks are optional, but new DT platforms should support all
1452                  * clocks as required by the DT-binding.
1453                  */
1454                 if (ret)
1455                         dwc->num_clks = 0;
1456         }
1457
1458         ret = reset_control_deassert(dwc->reset);
1459         if (ret)
1460                 return ret;
1461
1462         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1463         if (ret)
1464                 goto assert_reset;
1465
1466         if (!dwc3_core_is_valid(dwc)) {
1467                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1468                 ret = -ENODEV;
1469                 goto disable_clks;
1470         }
1471
1472         platform_set_drvdata(pdev, dwc);
1473         dwc3_cache_hwparams(dwc);
1474
1475         spin_lock_init(&dwc->lock);
1476
1477         pm_runtime_set_active(dev);
1478         pm_runtime_use_autosuspend(dev);
1479         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1480         pm_runtime_enable(dev);
1481         ret = pm_runtime_get_sync(dev);
1482         if (ret < 0)
1483                 goto err1;
1484
1485         pm_runtime_forbid(dev);
1486
1487         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1488         if (ret) {
1489                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1490                 ret = -ENOMEM;
1491                 goto err2;
1492         }
1493
1494         ret = dwc3_get_dr_mode(dwc);
1495         if (ret)
1496                 goto err3;
1497
1498         ret = dwc3_alloc_scratch_buffers(dwc);
1499         if (ret)
1500                 goto err3;
1501
1502         ret = dwc3_core_init(dwc);
1503         if (ret) {
1504                 if (ret != -EPROBE_DEFER)
1505                         dev_err(dev, "failed to initialize core: %d\n", ret);
1506                 goto err4;
1507         }
1508
1509         dwc3_check_params(dwc);
1510
1511         ret = dwc3_core_init_mode(dwc);
1512         if (ret)
1513                 goto err5;
1514
1515         dwc3_debugfs_init(dwc);
1516         pm_runtime_put(dev);
1517
1518         return 0;
1519
1520 err5:
1521         dwc3_event_buffers_cleanup(dwc);
1522         dwc3_ulpi_exit(dwc);
1523
1524 err4:
1525         dwc3_free_scratch_buffers(dwc);
1526
1527 err3:
1528         dwc3_free_event_buffers(dwc);
1529
1530 err2:
1531         pm_runtime_allow(&pdev->dev);
1532
1533 err1:
1534         pm_runtime_put_sync(&pdev->dev);
1535         pm_runtime_disable(&pdev->dev);
1536
1537 disable_clks:
1538         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1539 assert_reset:
1540         reset_control_assert(dwc->reset);
1541
1542         return ret;
1543 }
1544
1545 static int dwc3_remove(struct platform_device *pdev)
1546 {
1547         struct dwc3     *dwc = platform_get_drvdata(pdev);
1548
1549         pm_runtime_get_sync(&pdev->dev);
1550
1551         dwc3_debugfs_exit(dwc);
1552         dwc3_core_exit_mode(dwc);
1553
1554         dwc3_core_exit(dwc);
1555         dwc3_ulpi_exit(dwc);
1556
1557         pm_runtime_put_sync(&pdev->dev);
1558         pm_runtime_allow(&pdev->dev);
1559         pm_runtime_disable(&pdev->dev);
1560
1561         dwc3_free_event_buffers(dwc);
1562         dwc3_free_scratch_buffers(dwc);
1563
1564         return 0;
1565 }
1566
1567 #ifdef CONFIG_PM
1568 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1569 {
1570         int ret;
1571
1572         ret = reset_control_deassert(dwc->reset);
1573         if (ret)
1574                 return ret;
1575
1576         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1577         if (ret)
1578                 goto assert_reset;
1579
1580         ret = dwc3_core_init(dwc);
1581         if (ret)
1582                 goto disable_clks;
1583
1584         return 0;
1585
1586 disable_clks:
1587         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1588 assert_reset:
1589         reset_control_assert(dwc->reset);
1590
1591         return ret;
1592 }
1593
1594 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1595 {
1596         unsigned long   flags;
1597         u32 reg;
1598
1599         switch (dwc->current_dr_role) {
1600         case DWC3_GCTL_PRTCAP_DEVICE:
1601                 spin_lock_irqsave(&dwc->lock, flags);
1602                 dwc3_gadget_suspend(dwc);
1603                 spin_unlock_irqrestore(&dwc->lock, flags);
1604                 synchronize_irq(dwc->irq_gadget);
1605                 dwc3_core_exit(dwc);
1606                 break;
1607         case DWC3_GCTL_PRTCAP_HOST:
1608                 if (!PMSG_IS_AUTO(msg)) {
1609                         dwc3_core_exit(dwc);
1610                         break;
1611                 }
1612
1613                 /* Let controller to suspend HSPHY before PHY driver suspends */
1614                 if (dwc->dis_u2_susphy_quirk ||
1615                     dwc->dis_enblslpm_quirk) {
1616                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1617                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1618                                 DWC3_GUSB2PHYCFG_SUSPHY;
1619                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1620
1621                         /* Give some time for USB2 PHY to suspend */
1622                         usleep_range(5000, 6000);
1623                 }
1624
1625                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1626                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1627                 break;
1628         case DWC3_GCTL_PRTCAP_OTG:
1629                 /* do nothing during runtime_suspend */
1630                 if (PMSG_IS_AUTO(msg))
1631                         break;
1632
1633                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1634                         spin_lock_irqsave(&dwc->lock, flags);
1635                         dwc3_gadget_suspend(dwc);
1636                         spin_unlock_irqrestore(&dwc->lock, flags);
1637                         synchronize_irq(dwc->irq_gadget);
1638                 }
1639
1640                 dwc3_otg_exit(dwc);
1641                 dwc3_core_exit(dwc);
1642                 break;
1643         default:
1644                 /* do nothing */
1645                 break;
1646         }
1647
1648         return 0;
1649 }
1650
1651 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1652 {
1653         unsigned long   flags;
1654         int             ret;
1655         u32             reg;
1656
1657         switch (dwc->current_dr_role) {
1658         case DWC3_GCTL_PRTCAP_DEVICE:
1659                 ret = dwc3_core_init_for_resume(dwc);
1660                 if (ret)
1661                         return ret;
1662
1663                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1664                 spin_lock_irqsave(&dwc->lock, flags);
1665                 dwc3_gadget_resume(dwc);
1666                 spin_unlock_irqrestore(&dwc->lock, flags);
1667                 break;
1668         case DWC3_GCTL_PRTCAP_HOST:
1669                 if (!PMSG_IS_AUTO(msg)) {
1670                         ret = dwc3_core_init_for_resume(dwc);
1671                         if (ret)
1672                                 return ret;
1673                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1674                         break;
1675                 }
1676                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1677                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1678                 if (dwc->dis_u2_susphy_quirk)
1679                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1680
1681                 if (dwc->dis_enblslpm_quirk)
1682                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1683
1684                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1685
1686                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1687                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1688                 break;
1689         case DWC3_GCTL_PRTCAP_OTG:
1690                 /* nothing to do on runtime_resume */
1691                 if (PMSG_IS_AUTO(msg))
1692                         break;
1693
1694                 ret = dwc3_core_init(dwc);
1695                 if (ret)
1696                         return ret;
1697
1698                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1699
1700                 dwc3_otg_init(dwc);
1701                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1702                         dwc3_otg_host_init(dwc);
1703                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1704                         spin_lock_irqsave(&dwc->lock, flags);
1705                         dwc3_gadget_resume(dwc);
1706                         spin_unlock_irqrestore(&dwc->lock, flags);
1707                 }
1708
1709                 break;
1710         default:
1711                 /* do nothing */
1712                 break;
1713         }
1714
1715         return 0;
1716 }
1717
1718 static int dwc3_runtime_checks(struct dwc3 *dwc)
1719 {
1720         switch (dwc->current_dr_role) {
1721         case DWC3_GCTL_PRTCAP_DEVICE:
1722                 if (dwc->connected)
1723                         return -EBUSY;
1724                 break;
1725         case DWC3_GCTL_PRTCAP_HOST:
1726         default:
1727                 /* do nothing */
1728                 break;
1729         }
1730
1731         return 0;
1732 }
1733
1734 static int dwc3_runtime_suspend(struct device *dev)
1735 {
1736         struct dwc3     *dwc = dev_get_drvdata(dev);
1737         int             ret;
1738
1739         if (dwc3_runtime_checks(dwc))
1740                 return -EBUSY;
1741
1742         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1743         if (ret)
1744                 return ret;
1745
1746         device_init_wakeup(dev, true);
1747
1748         return 0;
1749 }
1750
1751 static int dwc3_runtime_resume(struct device *dev)
1752 {
1753         struct dwc3     *dwc = dev_get_drvdata(dev);
1754         int             ret;
1755
1756         device_init_wakeup(dev, false);
1757
1758         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1759         if (ret)
1760                 return ret;
1761
1762         switch (dwc->current_dr_role) {
1763         case DWC3_GCTL_PRTCAP_DEVICE:
1764                 dwc3_gadget_process_pending_events(dwc);
1765                 break;
1766         case DWC3_GCTL_PRTCAP_HOST:
1767         default:
1768                 /* do nothing */
1769                 break;
1770         }
1771
1772         pm_runtime_mark_last_busy(dev);
1773
1774         return 0;
1775 }
1776
1777 static int dwc3_runtime_idle(struct device *dev)
1778 {
1779         struct dwc3     *dwc = dev_get_drvdata(dev);
1780
1781         switch (dwc->current_dr_role) {
1782         case DWC3_GCTL_PRTCAP_DEVICE:
1783                 if (dwc3_runtime_checks(dwc))
1784                         return -EBUSY;
1785                 break;
1786         case DWC3_GCTL_PRTCAP_HOST:
1787         default:
1788                 /* do nothing */
1789                 break;
1790         }
1791
1792         pm_runtime_mark_last_busy(dev);
1793         pm_runtime_autosuspend(dev);
1794
1795         return 0;
1796 }
1797 #endif /* CONFIG_PM */
1798
1799 #ifdef CONFIG_PM_SLEEP
1800 static int dwc3_suspend(struct device *dev)
1801 {
1802         struct dwc3     *dwc = dev_get_drvdata(dev);
1803         int             ret;
1804
1805         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1806         if (ret)
1807                 return ret;
1808
1809         pinctrl_pm_select_sleep_state(dev);
1810
1811         return 0;
1812 }
1813
1814 static int dwc3_resume(struct device *dev)
1815 {
1816         struct dwc3     *dwc = dev_get_drvdata(dev);
1817         int             ret;
1818
1819         pinctrl_pm_select_default_state(dev);
1820
1821         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1822         if (ret)
1823                 return ret;
1824
1825         pm_runtime_disable(dev);
1826         pm_runtime_set_active(dev);
1827         pm_runtime_enable(dev);
1828
1829         return 0;
1830 }
1831 #endif /* CONFIG_PM_SLEEP */
1832
1833 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1834         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1835         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1836                         dwc3_runtime_idle)
1837 };
1838
1839 #ifdef CONFIG_OF
1840 static const struct of_device_id of_dwc3_match[] = {
1841         {
1842                 .compatible = "snps,dwc3"
1843         },
1844         {
1845                 .compatible = "synopsys,dwc3"
1846         },
1847         { },
1848 };
1849 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1850 #endif
1851
1852 #ifdef CONFIG_ACPI
1853
1854 #define ACPI_ID_INTEL_BSW       "808622B7"
1855
1856 static const struct acpi_device_id dwc3_acpi_match[] = {
1857         { ACPI_ID_INTEL_BSW, 0 },
1858         { },
1859 };
1860 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1861 #endif
1862
1863 static struct platform_driver dwc3_driver = {
1864         .probe          = dwc3_probe,
1865         .remove         = dwc3_remove,
1866         .driver         = {
1867                 .name   = "dwc3",
1868                 .of_match_table = of_match_ptr(of_dwc3_match),
1869                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1870                 .pm     = &dwc3_dev_pm_ops,
1871         },
1872 };
1873
1874 module_platform_driver(dwc3_driver);
1875
1876 MODULE_ALIAS("platform:dwc3");
1877 MODULE_AUTHOR("Felipe Balbi <[email protected]>");
1878 MODULE_LICENSE("GPL v2");
1879 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");