drivers/gpu/drm/vc4/vc4_hdmi_regs.h

   1 #ifndef _VC4_HDMI_REGS_H_
   2 #define _VC4_HDMI_REGS_H_
   3
   4 #include "vc4_hdmi.h"
   5
   6 #define VC4_HDMI_PACKET_STRIDE                  0x24
   7
   8 enum vc4_hdmi_regs {
   9         VC4_INVALID = 0,
  10         VC4_HDMI,
  11         VC4_HD,
  12         VC5_CEC,
  13         VC5_CSC,
  14         VC5_DVP,
  15         VC5_PHY,
  16         VC5_RAM,
  17         VC5_RM,
  18 };
  19
  20 enum vc4_hdmi_field {
  21         HDMI_AUDIO_PACKET_CONFIG,
  22         HDMI_CEC_CNTRL_1,
  23         HDMI_CEC_CNTRL_2,
  24         HDMI_CEC_CNTRL_3,
  25         HDMI_CEC_CNTRL_4,
  26         HDMI_CEC_CNTRL_5,
  27         HDMI_CEC_CPU_CLEAR,
  28         HDMI_CEC_CPU_MASK_CLEAR,
  29         HDMI_CEC_CPU_MASK_SET,
  30         HDMI_CEC_CPU_MASK_STATUS,
  31         HDMI_CEC_CPU_STATUS,
  32         HDMI_CEC_CPU_SET,
  33
  34         /*
  35          * Transmit data, first byte is low byte of the 32-bit reg.
  36          * MSB of each byte transmitted first.
  37          */
  38         HDMI_CEC_RX_DATA_1,
  39         HDMI_CEC_RX_DATA_2,
  40         HDMI_CEC_RX_DATA_3,
  41         HDMI_CEC_RX_DATA_4,
  42         HDMI_CEC_TX_DATA_1,
  43         HDMI_CEC_TX_DATA_2,
  44         HDMI_CEC_TX_DATA_3,
  45         HDMI_CEC_TX_DATA_4,
  46         HDMI_CLOCK_STOP,
  47         HDMI_CORE_REV,
  48         HDMI_CRP_CFG,
  49         HDMI_CSC_12_11,
  50         HDMI_CSC_14_13,
  51         HDMI_CSC_22_21,
  52         HDMI_CSC_24_23,
  53         HDMI_CSC_32_31,
  54         HDMI_CSC_34_33,
  55         HDMI_CSC_CTL,
  56
  57         /*
  58          * 20-bit fields containing CTS values to be transmitted if
  59          * !EXTERNAL_CTS_EN
  60          */
  61         HDMI_CTS_0,
  62         HDMI_CTS_1,
  63         HDMI_DEEP_COLOR_CONFIG_1,
  64         HDMI_DVP_CTL,
  65         HDMI_FIFO_CTL,
  66         HDMI_FRAME_COUNT,
  67         HDMI_GCP_CONFIG,
  68         HDMI_GCP_WORD_1,
  69         HDMI_HORZA,
  70         HDMI_HORZB,
  71         HDMI_HOTPLUG,
  72         HDMI_HOTPLUG_INT,
  73
  74         /*
  75          * 3 bits per field, where each field maps from that
  76          * corresponding MAI bus channel to the given HDMI channel.
  77          */
  78         HDMI_MAI_CHANNEL_MAP,
  79         HDMI_MAI_CONFIG,
  80         HDMI_MAI_CTL,
  81
  82         /*
  83          * Register for DMAing in audio data to be transported over
  84          * the MAI bus to the Falcon core.
  85          */
  86         HDMI_MAI_DATA,
  87
  88         /* Format header to be placed on the MAI data. Unused. */
  89         HDMI_MAI_FMT,
  90
  91         /* Last received format word on the MAI bus. */
  92         HDMI_MAI_FORMAT,
  93         HDMI_MAI_SMP,
  94         HDMI_MAI_THR,
  95         HDMI_M_CTL,
  96         HDMI_RAM_PACKET_CONFIG,
  97         HDMI_RAM_PACKET_START,
  98         HDMI_RAM_PACKET_STATUS,
  99         HDMI_RM_CONTROL,
 100         HDMI_RM_FORMAT,
 101         HDMI_RM_OFFSET,
 102         HDMI_SCHEDULER_CONTROL,
 103         HDMI_SW_RESET_CONTROL,
 104         HDMI_TX_PHY_CHANNEL_SWAP,
 105         HDMI_TX_PHY_CLK_DIV,
 106         HDMI_TX_PHY_CTL_0,
 107         HDMI_TX_PHY_CTL_1,
 108         HDMI_TX_PHY_CTL_2,
 109         HDMI_TX_PHY_CTL_3,
 110         HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
 111         HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
 112         HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
 113         HDMI_TX_PHY_PLL_CFG,
 114         HDMI_TX_PHY_PLL_CTL_0,
 115         HDMI_TX_PHY_PLL_CTL_1,
 116         HDMI_TX_PHY_POWERDOWN_CTL,
 117         HDMI_TX_PHY_RESET_CTL,
 118         HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
 119         HDMI_VEC_INTERFACE_XBAR,
 120         HDMI_VERTA0,
 121         HDMI_VERTA1,
 122         HDMI_VERTB0,
 123         HDMI_VERTB1,
 124         HDMI_VID_CTL,
 125 };
 126
 127 struct vc4_hdmi_register {
 128         char *name;
 129         enum vc4_hdmi_regs reg;
 130         unsigned int offset;
 131 };
 132
 133 #define _VC4_REG(_base, _reg, _offset)  \
 134         [_reg] = {                              \
 135                 .name = #_reg,                  \
 136                 .reg = _base,                   \
 137                 .offset = _offset,              \
 138         }
 139
 140 #define VC4_HD_REG(reg, offset)         _VC4_REG(VC4_HD, reg, offset)
 141 #define VC4_HDMI_REG(reg, offset)       _VC4_REG(VC4_HDMI, reg, offset)
 142 #define VC5_CEC_REG(reg, offset)        _VC4_REG(VC5_CEC, reg, offset)
 143 #define VC5_CSC_REG(reg, offset)        _VC4_REG(VC5_CSC, reg, offset)
 144 #define VC5_DVP_REG(reg, offset)        _VC4_REG(VC5_DVP, reg, offset)
 145 #define VC5_PHY_REG(reg, offset)        _VC4_REG(VC5_PHY, reg, offset)
 146 #define VC5_RAM_REG(reg, offset)        _VC4_REG(VC5_RAM, reg, offset)
 147 #define VC5_RM_REG(reg, offset)         _VC4_REG(VC5_RM, reg, offset)
 148
 149 static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
 150         VC4_HD_REG(HDMI_M_CTL, 0x000c),
 151         VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
 152         VC4_HD_REG(HDMI_MAI_THR, 0x0018),
 153         VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
 154         VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
 155         VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
 156         VC4_HD_REG(HDMI_VID_CTL, 0x0038),
 157         VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
 158         VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
 159         VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
 160         VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
 161         VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
 162         VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
 163         VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
 164         VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
 165
 166         VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
 167         VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
 168         VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
 169         VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
 170         VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
 171         VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
 172         VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
 173         VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
 174         VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
 175         VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
 176         VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
 177         VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
 178         VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
 179         VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
 180         VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
 181         VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
 182         VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
 183         VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
 184         VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
 185         VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
 186         VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
 187         VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
 188         VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
 189         VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
 190         VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
 191         VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
 192         VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
 193         VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
 194         VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
 195         VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
 196         VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
 197         VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
 198         VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
 199         VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
 200         VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
 201         VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
 202         VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
 203         VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
 204         VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
 205         VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
 206         VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
 207         VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
 208         VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
 209 };
 210
 211 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
 212         VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
 213         VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
 214         VC4_HD_REG(HDMI_MAI_THR, 0x0014),
 215         VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
 216         VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
 217         VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
 218         VC4_HD_REG(HDMI_VID_CTL, 0x0044),
 219         VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
 220
 221         VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
 222         VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
 223         VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
 224         VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
 225         VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
 226         VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
 227         VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
 228         VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
 229         VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
 230         VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
 231         VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
 232         VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
 233         VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
 234         VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
 235         VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
 236         VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
 237         VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
 238         VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
 239         VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
 240         VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
 241
 242         VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
 243         VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
 244
 245         VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
 246         VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
 247         VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
 248         VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
 249         VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
 250         VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
 251         VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
 252         VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
 253         VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
 254         VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
 255         VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
 256         VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
 257         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
 258         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
 259         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
 260
 261         VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
 262         VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
 263         VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
 264
 265         VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
 266
 267         VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
 268         VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
 269         VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
 270         VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
 271         VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
 272         VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
 273         VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
 274         VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
 275         VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
 276         VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
 277         VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
 278         VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
 279         VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
 280
 281         VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
 282         VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
 283         VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
 284         VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
 285         VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
 286         VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
 287         VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
 288 };
 289
 290 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
 291         VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
 292         VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
 293         VC4_HD_REG(HDMI_MAI_THR, 0x0034),
 294         VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
 295         VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
 296         VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
 297         VC4_HD_REG(HDMI_VID_CTL, 0x0048),
 298         VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
 299
 300         VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
 301         VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
 302         VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
 303         VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
 304         VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
 305         VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
 306         VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
 307         VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
 308         VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
 309         VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
 310         VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
 311         VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
 312         VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
 313         VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
 314         VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
 315         VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
 316         VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
 317         VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
 318         VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
 319         VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
 320
 321         VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
 322         VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
 323
 324         VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
 325         VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
 326         VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
 327         VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
 328         VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
 329         VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
 330         VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
 331         VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
 332         VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
 333         VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
 334         VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
 335         VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
 336         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
 337         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
 338         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
 339
 340         VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
 341         VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
 342         VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
 343
 344         VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
 345
 346         VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
 347         VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
 348         VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
 349         VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
 350         VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
 351         VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
 352         VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
 353         VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
 354         VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
 355         VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
 356         VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
 357         VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
 358         VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
 359
 360         VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
 361         VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
 362         VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
 363         VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
 364         VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
 365         VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
 366         VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
 367 };
 368
 369 static inline
 370 void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
 371                                         enum vc4_hdmi_regs reg)
 372 {
 373         switch (reg) {
 374         case VC4_HD:
 375                 return hdmi->hd_regs;
 376
 377         case VC4_HDMI:
 378                 return hdmi->hdmicore_regs;
 379
 380         case VC5_CSC:
 381                 return hdmi->csc_regs;
 382
 383         case VC5_CEC:
 384                 return hdmi->cec_regs;
 385
 386         case VC5_DVP:
 387                 return hdmi->dvp_regs;
 388
 389         case VC5_PHY:
 390                 return hdmi->phy_regs;
 391
 392         case VC5_RAM:
 393                 return hdmi->ram_regs;
 394
 395         case VC5_RM:
 396                 return hdmi->rm_regs;
 397
 398         default:
 399                 return NULL;
 400         }
 401
 402         return NULL;
 403 }
 404
 405 static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
 406                                 enum vc4_hdmi_field reg)
 407 {
 408         const struct vc4_hdmi_register *field;
 409         const struct vc4_hdmi_variant *variant = hdmi->variant;
 410         void __iomem *base;
 411
 412         if (reg >= variant->num_registers) {
 413                 dev_warn(&hdmi->pdev->dev,
 414                          "Invalid register ID %u\n", reg);
 415                 return 0;
 416         }
 417
 418         field = &variant->registers[reg];
 419         base = __vc4_hdmi_get_field_base(hdmi, field->reg);
 420         if (!base) {
 421                 dev_warn(&hdmi->pdev->dev,
 422                          "Unknown register ID %u\n", reg);
 423                 return 0;
 424         }
 425
 426         return readl(base + field->offset);
 427 }
 428 #define HDMI_READ(reg)          vc4_hdmi_read(vc4_hdmi, reg)
 429
 430 static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
 431                                   enum vc4_hdmi_field reg,
 432                                   u32 value)
 433 {
 434         const struct vc4_hdmi_register *field;
 435         const struct vc4_hdmi_variant *variant = hdmi->variant;
 436         void __iomem *base;
 437
 438         if (reg >= variant->num_registers) {
 439                 dev_warn(&hdmi->pdev->dev,
 440                          "Invalid register ID %u\n", reg);
 441                 return;
 442         }
 443
 444         field = &variant->registers[reg];
 445         base = __vc4_hdmi_get_field_base(hdmi, field->reg);
 446         if (!base)
 447                 return;
 448
 449         writel(value, base + field->offset);
 450 }
 451 #define HDMI_WRITE(reg, val)    vc4_hdmi_write(vc4_hdmi, reg, val)
 452
 453 #endif /* _VC4_HDMI_REGS_H_ */