drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <[email protected]>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Dave Airlie <[email protected]>
  27  *      Jesse Barnes <[email protected]>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47
  48         struct notifier_block lid_notifier;
  49 };
  50
  51 struct intel_lvds_pps {
  52         /* 100us units */
  53         int t1_t2;
  54         int t3;
  55         int t4;
  56         int t5;
  57         int tx;
  58
  59         int divider;
  60
  61         int port;
  62         bool powerdown_on_reset;
  63 };
  64
  65 struct intel_lvds_encoder {
  66         struct intel_encoder base;
  67
  68         bool is_dual_link;
  69         i915_reg_t reg;
  70         u32 a3_power;
  71
  72         struct intel_lvds_pps init_pps;
  73         u32 init_lvds_val;
  74
  75         struct intel_lvds_connector *attached_connector;
  76 };
  77
  78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  79 {
  80         return container_of(encoder, struct intel_lvds_encoder, base.base);
  81 }
  82
  83 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  84 {
  85         return container_of(connector, struct intel_lvds_connector, base.base);
  86 }
  87
  88 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  89                                     enum pipe *pipe)
  90 {
  91         struct drm_device *dev = encoder->base.dev;
  92         struct drm_i915_private *dev_priv = to_i915(dev);
  93         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  94         u32 tmp;
  95         bool ret;
  96
  97         if (!intel_display_power_get_if_enabled(dev_priv,
  98                                                 encoder->power_domain))
  99                 return false;
 100
 101         ret = false;
 102
 103         tmp = I915_READ(lvds_encoder->reg);
 104
 105         if (!(tmp & LVDS_PORT_EN))
 106                 goto out;
 107
 108         if (HAS_PCH_CPT(dev_priv))
 109                 *pipe = PORT_TO_PIPE_CPT(tmp);
 110         else
 111                 *pipe = PORT_TO_PIPE(tmp);
 112
 113         ret = true;
 114
 115 out:
 116         intel_display_power_put(dev_priv, encoder->power_domain);
 117
 118         return ret;
 119 }
 120
 121 static void intel_lvds_get_config(struct intel_encoder *encoder,
 122                                   struct intel_crtc_state *pipe_config)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 125         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 126         u32 tmp, flags = 0;
 127
 128         tmp = I915_READ(lvds_encoder->reg);
 129         if (tmp & LVDS_HSYNC_POLARITY)
 130                 flags |= DRM_MODE_FLAG_NHSYNC;
 131         else
 132                 flags |= DRM_MODE_FLAG_PHSYNC;
 133         if (tmp & LVDS_VSYNC_POLARITY)
 134                 flags |= DRM_MODE_FLAG_NVSYNC;
 135         else
 136                 flags |= DRM_MODE_FLAG_PVSYNC;
 137
 138         pipe_config->base.adjusted_mode.flags |= flags;
 139
 140         if (INTEL_GEN(dev_priv) < 5)
 141                 pipe_config->gmch_pfit.lvds_border_bits =
 142                         tmp & LVDS_BORDER_ENABLE;
 143
 144         /* gen2/3 store dither state in pfit control, needs to match */
 145         if (INTEL_GEN(dev_priv) < 4) {
 146                 tmp = I915_READ(PFIT_CONTROL);
 147
 148                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 149         }
 150
 151         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 152 }
 153
 154 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 155                                         struct intel_lvds_pps *pps)
 156 {
 157         u32 val;
 158
 159         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 160
 161         val = I915_READ(PP_ON_DELAYS(0));
 162         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 163                     PANEL_PORT_SELECT_SHIFT;
 164         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 165                      PANEL_POWER_UP_DELAY_SHIFT;
 166         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 167                   PANEL_LIGHT_ON_DELAY_SHIFT;
 168
 169         val = I915_READ(PP_OFF_DELAYS(0));
 170         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 171                   PANEL_POWER_DOWN_DELAY_SHIFT;
 172         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 173                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 174
 175         val = I915_READ(PP_DIVISOR(0));
 176         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 177                        PP_REFERENCE_DIVIDER_SHIFT;
 178         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 179               PANEL_POWER_CYCLE_DELAY_SHIFT;
 180         /*
 181          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 182          * too short power-cycle delay due to the asynchronous programming of
 183          * the register.
 184          */
 185         if (val)
 186                 val--;
 187         /* Convert from 100ms to 100us units */
 188         pps->t4 = val * 1000;
 189
 190         if (INTEL_INFO(dev_priv)->gen <= 4 &&
 191             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 192                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 193                               "setting defaults\n");
 194                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 195                 pps->t1_t2 = 40 * 10;
 196                 pps->t5 = 200 * 10;
 197                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 198                 pps->t3 = 35 * 10;
 199                 pps->tx = 200 * 10;
 200         }
 201
 202         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 203                          "divider %d port %d powerdown_on_reset %d\n",
 204                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 205                          pps->divider, pps->port, pps->powerdown_on_reset);
 206 }
 207
 208 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 209                                    struct intel_lvds_pps *pps)
 210 {
 211         u32 val;
 212
 213         val = I915_READ(PP_CONTROL(0));
 214         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 215         if (pps->powerdown_on_reset)
 216                 val |= PANEL_POWER_RESET;
 217         I915_WRITE(PP_CONTROL(0), val);
 218
 219         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 220                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 221                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 222         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 223                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 224
 225         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 226         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 227                PANEL_POWER_CYCLE_DELAY_SHIFT;
 228         I915_WRITE(PP_DIVISOR(0), val);
 229 }
 230
 231 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 232                                   struct intel_crtc_state *pipe_config,
 233                                   struct drm_connector_state *conn_state)
 234 {
 235         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 236         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 237         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 238         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 239         int pipe = crtc->pipe;
 240         u32 temp;
 241
 242         if (HAS_PCH_SPLIT(dev_priv)) {
 243                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 244                 assert_shared_dpll_disabled(dev_priv,
 245                                             pipe_config->shared_dpll);
 246         } else {
 247                 assert_pll_disabled(dev_priv, pipe);
 248         }
 249
 250         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 251
 252         temp = lvds_encoder->init_lvds_val;
 253         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 254
 255         if (HAS_PCH_CPT(dev_priv)) {
 256                 temp &= ~PORT_TRANS_SEL_MASK;
 257                 temp |= PORT_TRANS_SEL_CPT(pipe);
 258         } else {
 259                 if (pipe == 1) {
 260                         temp |= LVDS_PIPEB_SELECT;
 261                 } else {
 262                         temp &= ~LVDS_PIPEB_SELECT;
 263                 }
 264         }
 265
 266         /* set the corresponsding LVDS_BORDER bit */
 267         temp &= ~LVDS_BORDER_ENABLE;
 268         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 269         /* Set the B0-B3 data pairs corresponding to whether we're going to
 270          * set the DPLLs for dual-channel mode or not.
 271          */
 272         if (lvds_encoder->is_dual_link)
 273                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 274         else
 275                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 276
 277         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 278          * appropriately here, but we need to look more thoroughly into how
 279          * panels behave in the two modes. For now, let's just maintain the
 280          * value we got from the BIOS.
 281          */
 282         temp &= ~LVDS_A3_POWER_MASK;
 283         temp |= lvds_encoder->a3_power;
 284
 285         /* Set the dithering flag on LVDS as needed, note that there is no
 286          * special lvds dither control bit on pch-split platforms, dithering is
 287          * only controlled through the PIPECONF reg. */
 288         if (IS_GEN4(dev_priv)) {
 289                 /* Bspec wording suggests that LVDS port dithering only exists
 290                  * for 18bpp panels. */
 291                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 292                         temp |= LVDS_ENABLE_DITHER;
 293                 else
 294                         temp &= ~LVDS_ENABLE_DITHER;
 295         }
 296         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 297         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 298                 temp |= LVDS_HSYNC_POLARITY;
 299         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 300                 temp |= LVDS_VSYNC_POLARITY;
 301
 302         I915_WRITE(lvds_encoder->reg, temp);
 303 }
 304
 305 /**
 306  * Sets the power state for the panel.
 307  */
 308 static void intel_enable_lvds(struct intel_encoder *encoder,
 309                               struct intel_crtc_state *pipe_config,
 310                               struct drm_connector_state *conn_state)
 311 {
 312         struct drm_device *dev = encoder->base.dev;
 313         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 314         struct drm_i915_private *dev_priv = to_i915(dev);
 315
 316         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 317
 318         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 319         POSTING_READ(lvds_encoder->reg);
 320         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
 321                 DRM_ERROR("timed out waiting for panel to power on\n");
 322
 323         intel_panel_enable_backlight(pipe_config, conn_state);
 324 }
 325
 326 static void intel_disable_lvds(struct intel_encoder *encoder,
 327                                struct intel_crtc_state *old_crtc_state,
 328                                struct drm_connector_state *old_conn_state)
 329 {
 330         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 331         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 332
 333         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 334         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 335                 DRM_ERROR("timed out waiting for panel to power off\n");
 336
 337         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 338         POSTING_READ(lvds_encoder->reg);
 339 }
 340
 341 static void gmch_disable_lvds(struct intel_encoder *encoder,
 342                               struct intel_crtc_state *old_crtc_state,
 343                               struct drm_connector_state *old_conn_state)
 344
 345 {
 346         intel_panel_disable_backlight(old_conn_state);
 347
 348         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 349 }
 350
 351 static void pch_disable_lvds(struct intel_encoder *encoder,
 352                              struct intel_crtc_state *old_crtc_state,
 353                              struct drm_connector_state *old_conn_state)
 354 {
 355         intel_panel_disable_backlight(old_conn_state);
 356 }
 357
 358 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 359                                   struct intel_crtc_state *old_crtc_state,
 360                                   struct drm_connector_state *old_conn_state)
 361 {
 362         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 363 }
 364
 365 static enum drm_mode_status
 366 intel_lvds_mode_valid(struct drm_connector *connector,
 367                       struct drm_display_mode *mode)
 368 {
 369         struct intel_connector *intel_connector = to_intel_connector(connector);
 370         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 371         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 372
 373         if (mode->hdisplay > fixed_mode->hdisplay)
 374                 return MODE_PANEL;
 375         if (mode->vdisplay > fixed_mode->vdisplay)
 376                 return MODE_PANEL;
 377         if (fixed_mode->clock > max_pixclk)
 378                 return MODE_CLOCK_HIGH;
 379
 380         return MODE_OK;
 381 }
 382
 383 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 384                                       struct intel_crtc_state *pipe_config,
 385                                       struct drm_connector_state *conn_state)
 386 {
 387         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 388         struct intel_lvds_encoder *lvds_encoder =
 389                 to_lvds_encoder(&intel_encoder->base);
 390         struct intel_connector *intel_connector =
 391                 &lvds_encoder->attached_connector->base;
 392         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 393         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 394         unsigned int lvds_bpp;
 395
 396         /* Should never happen!! */
 397         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 398                 DRM_ERROR("Can't support LVDS on pipe A\n");
 399                 return false;
 400         }
 401
 402         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 403                 lvds_bpp = 8*3;
 404         else
 405                 lvds_bpp = 6*3;
 406
 407         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 408                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 409                               pipe_config->pipe_bpp, lvds_bpp);
 410                 pipe_config->pipe_bpp = lvds_bpp;
 411         }
 412
 413         /*
 414          * We have timings from the BIOS for the panel, put them in
 415          * to the adjusted mode.  The CRTC will be set up for this mode,
 416          * with the panel scaling set up to source from the H/VDisplay
 417          * of the original mode.
 418          */
 419         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 420                                adjusted_mode);
 421
 422         if (HAS_PCH_SPLIT(dev_priv)) {
 423                 pipe_config->has_pch_encoder = true;
 424
 425                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 426                                         conn_state->scaling_mode);
 427         } else {
 428                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 429                                          conn_state->scaling_mode);
 430
 431         }
 432
 433         /*
 434          * XXX: It would be nice to support lower refresh rates on the
 435          * panels to reduce power consumption, and perhaps match the
 436          * user's requested refresh rate.
 437          */
 438
 439         return true;
 440 }
 441
 442 /**
 443  * Detect the LVDS connection.
 444  *
 445  * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means
 446  * connected and closed means disconnected.  We also send hotplug events as
 447  * needed, using lid status notification from the input layer.
 448  */
 449 static enum drm_connector_status
 450 intel_lvds_detect(struct drm_connector *connector, bool force)
 451 {
 452         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 453         enum drm_connector_status status;
 454
 455         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 456                       connector->base.id, connector->name);
 457
 458         status = intel_panel_detect(dev_priv);
 459         if (status != connector_status_unknown)
 460                 return status;
 461
 462         return connector_status_connected;
 463 }
 464
 465 /**
 466  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 467  */
 468 static int intel_lvds_get_modes(struct drm_connector *connector)
 469 {
 470         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 471         struct drm_device *dev = connector->dev;
 472         struct drm_display_mode *mode;
 473
 474         /* use cached edid if we have one */
 475         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 476                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 477
 478         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 479         if (mode == NULL)
 480                 return 0;
 481
 482         drm_mode_probed_add(connector, mode);
 483         return 1;
 484 }
 485
 486 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
 487 {
 488         DRM_INFO("Skipping forced modeset for %s\n", id->ident);
 489         return 1;
 490 }
 491
 492 /* The GPU hangs up on these systems if modeset is performed on LID open */
 493 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
 494         {
 495                 .callback = intel_no_modeset_on_lid_dmi_callback,
 496                 .ident = "Toshiba Tecra A11",
 497                 .matches = {
 498                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 499                         DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
 500                 },
 501         },
 502
 503         { }     /* terminating entry */
 504 };
 505
 506 /*
 507  * Lid events. Note the use of 'modeset':
 508  *  - we set it to MODESET_ON_LID_OPEN on lid close,
 509  *    and set it to MODESET_DONE on open
 510  *  - we use it as a "only once" bit (ie we ignore
 511  *    duplicate events where it was already properly set)
 512  *  - the suspend/resume paths will set it to
 513  *    MODESET_SUSPENDED and ignore the lid open event,
 514  *    because they restore the mode ("lid open").
 515  */
 516 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
 517                             void *unused)
 518 {
 519         struct intel_lvds_connector *lvds_connector =
 520                 container_of(nb, struct intel_lvds_connector, lid_notifier);
 521         struct drm_connector *connector = &lvds_connector->base.base;
 522         struct drm_device *dev = connector->dev;
 523         struct drm_i915_private *dev_priv = to_i915(dev);
 524
 525         if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
 526                 return NOTIFY_OK;
 527
 528         mutex_lock(&dev_priv->modeset_restore_lock);
 529         if (dev_priv->modeset_restore == MODESET_SUSPENDED)
 530                 goto exit;
 531         /*
 532          * check and update the status of LVDS connector after receiving
 533          * the LID nofication event.
 534          */
 535         connector->status = connector->funcs->detect(connector, false);
 536
 537         /* Don't force modeset on machines where it causes a GPU lockup */
 538         if (dmi_check_system(intel_no_modeset_on_lid))
 539                 goto exit;
 540         if (!acpi_lid_open()) {
 541                 /* do modeset on next lid open event */
 542                 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
 543                 goto exit;
 544         }
 545
 546         if (dev_priv->modeset_restore == MODESET_DONE)
 547                 goto exit;
 548
 549         /*
 550          * Some old platform's BIOS love to wreak havoc while the lid is closed.
 551          * We try to detect this here and undo any damage. The split for PCH
 552          * platforms is rather conservative and a bit arbitrary expect that on
 553          * those platforms VGA disabling requires actual legacy VGA I/O access,
 554          * and as part of the cleanup in the hw state restore we also redisable
 555          * the vga plane.
 556          */
 557         if (!HAS_PCH_SPLIT(dev_priv))
 558                 intel_display_resume(dev);
 559
 560         dev_priv->modeset_restore = MODESET_DONE;
 561
 562 exit:
 563         mutex_unlock(&dev_priv->modeset_restore_lock);
 564         return NOTIFY_OK;
 565 }
 566
 567 /**
 568  * intel_lvds_destroy - unregister and free LVDS structures
 569  * @connector: connector to free
 570  *
 571  * Unregister the DDC bus for this connector then free the driver private
 572  * structure.
 573  */
 574 static void intel_lvds_destroy(struct drm_connector *connector)
 575 {
 576         struct intel_lvds_connector *lvds_connector =
 577                 to_lvds_connector(connector);
 578
 579         if (lvds_connector->lid_notifier.notifier_call)
 580                 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
 581
 582         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 583                 kfree(lvds_connector->base.edid);
 584
 585         intel_panel_fini(&lvds_connector->base.panel);
 586
 587         drm_connector_cleanup(connector);
 588         kfree(connector);
 589 }
 590
 591 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 592         .get_modes = intel_lvds_get_modes,
 593         .mode_valid = intel_lvds_mode_valid,
 594         .atomic_check = intel_digital_connector_atomic_check,
 595 };
 596
 597 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 598         .detect = intel_lvds_detect,
 599         .fill_modes = drm_helper_probe_single_connector_modes,
 600         .atomic_get_property = intel_digital_connector_atomic_get_property,
 601         .atomic_set_property = intel_digital_connector_atomic_set_property,
 602         .late_register = intel_connector_register,
 603         .early_unregister = intel_connector_unregister,
 604         .destroy = intel_lvds_destroy,
 605         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 606         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 607 };
 608
 609 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 610         .destroy = intel_encoder_destroy,
 611 };
 612
 613 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 614 {
 615         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 616         return 1;
 617 }
 618
 619 /* These systems claim to have LVDS, but really don't */
 620 static const struct dmi_system_id intel_no_lvds[] = {
 621         {
 622                 .callback = intel_no_lvds_dmi_callback,
 623                 .ident = "Apple Mac Mini (Core series)",
 624                 .matches = {
 625                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 626                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 627                 },
 628         },
 629         {
 630                 .callback = intel_no_lvds_dmi_callback,
 631                 .ident = "Apple Mac Mini (Core 2 series)",
 632                 .matches = {
 633                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 634                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 635                 },
 636         },
 637         {
 638                 .callback = intel_no_lvds_dmi_callback,
 639                 .ident = "MSI IM-945GSE-A",
 640                 .matches = {
 641                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 642                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 643                 },
 644         },
 645         {
 646                 .callback = intel_no_lvds_dmi_callback,
 647                 .ident = "Dell Studio Hybrid",
 648                 .matches = {
 649                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 650                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 651                 },
 652         },
 653         {
 654                 .callback = intel_no_lvds_dmi_callback,
 655                 .ident = "Dell OptiPlex FX170",
 656                 .matches = {
 657                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 658                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 659                 },
 660         },
 661         {
 662                 .callback = intel_no_lvds_dmi_callback,
 663                 .ident = "AOpen Mini PC",
 664                 .matches = {
 665                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 666                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 667                 },
 668         },
 669         {
 670                 .callback = intel_no_lvds_dmi_callback,
 671                 .ident = "AOpen Mini PC MP915",
 672                 .matches = {
 673                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 674                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 675                 },
 676         },
 677         {
 678                 .callback = intel_no_lvds_dmi_callback,
 679                 .ident = "AOpen i915GMm-HFS",
 680                 .matches = {
 681                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 682                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 683                 },
 684         },
 685         {
 686                 .callback = intel_no_lvds_dmi_callback,
 687                 .ident = "AOpen i45GMx-I",
 688                 .matches = {
 689                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 690                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 691                 },
 692         },
 693         {
 694                 .callback = intel_no_lvds_dmi_callback,
 695                 .ident = "Aopen i945GTt-VFA",
 696                 .matches = {
 697                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 698                 },
 699         },
 700         {
 701                 .callback = intel_no_lvds_dmi_callback,
 702                 .ident = "Clientron U800",
 703                 .matches = {
 704                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 705                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 706                 },
 707         },
 708         {
 709                 .callback = intel_no_lvds_dmi_callback,
 710                 .ident = "Clientron E830",
 711                 .matches = {
 712                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 713                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 714                 },
 715         },
 716         {
 717                 .callback = intel_no_lvds_dmi_callback,
 718                 .ident = "Asus EeeBox PC EB1007",
 719                 .matches = {
 720                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 721                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 722                 },
 723         },
 724         {
 725                 .callback = intel_no_lvds_dmi_callback,
 726                 .ident = "Asus AT5NM10T-I",
 727                 .matches = {
 728                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 729                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 730                 },
 731         },
 732         {
 733                 .callback = intel_no_lvds_dmi_callback,
 734                 .ident = "Hewlett-Packard HP t5740",
 735                 .matches = {
 736                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 737                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 738                 },
 739         },
 740         {
 741                 .callback = intel_no_lvds_dmi_callback,
 742                 .ident = "Hewlett-Packard t5745",
 743                 .matches = {
 744                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 745                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 746                 },
 747         },
 748         {
 749                 .callback = intel_no_lvds_dmi_callback,
 750                 .ident = "Hewlett-Packard st5747",
 751                 .matches = {
 752                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 753                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 754                 },
 755         },
 756         {
 757                 .callback = intel_no_lvds_dmi_callback,
 758                 .ident = "MSI Wind Box DC500",
 759                 .matches = {
 760                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 761                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 762                 },
 763         },
 764         {
 765                 .callback = intel_no_lvds_dmi_callback,
 766                 .ident = "Gigabyte GA-D525TUD",
 767                 .matches = {
 768                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 769                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 770                 },
 771         },
 772         {
 773                 .callback = intel_no_lvds_dmi_callback,
 774                 .ident = "Supermicro X7SPA-H",
 775                 .matches = {
 776                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 777                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 778                 },
 779         },
 780         {
 781                 .callback = intel_no_lvds_dmi_callback,
 782                 .ident = "Fujitsu Esprimo Q900",
 783                 .matches = {
 784                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 785                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 786                 },
 787         },
 788         {
 789                 .callback = intel_no_lvds_dmi_callback,
 790                 .ident = "Intel D410PT",
 791                 .matches = {
 792                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 793                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 794                 },
 795         },
 796         {
 797                 .callback = intel_no_lvds_dmi_callback,
 798                 .ident = "Intel D425KT",
 799                 .matches = {
 800                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 801                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 802                 },
 803         },
 804         {
 805                 .callback = intel_no_lvds_dmi_callback,
 806                 .ident = "Intel D510MO",
 807                 .matches = {
 808                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 809                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 810                 },
 811         },
 812         {
 813                 .callback = intel_no_lvds_dmi_callback,
 814                 .ident = "Intel D525MW",
 815                 .matches = {
 816                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 817                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 818                 },
 819         },
 820
 821         { }     /* terminating entry */
 822 };
 823
 824 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 825 {
 826         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 827         return 1;
 828 }
 829
 830 static const struct dmi_system_id intel_dual_link_lvds[] = {
 831         {
 832                 .callback = intel_dual_link_lvds_callback,
 833                 .ident = "Apple MacBook Pro 15\" (2010)",
 834                 .matches = {
 835                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 836                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 837                 },
 838         },
 839         {
 840                 .callback = intel_dual_link_lvds_callback,
 841                 .ident = "Apple MacBook Pro 15\" (2011)",
 842                 .matches = {
 843                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 844                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 845                 },
 846         },
 847         {
 848                 .callback = intel_dual_link_lvds_callback,
 849                 .ident = "Apple MacBook Pro 15\" (2012)",
 850                 .matches = {
 851                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 852                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 853                 },
 854         },
 855         { }     /* terminating entry */
 856 };
 857
 858 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 859 {
 860         struct intel_encoder *intel_encoder;
 861
 862         for_each_intel_encoder(dev, intel_encoder)
 863                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 864                         return intel_encoder;
 865
 866         return NULL;
 867 }
 868
 869 bool intel_is_dual_link_lvds(struct drm_device *dev)
 870 {
 871         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 872
 873         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 874 }
 875
 876 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 877 {
 878         struct drm_device *dev = lvds_encoder->base.base.dev;
 879         unsigned int val;
 880         struct drm_i915_private *dev_priv = to_i915(dev);
 881
 882         /* use the module option value if specified */
 883         if (i915.lvds_channel_mode > 0)
 884                 return i915.lvds_channel_mode == 2;
 885
 886         /* single channel LVDS is limited to 112 MHz */
 887         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 888             > 112999)
 889                 return true;
 890
 891         if (dmi_check_system(intel_dual_link_lvds))
 892                 return true;
 893
 894         /* BIOS should set the proper LVDS register value at boot, but
 895          * in reality, it doesn't set the value when the lid is closed;
 896          * we need to check "the value to be set" in VBT when LVDS
 897          * register is uninitialized.
 898          */
 899         val = I915_READ(lvds_encoder->reg);
 900         if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 901                 val = dev_priv->vbt.bios_lvds_val;
 902
 903         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 904 }
 905
 906 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 907 {
 908         /* With the introduction of the PCH we gained a dedicated
 909          * LVDS presence pin, use it. */
 910         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 911                 return true;
 912
 913         /* Otherwise LVDS was only attached to mobile products,
 914          * except for the inglorious 830gm */
 915         if (INTEL_GEN(dev_priv) <= 4 &&
 916             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 917                 return true;
 918
 919         return false;
 920 }
 921
 922 /**
 923  * intel_lvds_init - setup LVDS connectors on this device
 924  * @dev: drm device
 925  *
 926  * Create the connector, register the LVDS DDC bus, and try to figure out what
 927  * modes we can display on the LVDS panel (if present).
 928  */
 929 void intel_lvds_init(struct drm_i915_private *dev_priv)
 930 {
 931         struct drm_device *dev = &dev_priv->drm;
 932         struct intel_lvds_encoder *lvds_encoder;
 933         struct intel_encoder *intel_encoder;
 934         struct intel_lvds_connector *lvds_connector;
 935         struct intel_connector *intel_connector;
 936         struct drm_connector *connector;
 937         struct drm_encoder *encoder;
 938         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 939         struct drm_display_mode *fixed_mode = NULL;
 940         struct drm_display_mode *downclock_mode = NULL;
 941         struct edid *edid;
 942         struct intel_crtc *crtc;
 943         i915_reg_t lvds_reg;
 944         u32 lvds;
 945         int pipe;
 946         u8 pin;
 947         u32 allowed_scalers;
 948
 949         if (!intel_lvds_supported(dev_priv))
 950                 return;
 951
 952         /* Skip init on machines we know falsely report LVDS */
 953         if (dmi_check_system(intel_no_lvds))
 954                 return;
 955
 956         if (HAS_PCH_SPLIT(dev_priv))
 957                 lvds_reg = PCH_LVDS;
 958         else
 959                 lvds_reg = LVDS;
 960
 961         lvds = I915_READ(lvds_reg);
 962
 963         if (HAS_PCH_SPLIT(dev_priv)) {
 964                 if ((lvds & LVDS_DETECTED) == 0)
 965                         return;
 966                 if (dev_priv->vbt.edp.support) {
 967                         DRM_DEBUG_KMS("disable LVDS for eDP support\n");
 968                         return;
 969                 }
 970         }
 971
 972         pin = GMBUS_PIN_PANEL;
 973         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 974                 if ((lvds & LVDS_PORT_EN) == 0) {
 975                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 976                         return;
 977                 }
 978                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
 979         }
 980
 981         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 982         if (!lvds_encoder)
 983                 return;
 984
 985         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
 986         if (!lvds_connector) {
 987                 kfree(lvds_encoder);
 988                 return;
 989         }
 990
 991         if (intel_connector_init(&lvds_connector->base) < 0) {
 992                 kfree(lvds_connector);
 993                 kfree(lvds_encoder);
 994                 return;
 995         }
 996
 997         lvds_encoder->attached_connector = lvds_connector;
 998
 999         intel_encoder = &lvds_encoder->base;
1000         encoder = &intel_encoder->base;
1001         intel_connector = &lvds_connector->base;
1002         connector = &intel_connector->base;
1003         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1004                            DRM_MODE_CONNECTOR_LVDS);
1005
1006         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1007                          DRM_MODE_ENCODER_LVDS, "LVDS");
1008
1009         intel_encoder->enable = intel_enable_lvds;
1010         intel_encoder->pre_enable = intel_pre_enable_lvds;
1011         intel_encoder->compute_config = intel_lvds_compute_config;
1012         if (HAS_PCH_SPLIT(dev_priv)) {
1013                 intel_encoder->disable = pch_disable_lvds;
1014                 intel_encoder->post_disable = pch_post_disable_lvds;
1015         } else {
1016                 intel_encoder->disable = gmch_disable_lvds;
1017         }
1018         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1019         intel_encoder->get_config = intel_lvds_get_config;
1020         intel_connector->get_hw_state = intel_connector_get_hw_state;
1021
1022         intel_connector_attach_encoder(intel_connector, intel_encoder);
1023
1024         intel_encoder->type = INTEL_OUTPUT_LVDS;
1025         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1026         intel_encoder->port = PORT_NONE;
1027         intel_encoder->cloneable = 0;
1028         if (HAS_PCH_SPLIT(dev_priv))
1029                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1030         else if (IS_GEN4(dev_priv))
1031                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1032         else
1033                 intel_encoder->crtc_mask = (1 << 1);
1034
1035         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1036         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1037         connector->interlace_allowed = false;
1038         connector->doublescan_allowed = false;
1039
1040         lvds_encoder->reg = lvds_reg;
1041
1042         /* create the scaling mode property */
1043         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
1044         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
1045         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1046         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
1047         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1048
1049         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
1050         lvds_encoder->init_lvds_val = lvds;
1051
1052         /*
1053          * LVDS discovery:
1054          * 1) check for EDID on DDC
1055          * 2) check for VBT data
1056          * 3) check to see if LVDS is already on
1057          *    if none of the above, no panel
1058          * 4) make sure lid is open
1059          *    if closed, act like it's not there for now
1060          */
1061
1062         /*
1063          * Attempt to get the fixed panel mode from DDC.  Assume that the
1064          * preferred mode is the right one.
1065          */
1066         mutex_lock(&dev->mode_config.mutex);
1067         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1068                 edid = drm_get_edid_switcheroo(connector,
1069                                     intel_gmbus_get_adapter(dev_priv, pin));
1070         else
1071                 edid = drm_get_edid(connector,
1072                                     intel_gmbus_get_adapter(dev_priv, pin));
1073         if (edid) {
1074                 if (drm_add_edid_modes(connector, edid)) {
1075                         drm_mode_connector_update_edid_property(connector,
1076                                                                 edid);
1077                 } else {
1078                         kfree(edid);
1079                         edid = ERR_PTR(-EINVAL);
1080                 }
1081         } else {
1082                 edid = ERR_PTR(-ENOENT);
1083         }
1084         lvds_connector->base.edid = edid;
1085
1086         list_for_each_entry(scan, &connector->probed_modes, head) {
1087                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1088                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
1089                         drm_mode_debug_printmodeline(scan);
1090
1091                         fixed_mode = drm_mode_duplicate(dev, scan);
1092                         if (fixed_mode)
1093                                 goto out;
1094                 }
1095         }
1096
1097         /* Failed to get EDID, what about VBT? */
1098         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1099                 DRM_DEBUG_KMS("using mode from VBT: ");
1100                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1101
1102                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1103                 if (fixed_mode) {
1104                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1105                         connector->display_info.width_mm = fixed_mode->width_mm;
1106                         connector->display_info.height_mm = fixed_mode->height_mm;
1107                         goto out;
1108                 }
1109         }
1110
1111         /*
1112          * If we didn't get EDID, try checking if the panel is already turned
1113          * on.  If so, assume that whatever is currently programmed is the
1114          * correct mode.
1115          */
1116
1117         /* Ironlake: FIXME if still fail, not try pipe mode now */
1118         if (HAS_PCH_SPLIT(dev_priv))
1119                 goto failed;
1120
1121         pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1122         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1123
1124         if (crtc && (lvds & LVDS_PORT_EN)) {
1125                 fixed_mode = intel_crtc_mode_get(dev, &crtc->base);
1126                 if (fixed_mode) {
1127                         DRM_DEBUG_KMS("using current (BIOS) mode: ");
1128                         drm_mode_debug_printmodeline(fixed_mode);
1129                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1130                         goto out;
1131                 }
1132         }
1133
1134         /* If we still don't have a mode after all that, give up. */
1135         if (!fixed_mode)
1136                 goto failed;
1137
1138 out:
1139         mutex_unlock(&dev->mode_config.mutex);
1140
1141         intel_panel_init(&intel_connector->panel, fixed_mode, NULL,
1142                          downclock_mode);
1143         intel_panel_setup_backlight(connector, INVALID_PIPE);
1144
1145         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1146         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1147                       lvds_encoder->is_dual_link ? "dual" : "single");
1148
1149         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1150
1151         lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1152         if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
1153                 DRM_DEBUG_KMS("lid notifier registration failed\n");
1154                 lvds_connector->lid_notifier.notifier_call = NULL;
1155         }
1156
1157         return;
1158
1159 failed:
1160         mutex_unlock(&dev->mode_config.mutex);
1161
1162         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1163         drm_connector_cleanup(connector);
1164         drm_encoder_cleanup(encoder);
1165         kfree(lvds_encoder);
1166         kfree(lvds_connector);
1167         return;
1168 }