drivers/cpufreq/qcom-cpufreq-nvmem.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 /*
   7  * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
   8  * the CPU frequency subset and voltage value of each OPP varies
   9  * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
  10  * defines the voltage and frequency value based on the msm-id in SMEM
  11  * and speedbin blown in the efuse combination.
  12  * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
  13  * to provide the OPP framework with required information.
  14  * This is used to determine the voltage and frequency value for each OPP of
  15  * operating-points-v2 table when it is parsed by the OPP framework.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/nvmem-consumer.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_domain.h>
  27 #include <linux/pm_opp.h>
  28 #include <linux/slab.h>
  29 #include <linux/soc/qcom/smem.h>
  30
  31 #include <dt-bindings/arm/qcom,ids.h>
  32
  33 enum ipq806x_versions {
  34         IPQ8062_VERSION = 0,
  35         IPQ8064_VERSION,
  36         IPQ8065_VERSION,
  37 };
  38
  39 #define IPQ6000_VERSION BIT(2)
  40
  41 struct qcom_cpufreq_drv;
  42
  43 struct qcom_cpufreq_match_data {
  44         int (*get_version)(struct device *cpu_dev,
  45                            struct nvmem_cell *speedbin_nvmem,
  46                            char **pvs_name,
  47                            struct qcom_cpufreq_drv *drv);
  48         const char **genpd_names;
  49 };
  50
  51 struct qcom_cpufreq_drv_cpu {
  52         int opp_token;
  53 };
  54
  55 struct qcom_cpufreq_drv {
  56         u32 versions;
  57         const struct qcom_cpufreq_match_data *data;
  58         struct qcom_cpufreq_drv_cpu cpus[];
  59 };
  60
  61 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
  62
  63 static int qcom_cpufreq_simple_get_version(struct device *cpu_dev,
  64                                            struct nvmem_cell *speedbin_nvmem,
  65                                            char **pvs_name,
  66                                            struct qcom_cpufreq_drv *drv)
  67 {
  68         u8 *speedbin;
  69
  70         *pvs_name = NULL;
  71         speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
  72         if (IS_ERR(speedbin))
  73                 return PTR_ERR(speedbin);
  74
  75         dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin);
  76         drv->versions = 1 << *speedbin;
  77         kfree(speedbin);
  78         return 0;
  79 }
  80
  81 static void get_krait_bin_format_a(struct device *cpu_dev,
  82                                           int *speed, int *pvs,
  83                                           u8 *buf)
  84 {
  85         u32 pte_efuse;
  86
  87         pte_efuse = *((u32 *)buf);
  88
  89         *speed = pte_efuse & 0xf;
  90         if (*speed == 0xf)
  91                 *speed = (pte_efuse >> 4) & 0xf;
  92
  93         if (*speed == 0xf) {
  94                 *speed = 0;
  95                 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
  96         } else {
  97                 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
  98         }
  99
 100         *pvs = (pte_efuse >> 10) & 0x7;
 101         if (*pvs == 0x7)
 102                 *pvs = (pte_efuse >> 13) & 0x7;
 103
 104         if (*pvs == 0x7) {
 105                 *pvs = 0;
 106                 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
 107         } else {
 108                 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
 109         }
 110 }
 111
 112 static void get_krait_bin_format_b(struct device *cpu_dev,
 113                                           int *speed, int *pvs, int *pvs_ver,
 114                                           u8 *buf)
 115 {
 116         u32 pte_efuse, redundant_sel;
 117
 118         pte_efuse = *((u32 *)buf);
 119         redundant_sel = (pte_efuse >> 24) & 0x7;
 120
 121         *pvs_ver = (pte_efuse >> 4) & 0x3;
 122
 123         switch (redundant_sel) {
 124         case 1:
 125                 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
 126                 *speed = (pte_efuse >> 27) & 0xf;
 127                 break;
 128         case 2:
 129                 *pvs = (pte_efuse >> 27) & 0xf;
 130                 *speed = pte_efuse & 0x7;
 131                 break;
 132         default:
 133                 /* 4 bits of PVS are in efuse register bits 31, 8-6. */
 134                 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
 135                 *speed = pte_efuse & 0x7;
 136         }
 137
 138         /* Check SPEED_BIN_BLOW_STATUS */
 139         if (pte_efuse & BIT(3)) {
 140                 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
 141         } else {
 142                 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
 143                 *speed = 0;
 144         }
 145
 146         /* Check PVS_BLOW_STATUS */
 147         pte_efuse = *(((u32 *)buf) + 1);
 148         pte_efuse &= BIT(21);
 149         if (pte_efuse) {
 150                 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
 151         } else {
 152                 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
 153                 *pvs = 0;
 154         }
 155
 156         dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
 157 }
 158
 159 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 160                                           struct nvmem_cell *speedbin_nvmem,
 161                                           char **pvs_name,
 162                                           struct qcom_cpufreq_drv *drv)
 163 {
 164         size_t len;
 165         u32 msm_id;
 166         u8 *speedbin;
 167         int ret;
 168         *pvs_name = NULL;
 169
 170         ret = qcom_smem_get_soc_id(&msm_id);
 171         if (ret)
 172                 return ret;
 173
 174         speedbin = nvmem_cell_read(speedbin_nvmem, &len);
 175         if (IS_ERR(speedbin))
 176                 return PTR_ERR(speedbin);
 177
 178         switch (msm_id) {
 179         case QCOM_ID_MSM8996:
 180         case QCOM_ID_APQ8096:
 181                 drv->versions = 1 << (unsigned int)(*speedbin);
 182                 break;
 183         case QCOM_ID_MSM8996SG:
 184         case QCOM_ID_APQ8096SG:
 185                 drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
 186                 break;
 187         default:
 188                 BUG();
 189                 break;
 190         }
 191
 192         kfree(speedbin);
 193         return 0;
 194 }
 195
 196 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
 197                                            struct nvmem_cell *speedbin_nvmem,
 198                                            char **pvs_name,
 199                                            struct qcom_cpufreq_drv *drv)
 200 {
 201         int speed = 0, pvs = 0, pvs_ver = 0;
 202         u8 *speedbin;
 203         size_t len;
 204         int ret = 0;
 205
 206         speedbin = nvmem_cell_read(speedbin_nvmem, &len);
 207
 208         if (IS_ERR(speedbin))
 209                 return PTR_ERR(speedbin);
 210
 211         switch (len) {
 212         case 4:
 213                 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
 214                 break;
 215         case 8:
 216                 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
 217                                        speedbin);
 218                 break;
 219         default:
 220                 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
 221                 ret = -ENODEV;
 222                 goto len_error;
 223         }
 224
 225         snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
 226                  speed, pvs, pvs_ver);
 227
 228         drv->versions = (1 << speed);
 229
 230 len_error:
 231         kfree(speedbin);
 232         return ret;
 233 }
 234
 235 static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
 236                                              struct nvmem_cell *speedbin_nvmem,
 237                                              char **pvs_name,
 238                                              struct qcom_cpufreq_drv *drv)
 239 {
 240         int speed = 0, pvs = 0;
 241         int msm_id, ret = 0;
 242         u8 *speedbin;
 243         size_t len;
 244
 245         speedbin = nvmem_cell_read(speedbin_nvmem, &len);
 246         if (IS_ERR(speedbin))
 247                 return PTR_ERR(speedbin);
 248
 249         if (len != 4) {
 250                 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
 251                 ret = -ENODEV;
 252                 goto exit;
 253         }
 254
 255         get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
 256
 257         ret = qcom_smem_get_soc_id(&msm_id);
 258         if (ret)
 259                 goto exit;
 260
 261         switch (msm_id) {
 262         case QCOM_ID_IPQ8062:
 263                 drv->versions = BIT(IPQ8062_VERSION);
 264                 break;
 265         case QCOM_ID_IPQ8064:
 266         case QCOM_ID_IPQ8066:
 267         case QCOM_ID_IPQ8068:
 268                 drv->versions = BIT(IPQ8064_VERSION);
 269                 break;
 270         case QCOM_ID_IPQ8065:
 271         case QCOM_ID_IPQ8069:
 272                 drv->versions = BIT(IPQ8065_VERSION);
 273                 break;
 274         default:
 275                 dev_err(cpu_dev,
 276                         "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
 277                         msm_id);
 278                 drv->versions = BIT(IPQ8062_VERSION);
 279                 break;
 280         }
 281
 282         /* IPQ8064 speed is never fused. Only pvs values are fused. */
 283         snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs);
 284
 285 exit:
 286         kfree(speedbin);
 287         return ret;
 288 }
 289
 290 static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
 291                                              struct nvmem_cell *speedbin_nvmem,
 292                                              char **pvs_name,
 293                                              struct qcom_cpufreq_drv *drv)
 294 {
 295         u32 msm_id;
 296         int ret;
 297         u8 *speedbin;
 298         *pvs_name = NULL;
 299
 300         ret = qcom_smem_get_soc_id(&msm_id);
 301         if (ret)
 302                 return ret;
 303
 304         speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
 305         if (IS_ERR(speedbin))
 306                 return PTR_ERR(speedbin);
 307
 308         switch (msm_id) {
 309         case QCOM_ID_IPQ6005:
 310         case QCOM_ID_IPQ6010:
 311         case QCOM_ID_IPQ6018:
 312         case QCOM_ID_IPQ6028:
 313                 /* Fuse Value    Freq    BIT to set
 314                  * ---------------------------------
 315                  *   2’b0     No Limit     BIT(0)
 316                  *   2’b1     1.5 GHz      BIT(1)
 317                  */
 318                 drv->versions = 1 << (unsigned int)(*speedbin);
 319                 break;
 320         case QCOM_ID_IPQ6000:
 321                 /*
 322                  * IPQ6018 family only has one bit to advertise the CPU
 323                  * speed-bin, but that is not enough for IPQ6000 which
 324                  * is only rated up to 1.2GHz.
 325                  * So for IPQ6000 manually set BIT(2) based on SMEM ID.
 326                  */
 327                 drv->versions = IPQ6000_VERSION;
 328                 break;
 329         default:
 330                 dev_err(cpu_dev,
 331                         "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
 332                         msm_id);
 333                 drv->versions = IPQ6000_VERSION;
 334                 break;
 335         }
 336
 337         kfree(speedbin);
 338         return 0;
 339 }
 340
 341 static const char *generic_genpd_names[] = { "perf", NULL };
 342
 343 static const struct qcom_cpufreq_match_data match_data_kryo = {
 344         .get_version = qcom_cpufreq_kryo_name_version,
 345 };
 346
 347 static const struct qcom_cpufreq_match_data match_data_krait = {
 348         .get_version = qcom_cpufreq_krait_name_version,
 349 };
 350
 351 static const struct qcom_cpufreq_match_data match_data_msm8909 = {
 352         .get_version = qcom_cpufreq_simple_get_version,
 353         .genpd_names = generic_genpd_names,
 354 };
 355
 356 static const char *qcs404_genpd_names[] = { "cpr", NULL };
 357
 358 static const struct qcom_cpufreq_match_data match_data_qcs404 = {
 359         .genpd_names = qcs404_genpd_names,
 360 };
 361
 362 static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
 363         .get_version = qcom_cpufreq_ipq6018_name_version,
 364 };
 365
 366 static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
 367         .get_version = qcom_cpufreq_ipq8064_name_version,
 368 };
 369
 370 static int qcom_cpufreq_probe(struct platform_device *pdev)
 371 {
 372         struct qcom_cpufreq_drv *drv;
 373         struct nvmem_cell *speedbin_nvmem;
 374         struct device_node *np;
 375         struct device *cpu_dev;
 376         char pvs_name_buffer[] = "speedXX-pvsXX-vXX";
 377         char *pvs_name = pvs_name_buffer;
 378         unsigned cpu;
 379         const struct of_device_id *match;
 380         int ret;
 381
 382         cpu_dev = get_cpu_device(0);
 383         if (!cpu_dev)
 384                 return -ENODEV;
 385
 386         np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
 387         if (!np)
 388                 return -ENOENT;
 389
 390         ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
 391               of_device_is_compatible(np, "operating-points-v2-krait-cpu");
 392         if (!ret) {
 393                 of_node_put(np);
 394                 return -ENOENT;
 395         }
 396
 397         drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()),
 398                            GFP_KERNEL);
 399         if (!drv)
 400                 return -ENOMEM;
 401
 402         match = pdev->dev.platform_data;
 403         drv->data = match->data;
 404         if (!drv->data)
 405                 return -ENODEV;
 406
 407         if (drv->data->get_version) {
 408                 speedbin_nvmem = of_nvmem_cell_get(np, NULL);
 409                 if (IS_ERR(speedbin_nvmem))
 410                         return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
 411                                              "Could not get nvmem cell\n");
 412
 413                 ret = drv->data->get_version(cpu_dev,
 414                                                         speedbin_nvmem, &pvs_name, drv);
 415                 if (ret) {
 416                         nvmem_cell_put(speedbin_nvmem);
 417                         return ret;
 418                 }
 419                 nvmem_cell_put(speedbin_nvmem);
 420         }
 421         of_node_put(np);
 422
 423         for_each_possible_cpu(cpu) {
 424                 struct dev_pm_opp_config config = {
 425                         .supported_hw = NULL,
 426                 };
 427
 428                 cpu_dev = get_cpu_device(cpu);
 429                 if (NULL == cpu_dev) {
 430                         ret = -ENODEV;
 431                         goto free_opp;
 432                 }
 433
 434                 if (drv->data->get_version) {
 435                         config.supported_hw = &drv->versions;
 436                         config.supported_hw_count = 1;
 437
 438                         if (pvs_name)
 439                                 config.prop_name = pvs_name;
 440                 }
 441
 442                 if (drv->data->genpd_names) {
 443                         config.genpd_names = drv->data->genpd_names;
 444                         config.virt_devs = NULL;
 445                 }
 446
 447                 if (config.supported_hw || config.genpd_names) {
 448                         drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config);
 449                         if (drv->cpus[cpu].opp_token < 0) {
 450                                 ret = drv->cpus[cpu].opp_token;
 451                                 dev_err(cpu_dev, "Failed to set OPP config\n");
 452                                 goto free_opp;
 453                         }
 454                 }
 455         }
 456
 457         cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
 458                                                           NULL, 0);
 459         if (!IS_ERR(cpufreq_dt_pdev)) {
 460                 platform_set_drvdata(pdev, drv);
 461                 return 0;
 462         }
 463
 464         ret = PTR_ERR(cpufreq_dt_pdev);
 465         dev_err(cpu_dev, "Failed to register platform device\n");
 466
 467 free_opp:
 468         for_each_possible_cpu(cpu)
 469                 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
 470         return ret;
 471 }
 472
 473 static void qcom_cpufreq_remove(struct platform_device *pdev)
 474 {
 475         struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
 476         unsigned int cpu;
 477
 478         platform_device_unregister(cpufreq_dt_pdev);
 479
 480         for_each_possible_cpu(cpu)
 481                 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
 482 }
 483
 484 static struct platform_driver qcom_cpufreq_driver = {
 485         .probe = qcom_cpufreq_probe,
 486         .remove_new = qcom_cpufreq_remove,
 487         .driver = {
 488                 .name = "qcom-cpufreq-nvmem",
 489         },
 490 };
 491
 492 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
 493         { .compatible = "qcom,apq8096", .data = &match_data_kryo },
 494         { .compatible = "qcom,msm8909", .data = &match_data_msm8909 },
 495         { .compatible = "qcom,msm8996", .data = &match_data_kryo },
 496         { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
 497         { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
 498         { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
 499         { .compatible = "qcom,apq8064", .data = &match_data_krait },
 500         { .compatible = "qcom,msm8974", .data = &match_data_krait },
 501         { .compatible = "qcom,msm8960", .data = &match_data_krait },
 502         {},
 503 };
 504 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
 505
 506 /*
 507  * Since the driver depends on smem and nvmem drivers, which may
 508  * return EPROBE_DEFER, all the real activity is done in the probe,
 509  * which may be defered as well. The init here is only registering
 510  * the driver and the platform device.
 511  */
 512 static int __init qcom_cpufreq_init(void)
 513 {
 514         struct device_node *np = of_find_node_by_path("/");
 515         const struct of_device_id *match;
 516         int ret;
 517
 518         if (!np)
 519                 return -ENODEV;
 520
 521         match = of_match_node(qcom_cpufreq_match_list, np);
 522         of_node_put(np);
 523         if (!match)
 524                 return -ENODEV;
 525
 526         ret = platform_driver_register(&qcom_cpufreq_driver);
 527         if (unlikely(ret < 0))
 528                 return ret;
 529
 530         cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
 531                                                      -1, match, sizeof(*match));
 532         ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
 533         if (0 == ret)
 534                 return 0;
 535
 536         platform_driver_unregister(&qcom_cpufreq_driver);
 537         return ret;
 538 }
 539 module_init(qcom_cpufreq_init);
 540
 541 static void __exit qcom_cpufreq_exit(void)
 542 {
 543         platform_device_unregister(cpufreq_pdev);
 544         platform_driver_unregister(&qcom_cpufreq_driver);
 545 }
 546 module_exit(qcom_cpufreq_exit);
 547
 548 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
 549 MODULE_LICENSE("GPL v2");