drivers/gpu/drm/sun4i/sun4i_backend.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2015 Free Electrons
   4  * Copyright (C) 2015 NextThing Co
   5  *
   6  * Maxime Ripard <[email protected]>
   7  */
   8
   9 #include <linux/component.h>
  10 #include <linux/list.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_graph.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/reset.h>
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_blend.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_fb_cma_helper.h>
  23 #include <drm/drm_fourcc.h>
  24 #include <drm/drm_framebuffer.h>
  25 #include <drm/drm_gem_cma_helper.h>
  26 #include <drm/drm_plane_helper.h>
  27 #include <drm/drm_probe_helper.h>
  28
  29 #include "sun4i_backend.h"
  30 #include "sun4i_drv.h"
  31 #include "sun4i_frontend.h"
  32 #include "sun4i_layer.h"
  33 #include "sunxi_engine.h"
  34
  35 struct sun4i_backend_quirks {
  36         /* backend <-> TCON muxing selection done in backend */
  37         bool needs_output_muxing;
  38
  39         /* alpha at the lowest z position is not always supported */
  40         bool supports_lowest_plane_alpha;
  41 };
  42
  43 static const u32 sunxi_rgb2yuv_coef[12] = {
  44         0x00000107, 0x00000204, 0x00000064, 0x00000108,
  45         0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  46         0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  47 };
  48
  49 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
  50 {
  51         int i;
  52
  53         DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
  54
  55         /* Set color correction */
  56         regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
  57                      SUN4I_BACKEND_OCCTL_ENABLE);
  58
  59         for (i = 0; i < 12; i++)
  60                 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
  61                              sunxi_rgb2yuv_coef[i]);
  62 }
  63
  64 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
  65 {
  66         DRM_DEBUG_DRIVER("Disabling color correction\n");
  67
  68         /* Disable color correction */
  69         regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
  70                            SUN4I_BACKEND_OCCTL_ENABLE, 0);
  71 }
  72
  73 static void sun4i_backend_commit(struct sunxi_engine *engine)
  74 {
  75         DRM_DEBUG_DRIVER("Committing changes\n");
  76
  77         regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
  78                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
  79                      SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
  80 }
  81
  82 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
  83                                 int layer, bool enable)
  84 {
  85         u32 val;
  86
  87         DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
  88                          layer);
  89
  90         if (enable)
  91                 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
  92         else
  93                 val = 0;
  94
  95         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
  96                            SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
  97 }
  98
  99 static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode)
 100 {
 101         switch (format) {
 102         case DRM_FORMAT_ARGB8888:
 103                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
 104                 break;
 105
 106         case DRM_FORMAT_ARGB4444:
 107                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
 108                 break;
 109
 110         case DRM_FORMAT_ARGB1555:
 111                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
 112                 break;
 113
 114         case DRM_FORMAT_RGBA5551:
 115                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
 116                 break;
 117
 118         case DRM_FORMAT_RGBA4444:
 119                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
 120                 break;
 121
 122         case DRM_FORMAT_XRGB8888:
 123                 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
 124                 break;
 125
 126         case DRM_FORMAT_RGB888:
 127                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
 128                 break;
 129
 130         case DRM_FORMAT_RGB565:
 131                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
 132                 break;
 133
 134         default:
 135                 return -EINVAL;
 136         }
 137
 138         return 0;
 139 }
 140
 141 static const uint32_t sun4i_backend_formats[] = {
 142         DRM_FORMAT_ARGB1555,
 143         DRM_FORMAT_ARGB4444,
 144         DRM_FORMAT_ARGB8888,
 145         DRM_FORMAT_RGB565,
 146         DRM_FORMAT_RGB888,
 147         DRM_FORMAT_RGBA4444,
 148         DRM_FORMAT_RGBA5551,
 149         DRM_FORMAT_UYVY,
 150         DRM_FORMAT_VYUY,
 151         DRM_FORMAT_XRGB8888,
 152         DRM_FORMAT_YUYV,
 153         DRM_FORMAT_YVYU,
 154 };
 155
 156 bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier)
 157 {
 158         unsigned int i;
 159
 160         if (modifier != DRM_FORMAT_MOD_LINEAR)
 161                 return false;
 162
 163         for (i = 0; i < ARRAY_SIZE(sun4i_backend_formats); i++)
 164                 if (sun4i_backend_formats[i] == fmt)
 165                         return true;
 166
 167         return false;
 168 }
 169
 170 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
 171                                      int layer, struct drm_plane *plane)
 172 {
 173         struct drm_plane_state *state = plane->state;
 174
 175         DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
 176
 177         /* Set height and width */
 178         DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
 179                          state->crtc_w, state->crtc_h);
 180         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
 181                      SUN4I_BACKEND_LAYSIZE(state->crtc_w,
 182                                            state->crtc_h));
 183
 184         /* Set base coordinates */
 185         DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
 186                          state->crtc_x, state->crtc_y);
 187         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
 188                      SUN4I_BACKEND_LAYCOOR(state->crtc_x,
 189                                            state->crtc_y));
 190
 191         return 0;
 192 }
 193
 194 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
 195                                            int layer, struct drm_plane *plane)
 196 {
 197         struct drm_plane_state *state = plane->state;
 198         struct drm_framebuffer *fb = state->fb;
 199         const struct drm_format_info *format = fb->format;
 200         const uint32_t fmt = format->format;
 201         u32 val = SUN4I_BACKEND_IYUVCTL_EN;
 202         int i;
 203
 204         for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
 205                 regmap_write(backend->engine.regs,
 206                              SUN4I_BACKEND_YGCOEF_REG(i),
 207                              sunxi_bt601_yuv2rgb_coef[i]);
 208
 209         /*
 210          * We should do that only for a single plane, but the
 211          * framebuffer's atomic_check has our back on this.
 212          */
 213         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 214                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN,
 215                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN);
 216
 217         /* TODO: Add support for the multi-planar YUV formats */
 218         if (drm_format_info_is_yuv_packed(format) &&
 219             drm_format_info_is_yuv_sampling_422(format))
 220                 val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422;
 221         else
 222                 DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt);
 223
 224         /*
 225          * Allwinner seems to list the pixel sequence from right to left, while
 226          * DRM lists it from left to right.
 227          */
 228         switch (fmt) {
 229         case DRM_FORMAT_YUYV:
 230                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY;
 231                 break;
 232         case DRM_FORMAT_YVYU:
 233                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY;
 234                 break;
 235         case DRM_FORMAT_UYVY:
 236                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU;
 237                 break;
 238         case DRM_FORMAT_VYUY:
 239                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV;
 240                 break;
 241         default:
 242                 DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n",
 243                                  fmt);
 244         }
 245
 246         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
 247
 248         return 0;
 249 }
 250
 251 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
 252                                        int layer, struct drm_plane *plane)
 253 {
 254         struct drm_plane_state *state = plane->state;
 255         struct drm_framebuffer *fb = state->fb;
 256         u32 val;
 257         int ret;
 258
 259         /* Clear the YUV mode */
 260         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 261                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
 262
 263         val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8);
 264         if (state->alpha != DRM_BLEND_ALPHA_OPAQUE)
 265                 val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN;
 266         regmap_update_bits(backend->engine.regs,
 267                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 268                            SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK |
 269                            SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN,
 270                            val);
 271
 272         if (fb->format->is_yuv)
 273                 return sun4i_backend_update_yuv_format(backend, layer, plane);
 274
 275         ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val);
 276         if (ret) {
 277                 DRM_DEBUG_DRIVER("Invalid format\n");
 278                 return ret;
 279         }
 280
 281         regmap_update_bits(backend->engine.regs,
 282                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 283                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 284
 285         return 0;
 286 }
 287
 288 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
 289                                         int layer, uint32_t fmt)
 290 {
 291         u32 val;
 292         int ret;
 293
 294         ret = sun4i_backend_drm_format_to_layer(fmt, &val);
 295         if (ret) {
 296                 DRM_DEBUG_DRIVER("Invalid format\n");
 297                 return ret;
 298         }
 299
 300         regmap_update_bits(backend->engine.regs,
 301                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 302                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN,
 303                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN);
 304
 305         regmap_update_bits(backend->engine.regs,
 306                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 307                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 308
 309         return 0;
 310 }
 311
 312 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
 313                                            struct drm_framebuffer *fb,
 314                                            dma_addr_t paddr)
 315 {
 316         /* TODO: Add support for the multi-planar YUV formats */
 317         DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr);
 318         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
 319
 320         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 321         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
 322                      fb->pitches[0] * 8);
 323
 324         return 0;
 325 }
 326
 327 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 328                                       int layer, struct drm_plane *plane)
 329 {
 330         struct drm_plane_state *state = plane->state;
 331         struct drm_framebuffer *fb = state->fb;
 332         u32 lo_paddr, hi_paddr;
 333         dma_addr_t paddr;
 334
 335         /* Set the line width */
 336         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 337         regmap_write(backend->engine.regs,
 338                      SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
 339                      fb->pitches[0] * 8);
 340
 341         /* Get the start of the displayed memory */
 342         paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
 343         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 344
 345         if (fb->format->is_yuv)
 346                 return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
 347
 348         /* Write the 32 lower bits of the address (in bits) */
 349         lo_paddr = paddr << 3;
 350         DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
 351         regmap_write(backend->engine.regs,
 352                      SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
 353                      lo_paddr);
 354
 355         /* And the upper bits */
 356         hi_paddr = paddr >> 29;
 357         DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
 358         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
 359                            SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
 360                            SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
 361
 362         return 0;
 363 }
 364
 365 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
 366                                     struct drm_plane *plane)
 367 {
 368         struct drm_plane_state *state = plane->state;
 369         struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state);
 370         unsigned int priority = state->normalized_zpos;
 371         unsigned int pipe = p_state->pipe;
 372
 373         DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n",
 374                          layer, priority, pipe);
 375         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 376                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK |
 377                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK,
 378                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) |
 379                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority));
 380
 381         return 0;
 382 }
 383
 384 void sun4i_backend_cleanup_layer(struct sun4i_backend *backend,
 385                                  int layer)
 386 {
 387         regmap_update_bits(backend->engine.regs,
 388                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 389                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN |
 390                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
 391 }
 392
 393 static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state)
 394 {
 395         u16 src_h = state->src_h >> 16;
 396         u16 src_w = state->src_w >> 16;
 397
 398         DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n",
 399                          src_w, src_h, state->crtc_w, state->crtc_h);
 400
 401         if ((state->crtc_h != src_h) || (state->crtc_w != src_w))
 402                 return true;
 403
 404         return false;
 405 }
 406
 407 static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state)
 408 {
 409         struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane);
 410         struct sun4i_backend *backend = layer->backend;
 411         uint32_t format = state->fb->format->format;
 412         uint64_t modifier = state->fb->modifier;
 413
 414         if (IS_ERR(backend->frontend))
 415                 return false;
 416
 417         if (!sun4i_frontend_format_is_supported(format, modifier))
 418                 return false;
 419
 420         if (!sun4i_backend_format_is_supported(format, modifier))
 421                 return true;
 422
 423         /*
 424          * TODO: The backend alone allows 2x and 4x integer scaling, including
 425          * support for an alpha component (which the frontend doesn't support).
 426          * Use the backend directly instead of the frontend in this case, with
 427          * another test to return false.
 428          */
 429
 430         if (sun4i_backend_plane_uses_scaler(state))
 431                 return true;
 432
 433         /*
 434          * Here the format is supported by both the frontend and the backend
 435          * and no frontend scaling is required, so use the backend directly.
 436          */
 437         return false;
 438 }
 439
 440 static bool sun4i_backend_plane_is_supported(struct drm_plane_state *state,
 441                                              bool *uses_frontend)
 442 {
 443         if (sun4i_backend_plane_uses_frontend(state)) {
 444                 *uses_frontend = true;
 445                 return true;
 446         }
 447
 448         *uses_frontend = false;
 449
 450         /* Scaling is not supported without the frontend. */
 451         if (sun4i_backend_plane_uses_scaler(state))
 452                 return false;
 453
 454         return true;
 455 }
 456
 457 static void sun4i_backend_atomic_begin(struct sunxi_engine *engine,
 458                                        struct drm_crtc_state *old_state)
 459 {
 460         u32 val;
 461
 462         WARN_ON(regmap_read_poll_timeout(engine->regs,
 463                                          SUN4I_BACKEND_REGBUFFCTL_REG,
 464                                          val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL),
 465                                          100, 50000));
 466 }
 467
 468 static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
 469                                       struct drm_crtc_state *crtc_state)
 470 {
 471         struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 };
 472         struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
 473         struct drm_atomic_state *state = crtc_state->state;
 474         struct drm_device *drm = state->dev;
 475         struct drm_plane *plane;
 476         unsigned int num_planes = 0;
 477         unsigned int num_alpha_planes = 0;
 478         unsigned int num_frontend_planes = 0;
 479         unsigned int num_alpha_planes_max = 1;
 480         unsigned int num_yuv_planes = 0;
 481         unsigned int current_pipe = 0;
 482         unsigned int i;
 483
 484         DRM_DEBUG_DRIVER("Starting checking our planes\n");
 485
 486         if (!crtc_state->planes_changed)
 487                 return 0;
 488
 489         drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) {
 490                 struct drm_plane_state *plane_state =
 491                         drm_atomic_get_plane_state(state, plane);
 492                 struct sun4i_layer_state *layer_state =
 493                         state_to_sun4i_layer_state(plane_state);
 494                 struct drm_framebuffer *fb = plane_state->fb;
 495
 496                 if (!sun4i_backend_plane_is_supported(plane_state,
 497                                                       &layer_state->uses_frontend))
 498                         return -EINVAL;
 499
 500                 if (layer_state->uses_frontend) {
 501                         DRM_DEBUG_DRIVER("Using the frontend for plane %d\n",
 502                                          plane->index);
 503                         num_frontend_planes++;
 504                 } else {
 505                         if (fb->format->is_yuv) {
 506                                 DRM_DEBUG_DRIVER("Plane FB format is YUV\n");
 507                                 num_yuv_planes++;
 508                         }
 509                 }
 510
 511                 DRM_DEBUG_DRIVER("Plane FB format is %p4cc\n",
 512                                  &fb->format->format);
 513                 if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
 514                         num_alpha_planes++;
 515
 516                 DRM_DEBUG_DRIVER("Plane zpos is %d\n",
 517                                  plane_state->normalized_zpos);
 518
 519                 /* Sort our planes by Zpos */
 520                 plane_states[plane_state->normalized_zpos] = plane_state;
 521
 522                 num_planes++;
 523         }
 524
 525         /* All our planes were disabled, bail out */
 526         if (!num_planes)
 527                 return 0;
 528
 529         /*
 530          * The hardware is a bit unusual here.
 531          *
 532          * Even though it supports 4 layers, it does the composition
 533          * in two separate steps.
 534          *
 535          * The first one is assigning a layer to one of its two
 536          * pipes. If more that 1 layer is assigned to the same pipe,
 537          * and if pixels overlaps, the pipe will take the pixel from
 538          * the layer with the highest priority.
 539          *
 540          * The second step is the actual alpha blending, that takes
 541          * the two pipes as input, and uses the potential alpha
 542          * component to do the transparency between the two.
 543          *
 544          * This two-step scenario makes us unable to guarantee a
 545          * robust alpha blending between the 4 layers in all
 546          * situations, since this means that we need to have one layer
 547          * with alpha at the lowest position of our two pipes.
 548          *
 549          * However, we cannot even do that on every platform, since
 550          * the hardware has a bug where the lowest plane of the lowest
 551          * pipe (pipe 0, priority 0), if it has any alpha, will
 552          * discard the pixel data entirely and just display the pixels
 553          * in the background color (black by default).
 554          *
 555          * This means that on the affected platforms, we effectively
 556          * have only three valid configurations with alpha, all of
 557          * them with the alpha being on pipe1 with the lowest
 558          * position, which can be 1, 2 or 3 depending on the number of
 559          * planes and their zpos.
 560          */
 561
 562         /* For platforms that are not affected by the issue described above. */
 563         if (backend->quirks->supports_lowest_plane_alpha)
 564                 num_alpha_planes_max++;
 565
 566         if (num_alpha_planes > num_alpha_planes_max) {
 567                 DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n");
 568                 return -EINVAL;
 569         }
 570
 571         /* We can't have an alpha plane at the lowest position */
 572         if (!backend->quirks->supports_lowest_plane_alpha &&
 573             (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))
 574                 return -EINVAL;
 575
 576         for (i = 1; i < num_planes; i++) {
 577                 struct drm_plane_state *p_state = plane_states[i];
 578                 struct drm_framebuffer *fb = p_state->fb;
 579                 struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state);
 580
 581                 /*
 582                  * The only alpha position is the lowest plane of the
 583                  * second pipe.
 584                  */
 585                 if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
 586                         current_pipe++;
 587
 588                 s_state->pipe = current_pipe;
 589         }
 590
 591         /* We can only have a single YUV plane at a time */
 592         if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) {
 593                 DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n");
 594                 return -EINVAL;
 595         }
 596
 597         if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) {
 598                 DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n");
 599                 return -EINVAL;
 600         }
 601
 602         DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n",
 603                          num_planes, num_alpha_planes, num_frontend_planes,
 604                          num_yuv_planes);
 605
 606         return 0;
 607 }
 608
 609 static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine)
 610 {
 611         struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
 612         struct sun4i_frontend *frontend = backend->frontend;
 613
 614         if (!frontend)
 615                 return;
 616
 617         /*
 618          * In a teardown scenario with the frontend involved, we have
 619          * to keep the frontend enabled until the next vblank, and
 620          * only then disable it.
 621          *
 622          * This is due to the fact that the backend will not take into
 623          * account the new configuration (with the plane that used to
 624          * be fed by the frontend now disabled) until we write to the
 625          * commit bit and the hardware fetches the new configuration
 626          * during the next vblank.
 627          *
 628          * So we keep the frontend around in order to prevent any
 629          * visual artifacts.
 630          */
 631         spin_lock(&backend->frontend_lock);
 632         if (backend->frontend_teardown) {
 633                 sun4i_frontend_exit(frontend);
 634                 backend->frontend_teardown = false;
 635         }
 636         spin_unlock(&backend->frontend_lock);
 637 };
 638
 639 static void sun4i_backend_mode_set(struct sunxi_engine *engine,
 640                                    const struct drm_display_mode *mode)
 641 {
 642         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
 643
 644         DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n",
 645                          mode->hdisplay, mode->vdisplay);
 646
 647         regmap_write(engine->regs, SUN4I_BACKEND_DISSIZE_REG,
 648                      SUN4I_BACKEND_DISSIZE(mode->hdisplay, mode->vdisplay));
 649
 650         regmap_update_bits(engine->regs, SUN4I_BACKEND_MODCTL_REG,
 651                            SUN4I_BACKEND_MODCTL_ITLMOD_EN,
 652                            interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
 653
 654         DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
 655                          interlaced ? "on" : "off");
 656 }
 657
 658 static int sun4i_backend_init_sat(struct device *dev) {
 659         struct sun4i_backend *backend = dev_get_drvdata(dev);
 660         int ret;
 661
 662         backend->sat_reset = devm_reset_control_get(dev, "sat");
 663         if (IS_ERR(backend->sat_reset)) {
 664                 dev_err(dev, "Couldn't get the SAT reset line\n");
 665                 return PTR_ERR(backend->sat_reset);
 666         }
 667
 668         ret = reset_control_deassert(backend->sat_reset);
 669         if (ret) {
 670                 dev_err(dev, "Couldn't deassert the SAT reset line\n");
 671                 return ret;
 672         }
 673
 674         backend->sat_clk = devm_clk_get(dev, "sat");
 675         if (IS_ERR(backend->sat_clk)) {
 676                 dev_err(dev, "Couldn't get our SAT clock\n");
 677                 ret = PTR_ERR(backend->sat_clk);
 678                 goto err_assert_reset;
 679         }
 680
 681         ret = clk_prepare_enable(backend->sat_clk);
 682         if (ret) {
 683                 dev_err(dev, "Couldn't enable the SAT clock\n");
 684                 return ret;
 685         }
 686
 687         return 0;
 688
 689 err_assert_reset:
 690         reset_control_assert(backend->sat_reset);
 691         return ret;
 692 }
 693
 694 static int sun4i_backend_free_sat(struct device *dev) {
 695         struct sun4i_backend *backend = dev_get_drvdata(dev);
 696
 697         clk_disable_unprepare(backend->sat_clk);
 698         reset_control_assert(backend->sat_reset);
 699
 700         return 0;
 701 }
 702
 703 /*
 704  * The display backend can take video output from the display frontend, or
 705  * the display enhancement unit on the A80, as input for one it its layers.
 706  * This relationship within the display pipeline is encoded in the device
 707  * tree with of_graph, and we use it here to figure out which backend, if
 708  * there are 2 or more, we are currently probing. The number would be in
 709  * the "reg" property of the upstream output port endpoint.
 710  */
 711 static int sun4i_backend_of_get_id(struct device_node *node)
 712 {
 713         struct device_node *ep, *remote;
 714         struct of_endpoint of_ep;
 715
 716         /* Input port is 0, and we want the first endpoint. */
 717         ep = of_graph_get_endpoint_by_regs(node, 0, -1);
 718         if (!ep)
 719                 return -EINVAL;
 720
 721         remote = of_graph_get_remote_endpoint(ep);
 722         of_node_put(ep);
 723         if (!remote)
 724                 return -EINVAL;
 725
 726         of_graph_parse_endpoint(remote, &of_ep);
 727         of_node_put(remote);
 728         return of_ep.id;
 729 }
 730
 731 /* TODO: This needs to take multiple pipelines into account */
 732 static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv,
 733                                                           struct device_node *node)
 734 {
 735         struct device_node *port, *ep, *remote;
 736         struct sun4i_frontend *frontend;
 737
 738         port = of_graph_get_port_by_id(node, 0);
 739         if (!port)
 740                 return ERR_PTR(-EINVAL);
 741
 742         for_each_available_child_of_node(port, ep) {
 743                 remote = of_graph_get_remote_port_parent(ep);
 744                 if (!remote)
 745                         continue;
 746                 of_node_put(remote);
 747
 748                 /* does this node match any registered engines? */
 749                 list_for_each_entry(frontend, &drv->frontend_list, list) {
 750                         if (remote == frontend->node) {
 751                                 of_node_put(port);
 752                                 of_node_put(ep);
 753                                 return frontend;
 754                         }
 755                 }
 756         }
 757         of_node_put(port);
 758         return ERR_PTR(-EINVAL);
 759 }
 760
 761 static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
 762         .atomic_begin                   = sun4i_backend_atomic_begin,
 763         .atomic_check                   = sun4i_backend_atomic_check,
 764         .commit                         = sun4i_backend_commit,
 765         .layers_init                    = sun4i_layers_init,
 766         .apply_color_correction         = sun4i_backend_apply_color_correction,
 767         .disable_color_correction       = sun4i_backend_disable_color_correction,
 768         .vblank_quirk                   = sun4i_backend_vblank_quirk,
 769         .mode_set                       = sun4i_backend_mode_set,
 770 };
 771
 772 static const struct regmap_config sun4i_backend_regmap_config = {
 773         .reg_bits       = 32,
 774         .val_bits       = 32,
 775         .reg_stride     = 4,
 776         .max_register   = 0x5800,
 777 };
 778
 779 static int sun4i_backend_bind(struct device *dev, struct device *master,
 780                               void *data)
 781 {
 782         struct platform_device *pdev = to_platform_device(dev);
 783         struct drm_device *drm = data;
 784         struct sun4i_drv *drv = drm->dev_private;
 785         struct sun4i_backend *backend;
 786         const struct sun4i_backend_quirks *quirks;
 787         void __iomem *regs;
 788         int i, ret;
 789
 790         backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
 791         if (!backend)
 792                 return -ENOMEM;
 793         dev_set_drvdata(dev, backend);
 794         spin_lock_init(&backend->frontend_lock);
 795
 796         if (of_find_property(dev->of_node, "interconnects", NULL)) {
 797                 /*
 798                  * This assume we have the same DMA constraints for all our the
 799                  * devices in our pipeline (all the backends, but also the
 800                  * frontends). This sounds bad, but it has always been the case
 801                  * for us, and DRM doesn't do per-device allocation either, so
 802                  * we would need to fix DRM first...
 803                  */
 804                 ret = of_dma_configure(drm->dev, dev->of_node, true);
 805                 if (ret)
 806                         return ret;
 807         }
 808
 809         backend->engine.node = dev->of_node;
 810         backend->engine.ops = &sun4i_backend_engine_ops;
 811         backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
 812         if (backend->engine.id < 0)
 813                 return backend->engine.id;
 814
 815         backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
 816         if (IS_ERR(backend->frontend))
 817                 dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n");
 818
 819         regs = devm_platform_ioremap_resource(pdev, 0);
 820         if (IS_ERR(regs))
 821                 return PTR_ERR(regs);
 822
 823         backend->reset = devm_reset_control_get(dev, NULL);
 824         if (IS_ERR(backend->reset)) {
 825                 dev_err(dev, "Couldn't get our reset line\n");
 826                 return PTR_ERR(backend->reset);
 827         }
 828
 829         ret = reset_control_deassert(backend->reset);
 830         if (ret) {
 831                 dev_err(dev, "Couldn't deassert our reset line\n");
 832                 return ret;
 833         }
 834
 835         backend->bus_clk = devm_clk_get(dev, "ahb");
 836         if (IS_ERR(backend->bus_clk)) {
 837                 dev_err(dev, "Couldn't get the backend bus clock\n");
 838                 ret = PTR_ERR(backend->bus_clk);
 839                 goto err_assert_reset;
 840         }
 841         clk_prepare_enable(backend->bus_clk);
 842
 843         backend->mod_clk = devm_clk_get(dev, "mod");
 844         if (IS_ERR(backend->mod_clk)) {
 845                 dev_err(dev, "Couldn't get the backend module clock\n");
 846                 ret = PTR_ERR(backend->mod_clk);
 847                 goto err_disable_bus_clk;
 848         }
 849
 850         ret = clk_set_rate_exclusive(backend->mod_clk, 300000000);
 851         if (ret) {
 852                 dev_err(dev, "Couldn't set the module clock frequency\n");
 853                 goto err_disable_bus_clk;
 854         }
 855
 856         clk_prepare_enable(backend->mod_clk);
 857
 858         backend->ram_clk = devm_clk_get(dev, "ram");
 859         if (IS_ERR(backend->ram_clk)) {
 860                 dev_err(dev, "Couldn't get the backend RAM clock\n");
 861                 ret = PTR_ERR(backend->ram_clk);
 862                 goto err_disable_mod_clk;
 863         }
 864         clk_prepare_enable(backend->ram_clk);
 865
 866         if (of_device_is_compatible(dev->of_node,
 867                                     "allwinner,sun8i-a33-display-backend")) {
 868                 ret = sun4i_backend_init_sat(dev);
 869                 if (ret) {
 870                         dev_err(dev, "Couldn't init SAT resources\n");
 871                         goto err_disable_ram_clk;
 872                 }
 873         }
 874
 875         backend->engine.regs = devm_regmap_init_mmio(dev, regs,
 876                                                      &sun4i_backend_regmap_config);
 877         if (IS_ERR(backend->engine.regs)) {
 878                 dev_err(dev, "Couldn't create the backend regmap\n");
 879                 return PTR_ERR(backend->engine.regs);
 880         }
 881
 882         list_add_tail(&backend->engine.list, &drv->engine_list);
 883
 884         /*
 885          * Many of the backend's layer configuration registers have
 886          * undefined default values. This poses a risk as we use
 887          * regmap_update_bits in some places, and don't overwrite
 888          * the whole register.
 889          *
 890          * Clear the registers here to have something predictable.
 891          */
 892         for (i = 0x800; i < 0x1000; i += 4)
 893                 regmap_write(backend->engine.regs, i, 0);
 894
 895         /* Disable registers autoloading */
 896         regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 897                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
 898
 899         /* Enable the backend */
 900         regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 901                      SUN4I_BACKEND_MODCTL_DEBE_EN |
 902                      SUN4I_BACKEND_MODCTL_START_CTL);
 903
 904         /* Set output selection if needed */
 905         quirks = of_device_get_match_data(dev);
 906         if (quirks->needs_output_muxing) {
 907                 /*
 908                  * We assume there is no dynamic muxing of backends
 909                  * and TCONs, so we select the backend with same ID.
 910                  *
 911                  * While dynamic selection might be interesting, since
 912                  * the CRTC is tied to the TCON, while the layers are
 913                  * tied to the backends, this means, we will need to
 914                  * switch between groups of layers. There might not be
 915                  * a way to represent this constraint in DRM.
 916                  */
 917                 regmap_update_bits(backend->engine.regs,
 918                                    SUN4I_BACKEND_MODCTL_REG,
 919                                    SUN4I_BACKEND_MODCTL_OUT_SEL,
 920                                    (backend->engine.id
 921                                     ? SUN4I_BACKEND_MODCTL_OUT_LCD1
 922                                     : SUN4I_BACKEND_MODCTL_OUT_LCD0));
 923         }
 924
 925         backend->quirks = quirks;
 926
 927         return 0;
 928
 929 err_disable_ram_clk:
 930         clk_disable_unprepare(backend->ram_clk);
 931 err_disable_mod_clk:
 932         clk_rate_exclusive_put(backend->mod_clk);
 933         clk_disable_unprepare(backend->mod_clk);
 934 err_disable_bus_clk:
 935         clk_disable_unprepare(backend->bus_clk);
 936 err_assert_reset:
 937         reset_control_assert(backend->reset);
 938         return ret;
 939 }
 940
 941 static void sun4i_backend_unbind(struct device *dev, struct device *master,
 942                                  void *data)
 943 {
 944         struct sun4i_backend *backend = dev_get_drvdata(dev);
 945
 946         list_del(&backend->engine.list);
 947
 948         if (of_device_is_compatible(dev->of_node,
 949                                     "allwinner,sun8i-a33-display-backend"))
 950                 sun4i_backend_free_sat(dev);
 951
 952         clk_disable_unprepare(backend->ram_clk);
 953         clk_rate_exclusive_put(backend->mod_clk);
 954         clk_disable_unprepare(backend->mod_clk);
 955         clk_disable_unprepare(backend->bus_clk);
 956         reset_control_assert(backend->reset);
 957 }
 958
 959 static const struct component_ops sun4i_backend_ops = {
 960         .bind   = sun4i_backend_bind,
 961         .unbind = sun4i_backend_unbind,
 962 };
 963
 964 static int sun4i_backend_probe(struct platform_device *pdev)
 965 {
 966         return component_add(&pdev->dev, &sun4i_backend_ops);
 967 }
 968
 969 static int sun4i_backend_remove(struct platform_device *pdev)
 970 {
 971         component_del(&pdev->dev, &sun4i_backend_ops);
 972
 973         return 0;
 974 }
 975
 976 static const struct sun4i_backend_quirks sun4i_backend_quirks = {
 977         .needs_output_muxing = true,
 978 };
 979
 980 static const struct sun4i_backend_quirks sun5i_backend_quirks = {
 981 };
 982
 983 static const struct sun4i_backend_quirks sun6i_backend_quirks = {
 984 };
 985
 986 static const struct sun4i_backend_quirks sun7i_backend_quirks = {
 987         .needs_output_muxing = true,
 988 };
 989
 990 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = {
 991         .supports_lowest_plane_alpha = true,
 992 };
 993
 994 static const struct sun4i_backend_quirks sun9i_backend_quirks = {
 995 };
 996
 997 static const struct of_device_id sun4i_backend_of_table[] = {
 998         {
 999                 .compatible = "allwinner,sun4i-a10-display-backend",
1000                 .data = &sun4i_backend_quirks,
1001         },
1002         {
1003                 .compatible = "allwinner,sun5i-a13-display-backend",
1004                 .data = &sun5i_backend_quirks,
1005         },
1006         {
1007                 .compatible = "allwinner,sun6i-a31-display-backend",
1008                 .data = &sun6i_backend_quirks,
1009         },
1010         {
1011                 .compatible = "allwinner,sun7i-a20-display-backend",
1012                 .data = &sun7i_backend_quirks,
1013         },
1014         {
1015                 .compatible = "allwinner,sun8i-a23-display-backend",
1016                 .data = &sun8i_a33_backend_quirks,
1017         },
1018         {
1019                 .compatible = "allwinner,sun8i-a33-display-backend",
1020                 .data = &sun8i_a33_backend_quirks,
1021         },
1022         {
1023                 .compatible = "allwinner,sun9i-a80-display-backend",
1024                 .data = &sun9i_backend_quirks,
1025         },
1026         { }
1027 };
1028 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
1029
1030 static struct platform_driver sun4i_backend_platform_driver = {
1031         .probe          = sun4i_backend_probe,
1032         .remove         = sun4i_backend_remove,
1033         .driver         = {
1034                 .name           = "sun4i-backend",
1035                 .of_match_table = sun4i_backend_of_table,
1036         },
1037 };
1038 module_platform_driver(sun4i_backend_platform_driver);
1039
1040 MODULE_AUTHOR("Maxime Ripard <[email protected]>");
1041 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
1042 MODULE_LICENSE("GPL");