drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R-Car MIPI DSI Encoder
   4  *
   5  * Copyright (C) 2020 Renesas Electronics Corporation
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_graph.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/reset.h>
  18 #include <linux/slab.h>
  19
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_bridge.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drm_probe_helper.h>
  27
  28 #include "rcar_mipi_dsi_regs.h"
  29
  30 struct rcar_mipi_dsi {
  31         struct device *dev;
  32         const struct rcar_mipi_dsi_device_info *info;
  33         struct reset_control *rstc;
  34
  35         struct mipi_dsi_host host;
  36         struct drm_bridge bridge;
  37         struct drm_bridge *next_bridge;
  38         struct drm_connector connector;
  39
  40         void __iomem *mmio;
  41         struct {
  42                 struct clk *mod;
  43                 struct clk *pll;
  44                 struct clk *dsi;
  45         } clocks;
  46
  47         enum mipi_dsi_pixel_format format;
  48         unsigned int num_data_lanes;
  49         unsigned int lanes;
  50 };
  51
  52 static inline struct rcar_mipi_dsi *
  53 bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge)
  54 {
  55         return container_of(bridge, struct rcar_mipi_dsi, bridge);
  56 }
  57
  58 static inline struct rcar_mipi_dsi *
  59 host_to_rcar_mipi_dsi(struct mipi_dsi_host *host)
  60 {
  61         return container_of(host, struct rcar_mipi_dsi, host);
  62 }
  63
  64 static const u32 phtw[] = {
  65         0x01020114, 0x01600115, /* General testing */
  66         0x01030116, 0x0102011d, /* General testing */
  67         0x011101a4, 0x018601a4, /* 1Gbps testing */
  68         0x014201a0, 0x010001a3, /* 1Gbps testing */
  69         0x0101011f,             /* 1Gbps testing */
  70 };
  71
  72 static const u32 phtw2[] = {
  73         0x010c0130, 0x010c0140, /* General testing */
  74         0x010c0150, 0x010c0180, /* General testing */
  75         0x010c0190,
  76         0x010a0160, 0x010a0170,
  77         0x01800164, 0x01800174, /* 1Gbps testing */
  78 };
  79
  80 static const u32 hsfreqrange_table[][2] = {
  81         { 80000000U,   0x00 }, { 90000000U,   0x10 }, { 100000000U,  0x20 },
  82         { 110000000U,  0x30 }, { 120000000U,  0x01 }, { 130000000U,  0x11 },
  83         { 140000000U,  0x21 }, { 150000000U,  0x31 }, { 160000000U,  0x02 },
  84         { 170000000U,  0x12 }, { 180000000U,  0x22 }, { 190000000U,  0x32 },
  85         { 205000000U,  0x03 }, { 220000000U,  0x13 }, { 235000000U,  0x23 },
  86         { 250000000U,  0x33 }, { 275000000U,  0x04 }, { 300000000U,  0x14 },
  87         { 325000000U,  0x25 }, { 350000000U,  0x35 }, { 400000000U,  0x05 },
  88         { 450000000U,  0x16 }, { 500000000U,  0x26 }, { 550000000U,  0x37 },
  89         { 600000000U,  0x07 }, { 650000000U,  0x18 }, { 700000000U,  0x28 },
  90         { 750000000U,  0x39 }, { 800000000U,  0x09 }, { 850000000U,  0x19 },
  91         { 900000000U,  0x29 }, { 950000000U,  0x3a }, { 1000000000U, 0x0a },
  92         { 1050000000U, 0x1a }, { 1100000000U, 0x2a }, { 1150000000U, 0x3b },
  93         { 1200000000U, 0x0b }, { 1250000000U, 0x1b }, { 1300000000U, 0x2b },
  94         { 1350000000U, 0x3c }, { 1400000000U, 0x0c }, { 1450000000U, 0x1c },
  95         { 1500000000U, 0x2c }, { 1550000000U, 0x3d }, { 1600000000U, 0x0d },
  96         { 1650000000U, 0x1d }, { 1700000000U, 0x2e }, { 1750000000U, 0x3e },
  97         { 1800000000U, 0x0e }, { 1850000000U, 0x1e }, { 1900000000U, 0x2f },
  98         { 1950000000U, 0x3f }, { 2000000000U, 0x0f }, { 2050000000U, 0x40 },
  99         { 2100000000U, 0x41 }, { 2150000000U, 0x42 }, { 2200000000U, 0x43 },
 100         { 2250000000U, 0x44 }, { 2300000000U, 0x45 }, { 2350000000U, 0x46 },
 101         { 2400000000U, 0x47 }, { 2450000000U, 0x48 }, { 2500000000U, 0x49 },
 102         { /* sentinel */ },
 103 };
 104
 105 struct vco_cntrl_value {
 106         u32 min_freq;
 107         u32 max_freq;
 108         u16 value;
 109 };
 110
 111 static const struct vco_cntrl_value vco_cntrl_table[] = {
 112         { .min_freq = 40000000U,   .max_freq = 55000000U,   .value = 0x3f },
 113         { .min_freq = 52500000U,   .max_freq = 80000000U,   .value = 0x39 },
 114         { .min_freq = 80000000U,   .max_freq = 110000000U,  .value = 0x2f },
 115         { .min_freq = 105000000U,  .max_freq = 160000000U,  .value = 0x29 },
 116         { .min_freq = 160000000U,  .max_freq = 220000000U,  .value = 0x1f },
 117         { .min_freq = 210000000U,  .max_freq = 320000000U,  .value = 0x19 },
 118         { .min_freq = 320000000U,  .max_freq = 440000000U,  .value = 0x0f },
 119         { .min_freq = 420000000U,  .max_freq = 660000000U,  .value = 0x09 },
 120         { .min_freq = 630000000U,  .max_freq = 1149000000U, .value = 0x03 },
 121         { .min_freq = 1100000000U, .max_freq = 1152000000U, .value = 0x01 },
 122         { .min_freq = 1150000000U, .max_freq = 1250000000U, .value = 0x01 },
 123         { /* sentinel */ },
 124 };
 125
 126 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data)
 127 {
 128         iowrite32(data, dsi->mmio + reg);
 129 }
 130
 131 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg)
 132 {
 133         return ioread32(dsi->mmio + reg);
 134 }
 135
 136 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr)
 137 {
 138         rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr);
 139 }
 140
 141 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set)
 142 {
 143         rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set);
 144 }
 145
 146 static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *dsi, u32 phtw)
 147 {
 148         u32 status;
 149         int ret;
 150
 151         rcar_mipi_dsi_write(dsi, PHTW, phtw);
 152
 153         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 154                                 !(status & (PHTW_DWEN | PHTW_CWEN)),
 155                                 2000, 10000, false, dsi, PHTW);
 156         if (ret < 0) {
 157                 dev_err(dsi->dev, "PHY test interface write timeout (0x%08x)\n",
 158                         phtw);
 159                 return ret;
 160         }
 161
 162         return ret;
 163 }
 164
 165 /* -----------------------------------------------------------------------------
 166  * Hardware Setup
 167  */
 168
 169 struct dsi_setup_info {
 170         unsigned long fout;
 171         u16 vco_cntrl;
 172         u16 prop_cntrl;
 173         u16 hsfreqrange;
 174         u16 div;
 175         unsigned int m;
 176         unsigned int n;
 177 };
 178
 179 static void rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi *dsi,
 180                                           struct clk *clk, unsigned long target,
 181                                           struct dsi_setup_info *setup_info)
 182 {
 183
 184         const struct vco_cntrl_value *vco_cntrl;
 185         unsigned long fout_target;
 186         unsigned long fin, fout;
 187         unsigned long hsfreq;
 188         unsigned int best_err = -1;
 189         unsigned int divider;
 190         unsigned int n;
 191         unsigned int i;
 192         unsigned int err;
 193
 194         /*
 195          * Calculate Fout = dot clock * ColorDepth / (2 * Lane Count)
 196          * The range out Fout is [40 - 1250] Mhz
 197          */
 198         fout_target = target * mipi_dsi_pixel_format_to_bpp(dsi->format)
 199                     / (2 * dsi->lanes);
 200         if (fout_target < 40000000 || fout_target > 1250000000)
 201                 return;
 202
 203         /* Find vco_cntrl */
 204         for (vco_cntrl = vco_cntrl_table; vco_cntrl->min_freq != 0; vco_cntrl++) {
 205                 if (fout_target > vco_cntrl->min_freq &&
 206                     fout_target <= vco_cntrl->max_freq) {
 207                         setup_info->vco_cntrl = vco_cntrl->value;
 208                         if (fout_target >= 1150000000)
 209                                 setup_info->prop_cntrl = 0x0c;
 210                         else
 211                                 setup_info->prop_cntrl = 0x0b;
 212                         break;
 213                 }
 214         }
 215
 216         /* Add divider */
 217         setup_info->div = (setup_info->vco_cntrl & 0x30) >> 4;
 218
 219         /* Find hsfreqrange */
 220         hsfreq = fout_target * 2;
 221         for (i = 0; i < ARRAY_SIZE(hsfreqrange_table); i++) {
 222                 if (hsfreqrange_table[i][0] >= hsfreq) {
 223                         setup_info->hsfreqrange = hsfreqrange_table[i][1];
 224                         break;
 225                 }
 226         }
 227
 228         /*
 229          * Calculate n and m for PLL clock
 230          * Following the HW manual the ranges of n and m are
 231          * n = [3-8] and m = [64-625]
 232          */
 233         fin = clk_get_rate(clk);
 234         divider = 1 << setup_info->div;
 235         for (n = 3; n < 9; n++) {
 236                 unsigned long fpfd;
 237                 unsigned int m;
 238
 239                 fpfd = fin / n;
 240
 241                 for (m = 64; m < 626; m++) {
 242                         fout = fpfd * m / divider;
 243                         err = abs((long)(fout - fout_target) * 10000 /
 244                                   (long)fout_target);
 245                         if (err < best_err) {
 246                                 setup_info->m = m - 2;
 247                                 setup_info->n = n - 1;
 248                                 setup_info->fout = fout;
 249                                 best_err = err;
 250                                 if (err == 0)
 251                                         goto done;
 252                         }
 253                 }
 254         }
 255
 256 done:
 257         dev_dbg(dsi->dev,
 258                 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/DIV %u/%u/%u\n",
 259                 clk, fin, setup_info->fout, fout_target, best_err / 100,
 260                 best_err % 100, setup_info->m, setup_info->n, setup_info->div);
 261         dev_dbg(dsi->dev,
 262                 "vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n",
 263                 setup_info->vco_cntrl, setup_info->prop_cntrl,
 264                 setup_info->hsfreqrange);
 265 }
 266
 267 static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi,
 268                                              const struct drm_display_mode *mode)
 269 {
 270         u32 setr;
 271         u32 vprmset0r;
 272         u32 vprmset1r;
 273         u32 vprmset2r;
 274         u32 vprmset3r;
 275         u32 vprmset4r;
 276
 277         /* Configuration for Pixel Stream and Packet Header */
 278         if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24)
 279                 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24);
 280         else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18)
 281                 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18);
 282         else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16)
 283                 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16);
 284         else {
 285                 dev_warn(dsi->dev, "unsupported format");
 286                 return;
 287         }
 288
 289         /* Configuration for Blanking sequence and Input Pixel */
 290         setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN
 291              | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES
 292              | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
 293         rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
 294
 295         /* Configuration for Video Parameters */
 296         vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ?
 297                      TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW)
 298                   | (mode->flags & DRM_MODE_FLAG_PHSYNC ?
 299                      TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW)
 300                   | TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
 301
 302         vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay)
 303                   | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
 304
 305         vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay)
 306                   | TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
 307
 308         vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay)
 309                   | TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
 310
 311         vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay)
 312                   | TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
 313
 314         rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
 315         rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
 316         rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r);
 317         rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r);
 318         rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r);
 319 }
 320
 321 static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi,
 322                                  const struct drm_display_mode *mode)
 323 {
 324         struct dsi_setup_info setup_info = {};
 325         unsigned int timeout;
 326         int ret, i;
 327         int dsi_format;
 328         u32 phy_setup;
 329         u32 clockset2, clockset3;
 330         u32 ppisetr;
 331         u32 vclkset;
 332
 333         /* Checking valid format */
 334         dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
 335         if (dsi_format < 0) {
 336                 dev_warn(dsi->dev, "invalid format");
 337                 return -EINVAL;
 338         }
 339
 340         /* Parameters Calculation */
 341         rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.pll,
 342                                       mode->clock * 1000, &setup_info);
 343
 344         /* LPCLK enable */
 345         rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN);
 346
 347         /* CFGCLK enabled */
 348         rcar_mipi_dsi_set(dsi, CFGCLKSET, CFGCLKSET_CKEN);
 349
 350         rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
 351         rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
 352
 353         rcar_mipi_dsi_set(dsi, PHTC, PHTC_TESTCLR);
 354         rcar_mipi_dsi_clr(dsi, PHTC, PHTC_TESTCLR);
 355
 356         /* PHY setting */
 357         phy_setup = rcar_mipi_dsi_read(dsi, PHYSETUP);
 358         phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK;
 359         phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange);
 360         rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup);
 361
 362         for (i = 0; i < ARRAY_SIZE(phtw); i++) {
 363                 ret = rcar_mipi_dsi_phtw_test(dsi, phtw[i]);
 364                 if (ret < 0)
 365                         return ret;
 366         }
 367
 368         /* PLL Clock Setting */
 369         rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
 370         rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
 371         rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
 372
 373         clockset2 = CLOCKSET2_M(setup_info.m) | CLOCKSET2_N(setup_info.n)
 374                   | CLOCKSET2_VCO_CNTRL(setup_info.vco_cntrl);
 375         clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.prop_cntrl)
 376                   | CLOCKSET3_INT_CNTRL(0)
 377                   | CLOCKSET3_CPBIAS_CNTRL(0x10)
 378                   | CLOCKSET3_GMP_CNTRL(1);
 379         rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
 380         rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
 381
 382         rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
 383         rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
 384         udelay(10);
 385         rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
 386
 387         ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
 388         rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
 389
 390         rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
 391         rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_RSTZ);
 392         usleep_range(400, 500);
 393
 394         /* Checking PPI clock status register */
 395         for (timeout = 10; timeout > 0; --timeout) {
 396                 if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) &&
 397                     (rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) &&
 398                     (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK))
 399                         break;
 400
 401                 usleep_range(1000, 2000);
 402         }
 403
 404         if (!timeout) {
 405                 dev_err(dsi->dev, "failed to enable PPI clock\n");
 406                 return -ETIMEDOUT;
 407         }
 408
 409         for (i = 0; i < ARRAY_SIZE(phtw2); i++) {
 410                 ret = rcar_mipi_dsi_phtw_test(dsi, phtw2[i]);
 411                 if (ret < 0)
 412                         return ret;
 413         }
 414
 415         /* Enable DOT clock */
 416         vclkset = VCLKSET_CKEN;
 417         rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
 418
 419         if (dsi_format == 24)
 420                 vclkset |= VCLKSET_BPP_24;
 421         else if (dsi_format == 18)
 422                 vclkset |= VCLKSET_BPP_18;
 423         else if (dsi_format == 16)
 424                 vclkset |= VCLKSET_BPP_16;
 425         else {
 426                 dev_warn(dsi->dev, "unsupported format");
 427                 return -EINVAL;
 428         }
 429         vclkset |= VCLKSET_COLOR_RGB | VCLKSET_DIV(setup_info.div)
 430                 |  VCLKSET_LANE(dsi->lanes - 1);
 431
 432         rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
 433
 434         /* After setting VCLKSET register, enable VCLKEN */
 435         rcar_mipi_dsi_set(dsi, VCLKEN, VCLKEN_CKEN);
 436
 437         dev_dbg(dsi->dev, "DSI device is started\n");
 438
 439         return 0;
 440 }
 441
 442 static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
 443 {
 444         rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
 445         rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
 446
 447         dev_dbg(dsi->dev, "DSI device is shutdown\n");
 448 }
 449
 450 static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi)
 451 {
 452         int ret;
 453
 454         reset_control_deassert(dsi->rstc);
 455
 456         ret = clk_prepare_enable(dsi->clocks.mod);
 457         if (ret < 0)
 458                 goto err_reset;
 459
 460         ret = clk_prepare_enable(dsi->clocks.dsi);
 461         if (ret < 0)
 462                 goto err_clock;
 463
 464         return 0;
 465
 466 err_clock:
 467         clk_disable_unprepare(dsi->clocks.mod);
 468 err_reset:
 469         reset_control_assert(dsi->rstc);
 470         return ret;
 471 }
 472
 473 static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi)
 474 {
 475         clk_disable_unprepare(dsi->clocks.dsi);
 476         clk_disable_unprepare(dsi->clocks.mod);
 477
 478         reset_control_assert(dsi->rstc);
 479 }
 480
 481 static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
 482 {
 483         /*
 484          * In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
 485          * write how to check. So we skip this check in this patch
 486          */
 487         u32 status;
 488         int ret;
 489
 490         /* Start HS clock. */
 491         rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS);
 492
 493         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 494                                 status & PPICLSR_TOHS,
 495                                 2000, 10000, false, dsi, PPICLSR);
 496         if (ret < 0) {
 497                 dev_err(dsi->dev, "failed to enable HS clock\n");
 498                 return ret;
 499         }
 500
 501         rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
 502
 503         return 0;
 504 }
 505
 506 static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
 507 {
 508         u32 status;
 509         int ret;
 510
 511         /* Wait for the link to be ready. */
 512         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 513                                 !(status & (LINKSR_LPBUSY | LINKSR_HSBUSY)),
 514                                 2000, 10000, false, dsi, LINKSR);
 515         if (ret < 0) {
 516                 dev_err(dsi->dev, "Link failed to become ready\n");
 517                 return ret;
 518         }
 519
 520         /* De-assert video FIFO clear. */
 521         rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
 522
 523         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 524                                 status & TXVMSR_VFRDY,
 525                                 2000, 10000, false, dsi, TXVMSR);
 526         if (ret < 0) {
 527                 dev_err(dsi->dev, "Failed to de-assert video FIFO clear\n");
 528                 return ret;
 529         }
 530
 531         /* Enable transmission in video mode. */
 532         rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
 533
 534         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 535                                 status & TXVMSR_RDY,
 536                                 2000, 10000, false, dsi, TXVMSR);
 537         if (ret < 0) {
 538                 dev_err(dsi->dev, "Failed to enable video transmission\n");
 539                 return ret;
 540         }
 541
 542         return 0;
 543 }
 544
 545 /* -----------------------------------------------------------------------------
 546  * Bridge
 547  */
 548
 549 static int rcar_mipi_dsi_attach(struct drm_bridge *bridge,
 550                                 enum drm_bridge_attach_flags flags)
 551 {
 552         struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 553
 554         return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge,
 555                                  flags);
 556 }
 557
 558 static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
 559                                         struct drm_bridge_state *old_bridge_state)
 560 {
 561         struct drm_atomic_state *state = old_bridge_state->base.state;
 562         struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 563         const struct drm_display_mode *mode;
 564         struct drm_connector *connector;
 565         struct drm_crtc *crtc;
 566         int ret;
 567
 568         connector = drm_atomic_get_new_connector_for_encoder(state,
 569                                                              bridge->encoder);
 570         crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
 571         mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
 572
 573         ret = rcar_mipi_dsi_clk_enable(dsi);
 574         if (ret < 0) {
 575                 dev_err(dsi->dev, "failed to enable DSI clocks\n");
 576                 return;
 577         }
 578
 579         ret = rcar_mipi_dsi_startup(dsi, mode);
 580         if (ret < 0)
 581                 goto err_dsi_startup;
 582
 583         rcar_mipi_dsi_set_display_timing(dsi, mode);
 584
 585         ret = rcar_mipi_dsi_start_hs_clock(dsi);
 586         if (ret < 0)
 587                 goto err_dsi_start_hs;
 588
 589         rcar_mipi_dsi_start_video(dsi);
 590
 591         return;
 592
 593 err_dsi_start_hs:
 594         rcar_mipi_dsi_shutdown(dsi);
 595 err_dsi_startup:
 596         rcar_mipi_dsi_clk_disable(dsi);
 597 }
 598
 599 static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
 600                                          struct drm_bridge_state *old_bridge_state)
 601 {
 602         struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 603
 604         rcar_mipi_dsi_shutdown(dsi);
 605         rcar_mipi_dsi_clk_disable(dsi);
 606 }
 607
 608 static enum drm_mode_status
 609 rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
 610                                 const struct drm_display_info *info,
 611                                 const struct drm_display_mode *mode)
 612 {
 613         if (mode->clock > 297000)
 614                 return MODE_CLOCK_HIGH;
 615
 616         return MODE_OK;
 617 }
 618
 619 static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
 620         .attach = rcar_mipi_dsi_attach,
 621         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 622         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 623         .atomic_reset = drm_atomic_helper_bridge_reset,
 624         .atomic_enable = rcar_mipi_dsi_atomic_enable,
 625         .atomic_disable = rcar_mipi_dsi_atomic_disable,
 626         .mode_valid = rcar_mipi_dsi_bridge_mode_valid,
 627 };
 628
 629 /* -----------------------------------------------------------------------------
 630  * Host setting
 631  */
 632
 633 static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 634                                      struct mipi_dsi_device *device)
 635 {
 636         struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
 637         int ret;
 638
 639         if (device->lanes > dsi->num_data_lanes)
 640                 return -EINVAL;
 641
 642         dsi->lanes = device->lanes;
 643         dsi->format = device->format;
 644
 645         dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
 646                                                   1, 0);
 647         if (IS_ERR(dsi->next_bridge)) {
 648                 ret = PTR_ERR(dsi->next_bridge);
 649                 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
 650                 return ret;
 651         }
 652
 653         /* Initialize the DRM bridge. */
 654         dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
 655         dsi->bridge.of_node = dsi->dev->of_node;
 656         drm_bridge_add(&dsi->bridge);
 657
 658         return 0;
 659 }
 660
 661 static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 662                                         struct mipi_dsi_device *device)
 663 {
 664         struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
 665
 666         drm_bridge_remove(&dsi->bridge);
 667
 668         return 0;
 669 }
 670
 671 static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
 672         .attach = rcar_mipi_dsi_host_attach,
 673         .detach = rcar_mipi_dsi_host_detach,
 674 };
 675
 676 /* -----------------------------------------------------------------------------
 677  * Probe & Remove
 678  */
 679
 680 static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
 681 {
 682         int ret;
 683
 684         ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
 685         if (ret < 0) {
 686                 dev_err(dsi->dev, "missing or invalid data-lanes property\n");
 687                 return ret;
 688         }
 689
 690         dsi->num_data_lanes = ret;
 691         return 0;
 692 }
 693
 694 static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi,
 695                                            const char *name,
 696                                            bool optional)
 697 {
 698         struct clk *clk;
 699
 700         clk = devm_clk_get(dsi->dev, name);
 701         if (!IS_ERR(clk))
 702                 return clk;
 703
 704         if (PTR_ERR(clk) == -ENOENT && optional)
 705                 return NULL;
 706
 707         dev_err_probe(dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
 708                       name ? name : "module");
 709
 710         return clk;
 711 }
 712
 713 static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
 714 {
 715         dsi->clocks.mod = rcar_mipi_dsi_get_clock(dsi, NULL, false);
 716         if (IS_ERR(dsi->clocks.mod))
 717                 return PTR_ERR(dsi->clocks.mod);
 718
 719         dsi->clocks.pll = rcar_mipi_dsi_get_clock(dsi, "pll", true);
 720         if (IS_ERR(dsi->clocks.pll))
 721                 return PTR_ERR(dsi->clocks.pll);
 722
 723         dsi->clocks.dsi = rcar_mipi_dsi_get_clock(dsi, "dsi", true);
 724         if (IS_ERR(dsi->clocks.dsi))
 725                 return PTR_ERR(dsi->clocks.dsi);
 726
 727         if (!dsi->clocks.pll && !dsi->clocks.dsi) {
 728                 dev_err(dsi->dev, "no input clock (pll, dsi)\n");
 729                 return -EINVAL;
 730         }
 731
 732         return 0;
 733 }
 734
 735 static int rcar_mipi_dsi_probe(struct platform_device *pdev)
 736 {
 737         struct rcar_mipi_dsi *dsi;
 738         struct resource *mem;
 739         int ret;
 740
 741         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
 742         if (dsi == NULL)
 743                 return -ENOMEM;
 744
 745         platform_set_drvdata(pdev, dsi);
 746
 747         dsi->dev = &pdev->dev;
 748         dsi->info = of_device_get_match_data(&pdev->dev);
 749
 750         ret = rcar_mipi_dsi_parse_dt(dsi);
 751         if (ret < 0)
 752                 return ret;
 753
 754         /* Acquire resources. */
 755         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 756         dsi->mmio = devm_ioremap_resource(dsi->dev, mem);
 757         if (IS_ERR(dsi->mmio))
 758                 return PTR_ERR(dsi->mmio);
 759
 760         ret = rcar_mipi_dsi_get_clocks(dsi);
 761         if (ret < 0)
 762                 return ret;
 763
 764         dsi->rstc = devm_reset_control_get(dsi->dev, NULL);
 765         if (IS_ERR(dsi->rstc)) {
 766                 dev_err(dsi->dev, "failed to get cpg reset\n");
 767                 return PTR_ERR(dsi->rstc);
 768         }
 769
 770         /* Initialize the DSI host. */
 771         dsi->host.dev = dsi->dev;
 772         dsi->host.ops = &rcar_mipi_dsi_host_ops;
 773         ret = mipi_dsi_host_register(&dsi->host);
 774         if (ret < 0)
 775                 return ret;
 776
 777         return 0;
 778 }
 779
 780 static int rcar_mipi_dsi_remove(struct platform_device *pdev)
 781 {
 782         struct rcar_mipi_dsi *dsi = platform_get_drvdata(pdev);
 783
 784         mipi_dsi_host_unregister(&dsi->host);
 785
 786         return 0;
 787 }
 788
 789 static const struct of_device_id rcar_mipi_dsi_of_table[] = {
 790         { .compatible = "renesas,r8a779a0-dsi-csi2-tx" },
 791         { }
 792 };
 793
 794 MODULE_DEVICE_TABLE(of, rcar_mipi_dsi_of_table);
 795
 796 static struct platform_driver rcar_mipi_dsi_platform_driver = {
 797         .probe          = rcar_mipi_dsi_probe,
 798         .remove         = rcar_mipi_dsi_remove,
 799         .driver         = {
 800                 .name   = "rcar-mipi-dsi",
 801                 .of_match_table = rcar_mipi_dsi_of_table,
 802         },
 803 };
 804
 805 module_platform_driver(rcar_mipi_dsi_platform_driver);
 806
 807 MODULE_DESCRIPTION("Renesas R-Car MIPI DSI Encoder Driver");
 808 MODULE_LICENSE("GPL");