drivers/gpu/drm/amd/amdgpu/df_v1_7.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "df_v1_7.h"
  25
  26 #include "df/df_1_7_default.h"
  27 #include "df/df_1_7_offset.h"
  28 #include "df/df_1_7_sh_mask.h"
  29
  30 static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  31
  32 static void df_v1_7_sw_init(struct amdgpu_device *adev)
  33 {
  34 }
  35
  36 static void df_v1_7_sw_fini(struct amdgpu_device *adev)
  37 {
  38 }
  39
  40 static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
  41                                           bool enable)
  42 {
  43         u32 tmp;
  44
  45         if (enable) {
  46                 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
  47                 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
  48                 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
  49         } else
  50                 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
  51                              mmFabricConfigAccessControl_DEFAULT);
  52 }
  53
  54 static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
  55 {
  56         u32 tmp;
  57
  58         tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
  59         tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
  60         tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
  61
  62         return tmp;
  63 }
  64
  65 static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
  66 {
  67         int fb_channel_number;
  68
  69         fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
  70
  71         return df_v1_7_channel_number[fb_channel_number];
  72 }
  73
  74 static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
  75                                                      bool enable)
  76 {
  77         u32 tmp;
  78
  79         /* Put DF on broadcast mode */
  80         adev->df_funcs->enable_broadcast_mode(adev, true);
  81
  82         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
  83                 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
  84                 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
  85                 tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
  86                 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
  87         } else {
  88                 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
  89                 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
  90                 tmp |= DF_V1_7_MGCG_DISABLE;
  91                 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
  92         }
  93
  94         /* Exit boradcast mode */
  95         adev->df_funcs->enable_broadcast_mode(adev, false);
  96 }
  97
  98 static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
  99                                           u32 *flags)
 100 {
 101         u32 tmp;
 102
 103         /* AMD_CG_SUPPORT_DF_MGCG */
 104         tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
 105         if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
 106                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 107 }
 108
 109 static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
 110                                                 bool enable)
 111 {
 112         WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
 113                        ForceParWrRMW, enable);
 114 }
 115
 116 const struct amdgpu_df_funcs df_v1_7_funcs = {
 117         .sw_init = df_v1_7_sw_init,
 118         .sw_fini = df_v1_7_sw_fini,
 119         .enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
 120         .get_fb_channel_number = df_v1_7_get_fb_channel_number,
 121         .get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
 122         .update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
 123         .get_clockgating_state = df_v1_7_get_clockgating_state,
 124         .enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
 125 };