drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37
  38 #include <drm/drm_debugfs.h>
  39
  40 #include "amdgpu.h"
  41 #include "amdgpu_trace.h"
  42
  43 /*
  44  * Fences
  45  * Fences mark an event in the GPUs pipeline and are used
  46  * for GPU/CPU synchronization.  When the fence is written,
  47  * it is expected that all buffers associated with that fence
  48  * are no longer in use by the associated ring on the GPU and
  49  * that the the relevant GPU caches have been flushed.
  50  */
  51
  52 struct amdgpu_fence {
  53         struct dma_fence base;
  54
  55         /* RB, DMA, etc. */
  56         struct amdgpu_ring              *ring;
  57 };
  58
  59 static struct kmem_cache *amdgpu_fence_slab;
  60
  61 int amdgpu_fence_slab_init(void)
  62 {
  63         amdgpu_fence_slab = kmem_cache_create(
  64                 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
  65                 SLAB_HWCACHE_ALIGN, NULL);
  66         if (!amdgpu_fence_slab)
  67                 return -ENOMEM;
  68         return 0;
  69 }
  70
  71 void amdgpu_fence_slab_fini(void)
  72 {
  73         rcu_barrier();
  74         kmem_cache_destroy(amdgpu_fence_slab);
  75 }
  76 /*
  77  * Cast helper
  78  */
  79 static const struct dma_fence_ops amdgpu_fence_ops;
  80 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
  81 {
  82         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  83
  84         if (__f->base.ops == &amdgpu_fence_ops)
  85                 return __f;
  86
  87         return NULL;
  88 }
  89
  90 /**
  91  * amdgpu_fence_write - write a fence value
  92  *
  93  * @ring: ring the fence is associated with
  94  * @seq: sequence number to write
  95  *
  96  * Writes a fence value to memory (all asics).
  97  */
  98 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  99 {
 100         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 101
 102         if (drv->cpu_addr)
 103                 *drv->cpu_addr = cpu_to_le32(seq);
 104 }
 105
 106 /**
 107  * amdgpu_fence_read - read a fence value
 108  *
 109  * @ring: ring the fence is associated with
 110  *
 111  * Reads a fence value from memory (all asics).
 112  * Returns the value of the fence read from memory.
 113  */
 114 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
 115 {
 116         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 117         u32 seq = 0;
 118
 119         if (drv->cpu_addr)
 120                 seq = le32_to_cpu(*drv->cpu_addr);
 121         else
 122                 seq = atomic_read(&drv->last_seq);
 123
 124         return seq;
 125 }
 126
 127 /**
 128  * amdgpu_fence_emit - emit a fence on the requested ring
 129  *
 130  * @ring: ring the fence is associated with
 131  * @f: resulting fence object
 132  *
 133  * Emits a fence command on the requested ring (all asics).
 134  * Returns 0 on success, -ENOMEM on failure.
 135  */
 136 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
 137                       unsigned flags)
 138 {
 139         struct amdgpu_device *adev = ring->adev;
 140         struct amdgpu_fence *fence;
 141         struct dma_fence __rcu **ptr;
 142         uint32_t seq;
 143         int r;
 144
 145         fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
 146         if (fence == NULL)
 147                 return -ENOMEM;
 148
 149         seq = ++ring->fence_drv.sync_seq;
 150         fence->ring = ring;
 151         dma_fence_init(&fence->base, &amdgpu_fence_ops,
 152                        &ring->fence_drv.lock,
 153                        adev->fence_context + ring->idx,
 154                        seq);
 155         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 156                                seq, flags | AMDGPU_FENCE_FLAG_INT);
 157
 158         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 159         if (unlikely(rcu_dereference_protected(*ptr, 1))) {
 160                 struct dma_fence *old;
 161
 162                 rcu_read_lock();
 163                 old = dma_fence_get_rcu_safe(ptr);
 164                 rcu_read_unlock();
 165
 166                 if (old) {
 167                         r = dma_fence_wait(old, false);
 168                         dma_fence_put(old);
 169                         if (r)
 170                                 return r;
 171                 }
 172         }
 173
 174         /* This function can't be called concurrently anyway, otherwise
 175          * emitting the fence would mess up the hardware ring buffer.
 176          */
 177         rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
 178
 179         *f = &fence->base;
 180
 181         return 0;
 182 }
 183
 184 /**
 185  * amdgpu_fence_emit_polling - emit a fence on the requeste ring
 186  *
 187  * @ring: ring the fence is associated with
 188  * @s: resulting sequence number
 189  *
 190  * Emits a fence command on the requested ring (all asics).
 191  * Used For polling fence.
 192  * Returns 0 on success, -ENOMEM on failure.
 193  */
 194 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
 195 {
 196         uint32_t seq;
 197
 198         if (!s)
 199                 return -EINVAL;
 200
 201         seq = ++ring->fence_drv.sync_seq;
 202         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 203                                seq, 0);
 204
 205         *s = seq;
 206
 207         return 0;
 208 }
 209
 210 /**
 211  * amdgpu_fence_schedule_fallback - schedule fallback check
 212  *
 213  * @ring: pointer to struct amdgpu_ring
 214  *
 215  * Start a timer as fallback to our interrupts.
 216  */
 217 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 218 {
 219         mod_timer(&ring->fence_drv.fallback_timer,
 220                   jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
 221 }
 222
 223 /**
 224  * amdgpu_fence_process - check for fence activity
 225  *
 226  * @ring: pointer to struct amdgpu_ring
 227  *
 228  * Checks the current fence value and calculates the last
 229  * signalled fence value. Wakes the fence queue if the
 230  * sequence number has increased.
 231  *
 232  * Returns true if fence was processed
 233  */
 234 bool amdgpu_fence_process(struct amdgpu_ring *ring)
 235 {
 236         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 237         uint32_t seq, last_seq;
 238         int r;
 239
 240         do {
 241                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 242                 seq = amdgpu_fence_read(ring);
 243
 244         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 245
 246         if (del_timer(&ring->fence_drv.fallback_timer) &&
 247             seq != ring->fence_drv.sync_seq)
 248                 amdgpu_fence_schedule_fallback(ring);
 249
 250         if (unlikely(seq == last_seq))
 251                 return false;
 252
 253         last_seq &= drv->num_fences_mask;
 254         seq &= drv->num_fences_mask;
 255
 256         do {
 257                 struct dma_fence *fence, **ptr;
 258
 259                 ++last_seq;
 260                 last_seq &= drv->num_fences_mask;
 261                 ptr = &drv->fences[last_seq];
 262
 263                 /* There is always exactly one thread signaling this fence slot */
 264                 fence = rcu_dereference_protected(*ptr, 1);
 265                 RCU_INIT_POINTER(*ptr, NULL);
 266
 267                 if (!fence)
 268                         continue;
 269
 270                 r = dma_fence_signal(fence);
 271                 if (!r)
 272                         DMA_FENCE_TRACE(fence, "signaled from irq context\n");
 273                 else
 274                         BUG();
 275
 276                 dma_fence_put(fence);
 277         } while (last_seq != seq);
 278
 279         return true;
 280 }
 281
 282 /**
 283  * amdgpu_fence_fallback - fallback for hardware interrupts
 284  *
 285  * @work: delayed work item
 286  *
 287  * Checks for fence activity.
 288  */
 289 static void amdgpu_fence_fallback(struct timer_list *t)
 290 {
 291         struct amdgpu_ring *ring = from_timer(ring, t,
 292                                               fence_drv.fallback_timer);
 293
 294         if (amdgpu_fence_process(ring))
 295                 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
 296 }
 297
 298 /**
 299  * amdgpu_fence_wait_empty - wait for all fences to signal
 300  *
 301  * @adev: amdgpu device pointer
 302  * @ring: ring index the fence is associated with
 303  *
 304  * Wait for all fences on the requested ring to signal (all asics).
 305  * Returns 0 if the fences have passed, error for all other cases.
 306  */
 307 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 308 {
 309         uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
 310         struct dma_fence *fence, **ptr;
 311         int r;
 312
 313         if (!seq)
 314                 return 0;
 315
 316         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 317         rcu_read_lock();
 318         fence = rcu_dereference(*ptr);
 319         if (!fence || !dma_fence_get_rcu(fence)) {
 320                 rcu_read_unlock();
 321                 return 0;
 322         }
 323         rcu_read_unlock();
 324
 325         r = dma_fence_wait(fence, false);
 326         dma_fence_put(fence);
 327         return r;
 328 }
 329
 330 /**
 331  * amdgpu_fence_wait_polling - busy wait for givn sequence number
 332  *
 333  * @ring: ring index the fence is associated with
 334  * @wait_seq: sequence number to wait
 335  * @timeout: the timeout for waiting in usecs
 336  *
 337  * Wait for all fences on the requested ring to signal (all asics).
 338  * Returns left time if no timeout, 0 or minus if timeout.
 339  */
 340 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 341                                       uint32_t wait_seq,
 342                                       signed long timeout)
 343 {
 344         uint32_t seq;
 345
 346         do {
 347                 seq = amdgpu_fence_read(ring);
 348                 udelay(5);
 349                 timeout -= 5;
 350         } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
 351
 352         return timeout > 0 ? timeout : 0;
 353 }
 354 /**
 355  * amdgpu_fence_count_emitted - get the count of emitted fences
 356  *
 357  * @ring: ring the fence is associated with
 358  *
 359  * Get the number of fences emitted on the requested ring (all asics).
 360  * Returns the number of emitted fences on the ring.  Used by the
 361  * dynpm code to ring track activity.
 362  */
 363 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 364 {
 365         uint64_t emitted;
 366
 367         /* We are not protected by ring lock when reading the last sequence
 368          * but it's ok to report slightly wrong fence count here.
 369          */
 370         amdgpu_fence_process(ring);
 371         emitted = 0x100000000ull;
 372         emitted -= atomic_read(&ring->fence_drv.last_seq);
 373         emitted += READ_ONCE(ring->fence_drv.sync_seq);
 374         return lower_32_bits(emitted);
 375 }
 376
 377 /**
 378  * amdgpu_fence_driver_start_ring - make the fence driver
 379  * ready for use on the requested ring.
 380  *
 381  * @ring: ring to start the fence driver on
 382  * @irq_src: interrupt source to use for this ring
 383  * @irq_type: interrupt type to use for this ring
 384  *
 385  * Make the fence driver ready for processing (all asics).
 386  * Not all asics have all rings, so each asic will only
 387  * start the fence driver on the rings it has.
 388  * Returns 0 for success, errors for failure.
 389  */
 390 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 391                                    struct amdgpu_irq_src *irq_src,
 392                                    unsigned irq_type)
 393 {
 394         struct amdgpu_device *adev = ring->adev;
 395         uint64_t index;
 396
 397         if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
 398                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 399                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 400         } else {
 401                 /* put fence directly behind firmware */
 402                 index = ALIGN(adev->uvd.fw->size, 8);
 403                 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
 404                 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
 405         }
 406         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 407         amdgpu_irq_get(adev, irq_src, irq_type);
 408
 409         ring->fence_drv.irq_src = irq_src;
 410         ring->fence_drv.irq_type = irq_type;
 411         ring->fence_drv.initialized = true;
 412
 413         DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr "
 414                       "0x%016llx, cpu addr 0x%p\n", ring->name,
 415                       ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
 416         return 0;
 417 }
 418
 419 /**
 420  * amdgpu_fence_driver_init_ring - init the fence driver
 421  * for the requested ring.
 422  *
 423  * @ring: ring to init the fence driver on
 424  * @num_hw_submission: number of entries on the hardware queue
 425  *
 426  * Init the fence driver for the requested ring (all asics).
 427  * Helper function for amdgpu_fence_driver_init().
 428  */
 429 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 430                                   unsigned num_hw_submission)
 431 {
 432         struct amdgpu_device *adev = ring->adev;
 433         long timeout;
 434         int r;
 435
 436         if (!adev)
 437                 return -EINVAL;
 438
 439         /* Check that num_hw_submission is a power of two */
 440         if ((num_hw_submission & (num_hw_submission - 1)) != 0)
 441                 return -EINVAL;
 442
 443         ring->fence_drv.cpu_addr = NULL;
 444         ring->fence_drv.gpu_addr = 0;
 445         ring->fence_drv.sync_seq = 0;
 446         atomic_set(&ring->fence_drv.last_seq, 0);
 447         ring->fence_drv.initialized = false;
 448
 449         timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
 450
 451         ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
 452         spin_lock_init(&ring->fence_drv.lock);
 453         ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
 454                                          GFP_KERNEL);
 455         if (!ring->fence_drv.fences)
 456                 return -ENOMEM;
 457
 458         /* No need to setup the GPU scheduler for KIQ ring */
 459         if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
 460                 switch (ring->funcs->type) {
 461                 case AMDGPU_RING_TYPE_GFX:
 462                         timeout = adev->gfx_timeout;
 463                         break;
 464                 case AMDGPU_RING_TYPE_COMPUTE:
 465                         timeout = adev->compute_timeout;
 466                         break;
 467                 case AMDGPU_RING_TYPE_SDMA:
 468                         timeout = adev->sdma_timeout;
 469                         break;
 470                 default:
 471                         timeout = adev->video_timeout;
 472                         break;
 473                 }
 474
 475                 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
 476                                    num_hw_submission, amdgpu_job_hang_limit,
 477                                    timeout, ring->name);
 478                 if (r) {
 479                         DRM_ERROR("Failed to create scheduler on ring %s.\n",
 480                                   ring->name);
 481                         return r;
 482                 }
 483         }
 484
 485         return 0;
 486 }
 487
 488 /**
 489  * amdgpu_fence_driver_init - init the fence driver
 490  * for all possible rings.
 491  *
 492  * @adev: amdgpu device pointer
 493  *
 494  * Init the fence driver for all possible rings (all asics).
 495  * Not all asics have all rings, so each asic will only
 496  * start the fence driver on the rings it has using
 497  * amdgpu_fence_driver_start_ring().
 498  * Returns 0 for success.
 499  */
 500 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 501 {
 502         if (amdgpu_debugfs_fence_init(adev))
 503                 dev_err(adev->dev, "fence debugfs file creation failed\n");
 504
 505         return 0;
 506 }
 507
 508 /**
 509  * amdgpu_fence_driver_fini - tear down the fence driver
 510  * for all possible rings.
 511  *
 512  * @adev: amdgpu device pointer
 513  *
 514  * Tear down the fence driver for all possible rings (all asics).
 515  */
 516 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 517 {
 518         unsigned i, j;
 519         int r;
 520
 521         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 522                 struct amdgpu_ring *ring = adev->rings[i];
 523
 524                 if (!ring || !ring->fence_drv.initialized)
 525                         continue;
 526                 r = amdgpu_fence_wait_empty(ring);
 527                 if (r) {
 528                         /* no need to trigger GPU reset as we are unloading */
 529                         amdgpu_fence_driver_force_completion(ring);
 530                 }
 531                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 532                                ring->fence_drv.irq_type);
 533                 drm_sched_fini(&ring->sched);
 534                 del_timer_sync(&ring->fence_drv.fallback_timer);
 535                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 536                         dma_fence_put(ring->fence_drv.fences[j]);
 537                 kfree(ring->fence_drv.fences);
 538                 ring->fence_drv.fences = NULL;
 539                 ring->fence_drv.initialized = false;
 540         }
 541 }
 542
 543 /**
 544  * amdgpu_fence_driver_suspend - suspend the fence driver
 545  * for all possible rings.
 546  *
 547  * @adev: amdgpu device pointer
 548  *
 549  * Suspend the fence driver for all possible rings (all asics).
 550  */
 551 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
 552 {
 553         int i, r;
 554
 555         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 556                 struct amdgpu_ring *ring = adev->rings[i];
 557                 if (!ring || !ring->fence_drv.initialized)
 558                         continue;
 559
 560                 /* wait for gpu to finish processing current batch */
 561                 r = amdgpu_fence_wait_empty(ring);
 562                 if (r) {
 563                         /* delay GPU reset to resume */
 564                         amdgpu_fence_driver_force_completion(ring);
 565                 }
 566
 567                 /* disable the interrupt */
 568                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 569                                ring->fence_drv.irq_type);
 570         }
 571 }
 572
 573 /**
 574  * amdgpu_fence_driver_resume - resume the fence driver
 575  * for all possible rings.
 576  *
 577  * @adev: amdgpu device pointer
 578  *
 579  * Resume the fence driver for all possible rings (all asics).
 580  * Not all asics have all rings, so each asic will only
 581  * start the fence driver on the rings it has using
 582  * amdgpu_fence_driver_start_ring().
 583  * Returns 0 for success.
 584  */
 585 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
 586 {
 587         int i;
 588
 589         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 590                 struct amdgpu_ring *ring = adev->rings[i];
 591                 if (!ring || !ring->fence_drv.initialized)
 592                         continue;
 593
 594                 /* enable the interrupt */
 595                 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 596                                ring->fence_drv.irq_type);
 597         }
 598 }
 599
 600 /**
 601  * amdgpu_fence_driver_force_completion - force signal latest fence of ring
 602  *
 603  * @ring: fence of the ring to signal
 604  *
 605  */
 606 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
 607 {
 608         amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 609         amdgpu_fence_process(ring);
 610 }
 611
 612 /*
 613  * Common fence implementation
 614  */
 615
 616 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
 617 {
 618         return "amdgpu";
 619 }
 620
 621 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 622 {
 623         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 624         return (const char *)fence->ring->name;
 625 }
 626
 627 /**
 628  * amdgpu_fence_enable_signaling - enable signalling on fence
 629  * @fence: fence
 630  *
 631  * This function is called with fence_queue lock held, and adds a callback
 632  * to fence_queue that checks if this fence is signaled, and if so it
 633  * signals the fence and removes itself.
 634  */
 635 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
 636 {
 637         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 638         struct amdgpu_ring *ring = fence->ring;
 639
 640         if (!timer_pending(&ring->fence_drv.fallback_timer))
 641                 amdgpu_fence_schedule_fallback(ring);
 642
 643         DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
 644
 645         return true;
 646 }
 647
 648 /**
 649  * amdgpu_fence_free - free up the fence memory
 650  *
 651  * @rcu: RCU callback head
 652  *
 653  * Free up the fence memory after the RCU grace period.
 654  */
 655 static void amdgpu_fence_free(struct rcu_head *rcu)
 656 {
 657         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 658         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 659         kmem_cache_free(amdgpu_fence_slab, fence);
 660 }
 661
 662 /**
 663  * amdgpu_fence_release - callback that fence can be freed
 664  *
 665  * @fence: fence
 666  *
 667  * This function is called when the reference count becomes zero.
 668  * It just RCU schedules freeing up the fence.
 669  */
 670 static void amdgpu_fence_release(struct dma_fence *f)
 671 {
 672         call_rcu(&f->rcu, amdgpu_fence_free);
 673 }
 674
 675 static const struct dma_fence_ops amdgpu_fence_ops = {
 676         .get_driver_name = amdgpu_fence_get_driver_name,
 677         .get_timeline_name = amdgpu_fence_get_timeline_name,
 678         .enable_signaling = amdgpu_fence_enable_signaling,
 679         .release = amdgpu_fence_release,
 680 };
 681
 682 /*
 683  * Fence debugfs
 684  */
 685 #if defined(CONFIG_DEBUG_FS)
 686 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
 687 {
 688         struct drm_info_node *node = (struct drm_info_node *)m->private;
 689         struct drm_device *dev = node->minor->dev;
 690         struct amdgpu_device *adev = dev->dev_private;
 691         int i;
 692
 693         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 694                 struct amdgpu_ring *ring = adev->rings[i];
 695                 if (!ring || !ring->fence_drv.initialized)
 696                         continue;
 697
 698                 amdgpu_fence_process(ring);
 699
 700                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 701                 seq_printf(m, "Last signaled fence          0x%08x\n",
 702                            atomic_read(&ring->fence_drv.last_seq));
 703                 seq_printf(m, "Last emitted                 0x%08x\n",
 704                            ring->fence_drv.sync_seq);
 705
 706                 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
 707                     ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
 708                         seq_printf(m, "Last signaled trailing fence 0x%08x\n",
 709                                    le32_to_cpu(*ring->trail_fence_cpu_addr));
 710                         seq_printf(m, "Last emitted                 0x%08x\n",
 711                                    ring->trail_seq);
 712                 }
 713
 714                 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
 715                         continue;
 716
 717                 /* set in CP_VMID_PREEMPT and preemption occurred */
 718                 seq_printf(m, "Last preempted               0x%08x\n",
 719                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
 720                 /* set in CP_VMID_RESET and reset occurred */
 721                 seq_printf(m, "Last reset                   0x%08x\n",
 722                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
 723                 /* Both preemption and reset occurred */
 724                 seq_printf(m, "Last both                    0x%08x\n",
 725                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
 726         }
 727         return 0;
 728 }
 729
 730 /**
 731  * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
 732  *
 733  * Manually trigger a gpu reset at the next fence wait.
 734  */
 735 static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data)
 736 {
 737         struct drm_info_node *node = (struct drm_info_node *) m->private;
 738         struct drm_device *dev = node->minor->dev;
 739         struct amdgpu_device *adev = dev->dev_private;
 740
 741         seq_printf(m, "gpu recover\n");
 742         amdgpu_device_gpu_recover(adev, NULL);
 743
 744         return 0;
 745 }
 746
 747 static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
 748         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 749         {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL}
 750 };
 751
 752 static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = {
 753         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 754 };
 755 #endif
 756
 757 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 758 {
 759 #if defined(CONFIG_DEBUG_FS)
 760         if (amdgpu_sriov_vf(adev))
 761                 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1);
 762         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
 763 #else
 764         return 0;
 765 #endif
 766 }
 767