drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30
  31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
  32 {
  33         DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
  34         DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
  35         DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
  36         DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
  37         DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
  38         DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
  39         DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
  40         DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
  41         DRM_DEBUG("ucode_array_offset_bytes: %u\n",
  42                   le32_to_cpu(hdr->ucode_array_offset_bytes));
  43         DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
  44 }
  45
  46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
  47 {
  48         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  49         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  50
  51         DRM_DEBUG("MC\n");
  52         amdgpu_ucode_print_common_hdr(hdr);
  53
  54         if (version_major == 1) {
  55                 const struct mc_firmware_header_v1_0 *mc_hdr =
  56                         container_of(hdr, struct mc_firmware_header_v1_0, header);
  57
  58                 DRM_DEBUG("io_debug_size_bytes: %u\n",
  59                           le32_to_cpu(mc_hdr->io_debug_size_bytes));
  60                 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
  61                           le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
  62         } else {
  63                 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
  64         }
  65 }
  66
  67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
  68 {
  69         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  70         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  71         const struct smc_firmware_header_v1_0 *v1_0_hdr;
  72         const struct smc_firmware_header_v2_0 *v2_0_hdr;
  73         const struct smc_firmware_header_v2_1 *v2_1_hdr;
  74
  75         DRM_DEBUG("SMC\n");
  76         amdgpu_ucode_print_common_hdr(hdr);
  77
  78         if (version_major == 1) {
  79                 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
  80                 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
  81         } else if (version_major == 2) {
  82                 switch (version_minor) {
  83                 case 0:
  84                         v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
  85                         DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
  86                         DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
  87                         break;
  88                 case 1:
  89                         v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
  90                         DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
  91                         DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
  92                         break;
  93                 default:
  94                         break;
  95                 }
  96
  97         } else {
  98                 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
  99         }
 100 }
 101
 102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
 103 {
 104         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 105         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 106
 107         DRM_DEBUG("GFX\n");
 108         amdgpu_ucode_print_common_hdr(hdr);
 109
 110         if (version_major == 1) {
 111                 const struct gfx_firmware_header_v1_0 *gfx_hdr =
 112                         container_of(hdr, struct gfx_firmware_header_v1_0, header);
 113
 114                 DRM_DEBUG("ucode_feature_version: %u\n",
 115                           le32_to_cpu(gfx_hdr->ucode_feature_version));
 116                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
 117                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
 118         } else if (version_major == 2) {
 119                 const struct gfx_firmware_header_v2_0 *gfx_hdr =
 120                         container_of(hdr, struct gfx_firmware_header_v2_0, header);
 121
 122                 DRM_DEBUG("ucode_feature_version: %u\n",
 123                           le32_to_cpu(gfx_hdr->ucode_feature_version));
 124         } else {
 125                 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
 126         }
 127 }
 128
 129 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
 130 {
 131         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 132         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 133
 134         DRM_DEBUG("RLC\n");
 135         amdgpu_ucode_print_common_hdr(hdr);
 136
 137         if (version_major == 1) {
 138                 const struct rlc_firmware_header_v1_0 *rlc_hdr =
 139                         container_of(hdr, struct rlc_firmware_header_v1_0, header);
 140
 141                 DRM_DEBUG("ucode_feature_version: %u\n",
 142                           le32_to_cpu(rlc_hdr->ucode_feature_version));
 143                 DRM_DEBUG("save_and_restore_offset: %u\n",
 144                           le32_to_cpu(rlc_hdr->save_and_restore_offset));
 145                 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
 146                           le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
 147                 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
 148                           le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
 149                 DRM_DEBUG("master_pkt_description_offset: %u\n",
 150                           le32_to_cpu(rlc_hdr->master_pkt_description_offset));
 151         } else if (version_major == 2) {
 152                 const struct rlc_firmware_header_v2_0 *rlc_hdr =
 153                         container_of(hdr, struct rlc_firmware_header_v2_0, header);
 154                 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 =
 155                         container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
 156                 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 =
 157                         container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1);
 158                 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 =
 159                         container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2);
 160                 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 =
 161                         container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3);
 162
 163                 switch (version_minor) {
 164                 case 0:
 165                         /* rlc_hdr v2_0 */
 166                         DRM_DEBUG("ucode_feature_version: %u\n",
 167                                   le32_to_cpu(rlc_hdr->ucode_feature_version));
 168                         DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
 169                         DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
 170                         DRM_DEBUG("save_and_restore_offset: %u\n",
 171                                   le32_to_cpu(rlc_hdr->save_and_restore_offset));
 172                         DRM_DEBUG("clear_state_descriptor_offset: %u\n",
 173                                   le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
 174                         DRM_DEBUG("avail_scratch_ram_locations: %u\n",
 175                                   le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
 176                         DRM_DEBUG("reg_restore_list_size: %u\n",
 177                                   le32_to_cpu(rlc_hdr->reg_restore_list_size));
 178                         DRM_DEBUG("reg_list_format_start: %u\n",
 179                                   le32_to_cpu(rlc_hdr->reg_list_format_start));
 180                         DRM_DEBUG("reg_list_format_separate_start: %u\n",
 181                                   le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
 182                         DRM_DEBUG("starting_offsets_start: %u\n",
 183                                   le32_to_cpu(rlc_hdr->starting_offsets_start));
 184                         DRM_DEBUG("reg_list_format_size_bytes: %u\n",
 185                                   le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
 186                         DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
 187                                   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 188                         DRM_DEBUG("reg_list_size_bytes: %u\n",
 189                                   le32_to_cpu(rlc_hdr->reg_list_size_bytes));
 190                         DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
 191                                   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 192                         DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
 193                                   le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
 194                         DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
 195                                   le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
 196                         DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
 197                                   le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
 198                         DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
 199                                   le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
 200                         break;
 201                 case 1:
 202                         /* rlc_hdr v2_1 */
 203                         DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
 204                                   le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length));
 205                         DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
 206                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver));
 207                         DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
 208                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver));
 209                         DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
 210                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes));
 211                         DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
 212                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes));
 213                         DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
 214                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver));
 215                         DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
 216                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver));
 217                         DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
 218                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes));
 219                         DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
 220                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes));
 221                         DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
 222                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver));
 223                         DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
 224                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver));
 225                         DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
 226                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes));
 227                         DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
 228                                   le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes));
 229                         break;
 230                 case 2:
 231                         /* rlc_hdr v2_2 */
 232                         DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",
 233                                   le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes));
 234                         DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",
 235                                   le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes));
 236                         DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",
 237                                   le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes));
 238                         DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",
 239                                   le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes));
 240                         break;
 241                 case 3:
 242                         /* rlc_hdr v2_3 */
 243                         DRM_DEBUG("rlcp_ucode_version: %u\n",
 244                                   le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version));
 245                         DRM_DEBUG("rlcp_ucode_feature_version: %u\n",
 246                                   le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version));
 247                         DRM_DEBUG("rlcp_ucode_size_bytes: %u\n",
 248                                   le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes));
 249                         DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n",
 250                                   le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes));
 251                         DRM_DEBUG("rlcv_ucode_version: %u\n",
 252                                   le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version));
 253                         DRM_DEBUG("rlcv_ucode_feature_version: %u\n",
 254                                   le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version));
 255                         DRM_DEBUG("rlcv_ucode_size_bytes: %u\n",
 256                                   le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes));
 257                         DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n",
 258                                   le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes));
 259                         break;
 260                 case 4:
 261                         /* rlc_hdr v2_4 */
 262                         DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n",
 263                                   le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes));
 264                         DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n",
 265                                   le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes));
 266                         DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n",
 267                                   le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes));
 268                         DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n",
 269                                   le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes));
 270                         DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n",
 271                                   le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes));
 272                         DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n",
 273                                   le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes));
 274                         DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n",
 275                                   le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes));
 276                         DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n",
 277                                   le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes));
 278                         DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n",
 279                                   le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes));
 280                         DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",
 281                                   le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes));
 282                         break;
 283                 default:
 284                         DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor);
 285                         break;
 286                 }
 287         } else {
 288                 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
 289         }
 290 }
 291
 292 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
 293 {
 294         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 295         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 296
 297         DRM_DEBUG("SDMA\n");
 298         amdgpu_ucode_print_common_hdr(hdr);
 299
 300         if (version_major == 1) {
 301                 const struct sdma_firmware_header_v1_0 *sdma_hdr =
 302                         container_of(hdr, struct sdma_firmware_header_v1_0, header);
 303
 304                 DRM_DEBUG("ucode_feature_version: %u\n",
 305                           le32_to_cpu(sdma_hdr->ucode_feature_version));
 306                 DRM_DEBUG("ucode_change_version: %u\n",
 307                           le32_to_cpu(sdma_hdr->ucode_change_version));
 308                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
 309                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
 310                 if (version_minor >= 1) {
 311                         const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
 312                                 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
 313                         DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
 314                 }
 315         } else if (version_major == 2) {
 316                 const struct sdma_firmware_header_v2_0 *sdma_hdr =
 317                         container_of(hdr, struct sdma_firmware_header_v2_0, header);
 318
 319                 DRM_DEBUG("ucode_feature_version: %u\n",
 320                           le32_to_cpu(sdma_hdr->ucode_feature_version));
 321                 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));
 322                 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));
 323                 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));
 324                 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));
 325                 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));
 326         } else {
 327                 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
 328                           version_major, version_minor);
 329         }
 330 }
 331
 332 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
 333 {
 334         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 335         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 336         uint32_t fw_index;
 337         const struct psp_fw_bin_desc *desc;
 338
 339         DRM_DEBUG("PSP\n");
 340         amdgpu_ucode_print_common_hdr(hdr);
 341
 342         if (version_major == 1) {
 343                 const struct psp_firmware_header_v1_0 *psp_hdr =
 344                         container_of(hdr, struct psp_firmware_header_v1_0, header);
 345
 346                 DRM_DEBUG("ucode_feature_version: %u\n",
 347                           le32_to_cpu(psp_hdr->sos.fw_version));
 348                 DRM_DEBUG("sos_offset_bytes: %u\n",
 349                           le32_to_cpu(psp_hdr->sos.offset_bytes));
 350                 DRM_DEBUG("sos_size_bytes: %u\n",
 351                           le32_to_cpu(psp_hdr->sos.size_bytes));
 352                 if (version_minor == 1) {
 353                         const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
 354                                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
 355                         DRM_DEBUG("toc_header_version: %u\n",
 356                                   le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
 357                         DRM_DEBUG("toc_offset_bytes: %u\n",
 358                                   le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
 359                         DRM_DEBUG("toc_size_bytes: %u\n",
 360                                   le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
 361                         DRM_DEBUG("kdb_header_version: %u\n",
 362                                   le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
 363                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 364                                   le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
 365                         DRM_DEBUG("kdb_size_bytes: %u\n",
 366                                   le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
 367                 }
 368                 if (version_minor == 2) {
 369                         const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
 370                                 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
 371                         DRM_DEBUG("kdb_header_version: %u\n",
 372                                   le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
 373                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 374                                   le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
 375                         DRM_DEBUG("kdb_size_bytes: %u\n",
 376                                   le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
 377                 }
 378                 if (version_minor == 3) {
 379                         const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
 380                                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
 381                         const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
 382                                 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
 383                         DRM_DEBUG("toc_header_version: %u\n",
 384                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
 385                         DRM_DEBUG("toc_offset_bytes: %u\n",
 386                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
 387                         DRM_DEBUG("toc_size_bytes: %u\n",
 388                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
 389                         DRM_DEBUG("kdb_header_version: %u\n",
 390                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
 391                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 392                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
 393                         DRM_DEBUG("kdb_size_bytes: %u\n",
 394                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
 395                         DRM_DEBUG("spl_header_version: %u\n",
 396                                   le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
 397                         DRM_DEBUG("spl_offset_bytes: %u\n",
 398                                   le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
 399                         DRM_DEBUG("spl_size_bytes: %u\n",
 400                                   le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
 401                 }
 402         } else if (version_major == 2) {
 403                 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 =
 404                          container_of(hdr, struct psp_firmware_header_v2_0, header);
 405                 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) {
 406                         desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]);
 407                         switch (desc->fw_type) {
 408                         case PSP_FW_TYPE_PSP_SOS:
 409                                 DRM_DEBUG("psp_sos_version: %u\n",
 410                                           le32_to_cpu(desc->fw_version));
 411                                 DRM_DEBUG("psp_sos_size_bytes: %u\n",
 412                                           le32_to_cpu(desc->size_bytes));
 413                                 break;
 414                         case PSP_FW_TYPE_PSP_SYS_DRV:
 415                                 DRM_DEBUG("psp_sys_drv_version: %u\n",
 416                                           le32_to_cpu(desc->fw_version));
 417                                 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",
 418                                           le32_to_cpu(desc->size_bytes));
 419                                 break;
 420                         case PSP_FW_TYPE_PSP_KDB:
 421                                 DRM_DEBUG("psp_kdb_version: %u\n",
 422                                           le32_to_cpu(desc->fw_version));
 423                                 DRM_DEBUG("psp_kdb_size_bytes: %u\n",
 424                                           le32_to_cpu(desc->size_bytes));
 425                                 break;
 426                         case PSP_FW_TYPE_PSP_TOC:
 427                                 DRM_DEBUG("psp_toc_version: %u\n",
 428                                           le32_to_cpu(desc->fw_version));
 429                                 DRM_DEBUG("psp_toc_size_bytes: %u\n",
 430                                           le32_to_cpu(desc->size_bytes));
 431                                 break;
 432                         case PSP_FW_TYPE_PSP_SPL:
 433                                 DRM_DEBUG("psp_spl_version: %u\n",
 434                                           le32_to_cpu(desc->fw_version));
 435                                 DRM_DEBUG("psp_spl_size_bytes: %u\n",
 436                                           le32_to_cpu(desc->size_bytes));
 437                                 break;
 438                         case PSP_FW_TYPE_PSP_RL:
 439                                 DRM_DEBUG("psp_rl_version: %u\n",
 440                                           le32_to_cpu(desc->fw_version));
 441                                 DRM_DEBUG("psp_rl_size_bytes: %u\n",
 442                                           le32_to_cpu(desc->size_bytes));
 443                                 break;
 444                         case PSP_FW_TYPE_PSP_SOC_DRV:
 445                                 DRM_DEBUG("psp_soc_drv_version: %u\n",
 446                                           le32_to_cpu(desc->fw_version));
 447                                 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",
 448                                           le32_to_cpu(desc->size_bytes));
 449                                 break;
 450                         case PSP_FW_TYPE_PSP_INTF_DRV:
 451                                 DRM_DEBUG("psp_intf_drv_version: %u\n",
 452                                           le32_to_cpu(desc->fw_version));
 453                                 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",
 454                                           le32_to_cpu(desc->size_bytes));
 455                                 break;
 456                         case PSP_FW_TYPE_PSP_DBG_DRV:
 457                                 DRM_DEBUG("psp_dbg_drv_version: %u\n",
 458                                           le32_to_cpu(desc->fw_version));
 459                                 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
 460                                           le32_to_cpu(desc->size_bytes));
 461                                 break;
 462                         case PSP_FW_TYPE_PSP_RAS_DRV:
 463                                 DRM_DEBUG("psp_ras_drv_version: %u\n",
 464                                           le32_to_cpu(desc->fw_version));
 465                                 DRM_DEBUG("psp_ras_drv_size_bytes: %u\n",
 466                                           le32_to_cpu(desc->size_bytes));
 467                                 break;
 468                         default:
 469                                 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);
 470                                 break;
 471                         }
 472                 }
 473         } else {
 474                 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
 475                           version_major, version_minor);
 476         }
 477 }
 478
 479 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
 480 {
 481         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 482         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 483
 484         DRM_DEBUG("GPU_INFO\n");
 485         amdgpu_ucode_print_common_hdr(hdr);
 486
 487         if (version_major == 1) {
 488                 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
 489                         container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
 490
 491                 DRM_DEBUG("version_major: %u\n",
 492                           le16_to_cpu(gpu_info_hdr->version_major));
 493                 DRM_DEBUG("version_minor: %u\n",
 494                           le16_to_cpu(gpu_info_hdr->version_minor));
 495         } else {
 496                 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
 497         }
 498 }
 499
 500 static int amdgpu_ucode_validate(const struct firmware *fw)
 501 {
 502         const struct common_firmware_header *hdr =
 503                 (const struct common_firmware_header *)fw->data;
 504
 505         if (fw->size == le32_to_cpu(hdr->size_bytes))
 506                 return 0;
 507
 508         return -EINVAL;
 509 }
 510
 511 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 512                                 uint16_t hdr_major, uint16_t hdr_minor)
 513 {
 514         if ((hdr->common.header_version_major == hdr_major) &&
 515                 (hdr->common.header_version_minor == hdr_minor))
 516                 return true;
 517         return false;
 518 }
 519
 520 enum amdgpu_firmware_load_type
 521 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 522 {
 523         switch (adev->asic_type) {
 524 #ifdef CONFIG_DRM_AMDGPU_SI
 525         case CHIP_TAHITI:
 526         case CHIP_PITCAIRN:
 527         case CHIP_VERDE:
 528         case CHIP_OLAND:
 529         case CHIP_HAINAN:
 530                 return AMDGPU_FW_LOAD_DIRECT;
 531 #endif
 532 #ifdef CONFIG_DRM_AMDGPU_CIK
 533         case CHIP_BONAIRE:
 534         case CHIP_KAVERI:
 535         case CHIP_KABINI:
 536         case CHIP_HAWAII:
 537         case CHIP_MULLINS:
 538                 return AMDGPU_FW_LOAD_DIRECT;
 539 #endif
 540         case CHIP_TOPAZ:
 541         case CHIP_TONGA:
 542         case CHIP_FIJI:
 543         case CHIP_CARRIZO:
 544         case CHIP_STONEY:
 545         case CHIP_POLARIS10:
 546         case CHIP_POLARIS11:
 547         case CHIP_POLARIS12:
 548         case CHIP_VEGAM:
 549                 return AMDGPU_FW_LOAD_SMU;
 550         case CHIP_CYAN_SKILLFISH:
 551                 if (!(load_type &&
 552                       adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
 553                         return AMDGPU_FW_LOAD_DIRECT;
 554                 else
 555                         return AMDGPU_FW_LOAD_PSP;
 556         default:
 557                 if (!load_type)
 558                         return AMDGPU_FW_LOAD_DIRECT;
 559                 else
 560                         return AMDGPU_FW_LOAD_PSP;
 561         }
 562 }
 563
 564 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
 565 {
 566         switch (ucode_id) {
 567         case AMDGPU_UCODE_ID_SDMA0:
 568                 return "SDMA0";
 569         case AMDGPU_UCODE_ID_SDMA1:
 570                 return "SDMA1";
 571         case AMDGPU_UCODE_ID_SDMA2:
 572                 return "SDMA2";
 573         case AMDGPU_UCODE_ID_SDMA3:
 574                 return "SDMA3";
 575         case AMDGPU_UCODE_ID_SDMA4:
 576                 return "SDMA4";
 577         case AMDGPU_UCODE_ID_SDMA5:
 578                 return "SDMA5";
 579         case AMDGPU_UCODE_ID_SDMA6:
 580                 return "SDMA6";
 581         case AMDGPU_UCODE_ID_SDMA7:
 582                 return "SDMA7";
 583         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
 584                 return "SDMA_CTX";
 585         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
 586                 return "SDMA_CTL";
 587         case AMDGPU_UCODE_ID_CP_CE:
 588                 return "CP_CE";
 589         case AMDGPU_UCODE_ID_CP_PFP:
 590                 return "CP_PFP";
 591         case AMDGPU_UCODE_ID_CP_ME:
 592                 return "CP_ME";
 593         case AMDGPU_UCODE_ID_CP_MEC1:
 594                 return "CP_MEC1";
 595         case AMDGPU_UCODE_ID_CP_MEC1_JT:
 596                 return "CP_MEC1_JT";
 597         case AMDGPU_UCODE_ID_CP_MEC2:
 598                 return "CP_MEC2";
 599         case AMDGPU_UCODE_ID_CP_MEC2_JT:
 600                 return "CP_MEC2_JT";
 601         case AMDGPU_UCODE_ID_CP_MES:
 602                 return "CP_MES";
 603         case AMDGPU_UCODE_ID_CP_MES_DATA:
 604                 return "CP_MES_DATA";
 605         case AMDGPU_UCODE_ID_CP_MES1:
 606                 return "CP_MES_KIQ";
 607         case AMDGPU_UCODE_ID_CP_MES1_DATA:
 608                 return "CP_MES_KIQ_DATA";
 609         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 610                 return "RLC_RESTORE_LIST_CNTL";
 611         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 612                 return "RLC_RESTORE_LIST_GPM_MEM";
 613         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 614                 return "RLC_RESTORE_LIST_SRM_MEM";
 615         case AMDGPU_UCODE_ID_RLC_IRAM:
 616                 return "RLC_IRAM";
 617         case AMDGPU_UCODE_ID_RLC_DRAM:
 618                 return "RLC_DRAM";
 619         case AMDGPU_UCODE_ID_RLC_G:
 620                 return "RLC_G";
 621         case AMDGPU_UCODE_ID_RLC_P:
 622                 return "RLC_P";
 623         case AMDGPU_UCODE_ID_RLC_V:
 624                 return "RLC_V";
 625         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
 626                 return "GLOBAL_TAP_DELAYS";
 627         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
 628                 return "SE0_TAP_DELAYS";
 629         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
 630                 return "SE1_TAP_DELAYS";
 631         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
 632                 return "SE2_TAP_DELAYS";
 633         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
 634                 return "SE3_TAP_DELAYS";
 635         case AMDGPU_UCODE_ID_IMU_I:
 636                 return "IMU_I";
 637         case AMDGPU_UCODE_ID_IMU_D:
 638                 return "IMU_D";
 639         case AMDGPU_UCODE_ID_STORAGE:
 640                 return "STORAGE";
 641         case AMDGPU_UCODE_ID_SMC:
 642                 return "SMC";
 643         case AMDGPU_UCODE_ID_PPTABLE:
 644                 return "PPTABLE";
 645         case AMDGPU_UCODE_ID_P2S_TABLE:
 646                 return "P2STABLE";
 647         case AMDGPU_UCODE_ID_UVD:
 648                 return "UVD";
 649         case AMDGPU_UCODE_ID_UVD1:
 650                 return "UVD1";
 651         case AMDGPU_UCODE_ID_VCE:
 652                 return "VCE";
 653         case AMDGPU_UCODE_ID_VCN:
 654                 return "VCN";
 655         case AMDGPU_UCODE_ID_VCN1:
 656                 return "VCN1";
 657         case AMDGPU_UCODE_ID_DMCU_ERAM:
 658                 return "DMCU_ERAM";
 659         case AMDGPU_UCODE_ID_DMCU_INTV:
 660                 return "DMCU_INTV";
 661         case AMDGPU_UCODE_ID_VCN0_RAM:
 662                 return "VCN0_RAM";
 663         case AMDGPU_UCODE_ID_VCN1_RAM:
 664                 return "VCN1_RAM";
 665         case AMDGPU_UCODE_ID_DMCUB:
 666                 return "DMCUB";
 667         case AMDGPU_UCODE_ID_CAP:
 668                 return "CAP";
 669         case AMDGPU_UCODE_ID_VPE_CTX:
 670                 return "VPE_CTX";
 671         case AMDGPU_UCODE_ID_VPE_CTL:
 672                 return "VPE_CTL";
 673         case AMDGPU_UCODE_ID_VPE:
 674                 return "VPE";
 675         case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
 676                 return "UMSCH_MM_UCODE";
 677         case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
 678                 return "UMSCH_MM_DATA";
 679         default:
 680                 return "UNKNOWN UCODE";
 681         }
 682 }
 683
 684 static inline int amdgpu_ucode_is_valid(uint32_t fw_version)
 685 {
 686         if (!fw_version)
 687                 return -EINVAL;
 688
 689         return 0;
 690 }
 691
 692 #define FW_VERSION_ATTR(name, mode, field)                              \
 693 static ssize_t show_##name(struct device *dev,                          \
 694                            struct device_attribute *attr, char *buf)    \
 695 {                                                                       \
 696         struct drm_device *ddev = dev_get_drvdata(dev);                 \
 697         struct amdgpu_device *adev = drm_to_adev(ddev);                 \
 698                                                                         \
 699         if (!buf)                                                       \
 700                 return amdgpu_ucode_is_valid(adev->field);              \
 701                                                                         \
 702         return sysfs_emit(buf, "0x%08x\n", adev->field);                \
 703 }                                                                       \
 704 static DEVICE_ATTR(name, mode, show_##name, NULL)
 705
 706 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
 707 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
 708 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
 709 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
 710 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
 711 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
 712 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
 713 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
 714 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
 715 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
 716 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
 717 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
 718 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
 719 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
 720 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
 721 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
 722 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);
 723 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
 724 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
 725 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
 726 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
 727 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
 728 FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK);
 729 FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK);
 730
 731 static struct attribute *fw_attrs[] = {
 732         &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
 733         &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
 734         &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
 735         &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
 736         &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
 737         &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
 738         &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
 739         &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
 740         &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
 741         &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
 742         &dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr,
 743         &dev_attr_mes_fw_version.attr, &dev_attr_mes_kiq_fw_version.attr,
 744         NULL
 745 };
 746
 747 #define to_dev_attr(x) container_of(x, struct device_attribute, attr)
 748
 749 static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj,
 750                                         struct attribute *attr, int idx)
 751 {
 752         struct device_attribute *dev_attr = to_dev_attr(attr);
 753         struct device *dev = kobj_to_dev(kobj);
 754
 755         if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL)
 756                 return 0;
 757
 758         return attr->mode;
 759 }
 760
 761 static const struct attribute_group fw_attr_group = {
 762         .name = "fw_version",
 763         .attrs = fw_attrs,
 764         .is_visible = amdgpu_ucode_sys_visible
 765 };
 766
 767 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
 768 {
 769         return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
 770 }
 771
 772 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
 773 {
 774         sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
 775 }
 776
 777 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
 778                                        struct amdgpu_firmware_info *ucode,
 779                                        uint64_t mc_addr, void *kptr)
 780 {
 781         const struct common_firmware_header *header = NULL;
 782         const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
 783         const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL;
 784         const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
 785         const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
 786         const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
 787         const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
 788         const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
 789         const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;
 790         const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL;
 791         u8 *ucode_addr;
 792
 793         if (!ucode->fw)
 794                 return 0;
 795
 796         ucode->mc_addr = mc_addr;
 797         ucode->kaddr = kptr;
 798
 799         if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
 800                 return 0;
 801
 802         header = (const struct common_firmware_header *)ucode->fw->data;
 803         cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 804         cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data;
 805         dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
 806         dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
 807         mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
 808         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
 809         imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
 810         vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
 811
 812         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 813                 switch (ucode->ucode_id) {
 814                 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
 815                         ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
 816                         ucode_addr = (u8 *)ucode->fw->data +
 817                                 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);
 818                         break;
 819                 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
 820                         ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
 821                         ucode_addr = (u8 *)ucode->fw->data +
 822                                 le32_to_cpu(sdma_hdr->ctl_ucode_offset);
 823                         break;
 824                 case AMDGPU_UCODE_ID_CP_MEC1:
 825                 case AMDGPU_UCODE_ID_CP_MEC2:
 826                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
 827                                 le32_to_cpu(cp_hdr->jt_size) * 4;
 828                         ucode_addr = (u8 *)ucode->fw->data +
 829                                 le32_to_cpu(header->ucode_array_offset_bytes);
 830                         break;
 831                 case AMDGPU_UCODE_ID_CP_MEC1_JT:
 832                 case AMDGPU_UCODE_ID_CP_MEC2_JT:
 833                         ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
 834                         ucode_addr = (u8 *)ucode->fw->data +
 835                                 le32_to_cpu(header->ucode_array_offset_bytes) +
 836                                 le32_to_cpu(cp_hdr->jt_offset) * 4;
 837                         break;
 838                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 839                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
 840                         ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
 841                         break;
 842                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 843                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
 844                         ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
 845                         break;
 846                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 847                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
 848                         ucode_addr = adev->gfx.rlc.save_restore_list_srm;
 849                         break;
 850                 case AMDGPU_UCODE_ID_RLC_IRAM:
 851                         ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
 852                         ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
 853                         break;
 854                 case AMDGPU_UCODE_ID_RLC_DRAM:
 855                         ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
 856                         ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
 857                         break;
 858                 case AMDGPU_UCODE_ID_RLC_P:
 859                         ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
 860                         ucode_addr = adev->gfx.rlc.rlcp_ucode;
 861                         break;
 862                 case AMDGPU_UCODE_ID_RLC_V:
 863                         ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
 864                         ucode_addr = adev->gfx.rlc.rlcv_ucode;
 865                         break;
 866                 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
 867                         ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes;
 868                         ucode_addr = adev->gfx.rlc.global_tap_delays_ucode;
 869                         break;
 870                 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
 871                         ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes;
 872                         ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode;
 873                         break;
 874                 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
 875                         ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes;
 876                         ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode;
 877                         break;
 878                 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
 879                         ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes;
 880                         ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode;
 881                         break;
 882                 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
 883                         ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes;
 884                         ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode;
 885                         break;
 886                 case AMDGPU_UCODE_ID_CP_MES:
 887                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 888                         ucode_addr = (u8 *)ucode->fw->data +
 889                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
 890                         break;
 891                 case AMDGPU_UCODE_ID_CP_MES_DATA:
 892                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 893                         ucode_addr = (u8 *)ucode->fw->data +
 894                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
 895                         break;
 896                 case AMDGPU_UCODE_ID_CP_MES1:
 897                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 898                         ucode_addr = (u8 *)ucode->fw->data +
 899                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
 900                         break;
 901                 case AMDGPU_UCODE_ID_CP_MES1_DATA:
 902                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 903                         ucode_addr = (u8 *)ucode->fw->data +
 904                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
 905                         break;
 906                 case AMDGPU_UCODE_ID_DMCU_ERAM:
 907                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
 908                                 le32_to_cpu(dmcu_hdr->intv_size_bytes);
 909                         ucode_addr = (u8 *)ucode->fw->data +
 910                                 le32_to_cpu(header->ucode_array_offset_bytes);
 911                         break;
 912                 case AMDGPU_UCODE_ID_DMCU_INTV:
 913                         ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
 914                         ucode_addr = (u8 *)ucode->fw->data +
 915                                 le32_to_cpu(header->ucode_array_offset_bytes) +
 916                                 le32_to_cpu(dmcu_hdr->intv_offset_bytes);
 917                         break;
 918                 case AMDGPU_UCODE_ID_DMCUB:
 919                         ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
 920                         ucode_addr = (u8 *)ucode->fw->data +
 921                                 le32_to_cpu(header->ucode_array_offset_bytes);
 922                         break;
 923                 case AMDGPU_UCODE_ID_PPTABLE:
 924                         ucode->ucode_size = ucode->fw->size;
 925                         ucode_addr = (u8 *)ucode->fw->data;
 926                         break;
 927                 case AMDGPU_UCODE_ID_P2S_TABLE:
 928                         ucode->ucode_size = ucode->fw->size;
 929                         ucode_addr = (u8 *)ucode->fw->data;
 930                         break;
 931                 case AMDGPU_UCODE_ID_IMU_I:
 932                         ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
 933                         ucode_addr = (u8 *)ucode->fw->data +
 934                                 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
 935                         break;
 936                 case AMDGPU_UCODE_ID_IMU_D:
 937                         ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
 938                         ucode_addr = (u8 *)ucode->fw->data +
 939                                 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
 940                                 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
 941                         break;
 942                 case AMDGPU_UCODE_ID_CP_RS64_PFP:
 943                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
 944                         ucode_addr = (u8 *)ucode->fw->data +
 945                                 le32_to_cpu(header->ucode_array_offset_bytes);
 946                         break;
 947                 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
 948                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 949                         ucode_addr = (u8 *)ucode->fw->data +
 950                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 951                         break;
 952                 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
 953                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 954                         ucode_addr = (u8 *)ucode->fw->data +
 955                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 956                         break;
 957                 case AMDGPU_UCODE_ID_CP_RS64_ME:
 958                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
 959                         ucode_addr = (u8 *)ucode->fw->data +
 960                                 le32_to_cpu(header->ucode_array_offset_bytes);
 961                         break;
 962                 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
 963                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 964                         ucode_addr = (u8 *)ucode->fw->data +
 965                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 966                         break;
 967                 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
 968                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 969                         ucode_addr = (u8 *)ucode->fw->data +
 970                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 971                         break;
 972                 case AMDGPU_UCODE_ID_CP_RS64_MEC:
 973                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
 974                         ucode_addr = (u8 *)ucode->fw->data +
 975                                 le32_to_cpu(header->ucode_array_offset_bytes);
 976                         break;
 977                 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
 978                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 979                         ucode_addr = (u8 *)ucode->fw->data +
 980                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 981                         break;
 982                 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
 983                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 984                         ucode_addr = (u8 *)ucode->fw->data +
 985                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 986                         break;
 987                 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
 988                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 989                         ucode_addr = (u8 *)ucode->fw->data +
 990                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 991                         break;
 992                 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
 993                         ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
 994                         ucode_addr = (u8 *)ucode->fw->data +
 995                                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
 996                         break;
 997                 case AMDGPU_UCODE_ID_VPE_CTX:
 998                         ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes);
 999                         ucode_addr = (u8 *)ucode->fw->data +
1000                                 le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes);
1001                         break;
1002                 case AMDGPU_UCODE_ID_VPE_CTL:
1003                         ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes);
1004                         ucode_addr = (u8 *)ucode->fw->data +
1005                                 le32_to_cpu(vpe_hdr->ctl_ucode_offset);
1006                         break;
1007                 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
1008                         ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes);
1009                         ucode_addr = (u8 *)ucode->fw->data +
1010                                 le32_to_cpu(umsch_mm_hdr->header.ucode_array_offset_bytes);
1011                         break;
1012                 case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
1013                         ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes);
1014                         ucode_addr = (u8 *)ucode->fw->data +
1015                                 le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_offset_bytes);
1016                         break;
1017                 default:
1018                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
1019                         ucode_addr = (u8 *)ucode->fw->data +
1020                                 le32_to_cpu(header->ucode_array_offset_bytes);
1021                         break;
1022                 }
1023         } else {
1024                 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
1025                 ucode_addr = (u8 *)ucode->fw->data +
1026                         le32_to_cpu(header->ucode_array_offset_bytes);
1027         }
1028
1029         memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
1030
1031         return 0;
1032 }
1033
1034 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
1035                                 uint64_t mc_addr, void *kptr)
1036 {
1037         const struct gfx_firmware_header_v1_0 *header = NULL;
1038         const struct common_firmware_header *comm_hdr = NULL;
1039         uint8_t *src_addr = NULL;
1040         uint8_t *dst_addr = NULL;
1041
1042         if (!ucode->fw)
1043                 return 0;
1044
1045         comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
1046         header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
1047         dst_addr = ucode->kaddr +
1048                            ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
1049                            PAGE_SIZE);
1050         src_addr = (uint8_t *)ucode->fw->data +
1051                            le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
1052                            (le32_to_cpu(header->jt_offset) * 4);
1053         memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
1054
1055         return 0;
1056 }
1057
1058 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
1059 {
1060         if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
1061                 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
1062                         amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
1063                         &adev->firmware.fw_buf,
1064                         &adev->firmware.fw_buf_mc,
1065                         &adev->firmware.fw_buf_ptr);
1066                 if (!adev->firmware.fw_buf) {
1067                         dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
1068                         return -ENOMEM;
1069                 } else if (amdgpu_sriov_vf(adev)) {
1070                         memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
1071                 }
1072         }
1073         return 0;
1074 }
1075
1076 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
1077 {
1078         amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
1079                 &adev->firmware.fw_buf_mc,
1080                 &adev->firmware.fw_buf_ptr);
1081 }
1082
1083 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
1084 {
1085         uint64_t fw_offset = 0;
1086         int i;
1087         struct amdgpu_firmware_info *ucode = NULL;
1088
1089  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
1090         if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
1091                 return 0;
1092         /*
1093          * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
1094          * ucode info here
1095          */
1096         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1097                 if (amdgpu_sriov_vf(adev))
1098                         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
1099                 else
1100                         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
1101         } else {
1102                 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
1103         }
1104
1105         for (i = 0; i < adev->firmware.max_ucodes; i++) {
1106                 ucode = &adev->firmware.ucode[i];
1107                 if (ucode->fw) {
1108                         amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
1109                                                     adev->firmware.fw_buf_ptr + fw_offset);
1110                         if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
1111                             adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1112                                 const struct gfx_firmware_header_v1_0 *cp_hdr;
1113
1114                                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
1115                                 amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
1116                                                     adev->firmware.fw_buf_ptr + fw_offset);
1117                                 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1118                         }
1119                         fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
1120                 }
1121         }
1122         return 0;
1123 }
1124
1125 static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type)
1126 {
1127         if (block_type == MP0_HWIP) {
1128                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
1129                 case IP_VERSION(9, 0, 0):
1130                         switch (adev->asic_type) {
1131                         case CHIP_VEGA10:
1132                                 return "vega10";
1133                         case CHIP_VEGA12:
1134                                 return "vega12";
1135                         default:
1136                                 return NULL;
1137                         }
1138                 case IP_VERSION(10, 0, 0):
1139                 case IP_VERSION(10, 0, 1):
1140                         if (adev->asic_type == CHIP_RAVEN) {
1141                                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1142                                         return "raven2";
1143                                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1144                                         return "picasso";
1145                                 return "raven";
1146                         }
1147                         break;
1148                 case IP_VERSION(11, 0, 0):
1149                         return "navi10";
1150                 case IP_VERSION(11, 0, 2):
1151                         return "vega20";
1152                 case IP_VERSION(11, 0, 3):
1153                         return "renoir";
1154                 case IP_VERSION(11, 0, 4):
1155                         return "arcturus";
1156                 case IP_VERSION(11, 0, 5):
1157                         return "navi14";
1158                 case IP_VERSION(11, 0, 7):
1159                         return "sienna_cichlid";
1160                 case IP_VERSION(11, 0, 9):
1161                         return "navi12";
1162                 case IP_VERSION(11, 0, 11):
1163                         return "navy_flounder";
1164                 case IP_VERSION(11, 0, 12):
1165                         return "dimgrey_cavefish";
1166                 case IP_VERSION(11, 0, 13):
1167                         return "beige_goby";
1168                 case IP_VERSION(11, 5, 0):
1169                         return "vangogh";
1170                 case IP_VERSION(12, 0, 1):
1171                         return "green_sardine";
1172                 case IP_VERSION(13, 0, 2):
1173                         return "aldebaran";
1174                 case IP_VERSION(13, 0, 1):
1175                 case IP_VERSION(13, 0, 3):
1176                         return "yellow_carp";
1177                 }
1178         } else if (block_type == MP1_HWIP) {
1179                 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1180                 case IP_VERSION(9, 0, 0):
1181                 case IP_VERSION(10, 0, 0):
1182                 case IP_VERSION(10, 0, 1):
1183                 case IP_VERSION(11, 0, 2):
1184                         if (adev->asic_type == CHIP_ARCTURUS)
1185                                 return "arcturus_smc";
1186                         return NULL;
1187                 case IP_VERSION(11, 0, 0):
1188                         return "navi10_smc";
1189                 case IP_VERSION(11, 0, 5):
1190                         return "navi14_smc";
1191                 case IP_VERSION(11, 0, 9):
1192                         return "navi12_smc";
1193                 case IP_VERSION(11, 0, 7):
1194                         return "sienna_cichlid_smc";
1195                 case IP_VERSION(11, 0, 11):
1196                         return "navy_flounder_smc";
1197                 case IP_VERSION(11, 0, 12):
1198                         return "dimgrey_cavefish_smc";
1199                 case IP_VERSION(11, 0, 13):
1200                         return "beige_goby_smc";
1201                 case IP_VERSION(13, 0, 2):
1202                         return "aldebaran_smc";
1203                 }
1204         } else if (block_type == SDMA0_HWIP) {
1205                 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1206                 case IP_VERSION(4, 0, 0):
1207                         return "vega10_sdma";
1208                 case IP_VERSION(4, 0, 1):
1209                         return "vega12_sdma";
1210                 case IP_VERSION(4, 1, 0):
1211                 case IP_VERSION(4, 1, 1):
1212                         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1213                                 return "raven2_sdma";
1214                         else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1215                                 return "picasso_sdma";
1216                         return "raven_sdma";
1217                 case IP_VERSION(4, 1, 2):
1218                         if (adev->apu_flags & AMD_APU_IS_RENOIR)
1219                                 return "renoir_sdma";
1220                         return "green_sardine_sdma";
1221                 case IP_VERSION(4, 2, 0):
1222                         return "vega20_sdma";
1223                 case IP_VERSION(4, 2, 2):
1224                         return "arcturus_sdma";
1225                 case IP_VERSION(4, 4, 0):
1226                         return "aldebaran_sdma";
1227                 case IP_VERSION(5, 0, 0):
1228                         return "navi10_sdma";
1229                 case IP_VERSION(5, 0, 1):
1230                         return "cyan_skillfish2_sdma";
1231                 case IP_VERSION(5, 0, 2):
1232                         return "navi14_sdma";
1233                 case IP_VERSION(5, 0, 5):
1234                         return "navi12_sdma";
1235                 case IP_VERSION(5, 2, 0):
1236                         return "sienna_cichlid_sdma";
1237                 case IP_VERSION(5, 2, 2):
1238                         return "navy_flounder_sdma";
1239                 case IP_VERSION(5, 2, 4):
1240                         return "dimgrey_cavefish_sdma";
1241                 case IP_VERSION(5, 2, 5):
1242                         return "beige_goby_sdma";
1243                 case IP_VERSION(5, 2, 3):
1244                         return "yellow_carp_sdma";
1245                 case IP_VERSION(5, 2, 1):
1246                         return "vangogh_sdma";
1247                 }
1248         } else if (block_type == UVD_HWIP) {
1249                 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
1250                 case IP_VERSION(1, 0, 0):
1251                 case IP_VERSION(1, 0, 1):
1252                         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1253                                 return "raven2_vcn";
1254                         else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1255                                 return "picasso_vcn";
1256                         return "raven_vcn";
1257                 case IP_VERSION(2, 5, 0):
1258                         return "arcturus_vcn";
1259                 case IP_VERSION(2, 2, 0):
1260                         if (adev->apu_flags & AMD_APU_IS_RENOIR)
1261                                 return "renoir_vcn";
1262                         return "green_sardine_vcn";
1263                 case IP_VERSION(2, 6, 0):
1264                         return "aldebaran_vcn";
1265                 case IP_VERSION(2, 0, 0):
1266                         return "navi10_vcn";
1267                 case IP_VERSION(2, 0, 2):
1268                         if (adev->asic_type == CHIP_NAVI12)
1269                                 return "navi12_vcn";
1270                         return "navi14_vcn";
1271                 case IP_VERSION(3, 0, 0):
1272                 case IP_VERSION(3, 0, 64):
1273                 case IP_VERSION(3, 0, 192):
1274                         if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
1275                             IP_VERSION(10, 3, 0))
1276                                 return "sienna_cichlid_vcn";
1277                         return "navy_flounder_vcn";
1278                 case IP_VERSION(3, 0, 2):
1279                         return "vangogh_vcn";
1280                 case IP_VERSION(3, 0, 16):
1281                         return "dimgrey_cavefish_vcn";
1282                 case IP_VERSION(3, 0, 33):
1283                         return "beige_goby_vcn";
1284                 case IP_VERSION(3, 1, 1):
1285                         return "yellow_carp_vcn";
1286                 }
1287         } else if (block_type == GC_HWIP) {
1288                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1289                 case IP_VERSION(9, 0, 1):
1290                         return "vega10";
1291                 case IP_VERSION(9, 2, 1):
1292                         return "vega12";
1293                 case IP_VERSION(9, 4, 0):
1294                         return "vega20";
1295                 case IP_VERSION(9, 2, 2):
1296                 case IP_VERSION(9, 1, 0):
1297                         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1298                                 return "raven2";
1299                         else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1300                                 return "picasso";
1301                         return "raven";
1302                 case IP_VERSION(9, 4, 1):
1303                         return "arcturus";
1304                 case IP_VERSION(9, 3, 0):
1305                         if (adev->apu_flags & AMD_APU_IS_RENOIR)
1306                                 return "renoir";
1307                         return "green_sardine";
1308                 case IP_VERSION(9, 4, 2):
1309                         return "aldebaran";
1310                 case IP_VERSION(10, 1, 10):
1311                         return "navi10";
1312                 case IP_VERSION(10, 1, 1):
1313                         return "navi14";
1314                 case IP_VERSION(10, 1, 2):
1315                         return "navi12";
1316                 case IP_VERSION(10, 3, 0):
1317                         return "sienna_cichlid";
1318                 case IP_VERSION(10, 3, 2):
1319                         return "navy_flounder";
1320                 case IP_VERSION(10, 3, 1):
1321                         return "vangogh";
1322                 case IP_VERSION(10, 3, 4):
1323                         return "dimgrey_cavefish";
1324                 case IP_VERSION(10, 3, 5):
1325                         return "beige_goby";
1326                 case IP_VERSION(10, 3, 3):
1327                         return "yellow_carp";
1328                 case IP_VERSION(10, 1, 3):
1329                 case IP_VERSION(10, 1, 4):
1330                         return "cyan_skillfish2";
1331                 }
1332         }
1333         return NULL;
1334 }
1335
1336 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
1337 {
1338         int maj, min, rev;
1339         char *ip_name;
1340         const char *legacy;
1341         uint32_t version = amdgpu_ip_version(adev, block_type, 0);
1342
1343         legacy = amdgpu_ucode_legacy_naming(adev, block_type);
1344         if (legacy) {
1345                 snprintf(ucode_prefix, len, "%s", legacy);
1346                 return;
1347         }
1348
1349         switch (block_type) {
1350         case GC_HWIP:
1351                 ip_name = "gc";
1352                 break;
1353         case SDMA0_HWIP:
1354                 ip_name = "sdma";
1355                 break;
1356         case MP0_HWIP:
1357                 ip_name = "psp";
1358                 break;
1359         case MP1_HWIP:
1360                 ip_name = "smu";
1361                 break;
1362         case UVD_HWIP:
1363                 ip_name = "vcn";
1364                 break;
1365         case VPE_HWIP:
1366                 ip_name = "vpe";
1367                 break;
1368         default:
1369                 BUG();
1370         }
1371
1372         maj = IP_VERSION_MAJ(version);
1373         min = IP_VERSION_MIN(version);
1374         rev = IP_VERSION_REV(version);
1375
1376         snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev);
1377 }
1378
1379 /*
1380  * amdgpu_ucode_request - Fetch and validate amdgpu microcode
1381  *
1382  * @adev: amdgpu device
1383  * @fw: pointer to load firmware to
1384  * @fw_name: firmware to load
1385  *
1386  * This is a helper that will use request_firmware and amdgpu_ucode_validate
1387  * to load and run basic validation on firmware. If the load fails, remap
1388  * the error code to -ENODEV, so that early_init functions will fail to load.
1389  */
1390 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
1391                          const char *fw_name)
1392 {
1393         int err = request_firmware(fw, fw_name, adev->dev);
1394
1395         if (err)
1396                 return -ENODEV;
1397         err = amdgpu_ucode_validate(*fw);
1398         if (err)
1399                 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
1400
1401         return err;
1402 }
1403
1404 /*
1405  * amdgpu_ucode_release - Release firmware microcode
1406  *
1407  * @fw: pointer to firmware to release
1408  */
1409 void amdgpu_ucode_release(const struct firmware **fw)
1410 {
1411         release_firmware(*fw);
1412         *fw = NULL;
1413 }