drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  41 {
  42         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  43         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  44
  45         amdgpu_bo_kunmap(bo);
  46
  47         drm_gem_object_release(&bo->gem_base);
  48         amdgpu_bo_unref(&bo->parent);
  49         if (!list_empty(&bo->shadow_list)) {
  50                 mutex_lock(&adev->shadow_list_lock);
  51                 list_del_init(&bo->shadow_list);
  52                 mutex_unlock(&adev->shadow_list_lock);
  53         }
  54         kfree(bo->metadata);
  55         kfree(bo);
  56 }
  57
  58 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  59 {
  60         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  61                 return true;
  62         return false;
  63 }
  64
  65 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  66 {
  67         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  68         struct ttm_placement *placement = &abo->placement;
  69         struct ttm_place *places = abo->placements;
  70         u64 flags = abo->flags;
  71         u32 c = 0;
  72
  73         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  74                 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
  75
  76                 places[c].fpfn = 0;
  77                 places[c].lpfn = 0;
  78                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  79                         TTM_PL_FLAG_VRAM;
  80
  81                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
  82                         places[c].lpfn = visible_pfn;
  83                 else
  84                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
  85
  86                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
  87                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
  88                 c++;
  89         }
  90
  91         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
  92                 places[c].fpfn = 0;
  93                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
  94                         places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT;
  95                 else
  96                         places[c].lpfn = 0;
  97                 places[c].flags = TTM_PL_FLAG_TT;
  98                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
  99                         places[c].flags |= TTM_PL_FLAG_WC |
 100                                 TTM_PL_FLAG_UNCACHED;
 101                 else
 102                         places[c].flags |= TTM_PL_FLAG_CACHED;
 103                 c++;
 104         }
 105
 106         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 107                 places[c].fpfn = 0;
 108                 places[c].lpfn = 0;
 109                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 110                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 111                         places[c].flags |= TTM_PL_FLAG_WC |
 112                                 TTM_PL_FLAG_UNCACHED;
 113                 else
 114                         places[c].flags |= TTM_PL_FLAG_CACHED;
 115                 c++;
 116         }
 117
 118         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 119                 places[c].fpfn = 0;
 120                 places[c].lpfn = 0;
 121                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 122                 c++;
 123         }
 124
 125         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 126                 places[c].fpfn = 0;
 127                 places[c].lpfn = 0;
 128                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 129                 c++;
 130         }
 131
 132         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 133                 places[c].fpfn = 0;
 134                 places[c].lpfn = 0;
 135                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 136                 c++;
 137         }
 138
 139         if (!c) {
 140                 places[c].fpfn = 0;
 141                 places[c].lpfn = 0;
 142                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 143                 c++;
 144         }
 145
 146         placement->num_placement = c;
 147         placement->placement = places;
 148
 149         placement->num_busy_placement = c;
 150         placement->busy_placement = places;
 151 }
 152
 153 /**
 154  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 155  *
 156  * @adev: amdgpu device object
 157  * @size: size for the new BO
 158  * @align: alignment for the new BO
 159  * @domain: where to place it
 160  * @bo_ptr: resulting BO
 161  * @gpu_addr: GPU addr of the pinned BO
 162  * @cpu_addr: optional CPU address mapping
 163  *
 164  * Allocates and pins a BO for kernel internal use, and returns it still
 165  * reserved.
 166  *
 167  * Returns 0 on success, negative error code otherwise.
 168  */
 169 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 170                               unsigned long size, int align,
 171                               u32 domain, struct amdgpu_bo **bo_ptr,
 172                               u64 *gpu_addr, void **cpu_addr)
 173 {
 174         bool free = false;
 175         int r;
 176
 177         if (!*bo_ptr) {
 178                 r = amdgpu_bo_create(adev, size, align, true, domain,
 179                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 180                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 181                                      NULL, NULL, 0, bo_ptr);
 182                 if (r) {
 183                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 184                                 r);
 185                         return r;
 186                 }
 187                 free = true;
 188         }
 189
 190         r = amdgpu_bo_reserve(*bo_ptr, false);
 191         if (r) {
 192                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 193                 goto error_free;
 194         }
 195
 196         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 197         if (r) {
 198                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 199                 goto error_unreserve;
 200         }
 201
 202         if (cpu_addr) {
 203                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 204                 if (r) {
 205                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 206                         goto error_unreserve;
 207                 }
 208         }
 209
 210         return 0;
 211
 212 error_unreserve:
 213         amdgpu_bo_unreserve(*bo_ptr);
 214
 215 error_free:
 216         if (free)
 217                 amdgpu_bo_unref(bo_ptr);
 218
 219         return r;
 220 }
 221
 222 /**
 223  * amdgpu_bo_create_kernel - create BO for kernel use
 224  *
 225  * @adev: amdgpu device object
 226  * @size: size for the new BO
 227  * @align: alignment for the new BO
 228  * @domain: where to place it
 229  * @bo_ptr: resulting BO
 230  * @gpu_addr: GPU addr of the pinned BO
 231  * @cpu_addr: optional CPU address mapping
 232  *
 233  * Allocates and pins a BO for kernel internal use.
 234  *
 235  * Returns 0 on success, negative error code otherwise.
 236  */
 237 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 238                             unsigned long size, int align,
 239                             u32 domain, struct amdgpu_bo **bo_ptr,
 240                             u64 *gpu_addr, void **cpu_addr)
 241 {
 242         int r;
 243
 244         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 245                                       gpu_addr, cpu_addr);
 246
 247         if (r)
 248                 return r;
 249
 250         amdgpu_bo_unreserve(*bo_ptr);
 251
 252         return 0;
 253 }
 254
 255 /**
 256  * amdgpu_bo_free_kernel - free BO for kernel use
 257  *
 258  * @bo: amdgpu BO to free
 259  *
 260  * unmaps and unpin a BO for kernel internal use.
 261  */
 262 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 263                            void **cpu_addr)
 264 {
 265         if (*bo == NULL)
 266                 return;
 267
 268         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 269                 if (cpu_addr)
 270                         amdgpu_bo_kunmap(*bo);
 271
 272                 amdgpu_bo_unpin(*bo);
 273                 amdgpu_bo_unreserve(*bo);
 274         }
 275         amdgpu_bo_unref(bo);
 276
 277         if (gpu_addr)
 278                 *gpu_addr = 0;
 279
 280         if (cpu_addr)
 281                 *cpu_addr = NULL;
 282 }
 283
 284 /* Validate bo size is bit bigger then the request domain */
 285 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 286                                           unsigned long size, u32 domain)
 287 {
 288         struct ttm_mem_type_manager *man = NULL;
 289
 290         /*
 291          * If GTT is part of requested domains the check must succeed to
 292          * allow fall back to GTT
 293          */
 294         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 295                 man = &adev->mman.bdev.man[TTM_PL_TT];
 296
 297                 if (size < (man->size << PAGE_SHIFT))
 298                         return true;
 299                 else
 300                         goto fail;
 301         }
 302
 303         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 304                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 305
 306                 if (size < (man->size << PAGE_SHIFT))
 307                         return true;
 308                 else
 309                         goto fail;
 310         }
 311
 312
 313         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 314         return true;
 315
 316 fail:
 317         DRM_ERROR("BO size %lu > total memory in domain: %llu\n", size,
 318                                               man->size << PAGE_SHIFT);
 319         return false;
 320 }
 321
 322 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 323                                unsigned long size, int byte_align,
 324                                bool kernel, u32 domain, u64 flags,
 325                                struct sg_table *sg,
 326                                struct reservation_object *resv,
 327                                uint64_t init_value,
 328                                struct amdgpu_bo **bo_ptr)
 329 {
 330         struct amdgpu_bo *bo;
 331         enum ttm_bo_type type;
 332         unsigned long page_align;
 333         u64 initial_bytes_moved, bytes_moved;
 334         size_t acc_size;
 335         int r;
 336
 337         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 338         size = ALIGN(size, PAGE_SIZE);
 339
 340         if (!amdgpu_bo_validate_size(adev, size, domain))
 341                 return -ENOMEM;
 342
 343         if (kernel) {
 344                 type = ttm_bo_type_kernel;
 345         } else if (sg) {
 346                 type = ttm_bo_type_sg;
 347         } else {
 348                 type = ttm_bo_type_device;
 349         }
 350         *bo_ptr = NULL;
 351
 352         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 353                                        sizeof(struct amdgpu_bo));
 354
 355         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 356         if (bo == NULL)
 357                 return -ENOMEM;
 358         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 359         if (unlikely(r)) {
 360                 kfree(bo);
 361                 return r;
 362         }
 363         INIT_LIST_HEAD(&bo->shadow_list);
 364         INIT_LIST_HEAD(&bo->va);
 365         bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 366                                          AMDGPU_GEM_DOMAIN_GTT |
 367                                          AMDGPU_GEM_DOMAIN_CPU |
 368                                          AMDGPU_GEM_DOMAIN_GDS |
 369                                          AMDGPU_GEM_DOMAIN_GWS |
 370                                          AMDGPU_GEM_DOMAIN_OA);
 371         bo->allowed_domains = bo->preferred_domains;
 372         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 373                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 374
 375         bo->flags = flags;
 376
 377 #ifdef CONFIG_X86_32
 378         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 379          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 380          */
 381         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 382 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 383         /* Don't try to enable write-combining when it can't work, or things
 384          * may be slow
 385          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 386          */
 387
 388 #ifndef CONFIG_COMPILE_TEST
 389 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 390          thanks to write-combining
 391 #endif
 392
 393         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 394                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 395                               "better performance thanks to write-combining\n");
 396         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 397 #else
 398         /* For architectures that don't support WC memory,
 399          * mask out the WC flag from the BO
 400          */
 401         if (!drm_arch_can_wc_memory())
 402                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 403 #endif
 404
 405         bo->tbo.bdev = &adev->mman.bdev;
 406         amdgpu_ttm_placement_from_domain(bo, domain);
 407
 408         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 409         /* Kernel allocation are uninterruptible */
 410         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 411                                  &bo->placement, page_align, !kernel, NULL,
 412                                  acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 413         if (unlikely(r != 0))
 414                 return r;
 415
 416         bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 417                       initial_bytes_moved;
 418         if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 419             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 420             bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
 421                 amdgpu_cs_report_moved_bytes(adev, bytes_moved, bytes_moved);
 422         else
 423                 amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0);
 424
 425         if (kernel)
 426                 bo->tbo.priority = 1;
 427
 428         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 429             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 430                 struct dma_fence *fence;
 431
 432                 r = amdgpu_fill_buffer(bo, init_value, bo->tbo.resv, &fence);
 433                 if (unlikely(r))
 434                         goto fail_unreserve;
 435
 436                 amdgpu_bo_fence(bo, fence, false);
 437                 dma_fence_put(bo->tbo.moving);
 438                 bo->tbo.moving = dma_fence_get(fence);
 439                 dma_fence_put(fence);
 440         }
 441         if (!resv)
 442                 amdgpu_bo_unreserve(bo);
 443         *bo_ptr = bo;
 444
 445         trace_amdgpu_bo_create(bo);
 446
 447         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 448         if (type == ttm_bo_type_device)
 449                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 450
 451         return 0;
 452
 453 fail_unreserve:
 454         if (!resv)
 455                 ww_mutex_unlock(&bo->tbo.resv->lock);
 456         amdgpu_bo_unref(&bo);
 457         return r;
 458 }
 459
 460 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 461                                    unsigned long size, int byte_align,
 462                                    struct amdgpu_bo *bo)
 463 {
 464         int r;
 465
 466         if (bo->shadow)
 467                 return 0;
 468
 469         r = amdgpu_bo_do_create(adev, size, byte_align, true,
 470                                 AMDGPU_GEM_DOMAIN_GTT,
 471                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 472                                 AMDGPU_GEM_CREATE_SHADOW,
 473                                 NULL, bo->tbo.resv, 0,
 474                                 &bo->shadow);
 475         if (!r) {
 476                 bo->shadow->parent = amdgpu_bo_ref(bo);
 477                 mutex_lock(&adev->shadow_list_lock);
 478                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 479                 mutex_unlock(&adev->shadow_list_lock);
 480         }
 481
 482         return r;
 483 }
 484
 485 /* init_value will only take effect when flags contains
 486  * AMDGPU_GEM_CREATE_VRAM_CLEARED.
 487  */
 488 int amdgpu_bo_create(struct amdgpu_device *adev,
 489                      unsigned long size, int byte_align,
 490                      bool kernel, u32 domain, u64 flags,
 491                      struct sg_table *sg,
 492                      struct reservation_object *resv,
 493                      uint64_t init_value,
 494                      struct amdgpu_bo **bo_ptr)
 495 {
 496         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 497         int r;
 498
 499         r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain,
 500                                 parent_flags, sg, resv, init_value, bo_ptr);
 501         if (r)
 502                 return r;
 503
 504         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 505                 if (!resv)
 506                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 507                                                         NULL));
 508
 509                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 510
 511                 if (!resv)
 512                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 513
 514                 if (r)
 515                         amdgpu_bo_unref(bo_ptr);
 516         }
 517
 518         return r;
 519 }
 520
 521 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 522                                struct amdgpu_ring *ring,
 523                                struct amdgpu_bo *bo,
 524                                struct reservation_object *resv,
 525                                struct dma_fence **fence,
 526                                bool direct)
 527
 528 {
 529         struct amdgpu_bo *shadow = bo->shadow;
 530         uint64_t bo_addr, shadow_addr;
 531         int r;
 532
 533         if (!shadow)
 534                 return -EINVAL;
 535
 536         bo_addr = amdgpu_bo_gpu_offset(bo);
 537         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 538
 539         r = reservation_object_reserve_shared(bo->tbo.resv);
 540         if (r)
 541                 goto err;
 542
 543         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 544                                amdgpu_bo_size(bo), resv, fence,
 545                                direct, false);
 546         if (!r)
 547                 amdgpu_bo_fence(bo, *fence, true);
 548
 549 err:
 550         return r;
 551 }
 552
 553 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 554 {
 555         uint32_t domain;
 556         int r;
 557
 558         if (bo->pin_count)
 559                 return 0;
 560
 561         domain = bo->preferred_domains;
 562
 563 retry:
 564         amdgpu_ttm_placement_from_domain(bo, domain);
 565         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 566         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 567                 domain = bo->allowed_domains;
 568                 goto retry;
 569         }
 570
 571         return r;
 572 }
 573
 574 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 575                                   struct amdgpu_ring *ring,
 576                                   struct amdgpu_bo *bo,
 577                                   struct reservation_object *resv,
 578                                   struct dma_fence **fence,
 579                                   bool direct)
 580
 581 {
 582         struct amdgpu_bo *shadow = bo->shadow;
 583         uint64_t bo_addr, shadow_addr;
 584         int r;
 585
 586         if (!shadow)
 587                 return -EINVAL;
 588
 589         bo_addr = amdgpu_bo_gpu_offset(bo);
 590         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 591
 592         r = reservation_object_reserve_shared(bo->tbo.resv);
 593         if (r)
 594                 goto err;
 595
 596         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 597                                amdgpu_bo_size(bo), resv, fence,
 598                                direct, false);
 599         if (!r)
 600                 amdgpu_bo_fence(bo, *fence, true);
 601
 602 err:
 603         return r;
 604 }
 605
 606 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 607 {
 608         void *kptr;
 609         long r;
 610
 611         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 612                 return -EPERM;
 613
 614         kptr = amdgpu_bo_kptr(bo);
 615         if (kptr) {
 616                 if (ptr)
 617                         *ptr = kptr;
 618                 return 0;
 619         }
 620
 621         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 622                                                 MAX_SCHEDULE_TIMEOUT);
 623         if (r < 0)
 624                 return r;
 625
 626         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 627         if (r)
 628                 return r;
 629
 630         if (ptr)
 631                 *ptr = amdgpu_bo_kptr(bo);
 632
 633         return 0;
 634 }
 635
 636 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 637 {
 638         bool is_iomem;
 639
 640         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 641 }
 642
 643 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 644 {
 645         if (bo->kmap.bo)
 646                 ttm_bo_kunmap(&bo->kmap);
 647 }
 648
 649 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 650 {
 651         if (bo == NULL)
 652                 return NULL;
 653
 654         ttm_bo_reference(&bo->tbo);
 655         return bo;
 656 }
 657
 658 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 659 {
 660         struct ttm_buffer_object *tbo;
 661
 662         if ((*bo) == NULL)
 663                 return;
 664
 665         tbo = &((*bo)->tbo);
 666         ttm_bo_unref(&tbo);
 667         if (tbo == NULL)
 668                 *bo = NULL;
 669 }
 670
 671 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 672                              u64 min_offset, u64 max_offset,
 673                              u64 *gpu_addr)
 674 {
 675         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 676         int r, i;
 677
 678         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 679                 return -EPERM;
 680
 681         if (WARN_ON_ONCE(min_offset > max_offset))
 682                 return -EINVAL;
 683
 684         /* A shared bo cannot be migrated to VRAM */
 685         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 686                 return -EINVAL;
 687
 688         if (bo->pin_count) {
 689                 uint32_t mem_type = bo->tbo.mem.mem_type;
 690
 691                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 692                         return -EINVAL;
 693
 694                 bo->pin_count++;
 695                 if (gpu_addr)
 696                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 697
 698                 if (max_offset != 0) {
 699                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 700                         WARN_ON_ONCE(max_offset <
 701                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 702                 }
 703
 704                 return 0;
 705         }
 706
 707         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 708         /* force to pin into visible video ram */
 709         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 710                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 711         amdgpu_ttm_placement_from_domain(bo, domain);
 712         for (i = 0; i < bo->placement.num_placement; i++) {
 713                 unsigned fpfn, lpfn;
 714
 715                 fpfn = min_offset >> PAGE_SHIFT;
 716                 lpfn = max_offset >> PAGE_SHIFT;
 717
 718                 if (fpfn > bo->placements[i].fpfn)
 719                         bo->placements[i].fpfn = fpfn;
 720                 if (!bo->placements[i].lpfn ||
 721                     (lpfn && lpfn < bo->placements[i].lpfn))
 722                         bo->placements[i].lpfn = lpfn;
 723                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 724         }
 725
 726         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 727         if (unlikely(r)) {
 728                 dev_err(adev->dev, "%p pin failed\n", bo);
 729                 goto error;
 730         }
 731
 732         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 733         if (unlikely(r)) {
 734                 dev_err(adev->dev, "%p bind failed\n", bo);
 735                 goto error;
 736         }
 737
 738         bo->pin_count = 1;
 739         if (gpu_addr != NULL)
 740                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 741
 742         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 743         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 744                 adev->vram_pin_size += amdgpu_bo_size(bo);
 745                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 746                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 747         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 748                 adev->gart_pin_size += amdgpu_bo_size(bo);
 749         }
 750
 751 error:
 752         return r;
 753 }
 754
 755 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 756 {
 757         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 758 }
 759
 760 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 761 {
 762         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 763         int r, i;
 764
 765         if (!bo->pin_count) {
 766                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 767                 return 0;
 768         }
 769         bo->pin_count--;
 770         if (bo->pin_count)
 771                 return 0;
 772         for (i = 0; i < bo->placement.num_placement; i++) {
 773                 bo->placements[i].lpfn = 0;
 774                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 775         }
 776         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 777         if (unlikely(r)) {
 778                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 779                 goto error;
 780         }
 781
 782         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 783                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 784                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 785                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 786         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 787                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 788         }
 789
 790 error:
 791         return r;
 792 }
 793
 794 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 795 {
 796         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 797         if (0 && (adev->flags & AMD_IS_APU)) {
 798                 /* Useless to evict on IGP chips */
 799                 return 0;
 800         }
 801         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 802 }
 803
 804 static const char *amdgpu_vram_names[] = {
 805         "UNKNOWN",
 806         "GDDR1",
 807         "DDR2",
 808         "GDDR3",
 809         "GDDR4",
 810         "GDDR5",
 811         "HBM",
 812         "DDR3"
 813 };
 814
 815 int amdgpu_bo_init(struct amdgpu_device *adev)
 816 {
 817         /* reserve PAT memory space to WC for VRAM */
 818         arch_io_reserve_memtype_wc(adev->mc.aper_base,
 819                                    adev->mc.aper_size);
 820
 821         /* Add an MTRR for the VRAM */
 822         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 823                                               adev->mc.aper_size);
 824         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 825                  adev->mc.mc_vram_size >> 20,
 826                  (unsigned long long)adev->mc.aper_size >> 20);
 827         DRM_INFO("RAM width %dbits %s\n",
 828                  adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
 829         return amdgpu_ttm_init(adev);
 830 }
 831
 832 void amdgpu_bo_fini(struct amdgpu_device *adev)
 833 {
 834         amdgpu_ttm_fini(adev);
 835         arch_phys_wc_del(adev->mc.vram_mtrr);
 836         arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size);
 837 }
 838
 839 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 840                              struct vm_area_struct *vma)
 841 {
 842         return ttm_fbdev_mmap(vma, &bo->tbo);
 843 }
 844
 845 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 846 {
 847         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 848
 849         if (adev->family <= AMDGPU_FAMILY_CZ &&
 850             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 851                 return -EINVAL;
 852
 853         bo->tiling_flags = tiling_flags;
 854         return 0;
 855 }
 856
 857 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 858 {
 859         lockdep_assert_held(&bo->tbo.resv->lock.base);
 860
 861         if (tiling_flags)
 862                 *tiling_flags = bo->tiling_flags;
 863 }
 864
 865 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 866                             uint32_t metadata_size, uint64_t flags)
 867 {
 868         void *buffer;
 869
 870         if (!metadata_size) {
 871                 if (bo->metadata_size) {
 872                         kfree(bo->metadata);
 873                         bo->metadata = NULL;
 874                         bo->metadata_size = 0;
 875                 }
 876                 return 0;
 877         }
 878
 879         if (metadata == NULL)
 880                 return -EINVAL;
 881
 882         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 883         if (buffer == NULL)
 884                 return -ENOMEM;
 885
 886         kfree(bo->metadata);
 887         bo->metadata_flags = flags;
 888         bo->metadata = buffer;
 889         bo->metadata_size = metadata_size;
 890
 891         return 0;
 892 }
 893
 894 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 895                            size_t buffer_size, uint32_t *metadata_size,
 896                            uint64_t *flags)
 897 {
 898         if (!buffer && !metadata_size)
 899                 return -EINVAL;
 900
 901         if (buffer) {
 902                 if (buffer_size < bo->metadata_size)
 903                         return -EINVAL;
 904
 905                 if (bo->metadata_size)
 906                         memcpy(buffer, bo->metadata, bo->metadata_size);
 907         }
 908
 909         if (metadata_size)
 910                 *metadata_size = bo->metadata_size;
 911         if (flags)
 912                 *flags = bo->metadata_flags;
 913
 914         return 0;
 915 }
 916
 917 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 918                            bool evict,
 919                            struct ttm_mem_reg *new_mem)
 920 {
 921         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 922         struct amdgpu_bo *abo;
 923         struct ttm_mem_reg *old_mem = &bo->mem;
 924
 925         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 926                 return;
 927
 928         abo = ttm_to_amdgpu_bo(bo);
 929         amdgpu_vm_bo_invalidate(adev, abo, evict);
 930
 931         amdgpu_bo_kunmap(abo);
 932
 933         /* remember the eviction */
 934         if (evict)
 935                 atomic64_inc(&adev->num_evictions);
 936
 937         /* update statistics */
 938         if (!new_mem)
 939                 return;
 940
 941         /* move_notify is called before move happens */
 942         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 943 }
 944
 945 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 946 {
 947         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 948         struct amdgpu_bo *abo;
 949         unsigned long offset, size;
 950         int r;
 951
 952         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 953                 return 0;
 954
 955         abo = ttm_to_amdgpu_bo(bo);
 956
 957         /* Remember that this BO was accessed by the CPU */
 958         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 959
 960         if (bo->mem.mem_type != TTM_PL_VRAM)
 961                 return 0;
 962
 963         size = bo->mem.num_pages << PAGE_SHIFT;
 964         offset = bo->mem.start << PAGE_SHIFT;
 965         if ((offset + size) <= adev->mc.visible_vram_size)
 966                 return 0;
 967
 968         /* Can't move a pinned BO to visible VRAM */
 969         if (abo->pin_count > 0)
 970                 return -EINVAL;
 971
 972         /* hurrah the memory is not visible ! */
 973         atomic64_inc(&adev->num_vram_cpu_page_faults);
 974         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 975                                          AMDGPU_GEM_DOMAIN_GTT);
 976
 977         /* Avoid costly evictions; only set GTT as a busy placement */
 978         abo->placement.num_busy_placement = 1;
 979         abo->placement.busy_placement = &abo->placements[1];
 980
 981         r = ttm_bo_validate(bo, &abo->placement, false, false);
 982         if (unlikely(r != 0))
 983                 return r;
 984
 985         offset = bo->mem.start << PAGE_SHIFT;
 986         /* this should never happen */
 987         if (bo->mem.mem_type == TTM_PL_VRAM &&
 988             (offset + size) > adev->mc.visible_vram_size)
 989                 return -EINVAL;
 990
 991         return 0;
 992 }
 993
 994 /**
 995  * amdgpu_bo_fence - add fence to buffer object
 996  *
 997  * @bo: buffer object in question
 998  * @fence: fence to add
 999  * @shared: true if fence should be added shared
1000  *
1001  */
1002 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1003                      bool shared)
1004 {
1005         struct reservation_object *resv = bo->tbo.resv;
1006
1007         if (shared)
1008                 reservation_object_add_shared_fence(resv, fence);
1009         else
1010                 reservation_object_add_excl_fence(resv, fence);
1011 }
1012
1013 /**
1014  * amdgpu_bo_gpu_offset - return GPU offset of bo
1015  * @bo: amdgpu object for which we query the offset
1016  *
1017  * Returns current GPU offset of the object.
1018  *
1019  * Note: object should either be pinned or reserved when calling this
1020  * function, it might be useful to add check for this for debugging.
1021  */
1022 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1023 {
1024         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1025         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1026                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1027         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1028                      !bo->pin_count);
1029         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1030         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1031                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1032
1033         return bo->tbo.offset;
1034 }