drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "navi10_enum.h"
  39 #include "hdp/hdp_5_0_0_offset.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15_common.h"
  44 #include "clearstate_gfx10.h"
  45 #include "v10_structs.h"
  46 #include "gfx_v10_0.h"
  47 #include "nbio_v2_3.h"
  48
  49 /**
  50  * Navi10 has two graphic rings to share each graphic pipe.
  51  * 1. Primary ring
  52  * 2. Async ring
  53  *
  54  * In bring-up phase, it just used primary ring so set gfx ring number as 1 at
  55  * first.
  56  */
  57 #define GFX10_NUM_GFX_RINGS     2
  58 #define GFX10_MEC_HPD_SIZE      2048
  59
  60 #define F32_CE_PROGRAM_RAM_SIZE         65536
  61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  62
  63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  65
  66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
  67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
  68 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
  69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
  70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
  71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
  72
  73 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
  74 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
  75 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
  76 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
  77 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
  78 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
  79
  80 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
  81 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
  82 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
  83 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
  84 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
  85 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
  86
  87 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
  88 {
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
 126 };
 127
 128 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 129 {
 130         /* Pending on emulation bring up */
 131 };
 132
 133 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
 134 {
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
 170 };
 171
 172 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
 173 {
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
 214 };
 215
 216 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
 217 {
 218         /* Pending on emulation bring up */
 219 };
 220
 221 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
 222 {
 223         /* Pending on emulation bring up */
 224 };
 225
 226 #define DEFAULT_SH_MEM_CONFIG \
 227         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 228          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 229          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
 230          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 231
 232
 233 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
 234 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
 235 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
 236 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
 237 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
 238                                  struct amdgpu_cu_info *cu_info);
 239 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 240 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 241                                    u32 sh_num, u32 instance);
 242 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 243
 244 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
 245 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
 246 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
 247 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 248 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
 249 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 250 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
 251
 252 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 253 {
 254         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 255         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 256                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 257         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 258         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 259         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 260         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 261         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 262         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 263 }
 264
 265 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 266                                  struct amdgpu_ring *ring)
 267 {
 268         struct amdgpu_device *adev = kiq_ring->adev;
 269         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 270         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 271         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 272
 273         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 274         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 275         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 276                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 277                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 278                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 279                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 280                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
 281                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 282                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 283                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 284                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 285         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 286         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 287         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 288         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 289         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 290 }
 291
 292 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 293                                    struct amdgpu_ring *ring,
 294                                    enum amdgpu_unmap_queues_action action,
 295                                    u64 gpu_addr, u64 seq)
 296 {
 297         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 298
 299         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 300         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 301                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 302                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 303                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 304                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 305         amdgpu_ring_write(kiq_ring,
 306                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 307
 308         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 309                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 310                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 311                 amdgpu_ring_write(kiq_ring, seq);
 312         } else {
 313                 amdgpu_ring_write(kiq_ring, 0);
 314                 amdgpu_ring_write(kiq_ring, 0);
 315                 amdgpu_ring_write(kiq_ring, 0);
 316         }
 317 }
 318
 319 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
 320                                    struct amdgpu_ring *ring,
 321                                    u64 addr,
 322                                    u64 seq)
 323 {
 324         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 325
 326         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 327         amdgpu_ring_write(kiq_ring,
 328                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 329                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 330                           PACKET3_QUERY_STATUS_COMMAND(2));
 331         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 332                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 333                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 334         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 335         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 336         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 337         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 338 }
 339
 340 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
 341         .kiq_set_resources = gfx10_kiq_set_resources,
 342         .kiq_map_queues = gfx10_kiq_map_queues,
 343         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
 344         .kiq_query_status = gfx10_kiq_query_status,
 345         .set_resources_size = 8,
 346         .map_queues_size = 7,
 347         .unmap_queues_size = 6,
 348         .query_status_size = 7,
 349 };
 350
 351 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 352 {
 353         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
 354 }
 355
 356 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
 357 {
 358         switch (adev->asic_type) {
 359         case CHIP_NAVI10:
 360                 soc15_program_register_sequence(adev,
 361                                                 golden_settings_gc_10_1,
 362                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
 363                 soc15_program_register_sequence(adev,
 364                                                 golden_settings_gc_10_0_nv10,
 365                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
 366                 break;
 367         case CHIP_NAVI14:
 368                 soc15_program_register_sequence(adev,
 369                                                 golden_settings_gc_10_1_1,
 370                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
 371                 soc15_program_register_sequence(adev,
 372                                                 golden_settings_gc_10_1_nv14,
 373                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
 374                 break;
 375         case CHIP_NAVI12:
 376                 soc15_program_register_sequence(adev,
 377                                                 golden_settings_gc_10_1_2,
 378                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
 379                 soc15_program_register_sequence(adev,
 380                                                 golden_settings_gc_10_1_2_nv12,
 381                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
 382                 break;
 383         default:
 384                 break;
 385         }
 386 }
 387
 388 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
 389 {
 390         adev->gfx.scratch.num_reg = 8;
 391         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 392         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 393 }
 394
 395 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 396                                        bool wc, uint32_t reg, uint32_t val)
 397 {
 398         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 399         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 400                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 401         amdgpu_ring_write(ring, reg);
 402         amdgpu_ring_write(ring, 0);
 403         amdgpu_ring_write(ring, val);
 404 }
 405
 406 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 407                                   int mem_space, int opt, uint32_t addr0,
 408                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 409                                   uint32_t inv)
 410 {
 411         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 412         amdgpu_ring_write(ring,
 413                           /* memory (1) or register (0) */
 414                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 415                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 416                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 417                            WAIT_REG_MEM_ENGINE(eng_sel)));
 418
 419         if (mem_space)
 420                 BUG_ON(addr0 & 0x3); /* Dword align */
 421         amdgpu_ring_write(ring, addr0);
 422         amdgpu_ring_write(ring, addr1);
 423         amdgpu_ring_write(ring, ref);
 424         amdgpu_ring_write(ring, mask);
 425         amdgpu_ring_write(ring, inv); /* poll interval */
 426 }
 427
 428 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 429 {
 430         struct amdgpu_device *adev = ring->adev;
 431         uint32_t scratch;
 432         uint32_t tmp = 0;
 433         unsigned i;
 434         int r;
 435
 436         r = amdgpu_gfx_scratch_get(adev, &scratch);
 437         if (r) {
 438                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 439                 return r;
 440         }
 441
 442         WREG32(scratch, 0xCAFEDEAD);
 443
 444         r = amdgpu_ring_alloc(ring, 3);
 445         if (r) {
 446                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 447                           ring->idx, r);
 448                 amdgpu_gfx_scratch_free(adev, scratch);
 449                 return r;
 450         }
 451
 452         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 453         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 454         amdgpu_ring_write(ring, 0xDEADBEEF);
 455         amdgpu_ring_commit(ring);
 456
 457         for (i = 0; i < adev->usec_timeout; i++) {
 458                 tmp = RREG32(scratch);
 459                 if (tmp == 0xDEADBEEF)
 460                         break;
 461                 if (amdgpu_emu_mode == 1)
 462                         msleep(1);
 463                 else
 464                         udelay(1);
 465         }
 466         if (i < adev->usec_timeout) {
 467                 if (amdgpu_emu_mode == 1)
 468                         DRM_INFO("ring test on %d succeeded in %d msecs\n",
 469                                  ring->idx, i);
 470                 else
 471                         DRM_INFO("ring test on %d succeeded in %d usecs\n",
 472                                  ring->idx, i);
 473         } else {
 474                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 475                           ring->idx, scratch, tmp);
 476                 r = -EINVAL;
 477         }
 478         amdgpu_gfx_scratch_free(adev, scratch);
 479
 480         return r;
 481 }
 482
 483 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 484 {
 485         struct amdgpu_device *adev = ring->adev;
 486         struct amdgpu_ib ib;
 487         struct dma_fence *f = NULL;
 488         uint32_t scratch;
 489         uint32_t tmp = 0;
 490         long r;
 491
 492         r = amdgpu_gfx_scratch_get(adev, &scratch);
 493         if (r) {
 494                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
 495                 return r;
 496         }
 497
 498         WREG32(scratch, 0xCAFEDEAD);
 499
 500         memset(&ib, 0, sizeof(ib));
 501         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 502         if (r) {
 503                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 504                 goto err1;
 505         }
 506
 507         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 508         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 509         ib.ptr[2] = 0xDEADBEEF;
 510         ib.length_dw = 3;
 511
 512         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 513         if (r)
 514                 goto err2;
 515
 516         r = dma_fence_wait_timeout(f, false, timeout);
 517         if (r == 0) {
 518                 DRM_ERROR("amdgpu: IB test timed out.\n");
 519                 r = -ETIMEDOUT;
 520                 goto err2;
 521         } else if (r < 0) {
 522                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 523                 goto err2;
 524         }
 525
 526         tmp = RREG32(scratch);
 527         if (tmp == 0xDEADBEEF) {
 528                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 529                 r = 0;
 530         } else {
 531                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 532                           scratch, tmp);
 533                 r = -EINVAL;
 534         }
 535 err2:
 536         amdgpu_ib_free(adev, &ib, NULL);
 537         dma_fence_put(f);
 538 err1:
 539         amdgpu_gfx_scratch_free(adev, scratch);
 540
 541         return r;
 542 }
 543
 544 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
 545 {
 546         release_firmware(adev->gfx.pfp_fw);
 547         adev->gfx.pfp_fw = NULL;
 548         release_firmware(adev->gfx.me_fw);
 549         adev->gfx.me_fw = NULL;
 550         release_firmware(adev->gfx.ce_fw);
 551         adev->gfx.ce_fw = NULL;
 552         release_firmware(adev->gfx.rlc_fw);
 553         adev->gfx.rlc_fw = NULL;
 554         release_firmware(adev->gfx.mec_fw);
 555         adev->gfx.mec_fw = NULL;
 556         release_firmware(adev->gfx.mec2_fw);
 557         adev->gfx.mec2_fw = NULL;
 558
 559         kfree(adev->gfx.rlc.register_list_format);
 560 }
 561
 562 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 563 {
 564         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 565
 566         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 567         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 568         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 569         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 570         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 571         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 572         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 573         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 574         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 575         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 576         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 577         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 578         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 579         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 580                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 581 }
 582
 583 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
 584 {
 585         switch (adev->asic_type) {
 586         case CHIP_NAVI10:
 587                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 588                 break;
 589         default:
 590                 break;
 591         }
 592 }
 593
 594 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 595 {
 596         const char *chip_name;
 597         char fw_name[30];
 598         int err;
 599         struct amdgpu_firmware_info *info = NULL;
 600         const struct common_firmware_header *header = NULL;
 601         const struct gfx_firmware_header_v1_0 *cp_hdr;
 602         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 603         unsigned int *tmp = NULL;
 604         unsigned int i = 0;
 605         uint16_t version_major;
 606         uint16_t version_minor;
 607
 608         DRM_DEBUG("\n");
 609
 610         switch (adev->asic_type) {
 611         case CHIP_NAVI10:
 612                 chip_name = "navi10";
 613                 break;
 614         case CHIP_NAVI14:
 615                 chip_name = "navi14";
 616                 break;
 617         case CHIP_NAVI12:
 618                 chip_name = "navi12";
 619                 break;
 620         default:
 621                 BUG();
 622         }
 623
 624         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 625         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 626         if (err)
 627                 goto out;
 628         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 629         if (err)
 630                 goto out;
 631         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 632         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 633         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 634
 635         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 636         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 637         if (err)
 638                 goto out;
 639         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 640         if (err)
 641                 goto out;
 642         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 643         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 644         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 645
 646         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 647         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 648         if (err)
 649                 goto out;
 650         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 651         if (err)
 652                 goto out;
 653         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 654         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 655         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 656
 657         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 658         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 659         if (err)
 660                 goto out;
 661         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 662         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 663         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 664         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 665         if (version_major == 2 && version_minor == 1)
 666                 adev->gfx.rlc.is_rlc_v2_1 = true;
 667
 668         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 669         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 670         adev->gfx.rlc.save_and_restore_offset =
 671                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 672         adev->gfx.rlc.clear_state_descriptor_offset =
 673                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 674         adev->gfx.rlc.avail_scratch_ram_locations =
 675                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 676         adev->gfx.rlc.reg_restore_list_size =
 677                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 678         adev->gfx.rlc.reg_list_format_start =
 679                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 680         adev->gfx.rlc.reg_list_format_separate_start =
 681                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 682         adev->gfx.rlc.starting_offsets_start =
 683                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 684         adev->gfx.rlc.reg_list_format_size_bytes =
 685                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 686         adev->gfx.rlc.reg_list_size_bytes =
 687                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 688         adev->gfx.rlc.register_list_format =
 689                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 690                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 691         if (!adev->gfx.rlc.register_list_format) {
 692                 err = -ENOMEM;
 693                 goto out;
 694         }
 695
 696         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 697                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 698         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 699                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 700
 701         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 702
 703         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 704                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 705         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 706                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 707
 708         if (adev->gfx.rlc.is_rlc_v2_1)
 709                 gfx_v10_0_init_rlc_ext_microcode(adev);
 710
 711         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 712         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 713         if (err)
 714                 goto out;
 715         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 716         if (err)
 717                 goto out;
 718         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 719         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 720         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 721
 722         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 723         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 724         if (!err) {
 725                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 726                 if (err)
 727                         goto out;
 728                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 729                 adev->gfx.mec2_fw->data;
 730                 adev->gfx.mec2_fw_version =
 731                 le32_to_cpu(cp_hdr->header.ucode_version);
 732                 adev->gfx.mec2_feature_version =
 733                 le32_to_cpu(cp_hdr->ucode_feature_version);
 734         } else {
 735                 err = 0;
 736                 adev->gfx.mec2_fw = NULL;
 737         }
 738
 739         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 740                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 741                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 742                 info->fw = adev->gfx.pfp_fw;
 743                 header = (const struct common_firmware_header *)info->fw->data;
 744                 adev->firmware.fw_size +=
 745                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 746
 747                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 748                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 749                 info->fw = adev->gfx.me_fw;
 750                 header = (const struct common_firmware_header *)info->fw->data;
 751                 adev->firmware.fw_size +=
 752                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 753
 754                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 755                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 756                 info->fw = adev->gfx.ce_fw;
 757                 header = (const struct common_firmware_header *)info->fw->data;
 758                 adev->firmware.fw_size +=
 759                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 760
 761                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 762                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 763                 info->fw = adev->gfx.rlc_fw;
 764                 header = (const struct common_firmware_header *)info->fw->data;
 765                 adev->firmware.fw_size +=
 766                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 767
 768                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 769                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 770                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 771                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 772                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 773                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 774                         info->fw = adev->gfx.rlc_fw;
 775                         adev->firmware.fw_size +=
 776                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 777
 778                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 779                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 780                         info->fw = adev->gfx.rlc_fw;
 781                         adev->firmware.fw_size +=
 782                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 783
 784                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 785                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 786                         info->fw = adev->gfx.rlc_fw;
 787                         adev->firmware.fw_size +=
 788                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 789                 }
 790
 791                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 792                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 793                 info->fw = adev->gfx.mec_fw;
 794                 header = (const struct common_firmware_header *)info->fw->data;
 795                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 796                 adev->firmware.fw_size +=
 797                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
 798                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 799
 800                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 801                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 802                 info->fw = adev->gfx.mec_fw;
 803                 adev->firmware.fw_size +=
 804                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 805
 806                 if (adev->gfx.mec2_fw) {
 807                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 808                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 809                         info->fw = adev->gfx.mec2_fw;
 810                         header = (const struct common_firmware_header *)info->fw->data;
 811                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 812                         adev->firmware.fw_size +=
 813                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
 814                                       le32_to_cpu(cp_hdr->jt_size) * 4,
 815                                       PAGE_SIZE);
 816                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 817                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 818                         info->fw = adev->gfx.mec2_fw;
 819                         adev->firmware.fw_size +=
 820                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
 821                                       PAGE_SIZE);
 822                 }
 823         }
 824
 825 out:
 826         if (err) {
 827                 dev_err(adev->dev,
 828                         "gfx10: Failed to load firmware \"%s\"\n",
 829                         fw_name);
 830                 release_firmware(adev->gfx.pfp_fw);
 831                 adev->gfx.pfp_fw = NULL;
 832                 release_firmware(adev->gfx.me_fw);
 833                 adev->gfx.me_fw = NULL;
 834                 release_firmware(adev->gfx.ce_fw);
 835                 adev->gfx.ce_fw = NULL;
 836                 release_firmware(adev->gfx.rlc_fw);
 837                 adev->gfx.rlc_fw = NULL;
 838                 release_firmware(adev->gfx.mec_fw);
 839                 adev->gfx.mec_fw = NULL;
 840                 release_firmware(adev->gfx.mec2_fw);
 841                 adev->gfx.mec2_fw = NULL;
 842         }
 843
 844         gfx_v10_0_check_gfxoff_flag(adev);
 845
 846         return err;
 847 }
 848
 849 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
 850 {
 851         u32 count = 0;
 852         const struct cs_section_def *sect = NULL;
 853         const struct cs_extent_def *ext = NULL;
 854
 855         /* begin clear state */
 856         count += 2;
 857         /* context control state */
 858         count += 3;
 859
 860         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
 861                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 862                         if (sect->id == SECT_CONTEXT)
 863                                 count += 2 + ext->reg_count;
 864                         else
 865                                 return 0;
 866                 }
 867         }
 868
 869         /* set PA_SC_TILE_STEERING_OVERRIDE */
 870         count += 3;
 871         /* end clear state */
 872         count += 2;
 873         /* clear state */
 874         count += 2;
 875
 876         return count;
 877 }
 878
 879 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
 880                                     volatile u32 *buffer)
 881 {
 882         u32 count = 0, i;
 883         const struct cs_section_def *sect = NULL;
 884         const struct cs_extent_def *ext = NULL;
 885         int ctx_reg_offset;
 886
 887         if (adev->gfx.rlc.cs_data == NULL)
 888                 return;
 889         if (buffer == NULL)
 890                 return;
 891
 892         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 893         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 894
 895         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 896         buffer[count++] = cpu_to_le32(0x80000000);
 897         buffer[count++] = cpu_to_le32(0x80000000);
 898
 899         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 900                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 901                         if (sect->id == SECT_CONTEXT) {
 902                                 buffer[count++] =
 903                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 904                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 905                                                 PACKET3_SET_CONTEXT_REG_START);
 906                                 for (i = 0; i < ext->reg_count; i++)
 907                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 908                         } else {
 909                                 return;
 910                         }
 911                 }
 912         }
 913
 914         ctx_reg_offset =
 915                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 916         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 917         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 918         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 919
 920         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 921         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 922
 923         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 924         buffer[count++] = cpu_to_le32(0);
 925 }
 926
 927 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
 928 {
 929         /* clear state block */
 930         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 931                         &adev->gfx.rlc.clear_state_gpu_addr,
 932                         (void **)&adev->gfx.rlc.cs_ptr);
 933
 934         /* jump table block */
 935         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 936                         &adev->gfx.rlc.cp_table_gpu_addr,
 937                         (void **)&adev->gfx.rlc.cp_table_ptr);
 938 }
 939
 940 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
 941 {
 942         const struct cs_section_def *cs_data;
 943         int r;
 944
 945         adev->gfx.rlc.cs_data = gfx10_cs_data;
 946
 947         cs_data = adev->gfx.rlc.cs_data;
 948
 949         if (cs_data) {
 950                 /* init clear state block */
 951                 r = amdgpu_gfx_rlc_init_csb(adev);
 952                 if (r)
 953                         return r;
 954         }
 955
 956         return 0;
 957 }
 958
 959 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
 960 {
 961         int r;
 962
 963         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
 964         if (unlikely(r != 0))
 965                 return r;
 966
 967         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
 968                         AMDGPU_GEM_DOMAIN_VRAM);
 969         if (!r)
 970                 adev->gfx.rlc.clear_state_gpu_addr =
 971                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
 972
 973         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 974
 975         return r;
 976 }
 977
 978 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
 979 {
 980         int r;
 981
 982         if (!adev->gfx.rlc.clear_state_obj)
 983                 return;
 984
 985         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
 986         if (likely(r == 0)) {
 987                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
 988                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 989         }
 990 }
 991
 992 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
 993 {
 994         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 995         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 996 }
 997
 998 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
 999 {
1000         int r;
1001
1002         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1003
1004         amdgpu_gfx_graphics_queue_acquire(adev);
1005
1006         r = gfx_v10_0_init_microcode(adev);
1007         if (r)
1008                 DRM_ERROR("Failed to load gfx firmware!\n");
1009
1010         return r;
1011 }
1012
1013 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1014 {
1015         int r;
1016         u32 *hpd;
1017         const __le32 *fw_data = NULL;
1018         unsigned fw_size;
1019         u32 *fw = NULL;
1020         size_t mec_hpd_size;
1021
1022         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1023
1024         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1025
1026         /* take ownership of the relevant compute queues */
1027         amdgpu_gfx_compute_queue_acquire(adev);
1028         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1029
1030         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1031                                       AMDGPU_GEM_DOMAIN_GTT,
1032                                       &adev->gfx.mec.hpd_eop_obj,
1033                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1034                                       (void **)&hpd);
1035         if (r) {
1036                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1037                 gfx_v10_0_mec_fini(adev);
1038                 return r;
1039         }
1040
1041         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1042
1043         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1044         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1045
1046         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1047                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1048
1049                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1050                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1051                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1052
1053                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1054                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1055                                               &adev->gfx.mec.mec_fw_obj,
1056                                               &adev->gfx.mec.mec_fw_gpu_addr,
1057                                               (void **)&fw);
1058                 if (r) {
1059                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1060                         gfx_v10_0_mec_fini(adev);
1061                         return r;
1062                 }
1063
1064                 memcpy(fw, fw_data, fw_size);
1065
1066                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1067                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1068         }
1069
1070         return 0;
1071 }
1072
1073 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1074 {
1075         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1076                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1077                 (address << SQ_IND_INDEX__INDEX__SHIFT));
1078         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1079 }
1080
1081 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1082                            uint32_t thread, uint32_t regno,
1083                            uint32_t num, uint32_t *out)
1084 {
1085         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1086                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1087                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1088                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1089                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1090         while (num--)
1091                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1092 }
1093
1094 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1095 {
1096         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
1097          * field when performing a select_se_sh so it should be
1098          * zero here */
1099         WARN_ON(simd != 0);
1100
1101         /* type 2 wave data */
1102         dst[(*no_fields)++] = 2;
1103         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1104         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1105         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1106         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1107         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1108         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1109         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1110         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1111         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1112         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1113         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1114         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1115         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1116         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1117         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1118 }
1119
1120 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1121                                      uint32_t wave, uint32_t start,
1122                                      uint32_t size, uint32_t *dst)
1123 {
1124         WARN_ON(simd != 0);
1125
1126         wave_read_regs(
1127                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1128                 dst);
1129 }
1130
1131 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1132                                       uint32_t wave, uint32_t thread,
1133                                       uint32_t start, uint32_t size,
1134                                       uint32_t *dst)
1135 {
1136         wave_read_regs(
1137                 adev, wave, thread,
1138                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1139 }
1140
1141 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1142                                                                           u32 me, u32 pipe, u32 q, u32 vm)
1143  {
1144        nv_grbm_select(adev, me, pipe, q, vm);
1145  }
1146
1147
1148 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1149         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1150         .select_se_sh = &gfx_v10_0_select_se_sh,
1151         .read_wave_data = &gfx_v10_0_read_wave_data,
1152         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1153         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1154         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1155 };
1156
1157 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1158 {
1159         u32 gb_addr_config;
1160
1161         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1162
1163         switch (adev->asic_type) {
1164         case CHIP_NAVI10:
1165         case CHIP_NAVI14:
1166         case CHIP_NAVI12:
1167                 adev->gfx.config.max_hw_contexts = 8;
1168                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1169                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1170                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1171                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1172                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1173                 break;
1174         default:
1175                 BUG();
1176                 break;
1177         }
1178
1179         adev->gfx.config.gb_addr_config = gb_addr_config;
1180
1181         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1182                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1183                                       GB_ADDR_CONFIG, NUM_PIPES);
1184
1185         adev->gfx.config.max_tile_pipes =
1186                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1187
1188         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1189                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1190                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1191         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1192                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1193                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
1194         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1195                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1196                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1197         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1198                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1199                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1200 }
1201
1202 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1203                                    int me, int pipe, int queue)
1204 {
1205         int r;
1206         struct amdgpu_ring *ring;
1207         unsigned int irq_type;
1208
1209         ring = &adev->gfx.gfx_ring[ring_id];
1210
1211         ring->me = me;
1212         ring->pipe = pipe;
1213         ring->queue = queue;
1214
1215         ring->ring_obj = NULL;
1216         ring->use_doorbell = true;
1217
1218         if (!ring_id)
1219                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1220         else
1221                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1222         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1223
1224         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1225         r = amdgpu_ring_init(adev, ring, 1024,
1226                              &adev->gfx.eop_irq, irq_type);
1227         if (r)
1228                 return r;
1229         return 0;
1230 }
1231
1232 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1233                                        int mec, int pipe, int queue)
1234 {
1235         int r;
1236         unsigned irq_type;
1237         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1238
1239         ring = &adev->gfx.compute_ring[ring_id];
1240
1241         /* mec0 is me1 */
1242         ring->me = mec + 1;
1243         ring->pipe = pipe;
1244         ring->queue = queue;
1245
1246         ring->ring_obj = NULL;
1247         ring->use_doorbell = true;
1248         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1249         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1250                                 + (ring_id * GFX10_MEC_HPD_SIZE);
1251         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1252
1253         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1254                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1255                 + ring->pipe;
1256
1257         /* type-2 packets are deprecated on MEC, use type-3 instead */
1258         r = amdgpu_ring_init(adev, ring, 1024,
1259                              &adev->gfx.eop_irq, irq_type);
1260         if (r)
1261                 return r;
1262
1263         return 0;
1264 }
1265
1266 static int gfx_v10_0_sw_init(void *handle)
1267 {
1268         int i, j, k, r, ring_id = 0;
1269         struct amdgpu_kiq *kiq;
1270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
1272         switch (adev->asic_type) {
1273         case CHIP_NAVI10:
1274         case CHIP_NAVI14:
1275         case CHIP_NAVI12:
1276                 adev->gfx.me.num_me = 1;
1277                 adev->gfx.me.num_pipe_per_me = 2;
1278                 adev->gfx.me.num_queue_per_pipe = 1;
1279                 adev->gfx.mec.num_mec = 2;
1280                 adev->gfx.mec.num_pipe_per_mec = 4;
1281                 adev->gfx.mec.num_queue_per_pipe = 8;
1282                 break;
1283         default:
1284                 adev->gfx.me.num_me = 1;
1285                 adev->gfx.me.num_pipe_per_me = 1;
1286                 adev->gfx.me.num_queue_per_pipe = 1;
1287                 adev->gfx.mec.num_mec = 1;
1288                 adev->gfx.mec.num_pipe_per_mec = 4;
1289                 adev->gfx.mec.num_queue_per_pipe = 8;
1290                 break;
1291         }
1292
1293         /* KIQ event */
1294         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1295                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1296                               &adev->gfx.kiq.irq);
1297         if (r)
1298                 return r;
1299
1300         /* EOP Event */
1301         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1302                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1303                               &adev->gfx.eop_irq);
1304         if (r)
1305                 return r;
1306
1307         /* Privileged reg */
1308         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1309                               &adev->gfx.priv_reg_irq);
1310         if (r)
1311                 return r;
1312
1313         /* Privileged inst */
1314         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1315                               &adev->gfx.priv_inst_irq);
1316         if (r)
1317                 return r;
1318
1319         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1320
1321         gfx_v10_0_scratch_init(adev);
1322
1323         r = gfx_v10_0_me_init(adev);
1324         if (r)
1325                 return r;
1326
1327         r = gfx_v10_0_rlc_init(adev);
1328         if (r) {
1329                 DRM_ERROR("Failed to init rlc BOs!\n");
1330                 return r;
1331         }
1332
1333         r = gfx_v10_0_mec_init(adev);
1334         if (r) {
1335                 DRM_ERROR("Failed to init MEC BOs!\n");
1336                 return r;
1337         }
1338
1339         /* set up the gfx ring */
1340         for (i = 0; i < adev->gfx.me.num_me; i++) {
1341                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1342                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1343                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1344                                         continue;
1345
1346                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1347                                                             i, k, j);
1348                                 if (r)
1349                                         return r;
1350                                 ring_id++;
1351                         }
1352                 }
1353         }
1354
1355         ring_id = 0;
1356         /* set up the compute queues - allocate horizontally across pipes */
1357         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1358                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1359                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1360                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1361                                                                      j))
1362                                         continue;
1363
1364                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
1365                                                                 i, k, j);
1366                                 if (r)
1367                                         return r;
1368
1369                                 ring_id++;
1370                         }
1371                 }
1372         }
1373
1374         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1375         if (r) {
1376                 DRM_ERROR("Failed to init KIQ BOs!\n");
1377                 return r;
1378         }
1379
1380         kiq = &adev->gfx.kiq;
1381         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1382         if (r)
1383                 return r;
1384
1385         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1386         if (r)
1387                 return r;
1388
1389         /* allocate visible FB for rlc auto-loading fw */
1390         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1391                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1392                 if (r)
1393                         return r;
1394         }
1395
1396         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1397
1398         gfx_v10_0_gpu_early_init(adev);
1399
1400         return 0;
1401 }
1402
1403 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1404 {
1405         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1406                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1407                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1408 }
1409
1410 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1411 {
1412         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1413                               &adev->gfx.ce.ce_fw_gpu_addr,
1414                               (void **)&adev->gfx.ce.ce_fw_ptr);
1415 }
1416
1417 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1418 {
1419         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1420                               &adev->gfx.me.me_fw_gpu_addr,
1421                               (void **)&adev->gfx.me.me_fw_ptr);
1422 }
1423
1424 static int gfx_v10_0_sw_fini(void *handle)
1425 {
1426         int i;
1427         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1428
1429         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1430                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1431         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1432                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1433
1434         amdgpu_gfx_mqd_sw_fini(adev);
1435         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1436         amdgpu_gfx_kiq_fini(adev);
1437
1438         gfx_v10_0_pfp_fini(adev);
1439         gfx_v10_0_ce_fini(adev);
1440         gfx_v10_0_me_fini(adev);
1441         gfx_v10_0_rlc_fini(adev);
1442         gfx_v10_0_mec_fini(adev);
1443
1444         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1445                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1446
1447         gfx_v10_0_free_microcode(adev);
1448
1449         return 0;
1450 }
1451
1452
1453 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1454 {
1455         /* TODO */
1456 }
1457
1458 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1459                                    u32 sh_num, u32 instance)
1460 {
1461         u32 data;
1462
1463         if (instance == 0xffffffff)
1464                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1465                                      INSTANCE_BROADCAST_WRITES, 1);
1466         else
1467                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1468                                      instance);
1469
1470         if (se_num == 0xffffffff)
1471                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1472                                      1);
1473         else
1474                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1475
1476         if (sh_num == 0xffffffff)
1477                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1478                                      1);
1479         else
1480                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1481
1482         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1483 }
1484
1485 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1486 {
1487         u32 data, mask;
1488
1489         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1490         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1491
1492         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1493         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1494
1495         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1496                                          adev->gfx.config.max_sh_per_se);
1497
1498         return (~data) & mask;
1499 }
1500
1501 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1502 {
1503         int i, j;
1504         u32 data;
1505         u32 active_rbs = 0;
1506         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1507                                         adev->gfx.config.max_sh_per_se;
1508
1509         mutex_lock(&adev->grbm_idx_mutex);
1510         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1511                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1512                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1513                         data = gfx_v10_0_get_rb_active_bitmap(adev);
1514                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1515                                                rb_bitmap_width_per_sh);
1516                 }
1517         }
1518         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1519         mutex_unlock(&adev->grbm_idx_mutex);
1520
1521         adev->gfx.config.backend_enable_mask = active_rbs;
1522         adev->gfx.config.num_rbs = hweight32(active_rbs);
1523 }
1524
1525 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1526 {
1527         uint32_t num_sc;
1528         uint32_t enabled_rb_per_sh;
1529         uint32_t active_rb_bitmap;
1530         uint32_t num_rb_per_sc;
1531         uint32_t num_packer_per_sc;
1532         uint32_t pa_sc_tile_steering_override;
1533
1534         /* init num_sc */
1535         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1536                         adev->gfx.config.num_sc_per_sh;
1537         /* init num_rb_per_sc */
1538         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1539         enabled_rb_per_sh = hweight32(active_rb_bitmap);
1540         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1541         /* init num_packer_per_sc */
1542         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1543
1544         pa_sc_tile_steering_override = 0;
1545         pa_sc_tile_steering_override |=
1546                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1547                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1548         pa_sc_tile_steering_override |=
1549                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1550                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1551         pa_sc_tile_steering_override |=
1552                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1553                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1554
1555         return pa_sc_tile_steering_override;
1556 }
1557
1558 #define DEFAULT_SH_MEM_BASES    (0x6000)
1559 #define FIRST_COMPUTE_VMID      (8)
1560 #define LAST_COMPUTE_VMID       (16)
1561
1562 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1563 {
1564         int i;
1565         uint32_t sh_mem_bases;
1566
1567         /*
1568          * Configure apertures:
1569          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1570          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1571          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1572          */
1573         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1574
1575         mutex_lock(&adev->srbm_mutex);
1576         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1577                 nv_grbm_select(adev, 0, 0, 0, i);
1578                 /* CP and shaders */
1579                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1580                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1581         }
1582         nv_grbm_select(adev, 0, 0, 0, 0);
1583         mutex_unlock(&adev->srbm_mutex);
1584
1585         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1586            acccess. These should be enabled by FW for target VMIDs. */
1587         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1588                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1589                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1590                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1591                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1592         }
1593 }
1594
1595 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1596 {
1597         int vmid;
1598
1599         /*
1600          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1601          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1602          * the driver can enable them for graphics. VMID0 should maintain
1603          * access so that HWS firmware can save/restore entries.
1604          */
1605         for (vmid = 1; vmid < 16; vmid++) {
1606                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1607                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1608                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1609                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1610         }
1611 }
1612
1613
1614 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1615 {
1616         int i, j, k;
1617         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1618         u32 tmp, wgp_active_bitmap = 0;
1619         u32 gcrd_targets_disable_tcp = 0;
1620         u32 utcl_invreq_disable = 0;
1621         /*
1622          * GCRD_TARGETS_DISABLE field contains
1623          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
1624          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
1625          */
1626         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1627                 2 * max_wgp_per_sh + /* TCP */
1628                 max_wgp_per_sh + /* SQC */
1629                 4); /* GL1C */
1630         /*
1631          * UTCL1_UTCL0_INVREQ_DISABLE field contains
1632          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
1633          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
1634          */
1635         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1636                 2 * max_wgp_per_sh + /* TCP */
1637                 2 * max_wgp_per_sh + /* SQC */
1638                 4 + /* RMI */
1639                 1); /* SQG */
1640
1641         if (adev->asic_type == CHIP_NAVI10 ||
1642             adev->asic_type == CHIP_NAVI14 ||
1643             adev->asic_type == CHIP_NAVI12) {
1644                 mutex_lock(&adev->grbm_idx_mutex);
1645                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1646                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1647                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1648                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1649                                 /*
1650                                  * Set corresponding TCP bits for the inactive WGPs in
1651                                  * GCRD_SA_TARGETS_DISABLE
1652                                  */
1653                                 gcrd_targets_disable_tcp = 0;
1654                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
1655                                 utcl_invreq_disable = 0;
1656
1657                                 for (k = 0; k < max_wgp_per_sh; k++) {
1658                                         if (!(wgp_active_bitmap & (1 << k))) {
1659                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
1660                                                 utcl_invreq_disable |= (3 << (2 * k)) |
1661                                                         (3 << (2 * (max_wgp_per_sh + k)));
1662                                         }
1663                                 }
1664
1665                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1666                                 /* only override TCP & SQC bits */
1667                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1668                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1669                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1670
1671                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1672                                 /* only override TCP bits */
1673                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1674                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1675                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1676                         }
1677                 }
1678
1679                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1680                 mutex_unlock(&adev->grbm_idx_mutex);
1681         }
1682 }
1683
1684 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1685 {
1686         u32 tmp;
1687         int i;
1688
1689         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1690
1691         gfx_v10_0_tiling_mode_table_init(adev);
1692
1693         gfx_v10_0_setup_rb(adev);
1694         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1695         adev->gfx.config.pa_sc_tile_steering_override =
1696                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1697
1698         /* XXX SH_MEM regs */
1699         /* where to put LDS, scratch, GPUVM in FSA64 space */
1700         mutex_lock(&adev->srbm_mutex);
1701         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1702                 nv_grbm_select(adev, 0, 0, 0, i);
1703                 /* CP and shaders */
1704                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1705                 if (i != 0) {
1706                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1707                                 (adev->gmc.private_aperture_start >> 48));
1708                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1709                                 (adev->gmc.shared_aperture_start >> 48));
1710                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1711                 }
1712         }
1713         nv_grbm_select(adev, 0, 0, 0, 0);
1714
1715         mutex_unlock(&adev->srbm_mutex);
1716
1717         gfx_v10_0_init_compute_vmid(adev);
1718         gfx_v10_0_init_gds_vmid(adev);
1719
1720 }
1721
1722 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1723                                                bool enable)
1724 {
1725         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1726
1727         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1728                             enable ? 1 : 0);
1729         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1730                             enable ? 1 : 0);
1731         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1732                             enable ? 1 : 0);
1733         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1734                             enable ? 1 : 0);
1735
1736         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1737 }
1738
1739 static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
1740 {
1741         /* csib */
1742         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1743                      adev->gfx.rlc.clear_state_gpu_addr >> 32);
1744         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1745                      adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1746         WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1747 }
1748
1749 static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
1750 {
1751         int i;
1752
1753         gfx_v10_0_init_csb(adev);
1754
1755         for (i = 0; i < adev->num_vmhubs; i++)
1756                 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
1757
1758         /* TODO: init power gating */
1759         return;
1760 }
1761
1762 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1763 {
1764         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1765
1766         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1767         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1768 }
1769
1770 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1771 {
1772         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1773         udelay(50);
1774         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1775         udelay(50);
1776 }
1777
1778 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1779                                              bool enable)
1780 {
1781         uint32_t rlc_pg_cntl;
1782
1783         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1784
1785         if (!enable) {
1786                 /* RLC_PG_CNTL[23] = 0 (default)
1787                  * RLC will wait for handshake acks with SMU
1788                  * GFXOFF will be enabled
1789                  * RLC_PG_CNTL[23] = 1
1790                  * RLC will not issue any message to SMU
1791                  * hence no handshake between SMU & RLC
1792                  * GFXOFF will be disabled
1793                  */
1794                 rlc_pg_cntl |= 0x800000;
1795         } else
1796                 rlc_pg_cntl &= ~0x800000;
1797         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1798 }
1799
1800 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1801 {
1802         /* TODO: enable rlc & smu handshake until smu
1803          * and gfxoff feature works as expected */
1804         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1805                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1806
1807         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1808         udelay(50);
1809 }
1810
1811 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1812 {
1813         uint32_t tmp;
1814
1815         /* enable Save Restore Machine */
1816         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1817         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1818         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1819         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1820 }
1821
1822 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1823 {
1824         const struct rlc_firmware_header_v2_0 *hdr;
1825         const __le32 *fw_data;
1826         unsigned i, fw_size;
1827
1828         if (!adev->gfx.rlc_fw)
1829                 return -EINVAL;
1830
1831         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1832         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1833
1834         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1835                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1836         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1837
1838         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1839                      RLCG_UCODE_LOADING_START_ADDRESS);
1840
1841         for (i = 0; i < fw_size; i++)
1842                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1843                              le32_to_cpup(fw_data++));
1844
1845         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1846
1847         return 0;
1848 }
1849
1850 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1851 {
1852         int r;
1853
1854         if (amdgpu_sriov_vf(adev))
1855                 return 0;
1856
1857         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1858                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1859                 if (r)
1860                         return r;
1861                 gfx_v10_0_init_pg(adev);
1862
1863                 /* enable RLC SRM */
1864                 gfx_v10_0_rlc_enable_srm(adev);
1865
1866         } else {
1867                 adev->gfx.rlc.funcs->stop(adev);
1868
1869                 /* disable CG */
1870                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1871
1872                 /* disable PG */
1873                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1874
1875                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1876                         /* legacy rlc firmware loading */
1877                         r = gfx_v10_0_rlc_load_microcode(adev);
1878                         if (r)
1879                                 return r;
1880                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1881                         /* rlc backdoor autoload firmware */
1882                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1883                         if (r)
1884                                 return r;
1885                 }
1886
1887                 gfx_v10_0_init_pg(adev);
1888                 adev->gfx.rlc.funcs->start(adev);
1889
1890                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1891                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1892                         if (r)
1893                                 return r;
1894                 }
1895         }
1896         return 0;
1897 }
1898
1899 static struct {
1900         FIRMWARE_ID     id;
1901         unsigned int    offset;
1902         unsigned int    size;
1903 } rlc_autoload_info[FIRMWARE_ID_MAX];
1904
1905 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1906 {
1907         int ret;
1908         RLC_TABLE_OF_CONTENT *rlc_toc;
1909
1910         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1911                                         AMDGPU_GEM_DOMAIN_GTT,
1912                                         &adev->gfx.rlc.rlc_toc_bo,
1913                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
1914                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
1915         if (ret) {
1916                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1917                 return ret;
1918         }
1919
1920         /* Copy toc from psp sos fw to rlc toc buffer */
1921         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1922
1923         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1924         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1925                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
1926                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1927                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1928                         /* Offset needs 4KB alignment */
1929                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1930                 }
1931
1932                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1933                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1934                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1935
1936                 rlc_toc++;
1937         };
1938
1939         return 0;
1940 }
1941
1942 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1943 {
1944         uint32_t total_size = 0;
1945         FIRMWARE_ID id;
1946         int ret;
1947
1948         ret = gfx_v10_0_parse_rlc_toc(adev);
1949         if (ret) {
1950                 dev_err(adev->dev, "failed to parse rlc toc\n");
1951                 return 0;
1952         }
1953
1954         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
1955                 total_size += rlc_autoload_info[id].size;
1956
1957         /* In case the offset in rlc toc ucode is aligned */
1958         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
1959                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
1960                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
1961
1962         return total_size;
1963 }
1964
1965 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
1966 {
1967         int r;
1968         uint32_t total_size;
1969
1970         total_size = gfx_v10_0_calc_toc_total_size(adev);
1971
1972         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
1973                                       AMDGPU_GEM_DOMAIN_GTT,
1974                                       &adev->gfx.rlc.rlc_autoload_bo,
1975                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
1976                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1977         if (r) {
1978                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1979                 return r;
1980         }
1981
1982         return 0;
1983 }
1984
1985 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
1986 {
1987         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
1988                               &adev->gfx.rlc.rlc_toc_gpu_addr,
1989                               (void **)&adev->gfx.rlc.rlc_toc_buf);
1990         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1991                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
1992                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1993 }
1994
1995 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1996                                                        FIRMWARE_ID id,
1997                                                        const void *fw_data,
1998                                                        uint32_t fw_size)
1999 {
2000         uint32_t toc_offset;
2001         uint32_t toc_fw_size;
2002         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
2003
2004         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
2005                 return;
2006
2007         toc_offset = rlc_autoload_info[id].offset;
2008         toc_fw_size = rlc_autoload_info[id].size;
2009
2010         if (fw_size == 0)
2011                 fw_size = toc_fw_size;
2012
2013         if (fw_size > toc_fw_size)
2014                 fw_size = toc_fw_size;
2015
2016         memcpy(ptr + toc_offset, fw_data, fw_size);
2017
2018         if (fw_size < toc_fw_size)
2019                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2020 }
2021
2022 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2023 {
2024         void *data;
2025         uint32_t size;
2026
2027         data = adev->gfx.rlc.rlc_toc_buf;
2028         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2029
2030         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2031                                                    FIRMWARE_ID_RLC_TOC,
2032                                                    data, size);
2033 }
2034
2035 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2036 {
2037         const __le32 *fw_data;
2038         uint32_t fw_size;
2039         const struct gfx_firmware_header_v1_0 *cp_hdr;
2040         const struct rlc_firmware_header_v2_0 *rlc_hdr;
2041
2042         /* pfp ucode */
2043         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2044                 adev->gfx.pfp_fw->data;
2045         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2046                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2047         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2048         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2049                                                    FIRMWARE_ID_CP_PFP,
2050                                                    fw_data, fw_size);
2051
2052         /* ce ucode */
2053         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2054                 adev->gfx.ce_fw->data;
2055         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2056                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2057         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2058         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2059                                                    FIRMWARE_ID_CP_CE,
2060                                                    fw_data, fw_size);
2061
2062         /* me ucode */
2063         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2064                 adev->gfx.me_fw->data;
2065         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2066                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2067         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2068         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2069                                                    FIRMWARE_ID_CP_ME,
2070                                                    fw_data, fw_size);
2071
2072         /* rlc ucode */
2073         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2074                 adev->gfx.rlc_fw->data;
2075         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2076                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2077         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2078         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2079                                                    FIRMWARE_ID_RLC_G_UCODE,
2080                                                    fw_data, fw_size);
2081
2082         /* mec1 ucode */
2083         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2084                 adev->gfx.mec_fw->data;
2085         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2086                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2087         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2088                 cp_hdr->jt_size * 4;
2089         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2090                                                    FIRMWARE_ID_CP_MEC,
2091                                                    fw_data, fw_size);
2092         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
2093 }
2094
2095 /* Temporarily put sdma part here */
2096 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2097 {
2098         const __le32 *fw_data;
2099         uint32_t fw_size;
2100         const struct sdma_firmware_header_v1_0 *sdma_hdr;
2101         int i;
2102
2103         for (i = 0; i < adev->sdma.num_instances; i++) {
2104                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2105                         adev->sdma.instance[i].fw->data;
2106                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2107                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2108                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2109
2110                 if (i == 0) {
2111                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2112                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2113                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2114                                 FIRMWARE_ID_SDMA0_JT,
2115                                 (uint32_t *)fw_data +
2116                                 sdma_hdr->jt_offset,
2117                                 sdma_hdr->jt_size * 4);
2118                 } else if (i == 1) {
2119                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2120                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2121                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2122                                 FIRMWARE_ID_SDMA1_JT,
2123                                 (uint32_t *)fw_data +
2124                                 sdma_hdr->jt_offset,
2125                                 sdma_hdr->jt_size * 4);
2126                 }
2127         }
2128 }
2129
2130 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2131 {
2132         uint32_t rlc_g_offset, rlc_g_size, tmp;
2133         uint64_t gpu_addr;
2134
2135         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2136         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2137         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2138
2139         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2140         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2141         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2142
2143         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2144         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2145         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2146
2147         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2148         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2149                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2150                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2151                 return -EINVAL;
2152         }
2153
2154         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2155         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2156                 DRM_ERROR("RLC ROM should halt itself\n");
2157                 return -EINVAL;
2158         }
2159
2160         return 0;
2161 }
2162
2163 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2164 {
2165         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2166         uint32_t tmp;
2167         int i;
2168         uint64_t addr;
2169
2170         /* Trigger an invalidation of the L1 instruction caches */
2171         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2172         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2173         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2174
2175         /* Wait for invalidation complete */
2176         for (i = 0; i < usec_timeout; i++) {
2177                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2178                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2179                         INVALIDATE_CACHE_COMPLETE))
2180                         break;
2181                 udelay(1);
2182         }
2183
2184         if (i >= usec_timeout) {
2185                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2186                 return -EINVAL;
2187         }
2188
2189         /* Program me ucode address into intruction cache address register */
2190         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2191                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2192         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2193                         lower_32_bits(addr) & 0xFFFFF000);
2194         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2195                         upper_32_bits(addr));
2196
2197         return 0;
2198 }
2199
2200 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2201 {
2202         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2203         uint32_t tmp;
2204         int i;
2205         uint64_t addr;
2206
2207         /* Trigger an invalidation of the L1 instruction caches */
2208         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2209         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2210         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2211
2212         /* Wait for invalidation complete */
2213         for (i = 0; i < usec_timeout; i++) {
2214                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2215                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2216                         INVALIDATE_CACHE_COMPLETE))
2217                         break;
2218                 udelay(1);
2219         }
2220
2221         if (i >= usec_timeout) {
2222                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2223                 return -EINVAL;
2224         }
2225
2226         /* Program ce ucode address into intruction cache address register */
2227         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2228                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2229         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2230                         lower_32_bits(addr) & 0xFFFFF000);
2231         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2232                         upper_32_bits(addr));
2233
2234         return 0;
2235 }
2236
2237 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2238 {
2239         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2240         uint32_t tmp;
2241         int i;
2242         uint64_t addr;
2243
2244         /* Trigger an invalidation of the L1 instruction caches */
2245         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2246         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2247         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2248
2249         /* Wait for invalidation complete */
2250         for (i = 0; i < usec_timeout; i++) {
2251                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2252                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2253                         INVALIDATE_CACHE_COMPLETE))
2254                         break;
2255                 udelay(1);
2256         }
2257
2258         if (i >= usec_timeout) {
2259                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2260                 return -EINVAL;
2261         }
2262
2263         /* Program pfp ucode address into intruction cache address register */
2264         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2265                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2266         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2267                         lower_32_bits(addr) & 0xFFFFF000);
2268         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2269                         upper_32_bits(addr));
2270
2271         return 0;
2272 }
2273
2274 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2275 {
2276         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2277         uint32_t tmp;
2278         int i;
2279         uint64_t addr;
2280
2281         /* Trigger an invalidation of the L1 instruction caches */
2282         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2283         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2284         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2285
2286         /* Wait for invalidation complete */
2287         for (i = 0; i < usec_timeout; i++) {
2288                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2289                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2290                         INVALIDATE_CACHE_COMPLETE))
2291                         break;
2292                 udelay(1);
2293         }
2294
2295         if (i >= usec_timeout) {
2296                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2297                 return -EINVAL;
2298         }
2299
2300         /* Program mec1 ucode address into intruction cache address register */
2301         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2302                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2303         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2304                         lower_32_bits(addr) & 0xFFFFF000);
2305         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2306                         upper_32_bits(addr));
2307
2308         return 0;
2309 }
2310
2311 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2312 {
2313         uint32_t cp_status;
2314         uint32_t bootload_status;
2315         int i, r;
2316
2317         for (i = 0; i < adev->usec_timeout; i++) {
2318                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2319                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2320                 if ((cp_status == 0) &&
2321                     (REG_GET_FIELD(bootload_status,
2322                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2323                         break;
2324                 }
2325                 udelay(1);
2326         }
2327
2328         if (i >= adev->usec_timeout) {
2329                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2330                 return -ETIMEDOUT;
2331         }
2332
2333         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2334                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2335                 if (r)
2336                         return r;
2337
2338                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2339                 if (r)
2340                         return r;
2341
2342                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2343                 if (r)
2344                         return r;
2345
2346                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2347                 if (r)
2348                         return r;
2349         }
2350
2351         return 0;
2352 }
2353
2354 static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2355 {
2356         int i;
2357         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2358
2359         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2360         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2361         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2362         if (!enable) {
2363                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2364                         adev->gfx.gfx_ring[i].sched.ready = false;
2365         }
2366         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2367         udelay(50);
2368 }
2369
2370 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2371 {
2372         int r;
2373         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2374         const __le32 *fw_data;
2375         unsigned i, fw_size;
2376         uint32_t tmp;
2377         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2378
2379         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2380                 adev->gfx.pfp_fw->data;
2381
2382         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2383
2384         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2385                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2386         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2387
2388         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2389                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2390                                       &adev->gfx.pfp.pfp_fw_obj,
2391                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2392                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2393         if (r) {
2394                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2395                 gfx_v10_0_pfp_fini(adev);
2396                 return r;
2397         }
2398
2399         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2400
2401         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2402         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2403
2404         /* Trigger an invalidation of the L1 instruction caches */
2405         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2406         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2407         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2408
2409         /* Wait for invalidation complete */
2410         for (i = 0; i < usec_timeout; i++) {
2411                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2412                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2413                         INVALIDATE_CACHE_COMPLETE))
2414                         break;
2415                 udelay(1);
2416         }
2417
2418         if (i >= usec_timeout) {
2419                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2420                 return -EINVAL;
2421         }
2422
2423         if (amdgpu_emu_mode == 1)
2424                 adev->nbio_funcs->hdp_flush(adev, NULL);
2425
2426         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2427         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2428         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2429         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2430         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2431         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2432         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2433                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2434         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2435                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2436
2437         return 0;
2438 }
2439
2440 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2441 {
2442         int r;
2443         const struct gfx_firmware_header_v1_0 *ce_hdr;
2444         const __le32 *fw_data;
2445         unsigned i, fw_size;
2446         uint32_t tmp;
2447         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2448
2449         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2450                 adev->gfx.ce_fw->data;
2451
2452         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2453
2454         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2455                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2456         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2457
2458         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2459                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2460                                       &adev->gfx.ce.ce_fw_obj,
2461                                       &adev->gfx.ce.ce_fw_gpu_addr,
2462                                       (void **)&adev->gfx.ce.ce_fw_ptr);
2463         if (r) {
2464                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2465                 gfx_v10_0_ce_fini(adev);
2466                 return r;
2467         }
2468
2469         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2470
2471         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2472         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2473
2474         /* Trigger an invalidation of the L1 instruction caches */
2475         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2476         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2477         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2478
2479         /* Wait for invalidation complete */
2480         for (i = 0; i < usec_timeout; i++) {
2481                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2482                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2483                         INVALIDATE_CACHE_COMPLETE))
2484                         break;
2485                 udelay(1);
2486         }
2487
2488         if (i >= usec_timeout) {
2489                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2490                 return -EINVAL;
2491         }
2492
2493         if (amdgpu_emu_mode == 1)
2494                 adev->nbio_funcs->hdp_flush(adev, NULL);
2495
2496         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2497         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2498         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2499         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2500         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2501         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2502                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2503         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2504                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2505
2506         return 0;
2507 }
2508
2509 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2510 {
2511         int r;
2512         const struct gfx_firmware_header_v1_0 *me_hdr;
2513         const __le32 *fw_data;
2514         unsigned i, fw_size;
2515         uint32_t tmp;
2516         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2517
2518         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2519                 adev->gfx.me_fw->data;
2520
2521         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2522
2523         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2524                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2525         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2526
2527         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2528                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2529                                       &adev->gfx.me.me_fw_obj,
2530                                       &adev->gfx.me.me_fw_gpu_addr,
2531                                       (void **)&adev->gfx.me.me_fw_ptr);
2532         if (r) {
2533                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2534                 gfx_v10_0_me_fini(adev);
2535                 return r;
2536         }
2537
2538         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2539
2540         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2541         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2542
2543         /* Trigger an invalidation of the L1 instruction caches */
2544         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2545         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2546         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2547
2548         /* Wait for invalidation complete */
2549         for (i = 0; i < usec_timeout; i++) {
2550                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2551                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2552                         INVALIDATE_CACHE_COMPLETE))
2553                         break;
2554                 udelay(1);
2555         }
2556
2557         if (i >= usec_timeout) {
2558                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2559                 return -EINVAL;
2560         }
2561
2562         if (amdgpu_emu_mode == 1)
2563                 adev->nbio_funcs->hdp_flush(adev, NULL);
2564
2565         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2566         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2567         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2568         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2569         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2570         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2571                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2572         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2573                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2574
2575         return 0;
2576 }
2577
2578 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2579 {
2580         int r;
2581
2582         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2583                 return -EINVAL;
2584
2585         gfx_v10_0_cp_gfx_enable(adev, false);
2586
2587         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2588         if (r) {
2589                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2590                 return r;
2591         }
2592
2593         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2594         if (r) {
2595                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2596                 return r;
2597         }
2598
2599         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2600         if (r) {
2601                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2602                 return r;
2603         }
2604
2605         return 0;
2606 }
2607
2608 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2609 {
2610         struct amdgpu_ring *ring;
2611         const struct cs_section_def *sect = NULL;
2612         const struct cs_extent_def *ext = NULL;
2613         int r, i;
2614         int ctx_reg_offset;
2615
2616         /* init the CP */
2617         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2618                      adev->gfx.config.max_hw_contexts - 1);
2619         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2620
2621         gfx_v10_0_cp_gfx_enable(adev, true);
2622
2623         ring = &adev->gfx.gfx_ring[0];
2624         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2625         if (r) {
2626                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2627                 return r;
2628         }
2629
2630         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2631         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2632
2633         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2634         amdgpu_ring_write(ring, 0x80000000);
2635         amdgpu_ring_write(ring, 0x80000000);
2636
2637         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2638                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2639                         if (sect->id == SECT_CONTEXT) {
2640                                 amdgpu_ring_write(ring,
2641                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
2642                                                           ext->reg_count));
2643                                 amdgpu_ring_write(ring, ext->reg_index -
2644                                                   PACKET3_SET_CONTEXT_REG_START);
2645                                 for (i = 0; i < ext->reg_count; i++)
2646                                         amdgpu_ring_write(ring, ext->extent[i]);
2647                         }
2648                 }
2649         }
2650
2651         ctx_reg_offset =
2652                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2653         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2654         amdgpu_ring_write(ring, ctx_reg_offset);
2655         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2656
2657         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2658         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2659
2660         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2661         amdgpu_ring_write(ring, 0);
2662
2663         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2664         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2665         amdgpu_ring_write(ring, 0x8000);
2666         amdgpu_ring_write(ring, 0x8000);
2667
2668         amdgpu_ring_commit(ring);
2669
2670         /* submit cs packet to copy state 0 to next available state */
2671         ring = &adev->gfx.gfx_ring[1];
2672         r = amdgpu_ring_alloc(ring, 2);
2673         if (r) {
2674                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2675                 return r;
2676         }
2677
2678         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2679         amdgpu_ring_write(ring, 0);
2680
2681         amdgpu_ring_commit(ring);
2682
2683         return 0;
2684 }
2685
2686 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2687                                          CP_PIPE_ID pipe)
2688 {
2689         u32 tmp;
2690
2691         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2692         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2693
2694         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2695 }
2696
2697 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2698                                           struct amdgpu_ring *ring)
2699 {
2700         u32 tmp;
2701
2702         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2703         if (ring->use_doorbell) {
2704                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2705                                     DOORBELL_OFFSET, ring->doorbell_index);
2706                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2707                                     DOORBELL_EN, 1);
2708         } else {
2709                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2710                                     DOORBELL_EN, 0);
2711         }
2712         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2713         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2714                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
2715         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2716
2717         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2718                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2719 }
2720
2721 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2722 {
2723         struct amdgpu_ring *ring;
2724         u32 tmp;
2725         u32 rb_bufsz;
2726         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2727         u32 i;
2728
2729         /* Set the write pointer delay */
2730         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2731
2732         /* set the RB to use vmid 0 */
2733         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2734
2735         /* Init gfx ring 0 for pipe 0 */
2736         mutex_lock(&adev->srbm_mutex);
2737         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2738         mutex_unlock(&adev->srbm_mutex);
2739         /* Set ring buffer size */
2740         ring = &adev->gfx.gfx_ring[0];
2741         rb_bufsz = order_base_2(ring->ring_size / 8);
2742         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2743         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2744 #ifdef __BIG_ENDIAN
2745         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2746 #endif
2747         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2748
2749         /* Initialize the ring buffer's write pointers */
2750         ring->wptr = 0;
2751         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2752         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2753
2754         /* set the wb address wether it's enabled or not */
2755         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2756         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2757         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2758                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2759
2760         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2761         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2762                      lower_32_bits(wptr_gpu_addr));
2763         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2764                      upper_32_bits(wptr_gpu_addr));
2765
2766         mdelay(1);
2767         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2768
2769         rb_addr = ring->gpu_addr >> 8;
2770         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2771         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2772
2773         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2774
2775         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2776
2777         /* Init gfx ring 1 for pipe 1 */
2778         mutex_lock(&adev->srbm_mutex);
2779         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2780         mutex_unlock(&adev->srbm_mutex);
2781         ring = &adev->gfx.gfx_ring[1];
2782         rb_bufsz = order_base_2(ring->ring_size / 8);
2783         tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2784         tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2785         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2786         /* Initialize the ring buffer's write pointers */
2787         ring->wptr = 0;
2788         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2789         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2790         /* Set the wb address wether it's enabled or not */
2791         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2792         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2793         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2794                 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2795         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2796         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2797                 lower_32_bits(wptr_gpu_addr));
2798         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2799                 upper_32_bits(wptr_gpu_addr));
2800
2801         mdelay(1);
2802         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2803
2804         rb_addr = ring->gpu_addr >> 8;
2805         WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2806         WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2807         WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2808
2809         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2810
2811         /* Switch to pipe 0 */
2812         mutex_lock(&adev->srbm_mutex);
2813         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2814         mutex_unlock(&adev->srbm_mutex);
2815
2816         /* start the ring */
2817         gfx_v10_0_cp_gfx_start(adev);
2818
2819         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2820                 ring = &adev->gfx.gfx_ring[i];
2821                 ring->sched.ready = true;
2822         }
2823
2824         return 0;
2825 }
2826
2827 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2828 {
2829         int i;
2830
2831         if (enable) {
2832                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2833         } else {
2834                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2835                              (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2836                               CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2837                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2838                         adev->gfx.compute_ring[i].sched.ready = false;
2839                 adev->gfx.kiq.ring.sched.ready = false;
2840         }
2841         udelay(50);
2842 }
2843
2844 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2845 {
2846         const struct gfx_firmware_header_v1_0 *mec_hdr;
2847         const __le32 *fw_data;
2848         unsigned i;
2849         u32 tmp;
2850         u32 usec_timeout = 50000; /* Wait for 50 ms */
2851
2852         if (!adev->gfx.mec_fw)
2853                 return -EINVAL;
2854
2855         gfx_v10_0_cp_compute_enable(adev, false);
2856
2857         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2858         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2859
2860         fw_data = (const __le32 *)
2861                 (adev->gfx.mec_fw->data +
2862                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2863
2864         /* Trigger an invalidation of the L1 instruction caches */
2865         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2866         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2867         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2868
2869         /* Wait for invalidation complete */
2870         for (i = 0; i < usec_timeout; i++) {
2871                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2872                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2873                                        INVALIDATE_CACHE_COMPLETE))
2874                         break;
2875                 udelay(1);
2876         }
2877
2878         if (i >= usec_timeout) {
2879                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2880                 return -EINVAL;
2881         }
2882
2883         if (amdgpu_emu_mode == 1)
2884                 adev->nbio_funcs->hdp_flush(adev, NULL);
2885
2886         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2887         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2888         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2889         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2890         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2891
2892         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2893                      0xFFFFF000);
2894         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2895                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2896
2897         /* MEC1 */
2898         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2899
2900         for (i = 0; i < mec_hdr->jt_size; i++)
2901                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2902                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2903
2904         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2905
2906         /*
2907          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
2908          * different microcode than MEC1.
2909          */
2910
2911         return 0;
2912 }
2913
2914 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2915 {
2916         uint32_t tmp;
2917         struct amdgpu_device *adev = ring->adev;
2918
2919         /* tell RLC which is KIQ queue */
2920         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2921         tmp &= 0xffffff00;
2922         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2923         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2924         tmp |= 0x80;
2925         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2926 }
2927
2928 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2929 {
2930         struct amdgpu_device *adev = ring->adev;
2931         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2932         uint64_t hqd_gpu_addr, wb_gpu_addr;
2933         uint32_t tmp;
2934         uint32_t rb_bufsz;
2935
2936         /* set up gfx hqd wptr */
2937         mqd->cp_gfx_hqd_wptr = 0;
2938         mqd->cp_gfx_hqd_wptr_hi = 0;
2939
2940         /* set the pointer to the MQD */
2941         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2942         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2943
2944         /* set up mqd control */
2945         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2946         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2947         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2948         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2949         mqd->cp_gfx_mqd_control = tmp;
2950
2951         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2952         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
2953         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2954         mqd->cp_gfx_hqd_vmid = 0;
2955
2956         /* set up default queue priority level
2957          * 0x0 = low priority, 0x1 = high priority */
2958         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
2959         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2960         mqd->cp_gfx_hqd_queue_priority = tmp;
2961
2962         /* set up time quantum */
2963         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
2964         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
2965         mqd->cp_gfx_hqd_quantum = tmp;
2966
2967         /* set up gfx hqd base. this is similar as CP_RB_BASE */
2968         hqd_gpu_addr = ring->gpu_addr >> 8;
2969         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
2970         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
2971
2972         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
2973         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2974         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
2975         mqd->cp_gfx_hqd_rptr_addr_hi =
2976                 upper_32_bits(wb_gpu_addr) & 0xffff;
2977
2978         /* set up rb_wptr_poll addr */
2979         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2980         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2981         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2982
2983         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
2984         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
2985         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
2986         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
2987         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
2988 #ifdef __BIG_ENDIAN
2989         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
2990 #endif
2991         mqd->cp_gfx_hqd_cntl = tmp;
2992
2993         /* set up cp_doorbell_control */
2994         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2995         if (ring->use_doorbell) {
2996                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2997                                     DOORBELL_OFFSET, ring->doorbell_index);
2998                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2999                                     DOORBELL_EN, 1);
3000         } else
3001                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3002                                     DOORBELL_EN, 0);
3003         mqd->cp_rb_doorbell_control = tmp;
3004
3005         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3006         ring->wptr = 0;
3007         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
3008
3009         /* active the queue */
3010         mqd->cp_gfx_hqd_active = 1;
3011
3012         return 0;
3013 }
3014
3015 #ifdef BRING_UP_DEBUG
3016 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3017 {
3018         struct amdgpu_device *adev = ring->adev;
3019         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3020
3021         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3022         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3023         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3024
3025         /* set GFX_MQD_BASE */
3026         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3027         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3028
3029         /* set GFX_MQD_CONTROL */
3030         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3031
3032         /* set GFX_HQD_VMID to 0 */
3033         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3034
3035         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3036                         mqd->cp_gfx_hqd_queue_priority);
3037         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3038
3039         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
3040         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3041         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3042
3043         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3044         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3045         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3046
3047         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3048         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3049
3050         /* set RB_WPTR_POLL_ADDR */
3051         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3052         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3053
3054         /* set RB_DOORBELL_CONTROL */
3055         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3056
3057         /* active the queue */
3058         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3059
3060         return 0;
3061 }
3062 #endif
3063
3064 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
3065 {
3066         struct amdgpu_device *adev = ring->adev;
3067         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3068
3069         if (!adev->in_gpu_reset && !adev->in_suspend) {
3070                 memset((void *)mqd, 0, sizeof(*mqd));
3071                 mutex_lock(&adev->srbm_mutex);
3072                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3073                 gfx_v10_0_gfx_mqd_init(ring);
3074 #ifdef BRING_UP_DEBUG
3075                 gfx_v10_0_gfx_queue_init_register(ring);
3076 #endif
3077                 nv_grbm_select(adev, 0, 0, 0, 0);
3078                 mutex_unlock(&adev->srbm_mutex);
3079                 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
3080                         memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd));
3081         } else if (adev->in_gpu_reset) {
3082                 /* reset mqd with the backup copy */
3083                 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
3084                         memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
3085                 /* reset the ring */
3086                 ring->wptr = 0;
3087                 amdgpu_ring_clear_ring(ring);
3088 #ifdef BRING_UP_DEBUG
3089                 mutex_lock(&adev->srbm_mutex);
3090                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3091                 gfx_v10_0_gfx_queue_init_register(ring);
3092                 nv_grbm_select(adev, 0, 0, 0, 0);
3093                 mutex_unlock(&adev->srbm_mutex);
3094 #endif
3095         } else {
3096                 amdgpu_ring_clear_ring(ring);
3097         }
3098
3099         return 0;
3100 }
3101
3102 #ifndef BRING_UP_DEBUG
3103 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
3104 {
3105         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3106         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3107         int r, i;
3108
3109         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3110                 return -EINVAL;
3111
3112         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3113                                         adev->gfx.num_gfx_rings);
3114         if (r) {
3115                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3116                 return r;
3117         }
3118
3119         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3120                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3121
3122         r = amdgpu_ring_test_ring(kiq_ring);
3123         if (r) {
3124                 DRM_ERROR("kfq enable failed\n");
3125                 kiq_ring->sched.ready = false;
3126         }
3127         return r;
3128 }
3129 #endif
3130
3131 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3132 {
3133         int r, i;
3134         struct amdgpu_ring *ring;
3135
3136         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3137                 ring = &adev->gfx.gfx_ring[i];
3138
3139                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3140                 if (unlikely(r != 0))
3141                         goto done;
3142
3143                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3144                 if (!r) {
3145                         r = gfx_v10_0_gfx_init_queue(ring);
3146                         amdgpu_bo_kunmap(ring->mqd_obj);
3147                         ring->mqd_ptr = NULL;
3148                 }
3149                 amdgpu_bo_unreserve(ring->mqd_obj);
3150                 if (r)
3151                         goto done;
3152         }
3153 #ifndef BRING_UP_DEBUG
3154         r = gfx_v10_0_kiq_enable_kgq(adev);
3155         if (r)
3156                 goto done;
3157 #endif
3158         r = gfx_v10_0_cp_gfx_start(adev);
3159         if (r)
3160                 goto done;
3161
3162         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3163                 ring = &adev->gfx.gfx_ring[i];
3164                 ring->sched.ready = true;
3165         }
3166 done:
3167         return r;
3168 }
3169
3170 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
3171 {
3172         struct amdgpu_device *adev = ring->adev;
3173         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3174         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3175         uint32_t tmp;
3176
3177         mqd->header = 0xC0310800;
3178         mqd->compute_pipelinestat_enable = 0x00000001;
3179         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3180         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3181         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3182         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3183         mqd->compute_misc_reserved = 0x00000003;
3184
3185         eop_base_addr = ring->eop_gpu_addr >> 8;
3186         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3187         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3188
3189         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3190         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3191         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3192                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
3193
3194         mqd->cp_hqd_eop_control = tmp;
3195
3196         /* enable doorbell? */
3197         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3198
3199         if (ring->use_doorbell) {
3200                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3201                                     DOORBELL_OFFSET, ring->doorbell_index);
3202                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3203                                     DOORBELL_EN, 1);
3204                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3205                                     DOORBELL_SOURCE, 0);
3206                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3207                                     DOORBELL_HIT, 0);
3208         } else {
3209                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3210                                     DOORBELL_EN, 0);
3211         }
3212
3213         mqd->cp_hqd_pq_doorbell_control = tmp;
3214
3215         /* disable the queue if it's active */
3216         ring->wptr = 0;
3217         mqd->cp_hqd_dequeue_request = 0;
3218         mqd->cp_hqd_pq_rptr = 0;
3219         mqd->cp_hqd_pq_wptr_lo = 0;
3220         mqd->cp_hqd_pq_wptr_hi = 0;
3221
3222         /* set the pointer to the MQD */
3223         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3224         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3225
3226         /* set MQD vmid to 0 */
3227         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3228         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3229         mqd->cp_mqd_control = tmp;
3230
3231         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3232         hqd_gpu_addr = ring->gpu_addr >> 8;
3233         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3234         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3235
3236         /* set up the HQD, this is similar to CP_RB0_CNTL */
3237         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3238         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3239                             (order_base_2(ring->ring_size / 4) - 1));
3240         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3241                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3242 #ifdef __BIG_ENDIAN
3243         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3244 #endif
3245         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3246         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3247         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3248         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3249         mqd->cp_hqd_pq_control = tmp;
3250
3251         /* set the wb address whether it's enabled or not */
3252         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3253         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3254         mqd->cp_hqd_pq_rptr_report_addr_hi =
3255                 upper_32_bits(wb_gpu_addr) & 0xffff;
3256
3257         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3258         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3259         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3260         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3261
3262         tmp = 0;
3263         /* enable the doorbell if requested */
3264         if (ring->use_doorbell) {
3265                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3266                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3267                                 DOORBELL_OFFSET, ring->doorbell_index);
3268
3269                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3270                                     DOORBELL_EN, 1);
3271                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3272                                     DOORBELL_SOURCE, 0);
3273                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3274                                     DOORBELL_HIT, 0);
3275         }
3276
3277         mqd->cp_hqd_pq_doorbell_control = tmp;
3278
3279         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3280         ring->wptr = 0;
3281         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3282
3283         /* set the vmid for the queue */
3284         mqd->cp_hqd_vmid = 0;
3285
3286         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3287         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3288         mqd->cp_hqd_persistent_state = tmp;
3289
3290         /* set MIN_IB_AVAIL_SIZE */
3291         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3292         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3293         mqd->cp_hqd_ib_control = tmp;
3294
3295         /* activate the queue */
3296         mqd->cp_hqd_active = 1;
3297
3298         return 0;
3299 }
3300
3301 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
3302 {
3303         struct amdgpu_device *adev = ring->adev;
3304         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3305         int j;
3306
3307         /* disable wptr polling */
3308         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3309
3310         /* write the EOP addr */
3311         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3312                mqd->cp_hqd_eop_base_addr_lo);
3313         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3314                mqd->cp_hqd_eop_base_addr_hi);
3315
3316         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3317         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3318                mqd->cp_hqd_eop_control);
3319
3320         /* enable doorbell? */
3321         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3322                mqd->cp_hqd_pq_doorbell_control);
3323
3324         /* disable the queue if it's active */
3325         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3326                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3327                 for (j = 0; j < adev->usec_timeout; j++) {
3328                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3329                                 break;
3330                         udelay(1);
3331                 }
3332                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3333                        mqd->cp_hqd_dequeue_request);
3334                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3335                        mqd->cp_hqd_pq_rptr);
3336                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3337                        mqd->cp_hqd_pq_wptr_lo);
3338                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3339                        mqd->cp_hqd_pq_wptr_hi);
3340         }
3341
3342         /* set the pointer to the MQD */
3343         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3344                mqd->cp_mqd_base_addr_lo);
3345         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3346                mqd->cp_mqd_base_addr_hi);
3347
3348         /* set MQD vmid to 0 */
3349         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3350                mqd->cp_mqd_control);
3351
3352         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3353         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3354                mqd->cp_hqd_pq_base_lo);
3355         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3356                mqd->cp_hqd_pq_base_hi);
3357
3358         /* set up the HQD, this is similar to CP_RB0_CNTL */
3359         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3360                mqd->cp_hqd_pq_control);
3361
3362         /* set the wb address whether it's enabled or not */
3363         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3364                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3365         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3366                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3367
3368         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3369         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3370                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3371         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3372                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3373
3374         /* enable the doorbell if requested */
3375         if (ring->use_doorbell) {
3376                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3377                         (adev->doorbell_index.kiq * 2) << 2);
3378                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3379                         (adev->doorbell_index.userqueue_end * 2) << 2);
3380         }
3381
3382         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3383                mqd->cp_hqd_pq_doorbell_control);
3384
3385         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3386         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3387                mqd->cp_hqd_pq_wptr_lo);
3388         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3389                mqd->cp_hqd_pq_wptr_hi);
3390
3391         /* set the vmid for the queue */
3392         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3393
3394         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3395                mqd->cp_hqd_persistent_state);
3396
3397         /* activate the queue */
3398         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3399                mqd->cp_hqd_active);
3400
3401         if (ring->use_doorbell)
3402                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3403
3404         return 0;
3405 }
3406
3407 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
3408 {
3409         struct amdgpu_device *adev = ring->adev;
3410         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3411         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3412
3413         gfx_v10_0_kiq_setting(ring);
3414
3415         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3416                 /* reset MQD to a clean status */
3417                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3418                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3419
3420                 /* reset ring buffer */
3421                 ring->wptr = 0;
3422                 amdgpu_ring_clear_ring(ring);
3423
3424                 mutex_lock(&adev->srbm_mutex);
3425                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3426                 gfx_v10_0_kiq_init_register(ring);
3427                 nv_grbm_select(adev, 0, 0, 0, 0);
3428                 mutex_unlock(&adev->srbm_mutex);
3429         } else {
3430                 memset((void *)mqd, 0, sizeof(*mqd));
3431                 mutex_lock(&adev->srbm_mutex);
3432                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3433                 gfx_v10_0_compute_mqd_init(ring);
3434                 gfx_v10_0_kiq_init_register(ring);
3435                 nv_grbm_select(adev, 0, 0, 0, 0);
3436                 mutex_unlock(&adev->srbm_mutex);
3437
3438                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3439                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3440         }
3441
3442         return 0;
3443 }
3444
3445 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
3446 {
3447         struct amdgpu_device *adev = ring->adev;
3448         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3449         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3450
3451         if (!adev->in_gpu_reset && !adev->in_suspend) {
3452                 memset((void *)mqd, 0, sizeof(*mqd));
3453                 mutex_lock(&adev->srbm_mutex);
3454                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3455                 gfx_v10_0_compute_mqd_init(ring);
3456                 nv_grbm_select(adev, 0, 0, 0, 0);
3457                 mutex_unlock(&adev->srbm_mutex);
3458
3459                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3460                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3461         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3462                 /* reset MQD to a clean status */
3463                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3464                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3465
3466                 /* reset ring buffer */
3467                 ring->wptr = 0;
3468                 amdgpu_ring_clear_ring(ring);
3469         } else {
3470                 amdgpu_ring_clear_ring(ring);
3471         }
3472
3473         return 0;
3474 }
3475
3476 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
3477 {
3478         struct amdgpu_ring *ring;
3479         int r;
3480
3481         ring = &adev->gfx.kiq.ring;
3482
3483         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3484         if (unlikely(r != 0))
3485                 return r;
3486
3487         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3488         if (unlikely(r != 0))
3489                 return r;
3490
3491         gfx_v10_0_kiq_init_queue(ring);
3492         amdgpu_bo_kunmap(ring->mqd_obj);
3493         ring->mqd_ptr = NULL;
3494         amdgpu_bo_unreserve(ring->mqd_obj);
3495         ring->sched.ready = true;
3496         return 0;
3497 }
3498
3499 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
3500 {
3501         struct amdgpu_ring *ring = NULL;
3502         int r = 0, i;
3503
3504         gfx_v10_0_cp_compute_enable(adev, true);
3505
3506         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3507                 ring = &adev->gfx.compute_ring[i];
3508
3509                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3510                 if (unlikely(r != 0))
3511                         goto done;
3512                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3513                 if (!r) {
3514                         r = gfx_v10_0_kcq_init_queue(ring);
3515                         amdgpu_bo_kunmap(ring->mqd_obj);
3516                         ring->mqd_ptr = NULL;
3517                 }
3518                 amdgpu_bo_unreserve(ring->mqd_obj);
3519                 if (r)
3520                         goto done;
3521         }
3522
3523         r = amdgpu_gfx_enable_kcq(adev);
3524 done:
3525         return r;
3526 }
3527
3528 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
3529 {
3530         int r, i;
3531         struct amdgpu_ring *ring;
3532
3533         if (!(adev->flags & AMD_IS_APU))
3534                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3535
3536         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3537                 /* legacy firmware loading */
3538                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
3539                 if (r)
3540                         return r;
3541
3542                 r = gfx_v10_0_cp_compute_load_microcode(adev);
3543                 if (r)
3544                         return r;
3545         }
3546
3547         r = gfx_v10_0_kiq_resume(adev);
3548         if (r)
3549                 return r;
3550
3551         r = gfx_v10_0_kcq_resume(adev);
3552         if (r)
3553                 return r;
3554
3555         if (!amdgpu_async_gfx_ring) {
3556                 r = gfx_v10_0_cp_gfx_resume(adev);
3557                 if (r)
3558                         return r;
3559         } else {
3560                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
3561                 if (r)
3562                         return r;
3563         }
3564
3565         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3566                 ring = &adev->gfx.gfx_ring[i];
3567                 DRM_INFO("gfx %d ring me %d pipe %d q %d\n",
3568                          i, ring->me, ring->pipe, ring->queue);
3569                 r = amdgpu_ring_test_ring(ring);
3570                 if (r) {
3571                         ring->sched.ready = false;
3572                         return r;
3573                 }
3574         }
3575
3576         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3577                 ring = &adev->gfx.compute_ring[i];
3578                 ring->sched.ready = true;
3579                 DRM_INFO("compute ring %d mec %d pipe %d q %d\n",
3580                          i, ring->me, ring->pipe, ring->queue);
3581                 r = amdgpu_ring_test_ring(ring);
3582                 if (r)
3583                         ring->sched.ready = false;
3584         }
3585
3586         return 0;
3587 }
3588
3589 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
3590 {
3591         gfx_v10_0_cp_gfx_enable(adev, enable);
3592         gfx_v10_0_cp_compute_enable(adev, enable);
3593 }
3594
3595 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
3596 {
3597         uint32_t data, pattern = 0xDEADBEEF;
3598
3599         /* check if mmVGT_ESGS_RING_SIZE_UMD
3600          * has been remapped to mmVGT_ESGS_RING_SIZE */
3601         data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3602
3603         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3604
3605         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3606
3607         if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3608                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3609                 return true;
3610         } else {
3611                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3612                 return false;
3613         }
3614 }
3615
3616 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
3617 {
3618         uint32_t data;
3619
3620         /* initialize cam_index to 0
3621          * index will auto-inc after each data writting */
3622         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3623
3624         /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
3625         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3626                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3627                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3628                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3629         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3630         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3631
3632         /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
3633         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3634                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3635                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3636                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3637         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3638         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3639
3640         /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
3641         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3642                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3643                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3644                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3645         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3646         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3647
3648         /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
3649         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3650                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3651                (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3652                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3653         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3654         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3655
3656         /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
3657         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3658                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3659                (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3660                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3661         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3662         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3663
3664         /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
3665         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3666                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3667                (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3668                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3669         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3670         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3671
3672         /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
3673         data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3674                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3675                (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3676                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3677         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3678         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3679 }
3680
3681 static int gfx_v10_0_hw_init(void *handle)
3682 {
3683         int r;
3684         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3685
3686         r = gfx_v10_0_csb_vram_pin(adev);
3687         if (r)
3688                 return r;
3689
3690         if (!amdgpu_emu_mode)
3691                 gfx_v10_0_init_golden_registers(adev);
3692
3693         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3694                 /**
3695                  * For gfx 10, rlc firmware loading relies on smu firmware is
3696                  * loaded firstly, so in direct type, it has to load smc ucode
3697                  * here before rlc.
3698                  */
3699                 r = smu_load_microcode(&adev->smu);
3700                 if (r)
3701                         return r;
3702
3703                 r = smu_check_fw_status(&adev->smu);
3704                 if (r) {
3705                         pr_err("SMC firmware status is not correct\n");
3706                         return r;
3707                 }
3708         }
3709
3710         /* if GRBM CAM not remapped, set up the remapping */
3711         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
3712                 gfx_v10_0_setup_grbm_cam_remapping(adev);
3713
3714         gfx_v10_0_constants_init(adev);
3715
3716         r = gfx_v10_0_rlc_resume(adev);
3717         if (r)
3718                 return r;
3719
3720         /*
3721          * init golden registers and rlc resume may override some registers,
3722          * reconfig them here
3723          */
3724         gfx_v10_0_tcp_harvest(adev);
3725
3726         r = gfx_v10_0_cp_resume(adev);
3727         if (r)
3728                 return r;
3729
3730         return r;
3731 }
3732
3733 #ifndef BRING_UP_DEBUG
3734 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
3735 {
3736         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3737         struct amdgpu_ring *kiq_ring = &kiq->ring;
3738         int i;
3739
3740         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3741                 return -EINVAL;
3742
3743         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3744                                         adev->gfx.num_gfx_rings))
3745                 return -ENOMEM;
3746
3747         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3748                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3749                                            PREEMPT_QUEUES, 0, 0);
3750
3751         return amdgpu_ring_test_ring(kiq_ring);
3752 }
3753 #endif
3754
3755 static int gfx_v10_0_hw_fini(void *handle)
3756 {
3757         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3758         int r;
3759
3760         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3761         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3762 #ifndef BRING_UP_DEBUG
3763         if (amdgpu_async_gfx_ring) {
3764                 r = gfx_v10_0_kiq_disable_kgq(adev);
3765                 if (r)
3766                         DRM_ERROR("KGQ disable failed\n");
3767         }
3768 #endif
3769         if (amdgpu_gfx_disable_kcq(adev))
3770                 DRM_ERROR("KCQ disable failed\n");
3771         if (amdgpu_sriov_vf(adev)) {
3772                 pr_debug("For SRIOV client, shouldn't do anything.\n");
3773                 return 0;
3774         }
3775         gfx_v10_0_cp_enable(adev, false);
3776         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3777         gfx_v10_0_csb_vram_unpin(adev);
3778
3779         return 0;
3780 }
3781
3782 static int gfx_v10_0_suspend(void *handle)
3783 {
3784         return gfx_v10_0_hw_fini(handle);
3785 }
3786
3787 static int gfx_v10_0_resume(void *handle)
3788 {
3789         return gfx_v10_0_hw_init(handle);
3790 }
3791
3792 static bool gfx_v10_0_is_idle(void *handle)
3793 {
3794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3795
3796         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3797                                 GRBM_STATUS, GUI_ACTIVE))
3798                 return false;
3799         else
3800                 return true;
3801 }
3802
3803 static int gfx_v10_0_wait_for_idle(void *handle)
3804 {
3805         unsigned i;
3806         u32 tmp;
3807         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3808
3809         for (i = 0; i < adev->usec_timeout; i++) {
3810                 /* read MC_STATUS */
3811                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3812                         GRBM_STATUS__GUI_ACTIVE_MASK;
3813
3814                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3815                         return 0;
3816                 udelay(1);
3817         }
3818         return -ETIMEDOUT;
3819 }
3820
3821 static int gfx_v10_0_soft_reset(void *handle)
3822 {
3823         u32 grbm_soft_reset = 0;
3824         u32 tmp;
3825         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3826
3827         /* GRBM_STATUS */
3828         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3829         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3830                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3831                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
3832                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
3833                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
3834                    | GRBM_STATUS__BCI_BUSY_MASK)) {
3835                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3836                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
3837                                                 1);
3838                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3839                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
3840                                                 1);
3841         }
3842
3843         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3844                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3845                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
3846                                                 1);
3847         }
3848
3849         /* GRBM_STATUS2 */
3850         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3851         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3852                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3853                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC,
3854                                                 1);
3855
3856         if (grbm_soft_reset) {
3857                 /* stop the rlc */
3858                 gfx_v10_0_rlc_stop(adev);
3859
3860                 /* Disable GFX parsing/prefetching */
3861                 gfx_v10_0_cp_gfx_enable(adev, false);
3862
3863                 /* Disable MEC parsing/prefetching */
3864                 gfx_v10_0_cp_compute_enable(adev, false);
3865
3866                 if (grbm_soft_reset) {
3867                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3868                         tmp |= grbm_soft_reset;
3869                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3870                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3871                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3872
3873                         udelay(50);
3874
3875                         tmp &= ~grbm_soft_reset;
3876                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3877                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3878                 }
3879
3880                 /* Wait a little for things to settle down */
3881                 udelay(50);
3882         }
3883         return 0;
3884 }
3885
3886 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3887 {
3888         uint64_t clock;
3889
3890         mutex_lock(&adev->gfx.gpu_clock_mutex);
3891         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3892         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3893                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3894         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3895         return clock;
3896 }
3897
3898 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3899                                            uint32_t vmid,
3900                                            uint32_t gds_base, uint32_t gds_size,
3901                                            uint32_t gws_base, uint32_t gws_size,
3902                                            uint32_t oa_base, uint32_t oa_size)
3903 {
3904         struct amdgpu_device *adev = ring->adev;
3905
3906         /* GDS Base */
3907         gfx_v10_0_write_data_to_reg(ring, 0, false,
3908                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3909                                     gds_base);
3910
3911         /* GDS Size */
3912         gfx_v10_0_write_data_to_reg(ring, 0, false,
3913                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3914                                     gds_size);
3915
3916         /* GWS */
3917         gfx_v10_0_write_data_to_reg(ring, 0, false,
3918                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3919                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3920
3921         /* OA */
3922         gfx_v10_0_write_data_to_reg(ring, 0, false,
3923                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3924                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
3925 }
3926
3927 static int gfx_v10_0_early_init(void *handle)
3928 {
3929         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3930
3931         adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;
3932         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3933
3934         gfx_v10_0_set_kiq_pm4_funcs(adev);
3935         gfx_v10_0_set_ring_funcs(adev);
3936         gfx_v10_0_set_irq_funcs(adev);
3937         gfx_v10_0_set_gds_init(adev);
3938         gfx_v10_0_set_rlc_funcs(adev);
3939
3940         return 0;
3941 }
3942
3943 static int gfx_v10_0_late_init(void *handle)
3944 {
3945         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3946         int r;
3947
3948         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3949         if (r)
3950                 return r;
3951
3952         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3953         if (r)
3954                 return r;
3955
3956         return 0;
3957 }
3958
3959 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
3960 {
3961         uint32_t rlc_cntl;
3962
3963         /* if RLC is not enabled, do nothing */
3964         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3965         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3966 }
3967
3968 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
3969 {
3970         uint32_t data;
3971         unsigned i;
3972
3973         data = RLC_SAFE_MODE__CMD_MASK;
3974         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3975         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3976
3977         /* wait for RLC_SAFE_MODE */
3978         for (i = 0; i < adev->usec_timeout; i++) {
3979                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3980                         break;
3981                 udelay(1);
3982         }
3983 }
3984
3985 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
3986 {
3987         uint32_t data;
3988
3989         data = RLC_SAFE_MODE__CMD_MASK;
3990         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3991 }
3992
3993 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3994                                                       bool enable)
3995 {
3996         uint32_t data, def;
3997
3998         /* It is disabled by HW by default */
3999         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4000                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4001                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4002                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4003                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4004                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4005
4006                 /* only for Vega10 & Raven1 */
4007                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4008
4009                 if (def != data)
4010                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4011
4012                 /* MGLS is a global flag to control all MGLS in GFX */
4013                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4014                         /* 2 - RLC memory Light sleep */
4015                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4016                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4017                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4018                                 if (def != data)
4019                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4020                         }
4021                         /* 3 - CP memory Light sleep */
4022                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4023                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4024                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4025                                 if (def != data)
4026                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4027                         }
4028                 }
4029         } else {
4030                 /* 1 - MGCG_OVERRIDE */
4031                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4032                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4033                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4034                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4035                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4036                 if (def != data)
4037                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4038
4039                 /* 2 - disable MGLS in RLC */
4040                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4041                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4042                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4043                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4044                 }
4045
4046                 /* 3 - disable MGLS in CP */
4047                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4048                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4049                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4050                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4051                 }
4052         }
4053 }
4054
4055 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
4056                                            bool enable)
4057 {
4058         uint32_t data, def;
4059
4060         /* Enable 3D CGCG/CGLS */
4061         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4062                 /* write cmd to clear cgcg/cgls ov */
4063                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4064                 /* unset CGCG override */
4065                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4066                 /* update CGCG and CGLS override bits */
4067                 if (def != data)
4068                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4069                 /* enable 3Dcgcg FSM(0x0000363f) */
4070                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4071                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4072                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4073                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4074                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4075                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4076                 if (def != data)
4077                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4078
4079                 /* set IDLE_POLL_COUNT(0x00900100) */
4080                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4081                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4082                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4083                 if (def != data)
4084                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4085         } else {
4086                 /* Disable CGCG/CGLS */
4087                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4088                 /* disable cgcg, cgls should be disabled */
4089                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4090                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4091                 /* disable cgcg and cgls in FSM */
4092                 if (def != data)
4093                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4094         }
4095 }
4096
4097 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4098                                                       bool enable)
4099 {
4100         uint32_t def, data;
4101
4102         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4103                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4104                 /* unset CGCG override */
4105                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4106                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4107                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4108                 else
4109                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4110                 /* update CGCG and CGLS override bits */
4111                 if (def != data)
4112                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4113
4114                 /* enable cgcg FSM(0x0000363F) */
4115                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4116                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4117                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4118                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4119                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4120                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4121                 if (def != data)
4122                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4123
4124                 /* set IDLE_POLL_COUNT(0x00900100) */
4125                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4126                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4127                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4128                 if (def != data)
4129                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4130         } else {
4131                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4132                 /* reset CGCG/CGLS bits */
4133                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4134                 /* disable cgcg and cgls in FSM */
4135                 if (def != data)
4136                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4137         }
4138 }
4139
4140 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4141                                             bool enable)
4142 {
4143         amdgpu_gfx_rlc_enter_safe_mode(adev);
4144
4145         if (enable) {
4146                 /* CGCG/CGLS should be enabled after MGCG/MGLS
4147                  * ===  MGCG + MGLS ===
4148                  */
4149                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4150                 /* ===  CGCG /CGLS for GFX 3D Only === */
4151                 gfx_v10_0_update_3d_clock_gating(adev, enable);
4152                 /* ===  CGCG + CGLS === */
4153                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4154         } else {
4155                 /* CGCG/CGLS should be disabled before MGCG/MGLS
4156                  * ===  CGCG + CGLS ===
4157                  */
4158                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4159                 /* ===  CGCG /CGLS for GFX 3D Only === */
4160                 gfx_v10_0_update_3d_clock_gating(adev, enable);
4161                 /* ===  MGCG + MGLS === */
4162                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4163         }
4164
4165         if (adev->cg_flags &
4166             (AMD_CG_SUPPORT_GFX_MGCG |
4167              AMD_CG_SUPPORT_GFX_CGLS |
4168              AMD_CG_SUPPORT_GFX_CGCG |
4169              AMD_CG_SUPPORT_GFX_CGLS |
4170              AMD_CG_SUPPORT_GFX_3D_CGCG |
4171              AMD_CG_SUPPORT_GFX_3D_CGLS))
4172                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
4173
4174         amdgpu_gfx_rlc_exit_safe_mode(adev);
4175
4176         return 0;
4177 }
4178
4179 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
4180         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
4181         .set_safe_mode = gfx_v10_0_set_safe_mode,
4182         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
4183         .init = gfx_v10_0_rlc_init,
4184         .get_csb_size = gfx_v10_0_get_csb_size,
4185         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
4186         .resume = gfx_v10_0_rlc_resume,
4187         .stop = gfx_v10_0_rlc_stop,
4188         .reset = gfx_v10_0_rlc_reset,
4189         .start = gfx_v10_0_rlc_start
4190 };
4191
4192 static int gfx_v10_0_set_powergating_state(void *handle,
4193                                           enum amd_powergating_state state)
4194 {
4195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4196         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
4197         switch (adev->asic_type) {
4198         case CHIP_NAVI10:
4199         case CHIP_NAVI14:
4200                 if (!enable) {
4201                         amdgpu_gfx_off_ctrl(adev, false);
4202                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4203                 } else
4204                         amdgpu_gfx_off_ctrl(adev, true);
4205                 break;
4206         default:
4207                 break;
4208         }
4209         return 0;
4210 }
4211
4212 static int gfx_v10_0_set_clockgating_state(void *handle,
4213                                           enum amd_clockgating_state state)
4214 {
4215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4216
4217         switch (adev->asic_type) {
4218         case CHIP_NAVI10:
4219         case CHIP_NAVI14:
4220         case CHIP_NAVI12:
4221                 gfx_v10_0_update_gfx_clock_gating(adev,
4222                                                  state == AMD_CG_STATE_GATE ? true : false);
4223                 break;
4224         default:
4225                 break;
4226         }
4227         return 0;
4228 }
4229
4230 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
4231 {
4232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4233         int data;
4234
4235         /* AMD_CG_SUPPORT_GFX_MGCG */
4236         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4237         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4238                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4239
4240         /* AMD_CG_SUPPORT_GFX_CGCG */
4241         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4242         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4243                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4244
4245         /* AMD_CG_SUPPORT_GFX_CGLS */
4246         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4247                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4248
4249         /* AMD_CG_SUPPORT_GFX_RLC_LS */
4250         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4251         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4252                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4253
4254         /* AMD_CG_SUPPORT_GFX_CP_LS */
4255         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4256         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4257                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4258
4259         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4260         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4261         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4262                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4263
4264         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4265         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4266                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4267 }
4268
4269 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4270 {
4271         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
4272 }
4273
4274 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4275 {
4276         struct amdgpu_device *adev = ring->adev;
4277         u64 wptr;
4278
4279         /* XXX check if swapping is necessary on BE */
4280         if (ring->use_doorbell) {
4281                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4282         } else {
4283                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4284                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4285         }
4286
4287         return wptr;
4288 }
4289
4290 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4291 {
4292         struct amdgpu_device *adev = ring->adev;
4293
4294         if (ring->use_doorbell) {
4295                 /* XXX check if swapping is necessary on BE */
4296                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4297                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4298         } else {
4299                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4300                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4301         }
4302 }
4303
4304 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4305 {
4306         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
4307 }
4308
4309 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4310 {
4311         u64 wptr;
4312
4313         /* XXX check if swapping is necessary on BE */
4314         if (ring->use_doorbell)
4315                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4316         else
4317                 BUG();
4318         return wptr;
4319 }
4320
4321 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4322 {
4323         struct amdgpu_device *adev = ring->adev;
4324
4325         /* XXX check if swapping is necessary on BE */
4326         if (ring->use_doorbell) {
4327                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4328                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4329         } else {
4330                 BUG(); /* only DOORBELL method supported on gfx10 now */
4331         }
4332 }
4333
4334 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4335 {
4336         struct amdgpu_device *adev = ring->adev;
4337         u32 ref_and_mask, reg_mem_engine;
4338         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
4339
4340         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4341                 switch (ring->me) {
4342                 case 1:
4343                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4344                         break;
4345                 case 2:
4346                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4347                         break;
4348                 default:
4349                         return;
4350                 }
4351                 reg_mem_engine = 0;
4352         } else {
4353                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4354                 reg_mem_engine = 1; /* pfp */
4355         }
4356
4357         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4358                                adev->nbio_funcs->get_hdp_flush_req_offset(adev),
4359                                adev->nbio_funcs->get_hdp_flush_done_offset(adev),
4360                                ref_and_mask, ref_and_mask, 0x20);
4361 }
4362
4363 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4364                                        struct amdgpu_job *job,
4365                                        struct amdgpu_ib *ib,
4366                                        uint32_t flags)
4367 {
4368         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4369         u32 header, control = 0;
4370
4371         if (ib->flags & AMDGPU_IB_FLAG_CE)
4372                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4373         else
4374                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4375
4376         control |= ib->length_dw | (vmid << 24);
4377
4378         if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4379                 control |= INDIRECT_BUFFER_PRE_ENB(1);
4380
4381                 if (flags & AMDGPU_IB_PREEMPTED)
4382                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
4383
4384                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4385                         gfx_v10_0_ring_emit_de_meta(ring,
4386                                     flags & AMDGPU_IB_PREEMPTED ? true : false);
4387         }
4388
4389         amdgpu_ring_write(ring, header);
4390         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4391         amdgpu_ring_write(ring,
4392 #ifdef __BIG_ENDIAN
4393                 (2 << 0) |
4394 #endif
4395                 lower_32_bits(ib->gpu_addr));
4396         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4397         amdgpu_ring_write(ring, control);
4398 }
4399
4400 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4401                                            struct amdgpu_job *job,
4402                                            struct amdgpu_ib *ib,
4403                                            uint32_t flags)
4404 {
4405         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4406         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4407
4408         /* Currently, there is a high possibility to get wave ID mismatch
4409          * between ME and GDS, leading to a hw deadlock, because ME generates
4410          * different wave IDs than the GDS expects. This situation happens
4411          * randomly when at least 5 compute pipes use GDS ordered append.
4412          * The wave IDs generated by ME are also wrong after suspend/resume.
4413          * Those are probably bugs somewhere else in the kernel driver.
4414          *
4415          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4416          * GDS to 0 for this ring (me/pipe).
4417          */
4418         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4419                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4420                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4421                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4422         }
4423
4424         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4425         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4426         amdgpu_ring_write(ring,
4427 #ifdef __BIG_ENDIAN
4428                                 (2 << 0) |
4429 #endif
4430                                 lower_32_bits(ib->gpu_addr));
4431         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4432         amdgpu_ring_write(ring, control);
4433 }
4434
4435 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4436                                      u64 seq, unsigned flags)
4437 {
4438         struct amdgpu_device *adev = ring->adev;
4439         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4440         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4441
4442         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
4443         if (adev->pdev->device == 0x50)
4444                 int_sel = false;
4445
4446         /* RELEASE_MEM - flush caches, send int */
4447         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4448         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4449                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
4450                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
4451                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
4452                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4453                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4454                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4455         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4456                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4457
4458         /*
4459          * the address should be Qword aligned if 64bit write, Dword
4460          * aligned if only send 32bit data low (discard data high)
4461          */
4462         if (write64bit)
4463                 BUG_ON(addr & 0x7);
4464         else
4465                 BUG_ON(addr & 0x3);
4466         amdgpu_ring_write(ring, lower_32_bits(addr));
4467         amdgpu_ring_write(ring, upper_32_bits(addr));
4468         amdgpu_ring_write(ring, lower_32_bits(seq));
4469         amdgpu_ring_write(ring, upper_32_bits(seq));
4470         amdgpu_ring_write(ring, 0);
4471 }
4472
4473 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4474 {
4475         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4476         uint32_t seq = ring->fence_drv.sync_seq;
4477         uint64_t addr = ring->fence_drv.gpu_addr;
4478
4479         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4480                                upper_32_bits(addr), seq, 0xffffffff, 4);
4481 }
4482
4483 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4484                                          unsigned vmid, uint64_t pd_addr)
4485 {
4486         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4487
4488         /* compute doesn't have PFP */
4489         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4490                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4491                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4492                 amdgpu_ring_write(ring, 0x0);
4493         }
4494 }
4495
4496 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4497                                           u64 seq, unsigned int flags)
4498 {
4499         struct amdgpu_device *adev = ring->adev;
4500
4501         /* we only allocate 32bit for each seq wb address */
4502         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4503
4504         /* write fence seq to the "addr" */
4505         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4506         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4507                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4508         amdgpu_ring_write(ring, lower_32_bits(addr));
4509         amdgpu_ring_write(ring, upper_32_bits(addr));
4510         amdgpu_ring_write(ring, lower_32_bits(seq));
4511
4512         if (flags & AMDGPU_FENCE_FLAG_INT) {
4513                 /* set register to trigger INT */
4514                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4515                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4516                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4517                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4518                 amdgpu_ring_write(ring, 0);
4519                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4520         }
4521 }
4522
4523 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
4524 {
4525         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4526         amdgpu_ring_write(ring, 0);
4527 }
4528
4529 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4530 {
4531         uint32_t dw2 = 0;
4532
4533         if (amdgpu_mcbp)
4534                 gfx_v10_0_ring_emit_ce_meta(ring,
4535                                     flags & AMDGPU_IB_PREEMPTED ? true : false);
4536
4537         gfx_v10_0_ring_emit_tmz(ring, true);
4538
4539         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4540         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4541                 /* set load_global_config & load_global_uconfig */
4542                 dw2 |= 0x8001;
4543                 /* set load_cs_sh_regs */
4544                 dw2 |= 0x01000000;
4545                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4546                 dw2 |= 0x10002;
4547
4548                 /* set load_ce_ram if preamble presented */
4549                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4550                         dw2 |= 0x10000000;
4551         } else {
4552                 /* still load_ce_ram if this is the first time preamble presented
4553                  * although there is no context switch happens.
4554                  */
4555                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4556                         dw2 |= 0x10000000;
4557         }
4558
4559         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4560         amdgpu_ring_write(ring, dw2);
4561         amdgpu_ring_write(ring, 0);
4562 }
4563
4564 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4565 {
4566         unsigned ret;
4567
4568         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4569         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4570         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4571         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4572         ret = ring->wptr & ring->buf_mask;
4573         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4574
4575         return ret;
4576 }
4577
4578 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4579 {
4580         unsigned cur;
4581         BUG_ON(offset > ring->buf_mask);
4582         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4583
4584         cur = (ring->wptr - 1) & ring->buf_mask;
4585         if (likely(cur > offset))
4586                 ring->ring[offset] = cur - offset;
4587         else
4588                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
4589 }
4590
4591 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
4592 {
4593         int i, r = 0;
4594         struct amdgpu_device *adev = ring->adev;
4595         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4596         struct amdgpu_ring *kiq_ring = &kiq->ring;
4597
4598         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4599                 return -EINVAL;
4600
4601         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
4602                 return -ENOMEM;
4603
4604         /* assert preemption condition */
4605         amdgpu_ring_set_preempt_cond_exec(ring, false);
4606
4607         /* assert IB preemption, emit the trailing fence */
4608         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4609                                    ring->trail_fence_gpu_addr,
4610                                    ++ring->trail_seq);
4611         amdgpu_ring_commit(kiq_ring);
4612
4613         /* poll the trailing fence */
4614         for (i = 0; i < adev->usec_timeout; i++) {
4615                 if (ring->trail_seq ==
4616                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4617                         break;
4618                 udelay(1);
4619         }
4620
4621         if (i >= adev->usec_timeout) {
4622                 r = -EINVAL;
4623                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4624         }
4625
4626         /* deassert preemption condition */
4627         amdgpu_ring_set_preempt_cond_exec(ring, true);
4628         return r;
4629 }
4630
4631 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
4632 {
4633         struct amdgpu_device *adev = ring->adev;
4634         struct v10_ce_ib_state ce_payload = {0};
4635         uint64_t csa_addr;
4636         int cnt;
4637
4638         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4639         csa_addr = amdgpu_csa_vaddr(ring->adev);
4640
4641         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4642         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4643                                  WRITE_DATA_DST_SEL(8) |
4644                                  WR_CONFIRM) |
4645                                  WRITE_DATA_CACHE_POLICY(0));
4646         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4647                               offsetof(struct v10_gfx_meta_data, ce_payload)));
4648         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4649                               offsetof(struct v10_gfx_meta_data, ce_payload)));
4650
4651         if (resume)
4652                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4653                                            offsetof(struct v10_gfx_meta_data,
4654                                                     ce_payload),
4655                                            sizeof(ce_payload) >> 2);
4656         else
4657                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
4658                                            sizeof(ce_payload) >> 2);
4659 }
4660
4661 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
4662 {
4663         struct amdgpu_device *adev = ring->adev;
4664         struct v10_de_ib_state de_payload = {0};
4665         uint64_t csa_addr, gds_addr;
4666         int cnt;
4667
4668         csa_addr = amdgpu_csa_vaddr(ring->adev);
4669         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
4670                          PAGE_SIZE);
4671         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4672         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4673
4674         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4675         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4676         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4677                                  WRITE_DATA_DST_SEL(8) |
4678                                  WR_CONFIRM) |
4679                                  WRITE_DATA_CACHE_POLICY(0));
4680         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4681                               offsetof(struct v10_gfx_meta_data, de_payload)));
4682         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4683                               offsetof(struct v10_gfx_meta_data, de_payload)));
4684
4685         if (resume)
4686                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4687                                            offsetof(struct v10_gfx_meta_data,
4688                                                     de_payload),
4689                                            sizeof(de_payload) >> 2);
4690         else
4691                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
4692                                            sizeof(de_payload) >> 2);
4693 }
4694
4695 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4696 {
4697         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4698         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4699 }
4700
4701 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4702 {
4703         struct amdgpu_device *adev = ring->adev;
4704
4705         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4706         amdgpu_ring_write(ring, 0 |     /* src: register*/
4707                                 (5 << 8) |      /* dst: memory */
4708                                 (1 << 20));     /* write confirm */
4709         amdgpu_ring_write(ring, reg);
4710         amdgpu_ring_write(ring, 0);
4711         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4712                                 adev->virt.reg_val_offs * 4));
4713         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4714                                 adev->virt.reg_val_offs * 4));
4715 }
4716
4717 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4718                                    uint32_t val)
4719 {
4720         uint32_t cmd = 0;
4721
4722         switch (ring->funcs->type) {
4723         case AMDGPU_RING_TYPE_GFX:
4724                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4725                 break;
4726         case AMDGPU_RING_TYPE_KIQ:
4727                 cmd = (1 << 16); /* no inc addr */
4728                 break;
4729         default:
4730                 cmd = WR_CONFIRM;
4731                 break;
4732         }
4733         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4734         amdgpu_ring_write(ring, cmd);
4735         amdgpu_ring_write(ring, reg);
4736         amdgpu_ring_write(ring, 0);
4737         amdgpu_ring_write(ring, val);
4738 }
4739
4740 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4741                                         uint32_t val, uint32_t mask)
4742 {
4743         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4744 }
4745
4746 static void
4747 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4748                                       uint32_t me, uint32_t pipe,
4749                                       enum amdgpu_interrupt_state state)
4750 {
4751         uint32_t cp_int_cntl, cp_int_cntl_reg;
4752
4753         if (!me) {
4754                 switch (pipe) {
4755                 case 0:
4756                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4757                         break;
4758                 case 1:
4759                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4760                         break;
4761                 default:
4762                         DRM_DEBUG("invalid pipe %d\n", pipe);
4763                         return;
4764                 }
4765         } else {
4766                 DRM_DEBUG("invalid me %d\n", me);
4767                 return;
4768         }
4769
4770         switch (state) {
4771         case AMDGPU_IRQ_STATE_DISABLE:
4772                 cp_int_cntl = RREG32(cp_int_cntl_reg);
4773                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4774                                             TIME_STAMP_INT_ENABLE, 0);
4775                 WREG32(cp_int_cntl_reg, cp_int_cntl);
4776                 break;
4777         case AMDGPU_IRQ_STATE_ENABLE:
4778                 cp_int_cntl = RREG32(cp_int_cntl_reg);
4779                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4780                                             TIME_STAMP_INT_ENABLE, 1);
4781                 WREG32(cp_int_cntl_reg, cp_int_cntl);
4782                 break;
4783         default:
4784                 break;
4785         }
4786 }
4787
4788 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4789                                                      int me, int pipe,
4790                                                      enum amdgpu_interrupt_state state)
4791 {
4792         u32 mec_int_cntl, mec_int_cntl_reg;
4793
4794         /*
4795          * amdgpu controls only the first MEC. That's why this function only
4796          * handles the setting of interrupts for this specific MEC. All other
4797          * pipes' interrupts are set by amdkfd.
4798          */
4799
4800         if (me == 1) {
4801                 switch (pipe) {
4802                 case 0:
4803                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4804                         break;
4805                 case 1:
4806                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4807                         break;
4808                 case 2:
4809                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4810                         break;
4811                 case 3:
4812                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4813                         break;
4814                 default:
4815                         DRM_DEBUG("invalid pipe %d\n", pipe);
4816                         return;
4817                 }
4818         } else {
4819                 DRM_DEBUG("invalid me %d\n", me);
4820                 return;
4821         }
4822
4823         switch (state) {
4824         case AMDGPU_IRQ_STATE_DISABLE:
4825                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4826                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4827                                              TIME_STAMP_INT_ENABLE, 0);
4828                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4829                 break;
4830         case AMDGPU_IRQ_STATE_ENABLE:
4831                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4832                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4833                                              TIME_STAMP_INT_ENABLE, 1);
4834                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4835                 break;
4836         default:
4837                 break;
4838         }
4839 }
4840
4841 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4842                                             struct amdgpu_irq_src *src,
4843                                             unsigned type,
4844                                             enum amdgpu_interrupt_state state)
4845 {
4846         switch (type) {
4847         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4848                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4849                 break;
4850         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4851                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4852                 break;
4853         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4854                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4855                 break;
4856         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4857                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4858                 break;
4859         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4860                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4861                 break;
4862         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4863                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4864                 break;
4865         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4866                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4867                 break;
4868         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4869                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4870                 break;
4871         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4872                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4873                 break;
4874         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4875                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4876                 break;
4877         default:
4878                 break;
4879         }
4880         return 0;
4881 }
4882
4883 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
4884                              struct amdgpu_irq_src *source,
4885                              struct amdgpu_iv_entry *entry)
4886 {
4887         int i;
4888         u8 me_id, pipe_id, queue_id;
4889         struct amdgpu_ring *ring;
4890
4891         DRM_DEBUG("IH: CP EOP\n");
4892         me_id = (entry->ring_id & 0x0c) >> 2;
4893         pipe_id = (entry->ring_id & 0x03) >> 0;
4894         queue_id = (entry->ring_id & 0x70) >> 4;
4895
4896         switch (me_id) {
4897         case 0:
4898                 if (pipe_id == 0)
4899                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4900                 else
4901                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4902                 break;
4903         case 1:
4904         case 2:
4905                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4906                         ring = &adev->gfx.compute_ring[i];
4907                         /* Per-queue interrupt is supported for MEC starting from VI.
4908                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4909                           */
4910                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4911                                 amdgpu_fence_process(ring);
4912                 }
4913                 break;
4914         }
4915         return 0;
4916 }
4917
4918 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4919                                               struct amdgpu_irq_src *source,
4920                                               unsigned type,
4921                                               enum amdgpu_interrupt_state state)
4922 {
4923         switch (state) {
4924         case AMDGPU_IRQ_STATE_DISABLE:
4925         case AMDGPU_IRQ_STATE_ENABLE:
4926                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4927                                PRIV_REG_INT_ENABLE,
4928                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4929                 break;
4930         default:
4931                 break;
4932         }
4933
4934         return 0;
4935 }
4936
4937 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4938                                                struct amdgpu_irq_src *source,
4939                                                unsigned type,
4940                                                enum amdgpu_interrupt_state state)
4941 {
4942         switch (state) {
4943         case AMDGPU_IRQ_STATE_DISABLE:
4944         case AMDGPU_IRQ_STATE_ENABLE:
4945                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4946                                PRIV_INSTR_INT_ENABLE,
4947                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4948         default:
4949                 break;
4950         }
4951
4952         return 0;
4953 }
4954
4955 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
4956                                         struct amdgpu_iv_entry *entry)
4957 {
4958         u8 me_id, pipe_id, queue_id;
4959         struct amdgpu_ring *ring;
4960         int i;
4961
4962         me_id = (entry->ring_id & 0x0c) >> 2;
4963         pipe_id = (entry->ring_id & 0x03) >> 0;
4964         queue_id = (entry->ring_id & 0x70) >> 4;
4965
4966         switch (me_id) {
4967         case 0:
4968                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4969                         ring = &adev->gfx.gfx_ring[i];
4970                         /* we only enabled 1 gfx queue per pipe for now */
4971                         if (ring->me == me_id && ring->pipe == pipe_id)
4972                                 drm_sched_fault(&ring->sched);
4973                 }
4974                 break;
4975         case 1:
4976         case 2:
4977                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4978                         ring = &adev->gfx.compute_ring[i];
4979                         if (ring->me == me_id && ring->pipe == pipe_id &&
4980                             ring->queue == queue_id)
4981                                 drm_sched_fault(&ring->sched);
4982                 }
4983                 break;
4984         default:
4985                 BUG();
4986         }
4987 }
4988
4989 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
4990                                   struct amdgpu_irq_src *source,
4991                                   struct amdgpu_iv_entry *entry)
4992 {
4993         DRM_ERROR("Illegal register access in command stream\n");
4994         gfx_v10_0_handle_priv_fault(adev, entry);
4995         return 0;
4996 }
4997
4998 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
4999                                    struct amdgpu_irq_src *source,
5000                                    struct amdgpu_iv_entry *entry)
5001 {
5002         DRM_ERROR("Illegal instruction in command stream\n");
5003         gfx_v10_0_handle_priv_fault(adev, entry);
5004         return 0;
5005 }
5006
5007 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5008                                              struct amdgpu_irq_src *src,
5009                                              unsigned int type,
5010                                              enum amdgpu_interrupt_state state)
5011 {
5012         uint32_t tmp, target;
5013         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5014
5015         if (ring->me == 1)
5016                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5017         else
5018                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5019         target += ring->pipe;
5020
5021         switch (type) {
5022         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5023                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5024                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5025                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5026                                             GENERIC2_INT_ENABLE, 0);
5027                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5028
5029                         tmp = RREG32(target);
5030                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5031                                             GENERIC2_INT_ENABLE, 0);
5032                         WREG32(target, tmp);
5033                 } else {
5034                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5035                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5036                                             GENERIC2_INT_ENABLE, 1);
5037                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5038
5039                         tmp = RREG32(target);
5040                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5041                                             GENERIC2_INT_ENABLE, 1);
5042                         WREG32(target, tmp);
5043                 }
5044                 break;
5045         default:
5046                 BUG(); /* kiq only support GENERIC2_INT now */
5047                 break;
5048         }
5049         return 0;
5050 }
5051
5052 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
5053                              struct amdgpu_irq_src *source,
5054                              struct amdgpu_iv_entry *entry)
5055 {
5056         u8 me_id, pipe_id, queue_id;
5057         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5058
5059         me_id = (entry->ring_id & 0x0c) >> 2;
5060         pipe_id = (entry->ring_id & 0x03) >> 0;
5061         queue_id = (entry->ring_id & 0x70) >> 4;
5062         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
5063                    me_id, pipe_id, queue_id);
5064
5065         amdgpu_fence_process(ring);
5066         return 0;
5067 }
5068
5069 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
5070         .name = "gfx_v10_0",
5071         .early_init = gfx_v10_0_early_init,
5072         .late_init = gfx_v10_0_late_init,
5073         .sw_init = gfx_v10_0_sw_init,
5074         .sw_fini = gfx_v10_0_sw_fini,
5075         .hw_init = gfx_v10_0_hw_init,
5076         .hw_fini = gfx_v10_0_hw_fini,
5077         .suspend = gfx_v10_0_suspend,
5078         .resume = gfx_v10_0_resume,
5079         .is_idle = gfx_v10_0_is_idle,
5080         .wait_for_idle = gfx_v10_0_wait_for_idle,
5081         .soft_reset = gfx_v10_0_soft_reset,
5082         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
5083         .set_powergating_state = gfx_v10_0_set_powergating_state,
5084         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
5085 };
5086
5087 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
5088         .type = AMDGPU_RING_TYPE_GFX,
5089         .align_mask = 0xff,
5090         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5091         .support_64bit_ptrs = true,
5092         .vmhub = AMDGPU_GFXHUB_0,
5093         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
5094         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
5095         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5096         .emit_frame_size = /* totally 242 maximum if 16 IBs */
5097                 5 + /* COND_EXEC */
5098                 7 + /* PIPELINE_SYNC */
5099                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5100                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5101                 2 + /* VM_FLUSH */
5102                 8 + /* FENCE for VM_FLUSH */
5103                 20 + /* GDS switch */
5104                 4 + /* double SWITCH_BUFFER,
5105                      * the first COND_EXEC jump to the place
5106                      * just prior to this double SWITCH_BUFFER
5107                      */
5108                 5 + /* COND_EXEC */
5109                 7 + /* HDP_flush */
5110                 4 + /* VGT_flush */
5111                 14 + /* CE_META */
5112                 31 + /* DE_META */
5113                 3 + /* CNTX_CTRL */
5114                 5 + /* HDP_INVL */
5115                 8 + 8 + /* FENCE x2 */
5116                 2, /* SWITCH_BUFFER */
5117         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
5118         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
5119         .emit_fence = gfx_v10_0_ring_emit_fence,
5120         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5121         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5122         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5123         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5124         .test_ring = gfx_v10_0_ring_test_ring,
5125         .test_ib = gfx_v10_0_ring_test_ib,
5126         .insert_nop = amdgpu_ring_insert_nop,
5127         .pad_ib = amdgpu_ring_generic_pad_ib,
5128         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
5129         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
5130         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
5131         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
5132         .preempt_ib = gfx_v10_0_ring_preempt_ib,
5133         .emit_tmz = gfx_v10_0_ring_emit_tmz,
5134         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5135         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5136 };
5137
5138 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
5139         .type = AMDGPU_RING_TYPE_COMPUTE,
5140         .align_mask = 0xff,
5141         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5142         .support_64bit_ptrs = true,
5143         .vmhub = AMDGPU_GFXHUB_0,
5144         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5145         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5146         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5147         .emit_frame_size =
5148                 20 + /* gfx_v10_0_ring_emit_gds_switch */
5149                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5150                 5 + /* hdp invalidate */
5151                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5152                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5153                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5154                 2 + /* gfx_v10_0_ring_emit_vm_flush */
5155                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
5156         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5157         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5158         .emit_fence = gfx_v10_0_ring_emit_fence,
5159         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5160         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5161         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5162         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5163         .test_ring = gfx_v10_0_ring_test_ring,
5164         .test_ib = gfx_v10_0_ring_test_ib,
5165         .insert_nop = amdgpu_ring_insert_nop,
5166         .pad_ib = amdgpu_ring_generic_pad_ib,
5167         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5168         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5169 };
5170
5171 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
5172         .type = AMDGPU_RING_TYPE_KIQ,
5173         .align_mask = 0xff,
5174         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5175         .support_64bit_ptrs = true,
5176         .vmhub = AMDGPU_GFXHUB_0,
5177         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5178         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5179         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5180         .emit_frame_size =
5181                 20 + /* gfx_v10_0_ring_emit_gds_switch */
5182                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5183                 5 + /*hdp invalidate */
5184                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5185                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5186                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5187                 2 + /* gfx_v10_0_ring_emit_vm_flush */
5188                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5189         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5190         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5191         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
5192         .test_ring = gfx_v10_0_ring_test_ring,
5193         .test_ib = gfx_v10_0_ring_test_ib,
5194         .insert_nop = amdgpu_ring_insert_nop,
5195         .pad_ib = amdgpu_ring_generic_pad_ib,
5196         .emit_rreg = gfx_v10_0_ring_emit_rreg,
5197         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5198         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5199 };
5200
5201 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
5202 {
5203         int i;
5204
5205         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
5206
5207         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5208                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
5209
5210         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5211                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
5212 }
5213
5214 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
5215         .set = gfx_v10_0_set_eop_interrupt_state,
5216         .process = gfx_v10_0_eop_irq,
5217 };
5218
5219 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
5220         .set = gfx_v10_0_set_priv_reg_fault_state,
5221         .process = gfx_v10_0_priv_reg_irq,
5222 };
5223
5224 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
5225         .set = gfx_v10_0_set_priv_inst_fault_state,
5226         .process = gfx_v10_0_priv_inst_irq,
5227 };
5228
5229 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
5230         .set = gfx_v10_0_kiq_set_interrupt_state,
5231         .process = gfx_v10_0_kiq_irq,
5232 };
5233
5234 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
5235 {
5236         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5237         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
5238
5239         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
5240         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
5241
5242         adev->gfx.priv_reg_irq.num_types = 1;
5243         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
5244
5245         adev->gfx.priv_inst_irq.num_types = 1;
5246         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
5247 }
5248
5249 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
5250 {
5251         switch (adev->asic_type) {
5252         case CHIP_NAVI10:
5253         case CHIP_NAVI14:
5254         case CHIP_NAVI12:
5255                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
5256                 break;
5257         default:
5258                 break;
5259         }
5260 }
5261
5262 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
5263 {
5264         /* init asic gds info */
5265         switch (adev->asic_type) {
5266         case CHIP_NAVI10:
5267         default:
5268                 adev->gds.gds_size = 0x10000;
5269                 adev->gds.gds_compute_max_wave_id = 0x4ff;
5270                 break;
5271         }
5272
5273         adev->gds.gws_size = 64;
5274         adev->gds.oa_size = 16;
5275 }
5276
5277 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5278                                                           u32 bitmap)
5279 {
5280         u32 data;
5281
5282         if (!bitmap)
5283                 return;
5284
5285         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5286         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5287
5288         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5289 }
5290
5291 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5292 {
5293         u32 data, wgp_bitmask;
5294         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5295         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
5296
5297         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5298         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5299
5300         wgp_bitmask =
5301                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5302
5303         return (~data) & wgp_bitmask;
5304 }
5305
5306 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5307 {
5308         u32 wgp_idx, wgp_active_bitmap;
5309         u32 cu_bitmap_per_wgp, cu_active_bitmap;
5310
5311         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5312         cu_active_bitmap = 0;
5313
5314         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5315                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5316                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5317                 if (wgp_active_bitmap & (1 << wgp_idx))
5318                         cu_active_bitmap |= cu_bitmap_per_wgp;
5319         }
5320
5321         return cu_active_bitmap;
5322 }
5323
5324 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
5325                                  struct amdgpu_cu_info *cu_info)
5326 {
5327         int i, j, k, counter, active_cu_number = 0;
5328         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5329         unsigned disable_masks[4 * 2];
5330
5331         if (!adev || !cu_info)
5332                 return -EINVAL;
5333
5334         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5335
5336         mutex_lock(&adev->grbm_idx_mutex);
5337         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5338                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5339                         mask = 1;
5340                         ao_bitmap = 0;
5341                         counter = 0;
5342                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5343                         if (i < 4 && j < 2)
5344                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
5345                                         adev, disable_masks[i * 2 + j]);
5346                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
5347                         cu_info->bitmap[i][j] = bitmap;
5348
5349                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5350                                 if (bitmap & mask) {
5351                                         if (counter < adev->gfx.config.max_cu_per_sh)
5352                                                 ao_bitmap |= mask;
5353                                         counter++;
5354                                 }
5355                                 mask <<= 1;
5356                         }
5357                         active_cu_number += counter;
5358                         if (i < 2 && j < 2)
5359                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5360                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5361                 }
5362         }
5363         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5364         mutex_unlock(&adev->grbm_idx_mutex);
5365
5366         cu_info->number = active_cu_number;
5367         cu_info->ao_cu_mask = ao_cu_mask;
5368         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5369
5370         return 0;
5371 }
5372
5373 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
5374 {
5375         .type = AMD_IP_BLOCK_TYPE_GFX,
5376         .major = 10,
5377         .minor = 0,
5378         .rev = 0,
5379         .funcs = &gfx_v10_0_ip_funcs,
5380 };