drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include "drmP.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "vega10/soc15ip.h"
  38 #include "vega10/UVD/uvd_7_0_offset.h"
  39 #include "vega10/GC/gc_9_0_offset.h"
  40 #include "vega10/GC/gc_9_0_sh_mask.h"
  41 #include "vega10/SDMA0/sdma0_4_0_offset.h"
  42 #include "vega10/SDMA1/sdma1_4_0_offset.h"
  43 #include "vega10/HDP/hdp_4_0_offset.h"
  44 #include "vega10/HDP/hdp_4_0_sh_mask.h"
  45 #include "vega10/MP/mp_9_0_offset.h"
  46 #include "vega10/MP/mp_9_0_sh_mask.h"
  47 #include "vega10/SMUIO/smuio_9_0_offset.h"
  48 #include "vega10/SMUIO/smuio_9_0_sh_mask.h"
  49
  50 #include "soc15.h"
  51 #include "soc15_common.h"
  52 #include "gfx_v9_0.h"
  53 #include "gmc_v9_0.h"
  54 #include "gfxhub_v1_0.h"
  55 #include "mmhub_v1_0.h"
  56 #include "vega10_ih.h"
  57 #include "sdma_v4_0.h"
  58 #include "uvd_v7_0.h"
  59 #include "vce_v4_0.h"
  60 #include "vcn_v1_0.h"
  61 #include "amdgpu_powerplay.h"
  62 #include "dce_virtual.h"
  63 #include "mxgpu_ai.h"
  64
  65 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
  66
  67 #define mmFabricConfigAccessControl                                                                    0x0410
  68 #define mmFabricConfigAccessControl_BASE_IDX                                                           0
  69 #define mmFabricConfigAccessControl_DEFAULT                                      0x00000000
  70 //FabricConfigAccessControl
  71 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                                     0x0
  72 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                                0x1
  73 #define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                        0x10
  74 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                       0x00000001L
  75 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                                  0x00000002L
  76 #define FabricConfigAccessControl__CfgRegInstID_MASK                                                          0x00FF0000L
  77
  78
  79 #define mmDF_PIE_AON0_DfGlobalClkGater                                                                 0x00fc
  80 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                        0
  81 //DF_PIE_AON0_DfGlobalClkGater
  82 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                         0x0
  83 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                           0x0000000FL
  84
  85 enum {
  86         DF_MGCG_DISABLE = 0,
  87         DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
  88         DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
  89         DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
  90         DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
  91         DF_MGCG_ENABLE_63_CYCLE_DELAY =15
  92 };
  93
  94 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  95 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  96 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  97 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  98
  99 /*
 100  * Indirect registers accessor
 101  */
 102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 103 {
 104         unsigned long flags, address, data;
 105         u32 r;
 106         struct nbio_pcie_index_data *nbio_pcie_id;
 107
 108         if (adev->flags & AMD_IS_APU)
 109                 nbio_pcie_id = &nbio_v7_0_pcie_index_data;
 110         else
 111                 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
 112
 113         address = nbio_pcie_id->index_offset;
 114         data = nbio_pcie_id->data_offset;
 115
 116         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 117         WREG32(address, reg);
 118         (void)RREG32(address);
 119         r = RREG32(data);
 120         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 121         return r;
 122 }
 123
 124 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 125 {
 126         unsigned long flags, address, data;
 127         struct nbio_pcie_index_data *nbio_pcie_id;
 128
 129         if (adev->flags & AMD_IS_APU)
 130                 nbio_pcie_id = &nbio_v7_0_pcie_index_data;
 131         else
 132                 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
 133
 134         address = nbio_pcie_id->index_offset;
 135         data = nbio_pcie_id->data_offset;
 136
 137         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 138         WREG32(address, reg);
 139         (void)RREG32(address);
 140         WREG32(data, v);
 141         (void)RREG32(data);
 142         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 143 }
 144
 145 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 146 {
 147         unsigned long flags, address, data;
 148         u32 r;
 149
 150         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 151         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 152
 153         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 154         WREG32(address, ((reg) & 0x1ff));
 155         r = RREG32(data);
 156         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 157         return r;
 158 }
 159
 160 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 161 {
 162         unsigned long flags, address, data;
 163
 164         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 165         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 166
 167         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 168         WREG32(address, ((reg) & 0x1ff));
 169         WREG32(data, (v));
 170         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 171 }
 172
 173 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 174 {
 175         unsigned long flags, address, data;
 176         u32 r;
 177
 178         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 179         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 180
 181         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 182         WREG32(address, (reg));
 183         r = RREG32(data);
 184         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 185         return r;
 186 }
 187
 188 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 189 {
 190         unsigned long flags, address, data;
 191
 192         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 193         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 194
 195         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 196         WREG32(address, (reg));
 197         WREG32(data, (v));
 198         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 199 }
 200
 201 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 202 {
 203         if (adev->flags & AMD_IS_APU)
 204                 return nbio_v7_0_get_memsize(adev);
 205         else
 206                 return nbio_v6_1_get_memsize(adev);
 207 }
 208
 209 static const u32 vega10_golden_init[] =
 210 {
 211 };
 212
 213 static const u32 raven_golden_init[] =
 214 {
 215 };
 216
 217 static void soc15_init_golden_registers(struct amdgpu_device *adev)
 218 {
 219         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 220         mutex_lock(&adev->grbm_idx_mutex);
 221
 222         switch (adev->asic_type) {
 223         case CHIP_VEGA10:
 224                 amdgpu_program_register_sequence(adev,
 225                                                  vega10_golden_init,
 226                                                  (const u32)ARRAY_SIZE(vega10_golden_init));
 227                 break;
 228         case CHIP_RAVEN:
 229                 amdgpu_program_register_sequence(adev,
 230                                                  raven_golden_init,
 231                                                  (const u32)ARRAY_SIZE(raven_golden_init));
 232                 break;
 233         default:
 234                 break;
 235         }
 236         mutex_unlock(&adev->grbm_idx_mutex);
 237 }
 238 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 239 {
 240         if (adev->asic_type == CHIP_VEGA10)
 241                 return adev->clock.spll.reference_freq/4;
 242         else
 243                 return adev->clock.spll.reference_freq;
 244 }
 245
 246
 247 void soc15_grbm_select(struct amdgpu_device *adev,
 248                      u32 me, u32 pipe, u32 queue, u32 vmid)
 249 {
 250         u32 grbm_gfx_cntl = 0;
 251         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 252         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 253         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 254         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 255
 256         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 257 }
 258
 259 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 260 {
 261         /* todo */
 262 }
 263
 264 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 265 {
 266         /* todo */
 267         return false;
 268 }
 269
 270 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 271                                      u8 *bios, u32 length_bytes)
 272 {
 273         u32 *dw_ptr;
 274         u32 i, length_dw;
 275
 276         if (bios == NULL)
 277                 return false;
 278         if (length_bytes == 0)
 279                 return false;
 280         /* APU vbios image is part of sbios image */
 281         if (adev->flags & AMD_IS_APU)
 282                 return false;
 283
 284         dw_ptr = (u32 *)bios;
 285         length_dw = ALIGN(length_bytes, 4) / 4;
 286
 287         /* set rom index to 0 */
 288         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 289         /* read out the rom data */
 290         for (i = 0; i < length_dw; i++)
 291                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 292
 293         return true;
 294 }
 295
 296 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
 297         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)},
 298         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)},
 299         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)},
 300         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)},
 301         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)},
 302         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)},
 303         { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)},
 304         { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)},
 305         { SOC15_REG_OFFSET(GC, 0, mmCP_STAT)},
 306         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)},
 307         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)},
 308         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)},
 309         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)},
 310         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)},
 311         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)},
 312         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)},
 313         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)},
 314         { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)},
 315 };
 316
 317 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 318                                          u32 sh_num, u32 reg_offset)
 319 {
 320         uint32_t val;
 321
 322         mutex_lock(&adev->grbm_idx_mutex);
 323         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 324                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 325
 326         val = RREG32(reg_offset);
 327
 328         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 329                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 330         mutex_unlock(&adev->grbm_idx_mutex);
 331         return val;
 332 }
 333
 334 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 335                                          bool indexed, u32 se_num,
 336                                          u32 sh_num, u32 reg_offset)
 337 {
 338         if (indexed) {
 339                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 340         } else {
 341                 switch (reg_offset) {
 342                 case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
 343                         return adev->gfx.config.gb_addr_config;
 344                 default:
 345                         return RREG32(reg_offset);
 346                 }
 347         }
 348 }
 349
 350 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 351                             u32 sh_num, u32 reg_offset, u32 *value)
 352 {
 353         uint32_t i;
 354
 355         *value = 0;
 356         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 357                 if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
 358                         continue;
 359
 360                 *value = soc15_get_register_value(adev,
 361                                                   soc15_allowed_read_registers[i].grbm_indexed,
 362                                                   se_num, sh_num, reg_offset);
 363                 return 0;
 364         }
 365         return -EINVAL;
 366 }
 367
 368 static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
 369 {
 370         u32 i;
 371
 372         dev_info(adev->dev, "GPU pci config reset\n");
 373
 374         /* disable BM */
 375         pci_clear_master(adev->pdev);
 376         /* reset */
 377         amdgpu_pci_config_reset(adev);
 378
 379         udelay(100);
 380
 381         /* wait for asic to come out of reset */
 382         for (i = 0; i < adev->usec_timeout; i++) {
 383                 u32 memsize = (adev->flags & AMD_IS_APU) ?
 384                         nbio_v7_0_get_memsize(adev) :
 385                         nbio_v6_1_get_memsize(adev);
 386                 if (memsize != 0xffffffff)
 387                         break;
 388                 udelay(1);
 389         }
 390
 391 }
 392
 393 static int soc15_asic_reset(struct amdgpu_device *adev)
 394 {
 395         amdgpu_atomfirmware_scratch_regs_engine_hung(adev, true);
 396
 397         soc15_gpu_pci_config_reset(adev);
 398
 399         amdgpu_atomfirmware_scratch_regs_engine_hung(adev, false);
 400
 401         return 0;
 402 }
 403
 404 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 405                         u32 cntl_reg, u32 status_reg)
 406 {
 407         return 0;
 408 }*/
 409
 410 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 411 {
 412         /*int r;
 413
 414         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 415         if (r)
 416                 return r;
 417
 418         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 419         */
 420         return 0;
 421 }
 422
 423 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 424 {
 425         /* todo */
 426
 427         return 0;
 428 }
 429
 430 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 431 {
 432         if (pci_is_root_bus(adev->pdev->bus))
 433                 return;
 434
 435         if (amdgpu_pcie_gen2 == 0)
 436                 return;
 437
 438         if (adev->flags & AMD_IS_APU)
 439                 return;
 440
 441         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 442                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 443                 return;
 444
 445         /* todo */
 446 }
 447
 448 static void soc15_program_aspm(struct amdgpu_device *adev)
 449 {
 450
 451         if (amdgpu_aspm == 0)
 452                 return;
 453
 454         /* todo */
 455 }
 456
 457 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 458                                         bool enable)
 459 {
 460         if (adev->flags & AMD_IS_APU) {
 461                 nbio_v7_0_enable_doorbell_aperture(adev, enable);
 462         } else {
 463                 nbio_v6_1_enable_doorbell_aperture(adev, enable);
 464                 nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
 465         }
 466 }
 467
 468 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 469 {
 470         .type = AMD_IP_BLOCK_TYPE_COMMON,
 471         .major = 2,
 472         .minor = 0,
 473         .rev = 0,
 474         .funcs = &soc15_common_ip_funcs,
 475 };
 476
 477 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 478 {
 479         nbio_v6_1_detect_hw_virt(adev);
 480
 481         if (amdgpu_sriov_vf(adev))
 482                 adev->virt.ops = &xgpu_ai_virt_ops;
 483
 484         switch (adev->asic_type) {
 485         case CHIP_VEGA10:
 486                 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
 487                 amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
 488                 amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
 489                 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
 490                 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
 491                 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
 492                         amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
 493                 if (!amdgpu_sriov_vf(adev))
 494                         amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 495                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 496                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
 497                 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
 498                 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
 499                 amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
 500                 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
 501                 break;
 502         case CHIP_RAVEN:
 503                 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
 504                 amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
 505                 amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
 506                 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
 507                 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
 508                 amdgpu_ip_block_add(adev, &psp_v10_0_ip_block);
 509                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 510                 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
 511                 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
 512                 amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block);
 513                 break;
 514         default:
 515                 return -EINVAL;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 522 {
 523         if (adev->flags & AMD_IS_APU)
 524                 return nbio_v7_0_get_rev_id(adev);
 525         else
 526                 return nbio_v6_1_get_rev_id(adev);
 527 }
 528
 529
 530 int gmc_v9_0_mc_wait_for_idle(struct amdgpu_device *adev)
 531 {
 532         /* to be implemented in MC IP*/
 533         return 0;
 534 }
 535
 536 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 537 {
 538         .read_disabled_bios = &soc15_read_disabled_bios,
 539         .read_bios_from_rom = &soc15_read_bios_from_rom,
 540         .read_register = &soc15_read_register,
 541         .reset = &soc15_asic_reset,
 542         .set_vga_state = &soc15_vga_set_state,
 543         .get_xclk = &soc15_get_xclk,
 544         .set_uvd_clocks = &soc15_set_uvd_clocks,
 545         .set_vce_clocks = &soc15_set_vce_clocks,
 546         .get_config_memsize = &soc15_get_config_memsize,
 547 };
 548
 549 static int soc15_common_early_init(void *handle)
 550 {
 551         bool psp_enabled = false;
 552         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 553
 554         adev->smc_rreg = NULL;
 555         adev->smc_wreg = NULL;
 556         adev->pcie_rreg = &soc15_pcie_rreg;
 557         adev->pcie_wreg = &soc15_pcie_wreg;
 558         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 559         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 560         adev->didt_rreg = &soc15_didt_rreg;
 561         adev->didt_wreg = &soc15_didt_wreg;
 562
 563         adev->asic_funcs = &soc15_asic_funcs;
 564
 565         if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
 566                 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
 567                 psp_enabled = true;
 568
 569         /*
 570          * nbio need be used for both sdma and gfx9, but only
 571          * initializes once
 572          */
 573         switch(adev->asic_type) {
 574         case CHIP_VEGA10:
 575                 nbio_v6_1_init(adev);
 576                 break;
 577         case CHIP_RAVEN:
 578                 nbio_v7_0_init(adev);
 579                 break;
 580         default:
 581                 return -EINVAL;
 582         }
 583
 584         adev->rev_id = soc15_get_rev_id(adev);
 585         adev->external_rev_id = 0xFF;
 586         switch (adev->asic_type) {
 587         case CHIP_VEGA10:
 588                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 589                         AMD_CG_SUPPORT_GFX_MGLS |
 590                         AMD_CG_SUPPORT_GFX_RLC_LS |
 591                         AMD_CG_SUPPORT_GFX_CP_LS |
 592                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 593                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 594                         AMD_CG_SUPPORT_GFX_CGCG |
 595                         AMD_CG_SUPPORT_GFX_CGLS |
 596                         AMD_CG_SUPPORT_BIF_MGCG |
 597                         AMD_CG_SUPPORT_BIF_LS |
 598                         AMD_CG_SUPPORT_HDP_LS |
 599                         AMD_CG_SUPPORT_DRM_MGCG |
 600                         AMD_CG_SUPPORT_DRM_LS |
 601                         AMD_CG_SUPPORT_ROM_MGCG |
 602                         AMD_CG_SUPPORT_DF_MGCG |
 603                         AMD_CG_SUPPORT_SDMA_MGCG |
 604                         AMD_CG_SUPPORT_SDMA_LS |
 605                         AMD_CG_SUPPORT_MC_MGCG |
 606                         AMD_CG_SUPPORT_MC_LS;
 607                 adev->pg_flags = 0;
 608                 adev->external_rev_id = 0x1;
 609                 break;
 610         case CHIP_RAVEN:
 611                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 612                         AMD_CG_SUPPORT_GFX_MGLS |
 613                         AMD_CG_SUPPORT_GFX_RLC_LS |
 614                         AMD_CG_SUPPORT_GFX_CP_LS |
 615                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 616                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 617                         AMD_CG_SUPPORT_GFX_CGCG |
 618                         AMD_CG_SUPPORT_GFX_CGLS |
 619                         AMD_CG_SUPPORT_BIF_MGCG |
 620                         AMD_CG_SUPPORT_BIF_LS |
 621                         AMD_CG_SUPPORT_HDP_MGCG |
 622                         AMD_CG_SUPPORT_HDP_LS |
 623                         AMD_CG_SUPPORT_DRM_MGCG |
 624                         AMD_CG_SUPPORT_DRM_LS |
 625                         AMD_CG_SUPPORT_ROM_MGCG |
 626                         AMD_CG_SUPPORT_MC_MGCG |
 627                         AMD_CG_SUPPORT_MC_LS |
 628                         AMD_CG_SUPPORT_SDMA_MGCG |
 629                         AMD_CG_SUPPORT_SDMA_LS;
 630                 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
 631                 adev->external_rev_id = 0x1;
 632                 break;
 633         default:
 634                 /* FIXME: not supported yet */
 635                 return -EINVAL;
 636         }
 637
 638         if (amdgpu_sriov_vf(adev)) {
 639                 amdgpu_virt_init_setting(adev);
 640                 xgpu_ai_mailbox_set_irq_funcs(adev);
 641         }
 642
 643         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 644
 645         amdgpu_get_pcie_info(adev);
 646
 647         return 0;
 648 }
 649
 650 static int soc15_common_late_init(void *handle)
 651 {
 652         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 653
 654         if (amdgpu_sriov_vf(adev))
 655                 xgpu_ai_mailbox_get_irq(adev);
 656
 657         return 0;
 658 }
 659
 660 static int soc15_common_sw_init(void *handle)
 661 {
 662         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 663
 664         if (amdgpu_sriov_vf(adev))
 665                 xgpu_ai_mailbox_add_irq_id(adev);
 666
 667         return 0;
 668 }
 669
 670 static int soc15_common_sw_fini(void *handle)
 671 {
 672         return 0;
 673 }
 674
 675 static int soc15_common_hw_init(void *handle)
 676 {
 677         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 678
 679         /* move the golden regs per IP block */
 680         soc15_init_golden_registers(adev);
 681         /* enable pcie gen2/3 link */
 682         soc15_pcie_gen3_enable(adev);
 683         /* enable aspm */
 684         soc15_program_aspm(adev);
 685         /* enable the doorbell aperture */
 686         soc15_enable_doorbell_aperture(adev, true);
 687
 688         return 0;
 689 }
 690
 691 static int soc15_common_hw_fini(void *handle)
 692 {
 693         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 694
 695         /* disable the doorbell aperture */
 696         soc15_enable_doorbell_aperture(adev, false);
 697         if (amdgpu_sriov_vf(adev))
 698                 xgpu_ai_mailbox_put_irq(adev);
 699
 700         return 0;
 701 }
 702
 703 static int soc15_common_suspend(void *handle)
 704 {
 705         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 706
 707         return soc15_common_hw_fini(adev);
 708 }
 709
 710 static int soc15_common_resume(void *handle)
 711 {
 712         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 713
 714         return soc15_common_hw_init(adev);
 715 }
 716
 717 static bool soc15_common_is_idle(void *handle)
 718 {
 719         return true;
 720 }
 721
 722 static int soc15_common_wait_for_idle(void *handle)
 723 {
 724         return 0;
 725 }
 726
 727 static int soc15_common_soft_reset(void *handle)
 728 {
 729         return 0;
 730 }
 731
 732 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
 733 {
 734         uint32_t def, data;
 735
 736         def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 737
 738         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 739                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 740         else
 741                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 742
 743         if (def != data)
 744                 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 745 }
 746
 747 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
 748 {
 749         uint32_t def, data;
 750
 751         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 752
 753         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
 754                 data &= ~(0x01000000 |
 755                           0x02000000 |
 756                           0x04000000 |
 757                           0x08000000 |
 758                           0x10000000 |
 759                           0x20000000 |
 760                           0x40000000 |
 761                           0x80000000);
 762         else
 763                 data |= (0x01000000 |
 764                          0x02000000 |
 765                          0x04000000 |
 766                          0x08000000 |
 767                          0x10000000 |
 768                          0x20000000 |
 769                          0x40000000 |
 770                          0x80000000);
 771
 772         if (def != data)
 773                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
 774 }
 775
 776 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
 777 {
 778         uint32_t def, data;
 779
 780         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 781
 782         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
 783                 data |= 1;
 784         else
 785                 data &= ~1;
 786
 787         if (def != data)
 788                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
 789 }
 790
 791 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 792                                                        bool enable)
 793 {
 794         uint32_t def, data;
 795
 796         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 797
 798         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
 799                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 800                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
 801         else
 802                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 803                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
 804
 805         if (def != data)
 806                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 807 }
 808
 809 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
 810                                                        bool enable)
 811 {
 812         uint32_t data;
 813
 814         /* Put DF on broadcast mode */
 815         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
 816         data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
 817         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
 818
 819         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
 820                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 821                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 822                 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
 823                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 824         } else {
 825                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 826                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 827                 data |= DF_MGCG_DISABLE;
 828                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 829         }
 830
 831         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
 832                mmFabricConfigAccessControl_DEFAULT);
 833 }
 834
 835 static int soc15_common_set_clockgating_state(void *handle,
 836                                             enum amd_clockgating_state state)
 837 {
 838         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 839
 840         if (amdgpu_sriov_vf(adev))
 841                 return 0;
 842
 843         switch (adev->asic_type) {
 844         case CHIP_VEGA10:
 845                 nbio_v6_1_update_medium_grain_clock_gating(adev,
 846                                 state == AMD_CG_STATE_GATE ? true : false);
 847                 nbio_v6_1_update_medium_grain_light_sleep(adev,
 848                                 state == AMD_CG_STATE_GATE ? true : false);
 849                 soc15_update_hdp_light_sleep(adev,
 850                                 state == AMD_CG_STATE_GATE ? true : false);
 851                 soc15_update_drm_clock_gating(adev,
 852                                 state == AMD_CG_STATE_GATE ? true : false);
 853                 soc15_update_drm_light_sleep(adev,
 854                                 state == AMD_CG_STATE_GATE ? true : false);
 855                 soc15_update_rom_medium_grain_clock_gating(adev,
 856                                 state == AMD_CG_STATE_GATE ? true : false);
 857                 soc15_update_df_medium_grain_clock_gating(adev,
 858                                 state == AMD_CG_STATE_GATE ? true : false);
 859                 break;
 860         case CHIP_RAVEN:
 861                 nbio_v7_0_update_medium_grain_clock_gating(adev,
 862                                 state == AMD_CG_STATE_GATE ? true : false);
 863                 nbio_v6_1_update_medium_grain_light_sleep(adev,
 864                                 state == AMD_CG_STATE_GATE ? true : false);
 865                 soc15_update_hdp_light_sleep(adev,
 866                                 state == AMD_CG_STATE_GATE ? true : false);
 867                 soc15_update_drm_clock_gating(adev,
 868                                 state == AMD_CG_STATE_GATE ? true : false);
 869                 soc15_update_drm_light_sleep(adev,
 870                                 state == AMD_CG_STATE_GATE ? true : false);
 871                 soc15_update_rom_medium_grain_clock_gating(adev,
 872                                 state == AMD_CG_STATE_GATE ? true : false);
 873                 break;
 874         default:
 875                 break;
 876         }
 877         return 0;
 878 }
 879
 880 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 881 {
 882         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 883         int data;
 884
 885         if (amdgpu_sriov_vf(adev))
 886                 *flags = 0;
 887
 888         nbio_v6_1_get_clockgating_state(adev, flags);
 889
 890         /* AMD_CG_SUPPORT_HDP_LS */
 891         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 892         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 893                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 894
 895         /* AMD_CG_SUPPORT_DRM_MGCG */
 896         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 897         if (!(data & 0x01000000))
 898                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
 899
 900         /* AMD_CG_SUPPORT_DRM_LS */
 901         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 902         if (data & 0x1)
 903                 *flags |= AMD_CG_SUPPORT_DRM_LS;
 904
 905         /* AMD_CG_SUPPORT_ROM_MGCG */
 906         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 907         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 908                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 909
 910         /* AMD_CG_SUPPORT_DF_MGCG */
 911         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 912         if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
 913                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 914 }
 915
 916 static int soc15_common_set_powergating_state(void *handle,
 917                                             enum amd_powergating_state state)
 918 {
 919         /* todo */
 920         return 0;
 921 }
 922
 923 const struct amd_ip_funcs soc15_common_ip_funcs = {
 924         .name = "soc15_common",
 925         .early_init = soc15_common_early_init,
 926         .late_init = soc15_common_late_init,
 927         .sw_init = soc15_common_sw_init,
 928         .sw_fini = soc15_common_sw_fini,
 929         .hw_init = soc15_common_hw_init,
 930         .hw_fini = soc15_common_hw_fini,
 931         .suspend = soc15_common_suspend,
 932         .resume = soc15_common_resume,
 933         .is_idle = soc15_common_is_idle,
 934         .wait_for_idle = soc15_common_wait_for_idle,
 935         .soft_reset = soc15_common_soft_reset,
 936         .set_clockgating_state = soc15_common_set_clockgating_state,
 937         .set_powergating_state = soc15_common_set_powergating_state,
 938         .get_clockgating_state= soc15_common_get_clockgating_state,
 939 };