drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  34                                       struct drm_amdgpu_cs_chunk_fence *data,
  35                                       uint32_t *offset)
  36 {
  37         struct drm_gem_object *gobj;
  38         unsigned long size;
  39
  40         gobj = drm_gem_object_lookup(p->filp, data->handle);
  41         if (gobj == NULL)
  42                 return -EINVAL;
  43
  44         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  45         p->uf_entry.priority = 0;
  46         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  47         p->uf_entry.tv.shared = true;
  48         p->uf_entry.user_pages = NULL;
  49
  50         size = amdgpu_bo_size(p->uf_entry.robj);
  51         if (size != PAGE_SIZE || (data->offset + 8) > size)
  52                 return -EINVAL;
  53
  54         *offset = data->offset;
  55
  56         drm_gem_object_unreference_unlocked(gobj);
  57
  58         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  59                 amdgpu_bo_unref(&p->uf_entry.robj);
  60                 return -EINVAL;
  61         }
  62
  63         return 0;
  64 }
  65
  66 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
  67 {
  68         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  69         struct amdgpu_vm *vm = &fpriv->vm;
  70         union drm_amdgpu_cs *cs = data;
  71         uint64_t *chunk_array_user;
  72         uint64_t *chunk_array;
  73         unsigned size, num_ibs = 0;
  74         uint32_t uf_offset = 0;
  75         int i;
  76         int ret;
  77
  78         if (cs->in.num_chunks == 0)
  79                 return 0;
  80
  81         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
  82         if (!chunk_array)
  83                 return -ENOMEM;
  84
  85         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  86         if (!p->ctx) {
  87                 ret = -EINVAL;
  88                 goto free_chunk;
  89         }
  90
  91         /* get chunks */
  92         chunk_array_user = (uint64_t __user *)(uintptr_t)(cs->in.chunks);
  93         if (copy_from_user(chunk_array, chunk_array_user,
  94                            sizeof(uint64_t)*cs->in.num_chunks)) {
  95                 ret = -EFAULT;
  96                 goto put_ctx;
  97         }
  98
  99         p->nchunks = cs->in.num_chunks;
 100         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 101                             GFP_KERNEL);
 102         if (!p->chunks) {
 103                 ret = -ENOMEM;
 104                 goto put_ctx;
 105         }
 106
 107         for (i = 0; i < p->nchunks; i++) {
 108                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 109                 struct drm_amdgpu_cs_chunk user_chunk;
 110                 uint32_t __user *cdata;
 111
 112                 chunk_ptr = (void __user *)(uintptr_t)chunk_array[i];
 113                 if (copy_from_user(&user_chunk, chunk_ptr,
 114                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 115                         ret = -EFAULT;
 116                         i--;
 117                         goto free_partial_kdata;
 118                 }
 119                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 120                 p->chunks[i].length_dw = user_chunk.length_dw;
 121
 122                 size = p->chunks[i].length_dw;
 123                 cdata = (void __user *)(uintptr_t)user_chunk.chunk_data;
 124
 125                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 126                 if (p->chunks[i].kdata == NULL) {
 127                         ret = -ENOMEM;
 128                         i--;
 129                         goto free_partial_kdata;
 130                 }
 131                 size *= sizeof(uint32_t);
 132                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 133                         ret = -EFAULT;
 134                         goto free_partial_kdata;
 135                 }
 136
 137                 switch (p->chunks[i].chunk_id) {
 138                 case AMDGPU_CHUNK_ID_IB:
 139                         ++num_ibs;
 140                         break;
 141
 142                 case AMDGPU_CHUNK_ID_FENCE:
 143                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 144                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 145                                 ret = -EINVAL;
 146                                 goto free_partial_kdata;
 147                         }
 148
 149                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 150                                                          &uf_offset);
 151                         if (ret)
 152                                 goto free_partial_kdata;
 153
 154                         break;
 155
 156                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 157                         break;
 158
 159                 default:
 160                         ret = -EINVAL;
 161                         goto free_partial_kdata;
 162                 }
 163         }
 164
 165         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 166         if (ret)
 167                 goto free_all_kdata;
 168
 169         if (p->uf_entry.robj)
 170                 p->job->uf_addr = uf_offset;
 171         kfree(chunk_array);
 172         return 0;
 173
 174 free_all_kdata:
 175         i = p->nchunks - 1;
 176 free_partial_kdata:
 177         for (; i >= 0; i--)
 178                 drm_free_large(p->chunks[i].kdata);
 179         kfree(p->chunks);
 180         p->chunks = NULL;
 181         p->nchunks = 0;
 182 put_ctx:
 183         amdgpu_ctx_put(p->ctx);
 184 free_chunk:
 185         kfree(chunk_array);
 186
 187         return ret;
 188 }
 189
 190 /* Convert microseconds to bytes. */
 191 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 192 {
 193         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 194                 return 0;
 195
 196         /* Since accum_us is incremented by a million per second, just
 197          * multiply it by the number of MB/s to get the number of bytes.
 198          */
 199         return us << adev->mm_stats.log2_max_MBps;
 200 }
 201
 202 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 203 {
 204         if (!adev->mm_stats.log2_max_MBps)
 205                 return 0;
 206
 207         return bytes >> adev->mm_stats.log2_max_MBps;
 208 }
 209
 210 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 211  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 212  * which means it can go over the threshold once. If that happens, the driver
 213  * will be in debt and no other buffer migrations can be done until that debt
 214  * is repaid.
 215  *
 216  * This approach allows moving a buffer of any size (it's important to allow
 217  * that).
 218  *
 219  * The currency is simply time in microseconds and it increases as the clock
 220  * ticks. The accumulated microseconds (us) are converted to bytes and
 221  * returned.
 222  */
 223 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 224 {
 225         s64 time_us, increment_us;
 226         u64 max_bytes;
 227         u64 free_vram, total_vram, used_vram;
 228
 229         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 230          * throttling.
 231          *
 232          * It means that in order to get full max MBps, at least 5 IBs per
 233          * second must be submitted and not more than 200ms apart from each
 234          * other.
 235          */
 236         const s64 us_upper_bound = 200000;
 237
 238         if (!adev->mm_stats.log2_max_MBps)
 239                 return 0;
 240
 241         total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
 242         used_vram = atomic64_read(&adev->vram_usage);
 243         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 244
 245         spin_lock(&adev->mm_stats.lock);
 246
 247         /* Increase the amount of accumulated us. */
 248         time_us = ktime_to_us(ktime_get());
 249         increment_us = time_us - adev->mm_stats.last_update_us;
 250         adev->mm_stats.last_update_us = time_us;
 251         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 252                                       us_upper_bound);
 253
 254         /* This prevents the short period of low performance when the VRAM
 255          * usage is low and the driver is in debt or doesn't have enough
 256          * accumulated us to fill VRAM quickly.
 257          *
 258          * The situation can occur in these cases:
 259          * - a lot of VRAM is freed by userspace
 260          * - the presence of a big buffer causes a lot of evictions
 261          *   (solution: split buffers into smaller ones)
 262          *
 263          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 264          * accum_us to a positive number.
 265          */
 266         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 267                 s64 min_us;
 268
 269                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 270                  * VRAM now.
 271                  */
 272                 if (!(adev->flags & AMD_IS_APU))
 273                         min_us = bytes_to_us(adev, free_vram / 4);
 274                 else
 275                         min_us = 0; /* Reset accum_us on APUs. */
 276
 277                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 278         }
 279
 280         /* This returns 0 if the driver is in debt to disallow (optional)
 281          * buffer moves.
 282          */
 283         max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 284
 285         spin_unlock(&adev->mm_stats.lock);
 286         return max_bytes;
 287 }
 288
 289 /* Report how many bytes have really been moved for the last command
 290  * submission. This can result in a debt that can stop buffer migrations
 291  * temporarily.
 292  */
 293 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes)
 294 {
 295         spin_lock(&adev->mm_stats.lock);
 296         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 297         spin_unlock(&adev->mm_stats.lock);
 298 }
 299
 300 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 301                                  struct amdgpu_bo *bo)
 302 {
 303         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 304         u64 initial_bytes_moved;
 305         uint32_t domain;
 306         int r;
 307
 308         if (bo->pin_count)
 309                 return 0;
 310
 311         /* Don't move this buffer if we have depleted our allowance
 312          * to move it. Don't move anything if the threshold is zero.
 313          */
 314         if (p->bytes_moved < p->bytes_moved_threshold)
 315                 domain = bo->prefered_domains;
 316         else
 317                 domain = bo->allowed_domains;
 318
 319 retry:
 320         amdgpu_ttm_placement_from_domain(bo, domain);
 321         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 322         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 323         p->bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 324                 initial_bytes_moved;
 325
 326         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 327                 domain = bo->allowed_domains;
 328                 goto retry;
 329         }
 330
 331         return r;
 332 }
 333
 334 /* Last resort, try to evict something from the current working set */
 335 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 336                                 struct amdgpu_bo *validated)
 337 {
 338         uint32_t domain = validated->allowed_domains;
 339         int r;
 340
 341         if (!p->evictable)
 342                 return false;
 343
 344         for (;&p->evictable->tv.head != &p->validated;
 345              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 346
 347                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 348                 struct amdgpu_bo *bo = candidate->robj;
 349                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 350                 u64 initial_bytes_moved;
 351                 uint32_t other;
 352
 353                 /* If we reached our current BO we can forget it */
 354                 if (candidate->robj == validated)
 355                         break;
 356
 357                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 358
 359                 /* Check if this BO is in one of the domains we need space for */
 360                 if (!(other & domain))
 361                         continue;
 362
 363                 /* Check if we can move this BO somewhere else */
 364                 other = bo->allowed_domains & ~domain;
 365                 if (!other)
 366                         continue;
 367
 368                 /* Good we can try to move this BO somewhere else */
 369                 amdgpu_ttm_placement_from_domain(bo, other);
 370                 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 371                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 372                 p->bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 373                         initial_bytes_moved;
 374
 375                 if (unlikely(r))
 376                         break;
 377
 378                 p->evictable = list_prev_entry(p->evictable, tv.head);
 379                 list_move(&candidate->tv.head, &p->validated);
 380
 381                 return true;
 382         }
 383
 384         return false;
 385 }
 386
 387 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 388 {
 389         struct amdgpu_cs_parser *p = param;
 390         int r;
 391
 392         do {
 393                 r = amdgpu_cs_bo_validate(p, bo);
 394         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 395         if (r)
 396                 return r;
 397
 398         if (bo->shadow)
 399                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 400
 401         return r;
 402 }
 403
 404 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 405                             struct list_head *validated)
 406 {
 407         struct amdgpu_bo_list_entry *lobj;
 408         int r;
 409
 410         list_for_each_entry(lobj, validated, tv.head) {
 411                 struct amdgpu_bo *bo = lobj->robj;
 412                 bool binding_userptr = false;
 413                 struct mm_struct *usermm;
 414
 415                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 416                 if (usermm && usermm != current->mm)
 417                         return -EPERM;
 418
 419                 /* Check if we have user pages and nobody bound the BO already */
 420                 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
 421                         size_t size = sizeof(struct page *);
 422
 423                         size *= bo->tbo.ttm->num_pages;
 424                         memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
 425                         binding_userptr = true;
 426                 }
 427
 428                 if (p->evictable == lobj)
 429                         p->evictable = NULL;
 430
 431                 r = amdgpu_cs_validate(p, bo);
 432                 if (r)
 433                         return r;
 434
 435                 if (binding_userptr) {
 436                         drm_free_large(lobj->user_pages);
 437                         lobj->user_pages = NULL;
 438                 }
 439         }
 440         return 0;
 441 }
 442
 443 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 444                                 union drm_amdgpu_cs *cs)
 445 {
 446         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 447         struct amdgpu_bo_list_entry *e;
 448         struct list_head duplicates;
 449         bool need_mmap_lock = false;
 450         unsigned i, tries = 10;
 451         int r;
 452
 453         INIT_LIST_HEAD(&p->validated);
 454
 455         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 456         if (p->bo_list) {
 457                 need_mmap_lock = p->bo_list->first_userptr !=
 458                         p->bo_list->num_entries;
 459                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 460         }
 461
 462         INIT_LIST_HEAD(&duplicates);
 463         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 464
 465         if (p->uf_entry.robj)
 466                 list_add(&p->uf_entry.tv.head, &p->validated);
 467
 468         if (need_mmap_lock)
 469                 down_read(&current->mm->mmap_sem);
 470
 471         while (1) {
 472                 struct list_head need_pages;
 473                 unsigned i;
 474
 475                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 476                                            &duplicates);
 477                 if (unlikely(r != 0)) {
 478                         if (r != -ERESTARTSYS)
 479                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 480                         goto error_free_pages;
 481                 }
 482
 483                 /* Without a BO list we don't have userptr BOs */
 484                 if (!p->bo_list)
 485                         break;
 486
 487                 INIT_LIST_HEAD(&need_pages);
 488                 for (i = p->bo_list->first_userptr;
 489                      i < p->bo_list->num_entries; ++i) {
 490
 491                         e = &p->bo_list->array[i];
 492
 493                         if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
 494                                  &e->user_invalidated) && e->user_pages) {
 495
 496                                 /* We acquired a page array, but somebody
 497                                  * invalidated it. Free it an try again
 498                                  */
 499                                 release_pages(e->user_pages,
 500                                               e->robj->tbo.ttm->num_pages,
 501                                               false);
 502                                 drm_free_large(e->user_pages);
 503                                 e->user_pages = NULL;
 504                         }
 505
 506                         if (e->robj->tbo.ttm->state != tt_bound &&
 507                             !e->user_pages) {
 508                                 list_del(&e->tv.head);
 509                                 list_add(&e->tv.head, &need_pages);
 510
 511                                 amdgpu_bo_unreserve(e->robj);
 512                         }
 513                 }
 514
 515                 if (list_empty(&need_pages))
 516                         break;
 517
 518                 /* Unreserve everything again. */
 519                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 520
 521                 /* We tried too many times, just abort */
 522                 if (!--tries) {
 523                         r = -EDEADLK;
 524                         DRM_ERROR("deadlock in %s\n", __func__);
 525                         goto error_free_pages;
 526                 }
 527
 528                 /* Fill the page arrays for all useptrs. */
 529                 list_for_each_entry(e, &need_pages, tv.head) {
 530                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 531
 532                         e->user_pages = drm_calloc_large(ttm->num_pages,
 533                                                          sizeof(struct page*));
 534                         if (!e->user_pages) {
 535                                 r = -ENOMEM;
 536                                 DRM_ERROR("calloc failure in %s\n", __func__);
 537                                 goto error_free_pages;
 538                         }
 539
 540                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 541                         if (r) {
 542                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 543                                 drm_free_large(e->user_pages);
 544                                 e->user_pages = NULL;
 545                                 goto error_free_pages;
 546                         }
 547                 }
 548
 549                 /* And try again. */
 550                 list_splice(&need_pages, &p->validated);
 551         }
 552
 553         p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
 554         p->bytes_moved = 0;
 555         p->evictable = list_last_entry(&p->validated,
 556                                        struct amdgpu_bo_list_entry,
 557                                        tv.head);
 558
 559         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 560                                       amdgpu_cs_validate, p);
 561         if (r) {
 562                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 563                 goto error_validate;
 564         }
 565
 566         r = amdgpu_cs_list_validate(p, &duplicates);
 567         if (r) {
 568                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 569                 goto error_validate;
 570         }
 571
 572         r = amdgpu_cs_list_validate(p, &p->validated);
 573         if (r) {
 574                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 575                 goto error_validate;
 576         }
 577
 578         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved);
 579
 580         fpriv->vm.last_eviction_counter =
 581                 atomic64_read(&p->adev->num_evictions);
 582
 583         if (p->bo_list) {
 584                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
 585                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
 586                 struct amdgpu_bo *oa = p->bo_list->oa_obj;
 587                 struct amdgpu_vm *vm = &fpriv->vm;
 588                 unsigned i;
 589
 590                 for (i = 0; i < p->bo_list->num_entries; i++) {
 591                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 592
 593                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 594                 }
 595
 596                 if (gds) {
 597                         p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 598                         p->job->gds_size = amdgpu_bo_size(gds);
 599                 }
 600                 if (gws) {
 601                         p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 602                         p->job->gws_size = amdgpu_bo_size(gws);
 603                 }
 604                 if (oa) {
 605                         p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 606                         p->job->oa_size = amdgpu_bo_size(oa);
 607                 }
 608         }
 609
 610         if (!r && p->uf_entry.robj) {
 611                 struct amdgpu_bo *uf = p->uf_entry.robj;
 612
 613                 r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
 614                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 615         }
 616
 617 error_validate:
 618         if (r) {
 619                 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
 620                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 621         }
 622
 623 error_free_pages:
 624
 625         if (need_mmap_lock)
 626                 up_read(&current->mm->mmap_sem);
 627
 628         if (p->bo_list) {
 629                 for (i = p->bo_list->first_userptr;
 630                      i < p->bo_list->num_entries; ++i) {
 631                         e = &p->bo_list->array[i];
 632
 633                         if (!e->user_pages)
 634                                 continue;
 635
 636                         release_pages(e->user_pages,
 637                                       e->robj->tbo.ttm->num_pages,
 638                                       false);
 639                         drm_free_large(e->user_pages);
 640                 }
 641         }
 642
 643         return r;
 644 }
 645
 646 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 647 {
 648         struct amdgpu_bo_list_entry *e;
 649         int r;
 650
 651         list_for_each_entry(e, &p->validated, tv.head) {
 652                 struct reservation_object *resv = e->robj->tbo.resv;
 653                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
 654
 655                 if (r)
 656                         return r;
 657         }
 658         return 0;
 659 }
 660
 661 /**
 662  * cs_parser_fini() - clean parser states
 663  * @parser:     parser structure holding parsing context.
 664  * @error:      error number
 665  *
 666  * If error is set than unvalidate buffer, otherwise just free memory
 667  * used by parsing context.
 668  **/
 669 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 670 {
 671         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 672         unsigned i;
 673
 674         if (!error) {
 675                 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
 676
 677                 ttm_eu_fence_buffer_objects(&parser->ticket,
 678                                             &parser->validated,
 679                                             parser->fence);
 680         } else if (backoff) {
 681                 ttm_eu_backoff_reservation(&parser->ticket,
 682                                            &parser->validated);
 683         }
 684         dma_fence_put(parser->fence);
 685
 686         if (parser->ctx)
 687                 amdgpu_ctx_put(parser->ctx);
 688         if (parser->bo_list)
 689                 amdgpu_bo_list_put(parser->bo_list);
 690
 691         for (i = 0; i < parser->nchunks; i++)
 692                 drm_free_large(parser->chunks[i].kdata);
 693         kfree(parser->chunks);
 694         if (parser->job)
 695                 amdgpu_job_free(parser->job);
 696         amdgpu_bo_unref(&parser->uf_entry.robj);
 697 }
 698
 699 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 700 {
 701         struct amdgpu_device *adev = p->adev;
 702         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 703         struct amdgpu_vm *vm = &fpriv->vm;
 704         struct amdgpu_bo_va *bo_va;
 705         struct amdgpu_bo *bo;
 706         int i, r;
 707
 708         r = amdgpu_vm_update_directories(adev, vm);
 709         if (r)
 710                 return r;
 711
 712         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update);
 713         if (r)
 714                 return r;
 715
 716         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 717         if (r)
 718                 return r;
 719
 720         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 721         if (r)
 722                 return r;
 723
 724         r = amdgpu_sync_fence(adev, &p->job->sync,
 725                               fpriv->prt_va->last_pt_update);
 726         if (r)
 727                 return r;
 728
 729         if (amdgpu_sriov_vf(adev)) {
 730                 struct dma_fence *f;
 731                 bo_va = vm->csa_bo_va;
 732                 BUG_ON(!bo_va);
 733                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 734                 if (r)
 735                         return r;
 736
 737                 f = bo_va->last_pt_update;
 738                 r = amdgpu_sync_fence(adev, &p->job->sync, f);
 739                 if (r)
 740                         return r;
 741         }
 742
 743         if (p->bo_list) {
 744                 for (i = 0; i < p->bo_list->num_entries; i++) {
 745                         struct dma_fence *f;
 746
 747                         /* ignore duplicates */
 748                         bo = p->bo_list->array[i].robj;
 749                         if (!bo)
 750                                 continue;
 751
 752                         bo_va = p->bo_list->array[i].bo_va;
 753                         if (bo_va == NULL)
 754                                 continue;
 755
 756                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 757                         if (r)
 758                                 return r;
 759
 760                         f = bo_va->last_pt_update;
 761                         r = amdgpu_sync_fence(adev, &p->job->sync, f);
 762                         if (r)
 763                                 return r;
 764                 }
 765
 766         }
 767
 768         r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
 769
 770         if (amdgpu_vm_debug && p->bo_list) {
 771                 /* Invalidate all BOs to test for userspace bugs */
 772                 for (i = 0; i < p->bo_list->num_entries; i++) {
 773                         /* ignore duplicates */
 774                         bo = p->bo_list->array[i].robj;
 775                         if (!bo)
 776                                 continue;
 777
 778                         amdgpu_vm_bo_invalidate(adev, bo);
 779                 }
 780         }
 781
 782         return r;
 783 }
 784
 785 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 786                                  struct amdgpu_cs_parser *p)
 787 {
 788         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 789         struct amdgpu_vm *vm = &fpriv->vm;
 790         struct amdgpu_ring *ring = p->job->ring;
 791         int i, r;
 792
 793         /* Only for UVD/VCE VM emulation */
 794         if (ring->funcs->parse_cs) {
 795                 for (i = 0; i < p->job->num_ibs; i++) {
 796                         r = amdgpu_ring_parse_cs(ring, p, i);
 797                         if (r)
 798                                 return r;
 799                 }
 800         }
 801
 802         if (p->job->vm) {
 803                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
 804
 805                 r = amdgpu_bo_vm_update_pte(p);
 806                 if (r)
 807                         return r;
 808         }
 809
 810         return amdgpu_cs_sync_rings(p);
 811 }
 812
 813 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 814                              struct amdgpu_cs_parser *parser)
 815 {
 816         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 817         struct amdgpu_vm *vm = &fpriv->vm;
 818         int i, j;
 819         int r, ce_preempt = 0, de_preempt = 0;
 820
 821         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 822                 struct amdgpu_cs_chunk *chunk;
 823                 struct amdgpu_ib *ib;
 824                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 825                 struct amdgpu_ring *ring;
 826
 827                 chunk = &parser->chunks[i];
 828                 ib = &parser->job->ibs[j];
 829                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 830
 831                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 832                         continue;
 833
 834                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 835                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 836                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 837                                         ce_preempt++;
 838                                 else
 839                                         de_preempt++;
 840                         }
 841
 842                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 843                         if (ce_preempt > 1 || de_preempt > 1)
 844                                 return -EINVAL;
 845                 }
 846
 847                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
 848                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
 849                 if (r)
 850                         return r;
 851
 852                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 853                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 854                         if (!parser->ctx->preamble_presented) {
 855                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 856                                 parser->ctx->preamble_presented = true;
 857                         }
 858                 }
 859
 860                 if (parser->job->ring && parser->job->ring != ring)
 861                         return -EINVAL;
 862
 863                 parser->job->ring = ring;
 864
 865                 if (ring->funcs->parse_cs) {
 866                         struct amdgpu_bo_va_mapping *m;
 867                         struct amdgpu_bo *aobj = NULL;
 868                         uint64_t offset;
 869                         uint8_t *kptr;
 870
 871                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 872                                                    &aobj);
 873                         if (!aobj) {
 874                                 DRM_ERROR("IB va_start is invalid\n");
 875                                 return -EINVAL;
 876                         }
 877
 878                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 879                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 880                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 881                                 return -EINVAL;
 882                         }
 883
 884                         /* the IB should be reserved at this point */
 885                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 886                         if (r) {
 887                                 return r;
 888                         }
 889
 890                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 891                         kptr += chunk_ib->va_start - offset;
 892
 893                         r =  amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
 894                         if (r) {
 895                                 DRM_ERROR("Failed to get ib !\n");
 896                                 return r;
 897                         }
 898
 899                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 900                         amdgpu_bo_kunmap(aobj);
 901                 } else {
 902                         r =  amdgpu_ib_get(adev, vm, 0, ib);
 903                         if (r) {
 904                                 DRM_ERROR("Failed to get ib !\n");
 905                                 return r;
 906                         }
 907
 908                 }
 909
 910                 ib->gpu_addr = chunk_ib->va_start;
 911                 ib->length_dw = chunk_ib->ib_bytes / 4;
 912                 ib->flags = chunk_ib->flags;
 913                 j++;
 914         }
 915
 916         /* UVD & VCE fw doesn't support user fences */
 917         if (parser->job->uf_addr && (
 918             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
 919             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
 920                 return -EINVAL;
 921
 922         return 0;
 923 }
 924
 925 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 926                                   struct amdgpu_cs_parser *p)
 927 {
 928         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 929         int i, j, r;
 930
 931         for (i = 0; i < p->nchunks; ++i) {
 932                 struct drm_amdgpu_cs_chunk_dep *deps;
 933                 struct amdgpu_cs_chunk *chunk;
 934                 unsigned num_deps;
 935
 936                 chunk = &p->chunks[i];
 937
 938                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 939                         continue;
 940
 941                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 942                 num_deps = chunk->length_dw * 4 /
 943                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 944
 945                 for (j = 0; j < num_deps; ++j) {
 946                         struct amdgpu_ring *ring;
 947                         struct amdgpu_ctx *ctx;
 948                         struct dma_fence *fence;
 949
 950                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 951                         if (ctx == NULL)
 952                                 return -EINVAL;
 953
 954                         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
 955                                                  deps[j].ip_type,
 956                                                  deps[j].ip_instance,
 957                                                  deps[j].ring, &ring);
 958                         if (r) {
 959                                 amdgpu_ctx_put(ctx);
 960                                 return r;
 961                         }
 962
 963                         fence = amdgpu_ctx_get_fence(ctx, ring,
 964                                                      deps[j].handle);
 965                         if (IS_ERR(fence)) {
 966                                 r = PTR_ERR(fence);
 967                                 amdgpu_ctx_put(ctx);
 968                                 return r;
 969
 970                         } else if (fence) {
 971                                 r = amdgpu_sync_fence(adev, &p->job->sync,
 972                                                       fence);
 973                                 dma_fence_put(fence);
 974                                 amdgpu_ctx_put(ctx);
 975                                 if (r)
 976                                         return r;
 977                         }
 978                 }
 979         }
 980
 981         return 0;
 982 }
 983
 984 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 985                             union drm_amdgpu_cs *cs)
 986 {
 987         struct amdgpu_ring *ring = p->job->ring;
 988         struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
 989         struct amdgpu_job *job;
 990         int r;
 991
 992         job = p->job;
 993         p->job = NULL;
 994
 995         r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
 996         if (r) {
 997                 amdgpu_job_free(job);
 998                 return r;
 999         }
1000
1001         job->owner = p->filp;
1002         job->fence_ctx = entity->fence_context;
1003         p->fence = dma_fence_get(&job->base.s_fence->finished);
1004         cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
1005         job->uf_sequence = cs->out.handle;
1006         amdgpu_job_free_resources(job);
1007         amdgpu_cs_parser_fini(p, 0, true);
1008
1009         trace_amdgpu_cs_ioctl(job);
1010         amd_sched_entity_push_job(&job->base);
1011
1012         return 0;
1013 }
1014
1015 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1016 {
1017         struct amdgpu_device *adev = dev->dev_private;
1018         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1019         union drm_amdgpu_cs *cs = data;
1020         struct amdgpu_cs_parser parser = {};
1021         bool reserved_buffers = false;
1022         int i, r;
1023
1024         if (!adev->accel_working)
1025                 return -EBUSY;
1026         if (amdgpu_kms_vram_lost(adev, fpriv))
1027                 return -ENODEV;
1028
1029         parser.adev = adev;
1030         parser.filp = filp;
1031
1032         r = amdgpu_cs_parser_init(&parser, data);
1033         if (r) {
1034                 DRM_ERROR("Failed to initialize parser !\n");
1035                 goto out;
1036         }
1037
1038         r = amdgpu_cs_parser_bos(&parser, data);
1039         if (r) {
1040                 if (r == -ENOMEM)
1041                         DRM_ERROR("Not enough memory for command submission!\n");
1042                 else if (r != -ERESTARTSYS)
1043                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1044                 goto out;
1045         }
1046
1047         reserved_buffers = true;
1048         r = amdgpu_cs_ib_fill(adev, &parser);
1049         if (r)
1050                 goto out;
1051
1052         r = amdgpu_cs_dependencies(adev, &parser);
1053         if (r) {
1054                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1055                 goto out;
1056         }
1057
1058         for (i = 0; i < parser.job->num_ibs; i++)
1059                 trace_amdgpu_cs(&parser, i);
1060
1061         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1062         if (r)
1063                 goto out;
1064
1065         r = amdgpu_cs_submit(&parser, cs);
1066         if (r)
1067                 goto out;
1068
1069         return 0;
1070 out:
1071         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1072         return r;
1073 }
1074
1075 /**
1076  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1077  *
1078  * @dev: drm device
1079  * @data: data from userspace
1080  * @filp: file private
1081  *
1082  * Wait for the command submission identified by handle to finish.
1083  */
1084 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1085                          struct drm_file *filp)
1086 {
1087         union drm_amdgpu_wait_cs *wait = data;
1088         struct amdgpu_device *adev = dev->dev_private;
1089         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1090         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1091         struct amdgpu_ring *ring = NULL;
1092         struct amdgpu_ctx *ctx;
1093         struct dma_fence *fence;
1094         long r;
1095
1096         if (amdgpu_kms_vram_lost(adev, fpriv))
1097                 return -ENODEV;
1098
1099         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1100         if (ctx == NULL)
1101                 return -EINVAL;
1102
1103         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1104                                  wait->in.ip_type, wait->in.ip_instance,
1105                                  wait->in.ring, &ring);
1106         if (r) {
1107                 amdgpu_ctx_put(ctx);
1108                 return r;
1109         }
1110
1111         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1112         if (IS_ERR(fence))
1113                 r = PTR_ERR(fence);
1114         else if (fence) {
1115                 r = dma_fence_wait_timeout(fence, true, timeout);
1116                 dma_fence_put(fence);
1117         } else
1118                 r = 1;
1119
1120         amdgpu_ctx_put(ctx);
1121         if (r < 0)
1122                 return r;
1123
1124         memset(wait, 0, sizeof(*wait));
1125         wait->out.status = (r == 0);
1126
1127         return 0;
1128 }
1129
1130 /**
1131  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1132  *
1133  * @adev: amdgpu device
1134  * @filp: file private
1135  * @user: drm_amdgpu_fence copied from user space
1136  */
1137 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1138                                              struct drm_file *filp,
1139                                              struct drm_amdgpu_fence *user)
1140 {
1141         struct amdgpu_ring *ring;
1142         struct amdgpu_ctx *ctx;
1143         struct dma_fence *fence;
1144         int r;
1145
1146         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1147         if (ctx == NULL)
1148                 return ERR_PTR(-EINVAL);
1149
1150         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1151                                  user->ip_instance, user->ring, &ring);
1152         if (r) {
1153                 amdgpu_ctx_put(ctx);
1154                 return ERR_PTR(r);
1155         }
1156
1157         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1158         amdgpu_ctx_put(ctx);
1159
1160         return fence;
1161 }
1162
1163 /**
1164  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1165  *
1166  * @adev: amdgpu device
1167  * @filp: file private
1168  * @wait: wait parameters
1169  * @fences: array of drm_amdgpu_fence
1170  */
1171 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1172                                      struct drm_file *filp,
1173                                      union drm_amdgpu_wait_fences *wait,
1174                                      struct drm_amdgpu_fence *fences)
1175 {
1176         uint32_t fence_count = wait->in.fence_count;
1177         unsigned int i;
1178         long r = 1;
1179
1180         for (i = 0; i < fence_count; i++) {
1181                 struct dma_fence *fence;
1182                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1183
1184                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1185                 if (IS_ERR(fence))
1186                         return PTR_ERR(fence);
1187                 else if (!fence)
1188                         continue;
1189
1190                 r = dma_fence_wait_timeout(fence, true, timeout);
1191                 dma_fence_put(fence);
1192                 if (r < 0)
1193                         return r;
1194
1195                 if (r == 0)
1196                         break;
1197         }
1198
1199         memset(wait, 0, sizeof(*wait));
1200         wait->out.status = (r > 0);
1201
1202         return 0;
1203 }
1204
1205 /**
1206  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1207  *
1208  * @adev: amdgpu device
1209  * @filp: file private
1210  * @wait: wait parameters
1211  * @fences: array of drm_amdgpu_fence
1212  */
1213 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1214                                     struct drm_file *filp,
1215                                     union drm_amdgpu_wait_fences *wait,
1216                                     struct drm_amdgpu_fence *fences)
1217 {
1218         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1219         uint32_t fence_count = wait->in.fence_count;
1220         uint32_t first = ~0;
1221         struct dma_fence **array;
1222         unsigned int i;
1223         long r;
1224
1225         /* Prepare the fence array */
1226         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1227
1228         if (array == NULL)
1229                 return -ENOMEM;
1230
1231         for (i = 0; i < fence_count; i++) {
1232                 struct dma_fence *fence;
1233
1234                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1235                 if (IS_ERR(fence)) {
1236                         r = PTR_ERR(fence);
1237                         goto err_free_fence_array;
1238                 } else if (fence) {
1239                         array[i] = fence;
1240                 } else { /* NULL, the fence has been already signaled */
1241                         r = 1;
1242                         goto out;
1243                 }
1244         }
1245
1246         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1247                                        &first);
1248         if (r < 0)
1249                 goto err_free_fence_array;
1250
1251 out:
1252         memset(wait, 0, sizeof(*wait));
1253         wait->out.status = (r > 0);
1254         wait->out.first_signaled = first;
1255         /* set return value 0 to indicate success */
1256         r = 0;
1257
1258 err_free_fence_array:
1259         for (i = 0; i < fence_count; i++)
1260                 dma_fence_put(array[i]);
1261         kfree(array);
1262
1263         return r;
1264 }
1265
1266 /**
1267  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1268  *
1269  * @dev: drm device
1270  * @data: data from userspace
1271  * @filp: file private
1272  */
1273 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1274                                 struct drm_file *filp)
1275 {
1276         struct amdgpu_device *adev = dev->dev_private;
1277         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1278         union drm_amdgpu_wait_fences *wait = data;
1279         uint32_t fence_count = wait->in.fence_count;
1280         struct drm_amdgpu_fence *fences_user;
1281         struct drm_amdgpu_fence *fences;
1282         int r;
1283
1284         if (amdgpu_kms_vram_lost(adev, fpriv))
1285                 return -ENODEV;
1286         /* Get the fences from userspace */
1287         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1288                         GFP_KERNEL);
1289         if (fences == NULL)
1290                 return -ENOMEM;
1291
1292         fences_user = (void __user *)(uintptr_t)(wait->in.fences);
1293         if (copy_from_user(fences, fences_user,
1294                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1295                 r = -EFAULT;
1296                 goto err_free_fences;
1297         }
1298
1299         if (wait->in.wait_all)
1300                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1301         else
1302                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1303
1304 err_free_fences:
1305         kfree(fences);
1306
1307         return r;
1308 }
1309
1310 /**
1311  * amdgpu_cs_find_bo_va - find bo_va for VM address
1312  *
1313  * @parser: command submission parser context
1314  * @addr: VM address
1315  * @bo: resulting BO of the mapping found
1316  *
1317  * Search the buffer objects in the command submission context for a certain
1318  * virtual memory address. Returns allocation structure when found, NULL
1319  * otherwise.
1320  */
1321 struct amdgpu_bo_va_mapping *
1322 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1323                        uint64_t addr, struct amdgpu_bo **bo)
1324 {
1325         struct amdgpu_bo_va_mapping *mapping;
1326         unsigned i;
1327
1328         if (!parser->bo_list)
1329                 return NULL;
1330
1331         addr /= AMDGPU_GPU_PAGE_SIZE;
1332
1333         for (i = 0; i < parser->bo_list->num_entries; i++) {
1334                 struct amdgpu_bo_list_entry *lobj;
1335
1336                 lobj = &parser->bo_list->array[i];
1337                 if (!lobj->bo_va)
1338                         continue;
1339
1340                 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1341                         if (mapping->start > addr ||
1342                             addr > mapping->last)
1343                                 continue;
1344
1345                         *bo = lobj->bo_va->bo;
1346                         return mapping;
1347                 }
1348
1349                 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1350                         if (mapping->start > addr ||
1351                             addr > mapping->last)
1352                                 continue;
1353
1354                         *bo = lobj->bo_va->bo;
1355                         return mapping;
1356                 }
1357         }
1358
1359         return NULL;
1360 }
1361
1362 /**
1363  * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
1364  *
1365  * @parser: command submission parser context
1366  *
1367  * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
1368  */
1369 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
1370 {
1371         unsigned i;
1372         int r;
1373
1374         if (!parser->bo_list)
1375                 return 0;
1376
1377         for (i = 0; i < parser->bo_list->num_entries; i++) {
1378                 struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
1379
1380                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1381                 if (unlikely(r))
1382                         return r;
1383
1384                 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
1385                         continue;
1386
1387                 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1388                 amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
1389                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
1390                 if (unlikely(r))
1391                         return r;
1392         }
1393
1394         return 0;
1395 }