drivers/usb/dwc2/core.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * core.c - DesignWare HS OTG Controller common routines
   4  *
   5  * Copyright (C) 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * The Core code provides basic services for accessing and managing the
  40  * DWC_otg hardware. These services are used by both the Host Controller
  41  * Driver and the Peripheral Controller Driver.
  42  */
  43 #include <linux/kernel.h>
  44 #include <linux/module.h>
  45 #include <linux/moduleparam.h>
  46 #include <linux/spinlock.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/dma-mapping.h>
  49 #include <linux/delay.h>
  50 #include <linux/io.h>
  51 #include <linux/slab.h>
  52 #include <linux/usb.h>
  53
  54 #include <linux/usb/hcd.h>
  55 #include <linux/usb/ch11.h>
  56
  57 #include "core.h"
  58 #include "hcd.h"
  59
  60 /**
  61  * dwc2_backup_global_registers() - Backup global controller registers.
  62  * When suspending usb bus, registers needs to be backuped
  63  * if controller power is disabled once suspended.
  64  *
  65  * @hsotg: Programming view of the DWC_otg controller
  66  */
  67 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
  68 {
  69         struct dwc2_gregs_backup *gr;
  70
  71         dev_dbg(hsotg->dev, "%s\n", __func__);
  72
  73         /* Backup global regs */
  74         gr = &hsotg->gr_backup;
  75
  76         gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  77         gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  78         gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
  79         gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
  80         gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
  81         gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
  82         gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
  83         gr->pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1);
  84         gr->glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG);
  85         gr->gi2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
  86         gr->pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
  87
  88         gr->valid = true;
  89         return 0;
  90 }
  91
  92 /**
  93  * dwc2_restore_global_registers() - Restore controller global registers.
  94  * When resuming usb bus, device registers needs to be restored
  95  * if controller power were disabled.
  96  *
  97  * @hsotg: Programming view of the DWC_otg controller
  98  */
  99 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
 100 {
 101         struct dwc2_gregs_backup *gr;
 102
 103         dev_dbg(hsotg->dev, "%s\n", __func__);
 104
 105         /* Restore global regs */
 106         gr = &hsotg->gr_backup;
 107         if (!gr->valid) {
 108                 dev_err(hsotg->dev, "%s: no global registers to restore\n",
 109                         __func__);
 110                 return -EINVAL;
 111         }
 112         gr->valid = false;
 113
 114         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 115         dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
 116         dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
 117         dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
 118         dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
 119         dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
 120         dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
 121         dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
 122         dwc2_writel(gr->pcgcctl1, hsotg->regs + PCGCCTL1);
 123         dwc2_writel(gr->glpmcfg, hsotg->regs + GLPMCFG);
 124         dwc2_writel(gr->pcgcctl, hsotg->regs + PCGCTL);
 125         dwc2_writel(gr->gi2cctl, hsotg->regs + GI2CCTL);
 126
 127         return 0;
 128 }
 129
 130 /**
 131  * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
 132  *
 133  * @hsotg: Programming view of the DWC_otg controller
 134  * @restore: Controller registers need to be restored
 135  */
 136 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
 137 {
 138         u32 pcgcctl;
 139         int ret = 0;
 140
 141         if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
 142                 return -ENOTSUPP;
 143
 144         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 145         pcgcctl &= ~PCGCTL_STOPPCLK;
 146         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 147
 148         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 149         pcgcctl &= ~PCGCTL_PWRCLMP;
 150         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 151
 152         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 153         pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
 154         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 155
 156         udelay(100);
 157         if (restore) {
 158                 ret = dwc2_restore_global_registers(hsotg);
 159                 if (ret) {
 160                         dev_err(hsotg->dev, "%s: failed to restore registers\n",
 161                                 __func__);
 162                         return ret;
 163                 }
 164                 if (dwc2_is_host_mode(hsotg)) {
 165                         ret = dwc2_restore_host_registers(hsotg);
 166                         if (ret) {
 167                                 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
 168                                         __func__);
 169                                 return ret;
 170                         }
 171                 } else {
 172                         ret = dwc2_restore_device_registers(hsotg, 0);
 173                         if (ret) {
 174                                 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
 175                                         __func__);
 176                                 return ret;
 177                         }
 178                 }
 179         }
 180
 181         return ret;
 182 }
 183
 184 /**
 185  * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
 186  *
 187  * @hsotg: Programming view of the DWC_otg controller
 188  */
 189 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
 190 {
 191         u32 pcgcctl;
 192         int ret = 0;
 193
 194         if (!hsotg->params.power_down)
 195                 return -ENOTSUPP;
 196
 197         /* Backup all registers */
 198         ret = dwc2_backup_global_registers(hsotg);
 199         if (ret) {
 200                 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
 201                         __func__);
 202                 return ret;
 203         }
 204
 205         if (dwc2_is_host_mode(hsotg)) {
 206                 ret = dwc2_backup_host_registers(hsotg);
 207                 if (ret) {
 208                         dev_err(hsotg->dev, "%s: failed to backup host registers\n",
 209                                 __func__);
 210                         return ret;
 211                 }
 212         } else {
 213                 ret = dwc2_backup_device_registers(hsotg);
 214                 if (ret) {
 215                         dev_err(hsotg->dev, "%s: failed to backup device registers\n",
 216                                 __func__);
 217                         return ret;
 218                 }
 219         }
 220
 221         /*
 222          * Clear any pending interrupts since dwc2 will not be able to
 223          * clear them after entering partial_power_down.
 224          */
 225         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 226
 227         /* Put the controller in low power state */
 228         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 229
 230         pcgcctl |= PCGCTL_PWRCLMP;
 231         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 232         ndelay(20);
 233
 234         pcgcctl |= PCGCTL_RSTPDWNMODULE;
 235         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 236         ndelay(20);
 237
 238         pcgcctl |= PCGCTL_STOPPCLK;
 239         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 240
 241         return ret;
 242 }
 243
 244 /**
 245  * dwc2_restore_essential_regs() - Restore essiential regs of core.
 246  *
 247  * @hsotg: Programming view of the DWC_otg controller
 248  * @rmode: Restore mode, enabled in case of remote-wakeup.
 249  * @is_host: Host or device mode.
 250  */
 251 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
 252                                         int is_host)
 253 {
 254         u32 pcgcctl;
 255         struct dwc2_gregs_backup *gr;
 256         struct dwc2_dregs_backup *dr;
 257         struct dwc2_hregs_backup *hr;
 258
 259         gr = &hsotg->gr_backup;
 260         dr = &hsotg->dr_backup;
 261         hr = &hsotg->hr_backup;
 262
 263         dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
 264
 265         /* Load restore values for [31:14] bits */
 266         pcgcctl = (gr->pcgcctl & 0xffffc000);
 267         /* If High Speed */
 268         if (is_host) {
 269                 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
 270                         pcgcctl |= BIT(17);
 271         } else {
 272                 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
 273                         pcgcctl |= BIT(17);
 274         }
 275         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 276
 277         /* Umnask global Interrupt in GAHBCFG and restore it */
 278         dwc2_writel(gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
 279
 280         /* Clear all pending interupts */
 281         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 282
 283         /* Unmask restore done interrupt */
 284         dwc2_writel(GINTSTS_RESTOREDONE, hsotg->regs + GINTMSK);
 285
 286         /* Restore GUSBCFG and HCFG/DCFG */
 287         dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
 288
 289         if (is_host) {
 290                 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
 291                 if (rmode)
 292                         pcgcctl |= PCGCTL_RESTOREMODE;
 293                 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 294                 udelay(10);
 295
 296                 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
 297                 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 298                 udelay(10);
 299         } else {
 300                 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
 301                 if (!rmode)
 302                         pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
 303                 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 304                 udelay(10);
 305
 306                 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
 307                 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 308                 udelay(10);
 309         }
 310 }
 311
 312 /**
 313  * dwc2_hib_restore_common() - Common part of restore routine.
 314  *
 315  * @hsotg: Programming view of the DWC_otg controller
 316  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
 317  * @is_host: Host or device mode.
 318  */
 319 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
 320                              int is_host)
 321 {
 322         u32 gpwrdn;
 323
 324         /* Switch-on voltage to the core */
 325         gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
 326         gpwrdn &= ~GPWRDN_PWRDNSWTCH;
 327         dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
 328         udelay(10);
 329
 330         /* Reset core */
 331         gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
 332         gpwrdn &= ~GPWRDN_PWRDNRSTN;
 333         dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
 334         udelay(10);
 335
 336         /* Enable restore from PMU */
 337         gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
 338         gpwrdn |= GPWRDN_RESTORE;
 339         dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
 340         udelay(10);
 341
 342         /* Disable Power Down Clamp */
 343         gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
 344         gpwrdn &= ~GPWRDN_PWRDNCLMP;
 345         dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
 346         udelay(50);
 347
 348         if (!is_host && rem_wakeup)
 349                 udelay(70);
 350
 351         /* Deassert reset core */
 352         gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
 353         gpwrdn |= GPWRDN_PWRDNRSTN;
 354         dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
 355         udelay(10);
 356
 357         /* Disable PMU interrupt */
 358         gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
 359         gpwrdn &= ~GPWRDN_PMUINTSEL;
 360         dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
 361         udelay(10);
 362
 363         /* Set Restore Essential Regs bit in PCGCCTL register */
 364         dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
 365
 366         /*
 367          * Wait For Restore_done Interrupt. This mechanism of polling the
 368          * interrupt is introduced to avoid any possible race conditions
 369          */
 370         if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
 371                                     20000)) {
 372                 dev_dbg(hsotg->dev,
 373                         "%s: Restore Done wan't generated here\n",
 374                         __func__);
 375         } else {
 376                 dev_dbg(hsotg->dev, "restore done  generated here\n");
 377         }
 378 }
 379
 380 /**
 381  * dwc2_wait_for_mode() - Waits for the controller mode.
 382  * @hsotg:      Programming view of the DWC_otg controller.
 383  * @host_mode:  If true, waits for host mode, otherwise device mode.
 384  */
 385 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
 386                                bool host_mode)
 387 {
 388         ktime_t start;
 389         ktime_t end;
 390         unsigned int timeout = 110;
 391
 392         dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
 393                  host_mode ? "host" : "device");
 394
 395         start = ktime_get();
 396
 397         while (1) {
 398                 s64 ms;
 399
 400                 if (dwc2_is_host_mode(hsotg) == host_mode) {
 401                         dev_vdbg(hsotg->dev, "%s mode set\n",
 402                                  host_mode ? "Host" : "Device");
 403                         break;
 404                 }
 405
 406                 end = ktime_get();
 407                 ms = ktime_to_ms(ktime_sub(end, start));
 408
 409                 if (ms >= (s64)timeout) {
 410                         dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
 411                                  __func__, host_mode ? "host" : "device");
 412                         break;
 413                 }
 414
 415                 usleep_range(1000, 2000);
 416         }
 417 }
 418
 419 /**
 420  * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
 421  * filter is enabled.
 422  *
 423  * @hsotg: Programming view of DWC_otg controller
 424  */
 425 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
 426 {
 427         u32 gsnpsid;
 428         u32 ghwcfg4;
 429
 430         if (!dwc2_hw_is_otg(hsotg))
 431                 return false;
 432
 433         /* Check if core configuration includes the IDDIG filter. */
 434         ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
 435         if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
 436                 return false;
 437
 438         /*
 439          * Check if the IDDIG debounce filter is bypassed. Available
 440          * in core version >= 3.10a.
 441          */
 442         gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
 443         if (gsnpsid >= DWC2_CORE_REV_3_10a) {
 444                 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 445
 446                 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
 447                         return false;
 448         }
 449
 450         return true;
 451 }
 452
 453 /*
 454  * dwc2_enter_hibernation() - Common function to enter hibernation.
 455  *
 456  * @hsotg: Programming view of the DWC_otg controller
 457  * @is_host: True if core is in host mode.
 458  *
 459  * Return: 0 if successful, negative error code otherwise
 460  */
 461 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
 462 {
 463         if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_HIBERNATION)
 464                 return -ENOTSUPP;
 465
 466         if (is_host)
 467                 return dwc2_host_enter_hibernation(hsotg);
 468         else
 469                 return dwc2_gadget_enter_hibernation(hsotg);
 470 }
 471
 472 /*
 473  * dwc2_exit_hibernation() - Common function to exit from hibernation.
 474  *
 475  * @hsotg: Programming view of the DWC_otg controller
 476  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
 477  * @reset: Enabled in case of restore with reset.
 478  * @is_host: True if core is in host mode.
 479  *
 480  * Return: 0 if successful, negative error code otherwise
 481  */
 482 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
 483                           int reset, int is_host)
 484 {
 485         if (is_host)
 486                 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
 487         else
 488                 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
 489 }
 490
 491 /*
 492  * Do core a soft reset of the core.  Be careful with this because it
 493  * resets all the internal state machines of the core.
 494  */
 495 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
 496 {
 497         u32 greset;
 498         bool wait_for_host_mode = false;
 499
 500         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 501
 502         /*
 503          * If the current mode is host, either due to the force mode
 504          * bit being set (which persists after core reset) or the
 505          * connector id pin, a core soft reset will temporarily reset
 506          * the mode to device. A delay from the IDDIG debounce filter
 507          * will occur before going back to host mode.
 508          *
 509          * Determine whether we will go back into host mode after a
 510          * reset and account for this delay after the reset.
 511          */
 512         if (dwc2_iddig_filter_enabled(hsotg)) {
 513                 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 514                 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 515
 516                 if (!(gotgctl & GOTGCTL_CONID_B) ||
 517                     (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
 518                         wait_for_host_mode = true;
 519                 }
 520         }
 521
 522         /* Core Soft Reset */
 523         greset = dwc2_readl(hsotg->regs + GRSTCTL);
 524         greset |= GRSTCTL_CSFTRST;
 525         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 526
 527         if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {
 528                 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
 529                          __func__);
 530                 return -EBUSY;
 531         }
 532
 533         /* Wait for AHB master IDLE state */
 534         if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 50)) {
 535                 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
 536                          __func__);
 537                 return -EBUSY;
 538         }
 539
 540         if (wait_for_host_mode && !skip_wait)
 541                 dwc2_wait_for_mode(hsotg, true);
 542
 543         return 0;
 544 }
 545
 546 /**
 547  * dwc2_force_mode() - Force the mode of the controller.
 548  *
 549  * Forcing the mode is needed for two cases:
 550  *
 551  * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
 552  * controller to stay in a particular mode regardless of ID pin
 553  * changes. We do this once during probe.
 554  *
 555  * 2) During probe we want to read reset values of the hw
 556  * configuration registers that are only available in either host or
 557  * device mode. We may need to force the mode if the current mode does
 558  * not allow us to access the register in the mode that we want.
 559  *
 560  * In either case it only makes sense to force the mode if the
 561  * controller hardware is OTG capable.
 562  *
 563  * Checks are done in this function to determine whether doing a force
 564  * would be valid or not.
 565  *
 566  * If a force is done, it requires a IDDIG debounce filter delay if
 567  * the filter is configured and enabled. We poll the current mode of
 568  * the controller to account for this delay.
 569  *
 570  * @hsotg: Programming view of DWC_otg controller
 571  * @host: Host mode flag
 572  */
 573 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
 574 {
 575         u32 gusbcfg;
 576         u32 set;
 577         u32 clear;
 578
 579         dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
 580
 581         /*
 582          * Force mode has no effect if the hardware is not OTG.
 583          */
 584         if (!dwc2_hw_is_otg(hsotg))
 585                 return;
 586
 587         /*
 588          * If dr_mode is either peripheral or host only, there is no
 589          * need to ever force the mode to the opposite mode.
 590          */
 591         if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
 592                 return;
 593
 594         if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
 595                 return;
 596
 597         gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 598
 599         set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
 600         clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
 601
 602         gusbcfg &= ~clear;
 603         gusbcfg |= set;
 604         dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 605
 606         dwc2_wait_for_mode(hsotg, host);
 607         return;
 608 }
 609
 610 /**
 611  * dwc2_clear_force_mode() - Clears the force mode bits.
 612  *
 613  * After clearing the bits, wait up to 100 ms to account for any
 614  * potential IDDIG filter delay. We can't know if we expect this delay
 615  * or not because the value of the connector ID status is affected by
 616  * the force mode. We only need to call this once during probe if
 617  * dr_mode == OTG.
 618  *
 619  * @hsotg: Programming view of DWC_otg controller
 620  */
 621 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
 622 {
 623         u32 gusbcfg;
 624
 625         if (!dwc2_hw_is_otg(hsotg))
 626                 return;
 627
 628         dev_dbg(hsotg->dev, "Clearing force mode bits\n");
 629
 630         gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 631         gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
 632         gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
 633         dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 634
 635         if (dwc2_iddig_filter_enabled(hsotg))
 636                 msleep(100);
 637 }
 638
 639 /*
 640  * Sets or clears force mode based on the dr_mode parameter.
 641  */
 642 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
 643 {
 644         switch (hsotg->dr_mode) {
 645         case USB_DR_MODE_HOST:
 646                 /*
 647                  * NOTE: This is required for some rockchip soc based
 648                  * platforms on their host-only dwc2.
 649                  */
 650                 if (!dwc2_hw_is_otg(hsotg))
 651                         msleep(50);
 652
 653                 break;
 654         case USB_DR_MODE_PERIPHERAL:
 655                 dwc2_force_mode(hsotg, false);
 656                 break;
 657         case USB_DR_MODE_OTG:
 658                 dwc2_clear_force_mode(hsotg);
 659                 break;
 660         default:
 661                 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
 662                          __func__, hsotg->dr_mode);
 663                 break;
 664         }
 665 }
 666
 667 /*
 668  * dwc2_enable_acg - enable active clock gating feature
 669  */
 670 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
 671 {
 672         if (hsotg->params.acg_enable) {
 673                 u32 pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1);
 674
 675                 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
 676                 pcgcctl1 |= PCGCCTL1_GATEEN;
 677                 dwc2_writel(pcgcctl1, hsotg->regs + PCGCCTL1);
 678         }
 679 }
 680
 681 /**
 682  * dwc2_dump_host_registers() - Prints the host registers
 683  *
 684  * @hsotg: Programming view of DWC_otg controller
 685  *
 686  * NOTE: This function will be removed once the peripheral controller code
 687  * is integrated and the driver is stable
 688  */
 689 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
 690 {
 691 #ifdef DEBUG
 692         u32 __iomem *addr;
 693         int i;
 694
 695         dev_dbg(hsotg->dev, "Host Global Registers\n");
 696         addr = hsotg->regs + HCFG;
 697         dev_dbg(hsotg->dev, "HCFG        @0x%08lX : 0x%08X\n",
 698                 (unsigned long)addr, dwc2_readl(addr));
 699         addr = hsotg->regs + HFIR;
 700         dev_dbg(hsotg->dev, "HFIR        @0x%08lX : 0x%08X\n",
 701                 (unsigned long)addr, dwc2_readl(addr));
 702         addr = hsotg->regs + HFNUM;
 703         dev_dbg(hsotg->dev, "HFNUM       @0x%08lX : 0x%08X\n",
 704                 (unsigned long)addr, dwc2_readl(addr));
 705         addr = hsotg->regs + HPTXSTS;
 706         dev_dbg(hsotg->dev, "HPTXSTS     @0x%08lX : 0x%08X\n",
 707                 (unsigned long)addr, dwc2_readl(addr));
 708         addr = hsotg->regs + HAINT;
 709         dev_dbg(hsotg->dev, "HAINT       @0x%08lX : 0x%08X\n",
 710                 (unsigned long)addr, dwc2_readl(addr));
 711         addr = hsotg->regs + HAINTMSK;
 712         dev_dbg(hsotg->dev, "HAINTMSK    @0x%08lX : 0x%08X\n",
 713                 (unsigned long)addr, dwc2_readl(addr));
 714         if (hsotg->params.dma_desc_enable) {
 715                 addr = hsotg->regs + HFLBADDR;
 716                 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
 717                         (unsigned long)addr, dwc2_readl(addr));
 718         }
 719
 720         addr = hsotg->regs + HPRT0;
 721         dev_dbg(hsotg->dev, "HPRT0       @0x%08lX : 0x%08X\n",
 722                 (unsigned long)addr, dwc2_readl(addr));
 723
 724         for (i = 0; i < hsotg->params.host_channels; i++) {
 725                 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
 726                 addr = hsotg->regs + HCCHAR(i);
 727                 dev_dbg(hsotg->dev, "HCCHAR      @0x%08lX : 0x%08X\n",
 728                         (unsigned long)addr, dwc2_readl(addr));
 729                 addr = hsotg->regs + HCSPLT(i);
 730                 dev_dbg(hsotg->dev, "HCSPLT      @0x%08lX : 0x%08X\n",
 731                         (unsigned long)addr, dwc2_readl(addr));
 732                 addr = hsotg->regs + HCINT(i);
 733                 dev_dbg(hsotg->dev, "HCINT       @0x%08lX : 0x%08X\n",
 734                         (unsigned long)addr, dwc2_readl(addr));
 735                 addr = hsotg->regs + HCINTMSK(i);
 736                 dev_dbg(hsotg->dev, "HCINTMSK    @0x%08lX : 0x%08X\n",
 737                         (unsigned long)addr, dwc2_readl(addr));
 738                 addr = hsotg->regs + HCTSIZ(i);
 739                 dev_dbg(hsotg->dev, "HCTSIZ      @0x%08lX : 0x%08X\n",
 740                         (unsigned long)addr, dwc2_readl(addr));
 741                 addr = hsotg->regs + HCDMA(i);
 742                 dev_dbg(hsotg->dev, "HCDMA       @0x%08lX : 0x%08X\n",
 743                         (unsigned long)addr, dwc2_readl(addr));
 744                 if (hsotg->params.dma_desc_enable) {
 745                         addr = hsotg->regs + HCDMAB(i);
 746                         dev_dbg(hsotg->dev, "HCDMAB      @0x%08lX : 0x%08X\n",
 747                                 (unsigned long)addr, dwc2_readl(addr));
 748                 }
 749         }
 750 #endif
 751 }
 752
 753 /**
 754  * dwc2_dump_global_registers() - Prints the core global registers
 755  *
 756  * @hsotg: Programming view of DWC_otg controller
 757  *
 758  * NOTE: This function will be removed once the peripheral controller code
 759  * is integrated and the driver is stable
 760  */
 761 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
 762 {
 763 #ifdef DEBUG
 764         u32 __iomem *addr;
 765
 766         dev_dbg(hsotg->dev, "Core Global Registers\n");
 767         addr = hsotg->regs + GOTGCTL;
 768         dev_dbg(hsotg->dev, "GOTGCTL     @0x%08lX : 0x%08X\n",
 769                 (unsigned long)addr, dwc2_readl(addr));
 770         addr = hsotg->regs + GOTGINT;
 771         dev_dbg(hsotg->dev, "GOTGINT     @0x%08lX : 0x%08X\n",
 772                 (unsigned long)addr, dwc2_readl(addr));
 773         addr = hsotg->regs + GAHBCFG;
 774         dev_dbg(hsotg->dev, "GAHBCFG     @0x%08lX : 0x%08X\n",
 775                 (unsigned long)addr, dwc2_readl(addr));
 776         addr = hsotg->regs + GUSBCFG;
 777         dev_dbg(hsotg->dev, "GUSBCFG     @0x%08lX : 0x%08X\n",
 778                 (unsigned long)addr, dwc2_readl(addr));
 779         addr = hsotg->regs + GRSTCTL;
 780         dev_dbg(hsotg->dev, "GRSTCTL     @0x%08lX : 0x%08X\n",
 781                 (unsigned long)addr, dwc2_readl(addr));
 782         addr = hsotg->regs + GINTSTS;
 783         dev_dbg(hsotg->dev, "GINTSTS     @0x%08lX : 0x%08X\n",
 784                 (unsigned long)addr, dwc2_readl(addr));
 785         addr = hsotg->regs + GINTMSK;
 786         dev_dbg(hsotg->dev, "GINTMSK     @0x%08lX : 0x%08X\n",
 787                 (unsigned long)addr, dwc2_readl(addr));
 788         addr = hsotg->regs + GRXSTSR;
 789         dev_dbg(hsotg->dev, "GRXSTSR     @0x%08lX : 0x%08X\n",
 790                 (unsigned long)addr, dwc2_readl(addr));
 791         addr = hsotg->regs + GRXFSIZ;
 792         dev_dbg(hsotg->dev, "GRXFSIZ     @0x%08lX : 0x%08X\n",
 793                 (unsigned long)addr, dwc2_readl(addr));
 794         addr = hsotg->regs + GNPTXFSIZ;
 795         dev_dbg(hsotg->dev, "GNPTXFSIZ   @0x%08lX : 0x%08X\n",
 796                 (unsigned long)addr, dwc2_readl(addr));
 797         addr = hsotg->regs + GNPTXSTS;
 798         dev_dbg(hsotg->dev, "GNPTXSTS    @0x%08lX : 0x%08X\n",
 799                 (unsigned long)addr, dwc2_readl(addr));
 800         addr = hsotg->regs + GI2CCTL;
 801         dev_dbg(hsotg->dev, "GI2CCTL     @0x%08lX : 0x%08X\n",
 802                 (unsigned long)addr, dwc2_readl(addr));
 803         addr = hsotg->regs + GPVNDCTL;
 804         dev_dbg(hsotg->dev, "GPVNDCTL    @0x%08lX : 0x%08X\n",
 805                 (unsigned long)addr, dwc2_readl(addr));
 806         addr = hsotg->regs + GGPIO;
 807         dev_dbg(hsotg->dev, "GGPIO       @0x%08lX : 0x%08X\n",
 808                 (unsigned long)addr, dwc2_readl(addr));
 809         addr = hsotg->regs + GUID;
 810         dev_dbg(hsotg->dev, "GUID        @0x%08lX : 0x%08X\n",
 811                 (unsigned long)addr, dwc2_readl(addr));
 812         addr = hsotg->regs + GSNPSID;
 813         dev_dbg(hsotg->dev, "GSNPSID     @0x%08lX : 0x%08X\n",
 814                 (unsigned long)addr, dwc2_readl(addr));
 815         addr = hsotg->regs + GHWCFG1;
 816         dev_dbg(hsotg->dev, "GHWCFG1     @0x%08lX : 0x%08X\n",
 817                 (unsigned long)addr, dwc2_readl(addr));
 818         addr = hsotg->regs + GHWCFG2;
 819         dev_dbg(hsotg->dev, "GHWCFG2     @0x%08lX : 0x%08X\n",
 820                 (unsigned long)addr, dwc2_readl(addr));
 821         addr = hsotg->regs + GHWCFG3;
 822         dev_dbg(hsotg->dev, "GHWCFG3     @0x%08lX : 0x%08X\n",
 823                 (unsigned long)addr, dwc2_readl(addr));
 824         addr = hsotg->regs + GHWCFG4;
 825         dev_dbg(hsotg->dev, "GHWCFG4     @0x%08lX : 0x%08X\n",
 826                 (unsigned long)addr, dwc2_readl(addr));
 827         addr = hsotg->regs + GLPMCFG;
 828         dev_dbg(hsotg->dev, "GLPMCFG     @0x%08lX : 0x%08X\n",
 829                 (unsigned long)addr, dwc2_readl(addr));
 830         addr = hsotg->regs + GPWRDN;
 831         dev_dbg(hsotg->dev, "GPWRDN      @0x%08lX : 0x%08X\n",
 832                 (unsigned long)addr, dwc2_readl(addr));
 833         addr = hsotg->regs + GDFIFOCFG;
 834         dev_dbg(hsotg->dev, "GDFIFOCFG   @0x%08lX : 0x%08X\n",
 835                 (unsigned long)addr, dwc2_readl(addr));
 836         addr = hsotg->regs + HPTXFSIZ;
 837         dev_dbg(hsotg->dev, "HPTXFSIZ    @0x%08lX : 0x%08X\n",
 838                 (unsigned long)addr, dwc2_readl(addr));
 839
 840         addr = hsotg->regs + PCGCTL;
 841         dev_dbg(hsotg->dev, "PCGCTL      @0x%08lX : 0x%08X\n",
 842                 (unsigned long)addr, dwc2_readl(addr));
 843 #endif
 844 }
 845
 846 /**
 847  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
 848  *
 849  * @hsotg: Programming view of DWC_otg controller
 850  * @num:   Tx FIFO to flush
 851  */
 852 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
 853 {
 854         u32 greset;
 855
 856         dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
 857
 858         /* Wait for AHB master IDLE state */
 859         if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
 860                 dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",
 861                          __func__);
 862
 863         greset = GRSTCTL_TXFFLSH;
 864         greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
 865         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 866
 867         if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
 868                 dev_warn(hsotg->dev, "%s:  HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
 869                          __func__);
 870
 871         /* Wait for at least 3 PHY Clocks */
 872         udelay(1);
 873 }
 874
 875 /**
 876  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
 877  *
 878  * @hsotg: Programming view of DWC_otg controller
 879  */
 880 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
 881 {
 882         u32 greset;
 883
 884         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 885
 886         /* Wait for AHB master IDLE state */
 887         if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
 888                 dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",
 889                          __func__);
 890
 891         greset = GRSTCTL_RXFFLSH;
 892         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 893
 894         /* Wait for RxFIFO flush done */
 895         if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
 896                 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
 897                          __func__);
 898
 899         /* Wait for at least 3 PHY Clocks */
 900         udelay(1);
 901 }
 902
 903 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
 904 {
 905         if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
 906                 return false;
 907         else
 908                 return true;
 909 }
 910
 911 /**
 912  * dwc2_enable_global_interrupts() - Enables the controller's Global
 913  * Interrupt in the AHB Config register
 914  *
 915  * @hsotg: Programming view of DWC_otg controller
 916  */
 917 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
 918 {
 919         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 920
 921         ahbcfg |= GAHBCFG_GLBL_INTR_EN;
 922         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 923 }
 924
 925 /**
 926  * dwc2_disable_global_interrupts() - Disables the controller's Global
 927  * Interrupt in the AHB Config register
 928  *
 929  * @hsotg: Programming view of DWC_otg controller
 930  */
 931 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
 932 {
 933         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 934
 935         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
 936         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 937 }
 938
 939 /* Returns the controller's GHWCFG2.OTG_MODE. */
 940 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
 941 {
 942         u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
 943
 944         return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 945                 GHWCFG2_OP_MODE_SHIFT;
 946 }
 947
 948 /* Returns true if the controller is capable of DRD. */
 949 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
 950 {
 951         unsigned int op_mode = dwc2_op_mode(hsotg);
 952
 953         return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
 954                 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
 955                 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
 956 }
 957
 958 /* Returns true if the controller is host-only. */
 959 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
 960 {
 961         unsigned int op_mode = dwc2_op_mode(hsotg);
 962
 963         return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
 964                 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
 965 }
 966
 967 /* Returns true if the controller is device-only. */
 968 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
 969 {
 970         unsigned int op_mode = dwc2_op_mode(hsotg);
 971
 972         return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
 973                 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
 974 }
 975
 976 /**
 977  * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
 978  * @hsotg: Programming view of DWC_otg controller.
 979  * @offset: Register's offset where bit/bits must be set.
 980  * @mask: Mask of the bit/bits which must be set.
 981  * @timeout: Timeout to wait.
 982  *
 983  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
 984  */
 985 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
 986                             u32 timeout)
 987 {
 988         u32 i;
 989
 990         for (i = 0; i < timeout; i++) {
 991                 if (dwc2_readl(hsotg->regs + offset) & mask)
 992                         return 0;
 993                 udelay(1);
 994         }
 995
 996         return -ETIMEDOUT;
 997 }
 998
 999 /**
1000  * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
1001  * @hsotg: Programming view of DWC_otg controller.
1002  * @offset: Register's offset where bit/bits must be set.
1003  * @mask: Mask of the bit/bits which must be set.
1004  * @timeout: Timeout to wait.
1005  *
1006  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
1007  */
1008 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
1009                               u32 timeout)
1010 {
1011         u32 i;
1012
1013         for (i = 0; i < timeout; i++) {
1014                 if (!(dwc2_readl(hsotg->regs + offset) & mask))
1015                         return 0;
1016                 udelay(1);
1017         }
1018
1019         return -ETIMEDOUT;
1020 }
1021
1022 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1023 MODULE_AUTHOR("Synopsys, Inc.");
1024 MODULE_LICENSE("Dual BSD/GPL");