1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - ChipIdea USB IP core family device controller
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 * Copyright (C) 2020 NXP
12 * - Four transfers are supported, usbtest is passed
13 * - USB Certification for gadget: CH9 and Mass Storage are passed
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/extcon.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/module.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/otg.h>
34 #include <linux/usb/chipidea.h>
35 #include <linux/usb/of.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/usb/ehci_def.h>
47 /* Controller register map */
48 static const u8 ci_regs_nolpm[] = {
49 [CAP_CAPLENGTH] = 0x00U,
50 [CAP_HCCPARAMS] = 0x08U,
51 [CAP_DCCPARAMS] = 0x24U,
52 [CAP_TESTMODE] = 0x38U,
57 [OP_DEVICEADDR] = 0x14U,
58 [OP_ENDPTLISTADDR] = 0x18U,
60 [OP_BURSTSIZE] = 0x20U,
61 [OP_ULPI_VIEWPORT] = 0x30U,
66 [OP_ENDPTSETUPSTAT] = 0x6CU,
67 [OP_ENDPTPRIME] = 0x70U,
68 [OP_ENDPTFLUSH] = 0x74U,
69 [OP_ENDPTSTAT] = 0x78U,
70 [OP_ENDPTCOMPLETE] = 0x7CU,
71 [OP_ENDPTCTRL] = 0x80U,
74 static const u8 ci_regs_lpm[] = {
75 [CAP_CAPLENGTH] = 0x00U,
76 [CAP_HCCPARAMS] = 0x08U,
77 [CAP_DCCPARAMS] = 0x24U,
78 [CAP_TESTMODE] = 0xFCU,
83 [OP_DEVICEADDR] = 0x14U,
84 [OP_ENDPTLISTADDR] = 0x18U,
86 [OP_BURSTSIZE] = 0x20U,
87 [OP_ULPI_VIEWPORT] = 0x30U,
92 [OP_ENDPTSETUPSTAT] = 0xD8U,
93 [OP_ENDPTPRIME] = 0xDCU,
94 [OP_ENDPTFLUSH] = 0xE0U,
95 [OP_ENDPTSTAT] = 0xE4U,
96 [OP_ENDPTCOMPLETE] = 0xE8U,
97 [OP_ENDPTCTRL] = 0xECU,
100 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
104 for (i = 0; i < OP_ENDPTCTRL; i++)
105 ci->hw_bank.regmap[i] =
106 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
107 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
109 for (; i <= OP_LAST; i++)
110 ci->hw_bank.regmap[i] = ci->hw_bank.op +
111 4 * (i - OP_ENDPTCTRL) +
113 ? ci_regs_lpm[OP_ENDPTCTRL]
114 : ci_regs_nolpm[OP_ENDPTCTRL]);
118 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
120 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
121 enum ci_revision rev = CI_REVISION_UNKNOWN;
124 rev = hw_read_id_reg(ci, ID_ID, REVISION)
126 rev += CI_REVISION_20;
127 } else if (ver == 0x0) {
128 rev = CI_REVISION_1X;
135 * hw_read_intr_enable: returns interrupt enable register
137 * @ci: the controller
139 * This function returns register data
141 u32 hw_read_intr_enable(struct ci_hdrc *ci)
143 return hw_read(ci, OP_USBINTR, ~0);
147 * hw_read_intr_status: returns interrupt status register
149 * @ci: the controller
151 * This function returns register data
153 u32 hw_read_intr_status(struct ci_hdrc *ci)
155 return hw_read(ci, OP_USBSTS, ~0);
159 * hw_port_test_set: writes port test mode (execute without interruption)
160 * @ci: the controller
163 * This function returns an error code
165 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
167 const u8 TEST_MODE_MAX = 7;
169 if (mode > TEST_MODE_MAX)
172 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
177 * hw_port_test_get: reads port test mode value
179 * @ci: the controller
181 * This function returns port test mode value
183 u8 hw_port_test_get(struct ci_hdrc *ci)
185 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
188 static void hw_wait_phy_stable(void)
191 * The phy needs some delay to output the stable status from low
192 * power mode. And for OTGSC, the status inputs are debounced
193 * using a 1 ms time constant, so, delay 2ms for controller to get
194 * the stable status, like vbus and id when the phy leaves low power.
196 usleep_range(2000, 2500);
199 /* The PHY enters/leaves low power mode */
200 static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
202 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
203 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
206 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
207 PORTSC_PHCD(ci->hw_bank.lpm));
208 else if (!enable && lpm)
209 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
213 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
215 return ci->platdata->enter_lpm(ci, enable);
218 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
222 /* bank is a module variable */
223 ci->hw_bank.abs = base;
225 ci->hw_bank.cap = ci->hw_bank.abs;
226 ci->hw_bank.cap += ci->platdata->capoffset;
227 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
229 hw_alloc_regmap(ci, false);
230 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
231 __ffs(HCCPARAMS_LEN);
232 ci->hw_bank.lpm = reg;
234 hw_alloc_regmap(ci, !!reg);
235 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
236 ci->hw_bank.size += OP_LAST;
237 ci->hw_bank.size /= sizeof(u32);
239 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
240 __ffs(DCCPARAMS_DEN);
241 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
243 if (ci->hw_ep_max > ENDPT_MAX)
246 ci_hdrc_enter_lpm(ci, false);
248 /* Disable all interrupts bits */
249 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
251 /* Clear all interrupts status bits*/
252 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
254 ci->rev = ci_get_revision(ci);
257 "revision: %d, lpm: %d; cap: %px op: %px\n",
258 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
260 /* setup lock mode ? */
262 /* ENDPTSETUPSTAT is '0' by default */
264 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
269 void hw_phymode_configure(struct ci_hdrc *ci)
271 u32 portsc, lpm, sts = 0;
273 switch (ci->platdata->phy_mode) {
274 case USBPHY_INTERFACE_MODE_UTMI:
275 portsc = PORTSC_PTS(PTS_UTMI);
276 lpm = DEVLC_PTS(PTS_UTMI);
278 case USBPHY_INTERFACE_MODE_UTMIW:
279 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
280 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
282 case USBPHY_INTERFACE_MODE_ULPI:
283 portsc = PORTSC_PTS(PTS_ULPI);
284 lpm = DEVLC_PTS(PTS_ULPI);
286 case USBPHY_INTERFACE_MODE_SERIAL:
287 portsc = PORTSC_PTS(PTS_SERIAL);
288 lpm = DEVLC_PTS(PTS_SERIAL);
291 case USBPHY_INTERFACE_MODE_HSIC:
292 portsc = PORTSC_PTS(PTS_HSIC);
293 lpm = DEVLC_PTS(PTS_HSIC);
299 if (ci->hw_bank.lpm) {
300 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
302 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
304 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
306 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
309 EXPORT_SYMBOL_GPL(hw_phymode_configure);
312 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
314 * @ci: the controller
316 * This function returns an error code if the phy failed to init
318 static int _ci_usb_phy_init(struct ci_hdrc *ci)
323 ret = phy_init(ci->phy);
327 ret = phy_power_on(ci->phy);
333 ret = usb_phy_init(ci->usb_phy);
340 * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
342 * @ci: the controller
344 static void ci_usb_phy_exit(struct ci_hdrc *ci)
346 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
350 phy_power_off(ci->phy);
353 usb_phy_shutdown(ci->usb_phy);
358 * ci_usb_phy_init: initialize phy according to different phy type
359 * @ci: the controller
361 * This function returns an error code if usb_phy_init has failed
363 static int ci_usb_phy_init(struct ci_hdrc *ci)
367 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
370 switch (ci->platdata->phy_mode) {
371 case USBPHY_INTERFACE_MODE_UTMI:
372 case USBPHY_INTERFACE_MODE_UTMIW:
373 case USBPHY_INTERFACE_MODE_HSIC:
374 ret = _ci_usb_phy_init(ci);
376 hw_wait_phy_stable();
379 hw_phymode_configure(ci);
381 case USBPHY_INTERFACE_MODE_ULPI:
382 case USBPHY_INTERFACE_MODE_SERIAL:
383 hw_phymode_configure(ci);
384 ret = _ci_usb_phy_init(ci);
389 ret = _ci_usb_phy_init(ci);
391 hw_wait_phy_stable();
399 * ci_platform_configure: do controller configure
400 * @ci: the controller
403 void ci_platform_configure(struct ci_hdrc *ci)
405 bool is_device_mode, is_host_mode;
407 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
408 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
410 if (is_device_mode) {
411 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
413 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
414 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
419 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
421 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
422 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
426 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
428 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
430 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
433 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
434 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
436 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
438 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
439 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
440 ci->platdata->ahb_burst_config);
442 /* override burst size, take effect only when ahb_burst_config is 0 */
443 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
444 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
445 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
446 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
448 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
449 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
450 ci->platdata->rx_burst_size);
455 * hw_controller_reset: do controller reset
456 * @ci: the controller
458 * This function returns an error code
460 static int hw_controller_reset(struct ci_hdrc *ci)
464 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
465 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
475 * hw_device_reset: resets chip (execute without interruption)
476 * @ci: the controller
478 * This function returns an error code
480 int hw_device_reset(struct ci_hdrc *ci)
484 /* should flush & stop before reset */
485 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
486 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
488 ret = hw_controller_reset(ci);
490 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
494 if (ci->platdata->notify_event) {
495 ret = ci->platdata->notify_event(ci,
496 CI_HDRC_CONTROLLER_RESET_EVENT);
501 /* USBMODE should be configured step by step */
502 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
503 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
505 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
507 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
508 dev_err(ci->dev, "cannot enter in %s device mode\n",
510 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
514 ci_platform_configure(ci);
519 static irqreturn_t ci_irq_handler(int irq, void *data)
521 struct ci_hdrc *ci = data;
522 irqreturn_t ret = IRQ_NONE;
526 disable_irq_nosync(irq);
527 ci->wakeup_int = true;
528 pm_runtime_get(ci->dev);
533 otgsc = hw_read_otgsc(ci, ~0);
534 if (ci_otg_is_fsm_mode(ci)) {
535 ret = ci_otg_fsm_irq(ci);
536 if (ret == IRQ_HANDLED)
542 * Handle id change interrupt, it indicates device/host function
545 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
547 /* Clear ID change irq status */
548 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
549 ci_otg_queue_work(ci);
554 * Handle vbus change interrupt, it indicates device connection
555 * and disconnection events.
557 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
558 ci->b_sess_valid_event = true;
560 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
561 ci_otg_queue_work(ci);
565 /* Handle device/host interrupt */
566 if (ci->role != CI_ROLE_END)
567 ret = ci_role(ci)->irq(ci);
572 static void ci_irq(struct ci_hdrc *ci)
576 local_irq_save(flags);
577 ci_irq_handler(ci->irq, ci);
578 local_irq_restore(flags);
581 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
584 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
585 struct ci_hdrc *ci = cbl->ci;
587 cbl->connected = event;
594 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
596 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
600 spin_lock_irqsave(&ci->lock, flags);
601 role = ci_role_to_usb_role(ci);
602 spin_unlock_irqrestore(&ci->lock, flags);
607 static int ci_usb_role_switch_set(struct usb_role_switch *sw,
610 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
611 struct ci_hdrc_cable *cable = NULL;
612 enum usb_role current_role = ci_role_to_usb_role(ci);
613 enum ci_role ci_role = usb_role_to_ci_role(role);
616 if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) ||
617 (current_role == role))
620 pm_runtime_get_sync(ci->dev);
621 /* Stop current role */
622 spin_lock_irqsave(&ci->lock, flags);
623 if (current_role == USB_ROLE_DEVICE)
624 cable = &ci->platdata->vbus_extcon;
625 else if (current_role == USB_ROLE_HOST)
626 cable = &ci->platdata->id_extcon;
629 cable->changed = true;
630 cable->connected = false;
632 spin_unlock_irqrestore(&ci->lock, flags);
633 if (ci->wq && role != USB_ROLE_NONE)
634 flush_workqueue(ci->wq);
635 spin_lock_irqsave(&ci->lock, flags);
640 /* Start target role */
641 if (role == USB_ROLE_DEVICE)
642 cable = &ci->platdata->vbus_extcon;
643 else if (role == USB_ROLE_HOST)
644 cable = &ci->platdata->id_extcon;
647 cable->changed = true;
648 cable->connected = true;
651 spin_unlock_irqrestore(&ci->lock, flags);
652 pm_runtime_put_sync(ci->dev);
657 static struct usb_role_switch_desc ci_role_switch = {
658 .set = ci_usb_role_switch_set,
659 .get = ci_usb_role_switch_get,
660 .allow_userspace_control = true,
663 static int ci_get_platdata(struct device *dev,
664 struct ci_hdrc_platform_data *platdata)
666 struct extcon_dev *ext_vbus, *ext_id;
667 struct ci_hdrc_cable *cable;
670 if (!platdata->phy_mode)
671 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
673 if (!platdata->dr_mode)
674 platdata->dr_mode = usb_get_dr_mode(dev);
676 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
677 platdata->dr_mode = USB_DR_MODE_OTG;
679 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
680 /* Get the vbus regulator */
681 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
682 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
683 return -EPROBE_DEFER;
684 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
685 /* no vbus regulator is needed */
686 platdata->reg_vbus = NULL;
687 } else if (IS_ERR(platdata->reg_vbus)) {
688 dev_err(dev, "Getting regulator error: %ld\n",
689 PTR_ERR(platdata->reg_vbus));
690 return PTR_ERR(platdata->reg_vbus);
692 /* Get TPL support */
693 if (!platdata->tpl_support)
694 platdata->tpl_support =
695 of_usb_host_tpl_support(dev->of_node);
698 if (platdata->dr_mode == USB_DR_MODE_OTG) {
699 /* We can support HNP and SRP of OTG 2.0 */
700 platdata->ci_otg_caps.otg_rev = 0x0200;
701 platdata->ci_otg_caps.hnp_support = true;
702 platdata->ci_otg_caps.srp_support = true;
704 /* Update otg capabilities by DT properties */
705 ret = of_usb_update_otg_caps(dev->of_node,
706 &platdata->ci_otg_caps);
711 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
712 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
714 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
715 &platdata->phy_clkgate_delay_us);
717 platdata->itc_setting = 1;
719 of_property_read_u32(dev->of_node, "itc-setting",
720 &platdata->itc_setting);
722 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
723 &platdata->ahb_burst_config);
725 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
726 } else if (ret != -EINVAL) {
727 dev_err(dev, "failed to get ahb-burst-config\n");
731 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
732 &platdata->tx_burst_size);
734 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
735 } else if (ret != -EINVAL) {
736 dev_err(dev, "failed to get tx-burst-size-dword\n");
740 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
741 &platdata->rx_burst_size);
743 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
744 } else if (ret != -EINVAL) {
745 dev_err(dev, "failed to get rx-burst-size-dword\n");
749 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
750 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
752 ext_id = ERR_PTR(-ENODEV);
753 ext_vbus = ERR_PTR(-ENODEV);
754 if (of_property_read_bool(dev->of_node, "extcon")) {
755 /* Each one of them is not mandatory */
756 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
757 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
758 return PTR_ERR(ext_vbus);
760 ext_id = extcon_get_edev_by_phandle(dev, 1);
761 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
762 return PTR_ERR(ext_id);
765 cable = &platdata->vbus_extcon;
766 cable->nb.notifier_call = ci_cable_notifier;
767 cable->edev = ext_vbus;
769 if (!IS_ERR(ext_vbus)) {
770 ret = extcon_get_state(cable->edev, EXTCON_USB);
772 cable->connected = true;
774 cable->connected = false;
777 cable = &platdata->id_extcon;
778 cable->nb.notifier_call = ci_cable_notifier;
779 cable->edev = ext_id;
781 if (!IS_ERR(ext_id)) {
782 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
784 cable->connected = true;
786 cable->connected = false;
789 if (device_property_read_bool(dev, "usb-role-switch"))
790 ci_role_switch.fwnode = dev->fwnode;
792 platdata->pctl = devm_pinctrl_get(dev);
793 if (!IS_ERR(platdata->pctl)) {
794 struct pinctrl_state *p;
796 p = pinctrl_lookup_state(platdata->pctl, "default");
798 platdata->pins_default = p;
800 p = pinctrl_lookup_state(platdata->pctl, "host");
802 platdata->pins_host = p;
804 p = pinctrl_lookup_state(platdata->pctl, "device");
806 platdata->pins_device = p;
809 if (!platdata->enter_lpm)
810 platdata->enter_lpm = ci_hdrc_enter_lpm_common;
815 static int ci_extcon_register(struct ci_hdrc *ci)
817 struct ci_hdrc_cable *id, *vbus;
820 id = &ci->platdata->id_extcon;
822 if (!IS_ERR_OR_NULL(id->edev)) {
823 ret = devm_extcon_register_notifier(ci->dev, id->edev,
824 EXTCON_USB_HOST, &id->nb);
826 dev_err(ci->dev, "register ID failed\n");
831 vbus = &ci->platdata->vbus_extcon;
833 if (!IS_ERR_OR_NULL(vbus->edev)) {
834 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
835 EXTCON_USB, &vbus->nb);
837 dev_err(ci->dev, "register VBUS failed\n");
845 static DEFINE_IDA(ci_ida);
847 struct platform_device *ci_hdrc_add_device(struct device *dev,
848 struct resource *res, int nres,
849 struct ci_hdrc_platform_data *platdata)
851 struct platform_device *pdev;
854 ret = ci_get_platdata(dev, platdata);
858 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
862 pdev = platform_device_alloc("ci_hdrc", id);
868 pdev->dev.parent = dev;
869 device_set_of_node_from_dev(&pdev->dev, dev);
871 ret = platform_device_add_resources(pdev, res, nres);
875 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
879 ret = platform_device_add(pdev);
886 platform_device_put(pdev);
888 ida_simple_remove(&ci_ida, id);
891 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
893 void ci_hdrc_remove_device(struct platform_device *pdev)
896 platform_device_unregister(pdev);
897 ida_simple_remove(&ci_ida, id);
899 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
902 * ci_hdrc_query_available_role: get runtime available operation mode
904 * The glue layer can get current operation mode (host/peripheral/otg)
905 * This function should be called after ci core device has created.
907 * @pdev: the platform device of ci core.
909 * Return runtime usb_dr_mode.
911 enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
913 struct ci_hdrc *ci = platform_get_drvdata(pdev);
916 return USB_DR_MODE_UNKNOWN;
917 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
918 return USB_DR_MODE_OTG;
919 else if (ci->roles[CI_ROLE_HOST])
920 return USB_DR_MODE_HOST;
921 else if (ci->roles[CI_ROLE_GADGET])
922 return USB_DR_MODE_PERIPHERAL;
924 return USB_DR_MODE_UNKNOWN;
926 EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
928 static inline void ci_role_destroy(struct ci_hdrc *ci)
930 ci_hdrc_gadget_destroy(ci);
931 ci_hdrc_host_destroy(ci);
932 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
933 ci_hdrc_otg_destroy(ci);
936 static void ci_get_otg_capable(struct ci_hdrc *ci)
938 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
941 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
942 DCCPARAMS_DC | DCCPARAMS_HC)
943 == (DCCPARAMS_DC | DCCPARAMS_HC));
945 dev_dbg(ci->dev, "It is OTG capable controller\n");
946 /* Disable and clear all OTG irq */
947 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
948 OTGSC_INT_STATUS_BITS);
952 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
955 struct ci_hdrc *ci = dev_get_drvdata(dev);
957 if (ci->role != CI_ROLE_END)
958 return sprintf(buf, "%s\n", ci_role(ci)->name);
963 static ssize_t role_store(struct device *dev,
964 struct device_attribute *attr, const char *buf, size_t n)
966 struct ci_hdrc *ci = dev_get_drvdata(dev);
970 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
971 dev_warn(dev, "Current configuration is not dual-role, quit\n");
975 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
976 if (!strncmp(buf, ci->roles[role]->name,
977 strlen(ci->roles[role]->name)))
980 if (role == CI_ROLE_END || role == ci->role)
983 pm_runtime_get_sync(dev);
984 disable_irq(ci->irq);
986 ret = ci_role_start(ci, role);
987 if (!ret && ci->role == CI_ROLE_GADGET)
988 ci_handle_vbus_change(ci);
990 pm_runtime_put_sync(dev);
992 return (ret == 0) ? n : ret;
994 static DEVICE_ATTR_RW(role);
996 static struct attribute *ci_attrs[] = {
1000 ATTRIBUTE_GROUPS(ci);
1002 static int ci_hdrc_probe(struct platform_device *pdev)
1004 struct device *dev = &pdev->dev;
1006 struct resource *res;
1009 enum usb_dr_mode dr_mode;
1011 if (!dev_get_platdata(dev)) {
1012 dev_err(dev, "platform data missing\n");
1016 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1017 base = devm_ioremap_resource(dev, res);
1019 return PTR_ERR(base);
1021 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
1025 spin_lock_init(&ci->lock);
1027 ci->platdata = dev_get_platdata(dev);
1028 ci->imx28_write_fix = !!(ci->platdata->flags &
1029 CI_HDRC_IMX28_WRITE_FIX);
1030 ci->supports_runtime_pm = !!(ci->platdata->flags &
1031 CI_HDRC_SUPPORTS_RUNTIME_PM);
1032 platform_set_drvdata(pdev, ci);
1034 ret = hw_device_init(ci, base);
1036 dev_err(dev, "can't initialize hardware\n");
1040 ret = ci_ulpi_init(ci);
1044 if (ci->platdata->phy) {
1045 ci->phy = ci->platdata->phy;
1046 } else if (ci->platdata->usb_phy) {
1047 ci->usb_phy = ci->platdata->usb_phy;
1049 /* Look for a generic PHY first */
1050 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1052 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1053 ret = -EPROBE_DEFER;
1055 } else if (IS_ERR(ci->phy)) {
1059 /* Look for a legacy USB PHY from device-tree next */
1061 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1064 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1065 ret = -EPROBE_DEFER;
1067 } else if (IS_ERR(ci->usb_phy)) {
1072 /* Look for any registered legacy USB PHY as last resort */
1073 if (!ci->phy && !ci->usb_phy) {
1074 ci->usb_phy = devm_usb_get_phy(dev->parent,
1077 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1078 ret = -EPROBE_DEFER;
1080 } else if (IS_ERR(ci->usb_phy)) {
1085 /* No USB PHY was found in the end */
1086 if (!ci->phy && !ci->usb_phy) {
1092 ret = ci_usb_phy_init(ci);
1094 dev_err(dev, "unable to init phy: %d\n", ret);
1098 ci->hw_bank.phys = res->start;
1100 ci->irq = platform_get_irq(pdev, 0);
1106 ci_get_otg_capable(ci);
1108 dr_mode = ci->platdata->dr_mode;
1109 /* initialize role(s) before the interrupt is requested */
1110 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1111 ret = ci_hdrc_host_init(ci);
1114 dev_info(dev, "doesn't support host\n");
1120 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1121 ret = ci_hdrc_gadget_init(ci);
1124 dev_info(dev, "doesn't support gadget\n");
1130 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1131 dev_err(dev, "no supported roles\n");
1136 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1137 ret = ci_hdrc_otg_init(ci);
1139 dev_err(dev, "init otg fails, ret = %d\n", ret);
1144 if (ci_role_switch.fwnode) {
1145 ci_role_switch.driver_data = ci;
1146 ci->role_switch = usb_role_switch_register(dev,
1148 if (IS_ERR(ci->role_switch)) {
1149 ret = PTR_ERR(ci->role_switch);
1154 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1156 ci->role = ci_otg_role(ci);
1157 /* Enable ID change irq */
1158 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1161 * If the controller is not OTG capable, but support
1162 * role switch, the defalt role is gadget, and the
1163 * user can switch it through debugfs.
1165 ci->role = CI_ROLE_GADGET;
1168 ci->role = ci->roles[CI_ROLE_HOST]
1173 if (!ci_otg_is_fsm_mode(ci)) {
1174 /* only update vbus status for peripheral */
1175 if (ci->role == CI_ROLE_GADGET) {
1176 /* Pull down DP for possible charger detection */
1177 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
1178 ci_handle_vbus_change(ci);
1181 ret = ci_role_start(ci, ci->role);
1183 dev_err(dev, "can't start %s role\n",
1189 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1190 ci->platdata->name, ci);
1194 ret = ci_extcon_register(ci);
1198 if (ci->supports_runtime_pm) {
1199 pm_runtime_set_active(&pdev->dev);
1200 pm_runtime_enable(&pdev->dev);
1201 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1202 pm_runtime_mark_last_busy(ci->dev);
1203 pm_runtime_use_autosuspend(&pdev->dev);
1206 if (ci_otg_is_fsm_mode(ci))
1207 ci_hdrc_otg_fsm_start(ci);
1209 device_set_wakeup_capable(&pdev->dev, true);
1210 dbg_create_files(ci);
1215 if (ci->role_switch)
1216 usb_role_switch_unregister(ci->role_switch);
1218 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1219 ci_hdrc_otg_destroy(ci);
1221 ci_hdrc_gadget_destroy(ci);
1223 ci_hdrc_host_destroy(ci);
1225 ci_usb_phy_exit(ci);
1232 static int ci_hdrc_remove(struct platform_device *pdev)
1234 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1236 if (ci->role_switch)
1237 usb_role_switch_unregister(ci->role_switch);
1239 if (ci->supports_runtime_pm) {
1240 pm_runtime_get_sync(&pdev->dev);
1241 pm_runtime_disable(&pdev->dev);
1242 pm_runtime_put_noidle(&pdev->dev);
1245 dbg_remove_files(ci);
1246 ci_role_destroy(ci);
1247 ci_hdrc_enter_lpm(ci, true);
1248 ci_usb_phy_exit(ci);
1255 /* Prepare wakeup by SRP before suspend */
1256 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1258 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1259 !hw_read_otgsc(ci, OTGSC_ID)) {
1260 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1262 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1267 /* Handle SRP when wakeup by data pulse */
1268 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1270 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1271 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1272 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1273 ci->fsm.a_srp_det = 1;
1274 ci->fsm.a_bus_drop = 0;
1278 ci_otg_queue_work(ci);
1282 static void ci_controller_suspend(struct ci_hdrc *ci)
1284 disable_irq(ci->irq);
1285 ci_hdrc_enter_lpm(ci, true);
1286 if (ci->platdata->phy_clkgate_delay_us)
1287 usleep_range(ci->platdata->phy_clkgate_delay_us,
1288 ci->platdata->phy_clkgate_delay_us + 50);
1289 usb_phy_set_suspend(ci->usb_phy, 1);
1291 enable_irq(ci->irq);
1295 * Handle the wakeup interrupt triggered by extcon connector
1296 * We need to call ci_irq again for extcon since the first
1297 * interrupt (wakeup int) only let the controller be out of
1298 * low power mode, but not handle any interrupts.
1300 static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1302 struct ci_hdrc_cable *cable_id, *cable_vbus;
1303 u32 otgsc = hw_read_otgsc(ci, ~0);
1305 cable_id = &ci->platdata->id_extcon;
1306 cable_vbus = &ci->platdata->vbus_extcon;
1308 if (!IS_ERR(cable_id->edev) && ci->is_otg &&
1309 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1312 if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
1313 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1317 static int ci_controller_resume(struct device *dev)
1319 struct ci_hdrc *ci = dev_get_drvdata(dev);
1322 dev_dbg(dev, "at %s\n", __func__);
1329 ci_hdrc_enter_lpm(ci, false);
1331 ret = ci_ulpi_resume(ci);
1336 usb_phy_set_suspend(ci->usb_phy, 0);
1337 usb_phy_set_wakeup(ci->usb_phy, false);
1338 hw_wait_phy_stable();
1342 if (ci->wakeup_int) {
1343 ci->wakeup_int = false;
1344 pm_runtime_mark_last_busy(ci->dev);
1345 pm_runtime_put_autosuspend(ci->dev);
1346 enable_irq(ci->irq);
1347 if (ci_otg_is_fsm_mode(ci))
1348 ci_otg_fsm_wakeup_by_srp(ci);
1349 ci_extcon_wakeup_int(ci);
1355 #ifdef CONFIG_PM_SLEEP
1356 static int ci_suspend(struct device *dev)
1358 struct ci_hdrc *ci = dev_get_drvdata(dev);
1361 flush_workqueue(ci->wq);
1363 * Controller needs to be active during suspend, otherwise the core
1364 * may run resume when the parent is at suspend if other driver's
1365 * suspend fails, it occurs before parent's suspend has not started,
1366 * but the core suspend has finished.
1369 pm_runtime_resume(dev);
1376 if (device_may_wakeup(dev)) {
1377 if (ci_otg_is_fsm_mode(ci))
1378 ci_otg_fsm_suspend_for_srp(ci);
1380 usb_phy_set_wakeup(ci->usb_phy, true);
1381 enable_irq_wake(ci->irq);
1384 ci_controller_suspend(ci);
1389 static int ci_resume(struct device *dev)
1391 struct ci_hdrc *ci = dev_get_drvdata(dev);
1394 if (device_may_wakeup(dev))
1395 disable_irq_wake(ci->irq);
1397 ret = ci_controller_resume(dev);
1401 if (ci->supports_runtime_pm) {
1402 pm_runtime_disable(dev);
1403 pm_runtime_set_active(dev);
1404 pm_runtime_enable(dev);
1409 #endif /* CONFIG_PM_SLEEP */
1411 static int ci_runtime_suspend(struct device *dev)
1413 struct ci_hdrc *ci = dev_get_drvdata(dev);
1415 dev_dbg(dev, "at %s\n", __func__);
1422 if (ci_otg_is_fsm_mode(ci))
1423 ci_otg_fsm_suspend_for_srp(ci);
1425 usb_phy_set_wakeup(ci->usb_phy, true);
1426 ci_controller_suspend(ci);
1431 static int ci_runtime_resume(struct device *dev)
1433 return ci_controller_resume(dev);
1436 #endif /* CONFIG_PM */
1437 static const struct dev_pm_ops ci_pm_ops = {
1438 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1439 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1442 static struct platform_driver ci_hdrc_driver = {
1443 .probe = ci_hdrc_probe,
1444 .remove = ci_hdrc_remove,
1448 .dev_groups = ci_groups,
1452 static int __init ci_hdrc_platform_register(void)
1454 ci_hdrc_host_driver_init();
1455 return platform_driver_register(&ci_hdrc_driver);
1457 module_init(ci_hdrc_platform_register);
1459 static void __exit ci_hdrc_platform_unregister(void)
1461 platform_driver_unregister(&ci_hdrc_driver);
1463 module_exit(ci_hdrc_platform_unregister);
1465 MODULE_ALIAS("platform:ci_hdrc");
1466 MODULE_LICENSE("GPL v2");
1468 MODULE_DESCRIPTION("ChipIdea HDRC Driver");