drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "navi10_enum.h"
  39 #include "hdp/hdp_5_0_0_offset.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15_common.h"
  44 #include "clearstate_gfx10.h"
  45 #include "v10_structs.h"
  46 #include "gfx_v10_0.h"
  47 #include "nbio_v2_3.h"
  48
  49 /**
  50  * Navi10 has two graphic rings to share each graphic pipe.
  51  * 1. Primary ring
  52  * 2. Async ring
  53  *
  54  * In bring-up phase, it just used primary ring so set gfx ring number as 1 at
  55  * first.
  56  */
  57 #define GFX10_NUM_GFX_RINGS     2
  58 #define GFX10_MEC_HPD_SIZE      2048
  59
  60 #define F32_CE_PROGRAM_RAM_SIZE         65536
  61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  62
  63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  65
  66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
  67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
  68 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
  69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
  70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
  71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
  72
  73 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
  74 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
  75 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
  76 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
  77 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
  78 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
  79 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
  80 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
  81 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
  82 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
  83 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
  84
  85 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
  86 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
  87 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
  88 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
  89 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
  90 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
  91
  92 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
  93 {
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 131 };
 132
 133 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 134 {
 135         /* Pending on emulation bring up */
 136 };
 137
 138 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
 139 {
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
 175 };
 176
 177 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
 178 {
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
 219 };
 220
 221 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
 222 {
 223         /* Pending on emulation bring up */
 224 };
 225
 226 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
 227 {
 228         /* Pending on emulation bring up */
 229 };
 230
 231 #define DEFAULT_SH_MEM_CONFIG \
 232         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 233          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 234          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
 235          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 236
 237
 238 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
 239 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
 240 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
 241 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
 242 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
 243                                  struct amdgpu_cu_info *cu_info);
 244 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 245 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 246                                    u32 sh_num, u32 instance);
 247 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 248
 249 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
 250 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
 251 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
 252 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 253 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
 254 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 255 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
 256
 257 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 258 {
 259         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 260         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 261                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 262         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 263         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 264         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 265         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 266         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 267         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 268 }
 269
 270 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 271                                  struct amdgpu_ring *ring)
 272 {
 273         struct amdgpu_device *adev = kiq_ring->adev;
 274         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 275         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 276         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 277
 278         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 279         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 280         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 281                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 282                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 283                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 284                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 285                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
 286                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 287                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 288                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 289                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 290         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 291         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 292         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 293         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 294         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 295 }
 296
 297 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 298                                    struct amdgpu_ring *ring,
 299                                    enum amdgpu_unmap_queues_action action,
 300                                    u64 gpu_addr, u64 seq)
 301 {
 302         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 303
 304         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 305         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 306                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 307                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 308                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 309                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 310         amdgpu_ring_write(kiq_ring,
 311                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 312
 313         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 314                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 315                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 316                 amdgpu_ring_write(kiq_ring, seq);
 317         } else {
 318                 amdgpu_ring_write(kiq_ring, 0);
 319                 amdgpu_ring_write(kiq_ring, 0);
 320                 amdgpu_ring_write(kiq_ring, 0);
 321         }
 322 }
 323
 324 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
 325                                    struct amdgpu_ring *ring,
 326                                    u64 addr,
 327                                    u64 seq)
 328 {
 329         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 330
 331         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 332         amdgpu_ring_write(kiq_ring,
 333                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 334                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 335                           PACKET3_QUERY_STATUS_COMMAND(2));
 336         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 337                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 338                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 339         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 340         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 341         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 342         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 343 }
 344
 345 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
 346         .kiq_set_resources = gfx10_kiq_set_resources,
 347         .kiq_map_queues = gfx10_kiq_map_queues,
 348         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
 349         .kiq_query_status = gfx10_kiq_query_status,
 350         .set_resources_size = 8,
 351         .map_queues_size = 7,
 352         .unmap_queues_size = 6,
 353         .query_status_size = 7,
 354 };
 355
 356 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 357 {
 358         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
 359 }
 360
 361 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
 362 {
 363         switch (adev->asic_type) {
 364         case CHIP_NAVI10:
 365                 soc15_program_register_sequence(adev,
 366                                                 golden_settings_gc_10_1,
 367                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
 368                 soc15_program_register_sequence(adev,
 369                                                 golden_settings_gc_10_0_nv10,
 370                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
 371                 break;
 372         case CHIP_NAVI14:
 373                 soc15_program_register_sequence(adev,
 374                                                 golden_settings_gc_10_1_1,
 375                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
 376                 soc15_program_register_sequence(adev,
 377                                                 golden_settings_gc_10_1_nv14,
 378                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
 379                 break;
 380         case CHIP_NAVI12:
 381                 soc15_program_register_sequence(adev,
 382                                                 golden_settings_gc_10_1_2,
 383                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
 384                 soc15_program_register_sequence(adev,
 385                                                 golden_settings_gc_10_1_2_nv12,
 386                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
 387                 break;
 388         default:
 389                 break;
 390         }
 391 }
 392
 393 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
 394 {
 395         adev->gfx.scratch.num_reg = 8;
 396         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 397         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 398 }
 399
 400 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 401                                        bool wc, uint32_t reg, uint32_t val)
 402 {
 403         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 404         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 405                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 406         amdgpu_ring_write(ring, reg);
 407         amdgpu_ring_write(ring, 0);
 408         amdgpu_ring_write(ring, val);
 409 }
 410
 411 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 412                                   int mem_space, int opt, uint32_t addr0,
 413                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 414                                   uint32_t inv)
 415 {
 416         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 417         amdgpu_ring_write(ring,
 418                           /* memory (1) or register (0) */
 419                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 420                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 421                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 422                            WAIT_REG_MEM_ENGINE(eng_sel)));
 423
 424         if (mem_space)
 425                 BUG_ON(addr0 & 0x3); /* Dword align */
 426         amdgpu_ring_write(ring, addr0);
 427         amdgpu_ring_write(ring, addr1);
 428         amdgpu_ring_write(ring, ref);
 429         amdgpu_ring_write(ring, mask);
 430         amdgpu_ring_write(ring, inv); /* poll interval */
 431 }
 432
 433 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 434 {
 435         struct amdgpu_device *adev = ring->adev;
 436         uint32_t scratch;
 437         uint32_t tmp = 0;
 438         unsigned i;
 439         int r;
 440
 441         r = amdgpu_gfx_scratch_get(adev, &scratch);
 442         if (r) {
 443                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 444                 return r;
 445         }
 446
 447         WREG32(scratch, 0xCAFEDEAD);
 448
 449         r = amdgpu_ring_alloc(ring, 3);
 450         if (r) {
 451                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 452                           ring->idx, r);
 453                 amdgpu_gfx_scratch_free(adev, scratch);
 454                 return r;
 455         }
 456
 457         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 458         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 459         amdgpu_ring_write(ring, 0xDEADBEEF);
 460         amdgpu_ring_commit(ring);
 461
 462         for (i = 0; i < adev->usec_timeout; i++) {
 463                 tmp = RREG32(scratch);
 464                 if (tmp == 0xDEADBEEF)
 465                         break;
 466                 if (amdgpu_emu_mode == 1)
 467                         msleep(1);
 468                 else
 469                         udelay(1);
 470         }
 471         if (i < adev->usec_timeout) {
 472                 if (amdgpu_emu_mode == 1)
 473                         DRM_INFO("ring test on %d succeeded in %d msecs\n",
 474                                  ring->idx, i);
 475                 else
 476                         DRM_INFO("ring test on %d succeeded in %d usecs\n",
 477                                  ring->idx, i);
 478         } else {
 479                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 480                           ring->idx, scratch, tmp);
 481                 r = -EINVAL;
 482         }
 483         amdgpu_gfx_scratch_free(adev, scratch);
 484
 485         return r;
 486 }
 487
 488 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 489 {
 490         struct amdgpu_device *adev = ring->adev;
 491         struct amdgpu_ib ib;
 492         struct dma_fence *f = NULL;
 493         uint32_t scratch;
 494         uint32_t tmp = 0;
 495         long r;
 496
 497         r = amdgpu_gfx_scratch_get(adev, &scratch);
 498         if (r) {
 499                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
 500                 return r;
 501         }
 502
 503         WREG32(scratch, 0xCAFEDEAD);
 504
 505         memset(&ib, 0, sizeof(ib));
 506         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 507         if (r) {
 508                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 509                 goto err1;
 510         }
 511
 512         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 513         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 514         ib.ptr[2] = 0xDEADBEEF;
 515         ib.length_dw = 3;
 516
 517         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 518         if (r)
 519                 goto err2;
 520
 521         r = dma_fence_wait_timeout(f, false, timeout);
 522         if (r == 0) {
 523                 DRM_ERROR("amdgpu: IB test timed out.\n");
 524                 r = -ETIMEDOUT;
 525                 goto err2;
 526         } else if (r < 0) {
 527                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 528                 goto err2;
 529         }
 530
 531         tmp = RREG32(scratch);
 532         if (tmp == 0xDEADBEEF) {
 533                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 534                 r = 0;
 535         } else {
 536                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 537                           scratch, tmp);
 538                 r = -EINVAL;
 539         }
 540 err2:
 541         amdgpu_ib_free(adev, &ib, NULL);
 542         dma_fence_put(f);
 543 err1:
 544         amdgpu_gfx_scratch_free(adev, scratch);
 545
 546         return r;
 547 }
 548
 549 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
 550 {
 551         release_firmware(adev->gfx.pfp_fw);
 552         adev->gfx.pfp_fw = NULL;
 553         release_firmware(adev->gfx.me_fw);
 554         adev->gfx.me_fw = NULL;
 555         release_firmware(adev->gfx.ce_fw);
 556         adev->gfx.ce_fw = NULL;
 557         release_firmware(adev->gfx.rlc_fw);
 558         adev->gfx.rlc_fw = NULL;
 559         release_firmware(adev->gfx.mec_fw);
 560         adev->gfx.mec_fw = NULL;
 561         release_firmware(adev->gfx.mec2_fw);
 562         adev->gfx.mec2_fw = NULL;
 563
 564         kfree(adev->gfx.rlc.register_list_format);
 565 }
 566
 567 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
 568 {
 569         adev->gfx.cp_fw_write_wait = false;
 570
 571         switch (adev->asic_type) {
 572         case CHIP_NAVI10:
 573         case CHIP_NAVI12:
 574         case CHIP_NAVI14:
 575                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
 576                     (adev->gfx.me_feature_version >= 27) &&
 577                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
 578                     (adev->gfx.pfp_feature_version >= 27) &&
 579                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
 580                     (adev->gfx.mec_feature_version >= 27))
 581                         adev->gfx.cp_fw_write_wait = true;
 582                 break;
 583         default:
 584                 break;
 585         }
 586
 587         if (adev->gfx.cp_fw_write_wait == false)
 588                 DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \
 589                               GRBM requires 1-cycle delay in cp firmware\n");
 590 }
 591
 592
 593 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 594 {
 595         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 596
 597         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 598         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 599         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 600         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 601         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 602         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 603         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 604         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 605         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 606         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 607         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 608         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 609         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 610         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 611                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 612 }
 613
 614 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
 615 {
 616         switch (adev->asic_type) {
 617         case CHIP_NAVI10:
 618                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 619                 break;
 620         default:
 621                 break;
 622         }
 623 }
 624
 625 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 626 {
 627         const char *chip_name;
 628         char fw_name[40];
 629         char wks[10];
 630         int err;
 631         struct amdgpu_firmware_info *info = NULL;
 632         const struct common_firmware_header *header = NULL;
 633         const struct gfx_firmware_header_v1_0 *cp_hdr;
 634         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 635         unsigned int *tmp = NULL;
 636         unsigned int i = 0;
 637         uint16_t version_major;
 638         uint16_t version_minor;
 639
 640         DRM_DEBUG("\n");
 641
 642         memset(wks, 0, sizeof(wks));
 643         switch (adev->asic_type) {
 644         case CHIP_NAVI10:
 645                 chip_name = "navi10";
 646                 break;
 647         case CHIP_NAVI14:
 648                 chip_name = "navi14";
 649                 if (!(adev->pdev->device == 0x7340 &&
 650                       adev->pdev->revision != 0x00))
 651                         snprintf(wks, sizeof(wks), "_wks");
 652                 break;
 653         case CHIP_NAVI12:
 654                 chip_name = "navi12";
 655                 break;
 656         default:
 657                 BUG();
 658         }
 659
 660         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
 661         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 662         if (err)
 663                 goto out;
 664         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 665         if (err)
 666                 goto out;
 667         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 668         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 669         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 670
 671         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
 672         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 673         if (err)
 674                 goto out;
 675         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 676         if (err)
 677                 goto out;
 678         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 679         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 680         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 681
 682         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
 683         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 684         if (err)
 685                 goto out;
 686         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 687         if (err)
 688                 goto out;
 689         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 690         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 691         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 692
 693         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 694         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 695         if (err)
 696                 goto out;
 697         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 698         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 699         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 700         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 701         if (version_major == 2 && version_minor == 1)
 702                 adev->gfx.rlc.is_rlc_v2_1 = true;
 703
 704         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 705         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 706         adev->gfx.rlc.save_and_restore_offset =
 707                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 708         adev->gfx.rlc.clear_state_descriptor_offset =
 709                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 710         adev->gfx.rlc.avail_scratch_ram_locations =
 711                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 712         adev->gfx.rlc.reg_restore_list_size =
 713                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 714         adev->gfx.rlc.reg_list_format_start =
 715                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 716         adev->gfx.rlc.reg_list_format_separate_start =
 717                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 718         adev->gfx.rlc.starting_offsets_start =
 719                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 720         adev->gfx.rlc.reg_list_format_size_bytes =
 721                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 722         adev->gfx.rlc.reg_list_size_bytes =
 723                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 724         adev->gfx.rlc.register_list_format =
 725                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 726                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 727         if (!adev->gfx.rlc.register_list_format) {
 728                 err = -ENOMEM;
 729                 goto out;
 730         }
 731
 732         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 733                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 734         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 735                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 736
 737         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 738
 739         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 740                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 741         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 742                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 743
 744         if (adev->gfx.rlc.is_rlc_v2_1)
 745                 gfx_v10_0_init_rlc_ext_microcode(adev);
 746
 747         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
 748         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 749         if (err)
 750                 goto out;
 751         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 752         if (err)
 753                 goto out;
 754         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 755         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 756         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 757
 758         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
 759         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 760         if (!err) {
 761                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 762                 if (err)
 763                         goto out;
 764                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 765                 adev->gfx.mec2_fw->data;
 766                 adev->gfx.mec2_fw_version =
 767                 le32_to_cpu(cp_hdr->header.ucode_version);
 768                 adev->gfx.mec2_feature_version =
 769                 le32_to_cpu(cp_hdr->ucode_feature_version);
 770         } else {
 771                 err = 0;
 772                 adev->gfx.mec2_fw = NULL;
 773         }
 774
 775         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 776                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 777                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 778                 info->fw = adev->gfx.pfp_fw;
 779                 header = (const struct common_firmware_header *)info->fw->data;
 780                 adev->firmware.fw_size +=
 781                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 782
 783                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 784                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 785                 info->fw = adev->gfx.me_fw;
 786                 header = (const struct common_firmware_header *)info->fw->data;
 787                 adev->firmware.fw_size +=
 788                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 789
 790                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 791                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 792                 info->fw = adev->gfx.ce_fw;
 793                 header = (const struct common_firmware_header *)info->fw->data;
 794                 adev->firmware.fw_size +=
 795                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 796
 797                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 798                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 799                 info->fw = adev->gfx.rlc_fw;
 800                 header = (const struct common_firmware_header *)info->fw->data;
 801                 adev->firmware.fw_size +=
 802                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 803
 804                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 805                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 806                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 807                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 808                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 809                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 810                         info->fw = adev->gfx.rlc_fw;
 811                         adev->firmware.fw_size +=
 812                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 813
 814                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 815                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 816                         info->fw = adev->gfx.rlc_fw;
 817                         adev->firmware.fw_size +=
 818                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 819
 820                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 821                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 822                         info->fw = adev->gfx.rlc_fw;
 823                         adev->firmware.fw_size +=
 824                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 825                 }
 826
 827                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 828                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 829                 info->fw = adev->gfx.mec_fw;
 830                 header = (const struct common_firmware_header *)info->fw->data;
 831                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 832                 adev->firmware.fw_size +=
 833                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
 834                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 835
 836                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 837                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 838                 info->fw = adev->gfx.mec_fw;
 839                 adev->firmware.fw_size +=
 840                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 841
 842                 if (adev->gfx.mec2_fw) {
 843                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 844                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 845                         info->fw = adev->gfx.mec2_fw;
 846                         header = (const struct common_firmware_header *)info->fw->data;
 847                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 848                         adev->firmware.fw_size +=
 849                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
 850                                       le32_to_cpu(cp_hdr->jt_size) * 4,
 851                                       PAGE_SIZE);
 852                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 853                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 854                         info->fw = adev->gfx.mec2_fw;
 855                         adev->firmware.fw_size +=
 856                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
 857                                       PAGE_SIZE);
 858                 }
 859         }
 860
 861         gfx_v10_0_check_fw_write_wait(adev);
 862 out:
 863         if (err) {
 864                 dev_err(adev->dev,
 865                         "gfx10: Failed to load firmware \"%s\"\n",
 866                         fw_name);
 867                 release_firmware(adev->gfx.pfp_fw);
 868                 adev->gfx.pfp_fw = NULL;
 869                 release_firmware(adev->gfx.me_fw);
 870                 adev->gfx.me_fw = NULL;
 871                 release_firmware(adev->gfx.ce_fw);
 872                 adev->gfx.ce_fw = NULL;
 873                 release_firmware(adev->gfx.rlc_fw);
 874                 adev->gfx.rlc_fw = NULL;
 875                 release_firmware(adev->gfx.mec_fw);
 876                 adev->gfx.mec_fw = NULL;
 877                 release_firmware(adev->gfx.mec2_fw);
 878                 adev->gfx.mec2_fw = NULL;
 879         }
 880
 881         gfx_v10_0_check_gfxoff_flag(adev);
 882
 883         return err;
 884 }
 885
 886 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
 887 {
 888         u32 count = 0;
 889         const struct cs_section_def *sect = NULL;
 890         const struct cs_extent_def *ext = NULL;
 891
 892         /* begin clear state */
 893         count += 2;
 894         /* context control state */
 895         count += 3;
 896
 897         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
 898                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 899                         if (sect->id == SECT_CONTEXT)
 900                                 count += 2 + ext->reg_count;
 901                         else
 902                                 return 0;
 903                 }
 904         }
 905
 906         /* set PA_SC_TILE_STEERING_OVERRIDE */
 907         count += 3;
 908         /* end clear state */
 909         count += 2;
 910         /* clear state */
 911         count += 2;
 912
 913         return count;
 914 }
 915
 916 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
 917                                     volatile u32 *buffer)
 918 {
 919         u32 count = 0, i;
 920         const struct cs_section_def *sect = NULL;
 921         const struct cs_extent_def *ext = NULL;
 922         int ctx_reg_offset;
 923
 924         if (adev->gfx.rlc.cs_data == NULL)
 925                 return;
 926         if (buffer == NULL)
 927                 return;
 928
 929         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 930         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 931
 932         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 933         buffer[count++] = cpu_to_le32(0x80000000);
 934         buffer[count++] = cpu_to_le32(0x80000000);
 935
 936         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 937                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 938                         if (sect->id == SECT_CONTEXT) {
 939                                 buffer[count++] =
 940                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 941                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 942                                                 PACKET3_SET_CONTEXT_REG_START);
 943                                 for (i = 0; i < ext->reg_count; i++)
 944                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 945                         } else {
 946                                 return;
 947                         }
 948                 }
 949         }
 950
 951         ctx_reg_offset =
 952                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 953         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 954         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 955         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 956
 957         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 958         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 959
 960         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 961         buffer[count++] = cpu_to_le32(0);
 962 }
 963
 964 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
 965 {
 966         /* clear state block */
 967         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 968                         &adev->gfx.rlc.clear_state_gpu_addr,
 969                         (void **)&adev->gfx.rlc.cs_ptr);
 970
 971         /* jump table block */
 972         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 973                         &adev->gfx.rlc.cp_table_gpu_addr,
 974                         (void **)&adev->gfx.rlc.cp_table_ptr);
 975 }
 976
 977 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
 978 {
 979         const struct cs_section_def *cs_data;
 980         int r;
 981
 982         adev->gfx.rlc.cs_data = gfx10_cs_data;
 983
 984         cs_data = adev->gfx.rlc.cs_data;
 985
 986         if (cs_data) {
 987                 /* init clear state block */
 988                 r = amdgpu_gfx_rlc_init_csb(adev);
 989                 if (r)
 990                         return r;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
 997 {
 998         int r;
 999
1000         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1001         if (unlikely(r != 0))
1002                 return r;
1003
1004         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1005                         AMDGPU_GEM_DOMAIN_VRAM);
1006         if (!r)
1007                 adev->gfx.rlc.clear_state_gpu_addr =
1008                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1009
1010         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1011
1012         return r;
1013 }
1014
1015 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
1016 {
1017         int r;
1018
1019         if (!adev->gfx.rlc.clear_state_obj)
1020                 return;
1021
1022         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1023         if (likely(r == 0)) {
1024                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1025                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1026         }
1027 }
1028
1029 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
1030 {
1031         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1032         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1033 }
1034
1035 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
1036 {
1037         int r;
1038
1039         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1040
1041         amdgpu_gfx_graphics_queue_acquire(adev);
1042
1043         r = gfx_v10_0_init_microcode(adev);
1044         if (r)
1045                 DRM_ERROR("Failed to load gfx firmware!\n");
1046
1047         return r;
1048 }
1049
1050 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1051 {
1052         int r;
1053         u32 *hpd;
1054         const __le32 *fw_data = NULL;
1055         unsigned fw_size;
1056         u32 *fw = NULL;
1057         size_t mec_hpd_size;
1058
1059         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1060
1061         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1062
1063         /* take ownership of the relevant compute queues */
1064         amdgpu_gfx_compute_queue_acquire(adev);
1065         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1066
1067         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1068                                       AMDGPU_GEM_DOMAIN_GTT,
1069                                       &adev->gfx.mec.hpd_eop_obj,
1070                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1071                                       (void **)&hpd);
1072         if (r) {
1073                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1074                 gfx_v10_0_mec_fini(adev);
1075                 return r;
1076         }
1077
1078         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1079
1080         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1081         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1082
1083         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1084                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1085
1086                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1087                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1088                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1089
1090                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1091                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1092                                               &adev->gfx.mec.mec_fw_obj,
1093                                               &adev->gfx.mec.mec_fw_gpu_addr,
1094                                               (void **)&fw);
1095                 if (r) {
1096                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1097                         gfx_v10_0_mec_fini(adev);
1098                         return r;
1099                 }
1100
1101                 memcpy(fw, fw_data, fw_size);
1102
1103                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1104                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1105         }
1106
1107         return 0;
1108 }
1109
1110 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1111 {
1112         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1113                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1114                 (address << SQ_IND_INDEX__INDEX__SHIFT));
1115         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1116 }
1117
1118 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1119                            uint32_t thread, uint32_t regno,
1120                            uint32_t num, uint32_t *out)
1121 {
1122         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1123                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1124                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1125                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1126                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1127         while (num--)
1128                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1129 }
1130
1131 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1132 {
1133         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
1134          * field when performing a select_se_sh so it should be
1135          * zero here */
1136         WARN_ON(simd != 0);
1137
1138         /* type 2 wave data */
1139         dst[(*no_fields)++] = 2;
1140         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1141         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1142         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1143         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1144         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1145         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1146         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1147         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1148         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1149         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1150         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1151         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1152         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1153         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1154         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1155 }
1156
1157 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1158                                      uint32_t wave, uint32_t start,
1159                                      uint32_t size, uint32_t *dst)
1160 {
1161         WARN_ON(simd != 0);
1162
1163         wave_read_regs(
1164                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1165                 dst);
1166 }
1167
1168 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1169                                       uint32_t wave, uint32_t thread,
1170                                       uint32_t start, uint32_t size,
1171                                       uint32_t *dst)
1172 {
1173         wave_read_regs(
1174                 adev, wave, thread,
1175                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1176 }
1177
1178 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1179                                                                           u32 me, u32 pipe, u32 q, u32 vm)
1180  {
1181        nv_grbm_select(adev, me, pipe, q, vm);
1182  }
1183
1184
1185 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1186         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1187         .select_se_sh = &gfx_v10_0_select_se_sh,
1188         .read_wave_data = &gfx_v10_0_read_wave_data,
1189         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1190         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1191         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1192 };
1193
1194 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1195 {
1196         u32 gb_addr_config;
1197
1198         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1199
1200         switch (adev->asic_type) {
1201         case CHIP_NAVI10:
1202         case CHIP_NAVI14:
1203         case CHIP_NAVI12:
1204                 adev->gfx.config.max_hw_contexts = 8;
1205                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1206                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1207                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1208                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1209                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1210                 break;
1211         default:
1212                 BUG();
1213                 break;
1214         }
1215
1216         adev->gfx.config.gb_addr_config = gb_addr_config;
1217
1218         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1219                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1220                                       GB_ADDR_CONFIG, NUM_PIPES);
1221
1222         adev->gfx.config.max_tile_pipes =
1223                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1224
1225         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1226                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1227                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1228         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1229                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1230                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
1231         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1232                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1233                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1234         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1235                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1236                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1237 }
1238
1239 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1240                                    int me, int pipe, int queue)
1241 {
1242         int r;
1243         struct amdgpu_ring *ring;
1244         unsigned int irq_type;
1245
1246         ring = &adev->gfx.gfx_ring[ring_id];
1247
1248         ring->me = me;
1249         ring->pipe = pipe;
1250         ring->queue = queue;
1251
1252         ring->ring_obj = NULL;
1253         ring->use_doorbell = true;
1254
1255         if (!ring_id)
1256                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1257         else
1258                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1259         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1260
1261         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1262         r = amdgpu_ring_init(adev, ring, 1024,
1263                              &adev->gfx.eop_irq, irq_type);
1264         if (r)
1265                 return r;
1266         return 0;
1267 }
1268
1269 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1270                                        int mec, int pipe, int queue)
1271 {
1272         int r;
1273         unsigned irq_type;
1274         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1275
1276         ring = &adev->gfx.compute_ring[ring_id];
1277
1278         /* mec0 is me1 */
1279         ring->me = mec + 1;
1280         ring->pipe = pipe;
1281         ring->queue = queue;
1282
1283         ring->ring_obj = NULL;
1284         ring->use_doorbell = true;
1285         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1286         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1287                                 + (ring_id * GFX10_MEC_HPD_SIZE);
1288         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1289
1290         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1291                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1292                 + ring->pipe;
1293
1294         /* type-2 packets are deprecated on MEC, use type-3 instead */
1295         r = amdgpu_ring_init(adev, ring, 1024,
1296                              &adev->gfx.eop_irq, irq_type);
1297         if (r)
1298                 return r;
1299
1300         return 0;
1301 }
1302
1303 static int gfx_v10_0_sw_init(void *handle)
1304 {
1305         int i, j, k, r, ring_id = 0;
1306         struct amdgpu_kiq *kiq;
1307         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1308
1309         switch (adev->asic_type) {
1310         case CHIP_NAVI10:
1311         case CHIP_NAVI14:
1312         case CHIP_NAVI12:
1313                 adev->gfx.me.num_me = 1;
1314                 adev->gfx.me.num_pipe_per_me = 2;
1315                 adev->gfx.me.num_queue_per_pipe = 1;
1316                 adev->gfx.mec.num_mec = 2;
1317                 adev->gfx.mec.num_pipe_per_mec = 4;
1318                 adev->gfx.mec.num_queue_per_pipe = 8;
1319                 break;
1320         default:
1321                 adev->gfx.me.num_me = 1;
1322                 adev->gfx.me.num_pipe_per_me = 1;
1323                 adev->gfx.me.num_queue_per_pipe = 1;
1324                 adev->gfx.mec.num_mec = 1;
1325                 adev->gfx.mec.num_pipe_per_mec = 4;
1326                 adev->gfx.mec.num_queue_per_pipe = 8;
1327                 break;
1328         }
1329
1330         /* KIQ event */
1331         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1332                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1333                               &adev->gfx.kiq.irq);
1334         if (r)
1335                 return r;
1336
1337         /* EOP Event */
1338         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1339                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1340                               &adev->gfx.eop_irq);
1341         if (r)
1342                 return r;
1343
1344         /* Privileged reg */
1345         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1346                               &adev->gfx.priv_reg_irq);
1347         if (r)
1348                 return r;
1349
1350         /* Privileged inst */
1351         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1352                               &adev->gfx.priv_inst_irq);
1353         if (r)
1354                 return r;
1355
1356         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1357
1358         gfx_v10_0_scratch_init(adev);
1359
1360         r = gfx_v10_0_me_init(adev);
1361         if (r)
1362                 return r;
1363
1364         r = gfx_v10_0_rlc_init(adev);
1365         if (r) {
1366                 DRM_ERROR("Failed to init rlc BOs!\n");
1367                 return r;
1368         }
1369
1370         r = gfx_v10_0_mec_init(adev);
1371         if (r) {
1372                 DRM_ERROR("Failed to init MEC BOs!\n");
1373                 return r;
1374         }
1375
1376         /* set up the gfx ring */
1377         for (i = 0; i < adev->gfx.me.num_me; i++) {
1378                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1379                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1380                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1381                                         continue;
1382
1383                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1384                                                             i, k, j);
1385                                 if (r)
1386                                         return r;
1387                                 ring_id++;
1388                         }
1389                 }
1390         }
1391
1392         ring_id = 0;
1393         /* set up the compute queues - allocate horizontally across pipes */
1394         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1395                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1396                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1397                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1398                                                                      j))
1399                                         continue;
1400
1401                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
1402                                                                 i, k, j);
1403                                 if (r)
1404                                         return r;
1405
1406                                 ring_id++;
1407                         }
1408                 }
1409         }
1410
1411         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1412         if (r) {
1413                 DRM_ERROR("Failed to init KIQ BOs!\n");
1414                 return r;
1415         }
1416
1417         kiq = &adev->gfx.kiq;
1418         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1419         if (r)
1420                 return r;
1421
1422         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1423         if (r)
1424                 return r;
1425
1426         /* allocate visible FB for rlc auto-loading fw */
1427         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1428                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1429                 if (r)
1430                         return r;
1431         }
1432
1433         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1434
1435         gfx_v10_0_gpu_early_init(adev);
1436
1437         return 0;
1438 }
1439
1440 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1441 {
1442         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1443                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1444                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1445 }
1446
1447 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1448 {
1449         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1450                               &adev->gfx.ce.ce_fw_gpu_addr,
1451                               (void **)&adev->gfx.ce.ce_fw_ptr);
1452 }
1453
1454 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1455 {
1456         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1457                               &adev->gfx.me.me_fw_gpu_addr,
1458                               (void **)&adev->gfx.me.me_fw_ptr);
1459 }
1460
1461 static int gfx_v10_0_sw_fini(void *handle)
1462 {
1463         int i;
1464         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1465
1466         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1467                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1468         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1469                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1470
1471         amdgpu_gfx_mqd_sw_fini(adev);
1472         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1473         amdgpu_gfx_kiq_fini(adev);
1474
1475         gfx_v10_0_pfp_fini(adev);
1476         gfx_v10_0_ce_fini(adev);
1477         gfx_v10_0_me_fini(adev);
1478         gfx_v10_0_rlc_fini(adev);
1479         gfx_v10_0_mec_fini(adev);
1480
1481         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1482                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1483
1484         gfx_v10_0_free_microcode(adev);
1485
1486         return 0;
1487 }
1488
1489
1490 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1491 {
1492         /* TODO */
1493 }
1494
1495 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1496                                    u32 sh_num, u32 instance)
1497 {
1498         u32 data;
1499
1500         if (instance == 0xffffffff)
1501                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1502                                      INSTANCE_BROADCAST_WRITES, 1);
1503         else
1504                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1505                                      instance);
1506
1507         if (se_num == 0xffffffff)
1508                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1509                                      1);
1510         else
1511                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1512
1513         if (sh_num == 0xffffffff)
1514                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1515                                      1);
1516         else
1517                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1518
1519         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1520 }
1521
1522 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1523 {
1524         u32 data, mask;
1525
1526         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1527         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1528
1529         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1530         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1531
1532         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1533                                          adev->gfx.config.max_sh_per_se);
1534
1535         return (~data) & mask;
1536 }
1537
1538 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1539 {
1540         int i, j;
1541         u32 data;
1542         u32 active_rbs = 0;
1543         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1544                                         adev->gfx.config.max_sh_per_se;
1545
1546         mutex_lock(&adev->grbm_idx_mutex);
1547         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1548                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1549                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1550                         data = gfx_v10_0_get_rb_active_bitmap(adev);
1551                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1552                                                rb_bitmap_width_per_sh);
1553                 }
1554         }
1555         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1556         mutex_unlock(&adev->grbm_idx_mutex);
1557
1558         adev->gfx.config.backend_enable_mask = active_rbs;
1559         adev->gfx.config.num_rbs = hweight32(active_rbs);
1560 }
1561
1562 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1563 {
1564         uint32_t num_sc;
1565         uint32_t enabled_rb_per_sh;
1566         uint32_t active_rb_bitmap;
1567         uint32_t num_rb_per_sc;
1568         uint32_t num_packer_per_sc;
1569         uint32_t pa_sc_tile_steering_override;
1570
1571         /* init num_sc */
1572         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1573                         adev->gfx.config.num_sc_per_sh;
1574         /* init num_rb_per_sc */
1575         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1576         enabled_rb_per_sh = hweight32(active_rb_bitmap);
1577         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1578         /* init num_packer_per_sc */
1579         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1580
1581         pa_sc_tile_steering_override = 0;
1582         pa_sc_tile_steering_override |=
1583                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1584                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1585         pa_sc_tile_steering_override |=
1586                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1587                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1588         pa_sc_tile_steering_override |=
1589                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1590                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1591
1592         return pa_sc_tile_steering_override;
1593 }
1594
1595 #define DEFAULT_SH_MEM_BASES    (0x6000)
1596 #define FIRST_COMPUTE_VMID      (8)
1597 #define LAST_COMPUTE_VMID       (16)
1598
1599 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1600 {
1601         int i;
1602         uint32_t sh_mem_bases;
1603
1604         /*
1605          * Configure apertures:
1606          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1607          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1608          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1609          */
1610         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1611
1612         mutex_lock(&adev->srbm_mutex);
1613         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1614                 nv_grbm_select(adev, 0, 0, 0, i);
1615                 /* CP and shaders */
1616                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1617                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1618         }
1619         nv_grbm_select(adev, 0, 0, 0, 0);
1620         mutex_unlock(&adev->srbm_mutex);
1621
1622         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1623            acccess. These should be enabled by FW for target VMIDs. */
1624         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1625                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1626                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1627                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1628                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1629         }
1630 }
1631
1632 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1633 {
1634         int vmid;
1635
1636         /*
1637          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1638          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1639          * the driver can enable them for graphics. VMID0 should maintain
1640          * access so that HWS firmware can save/restore entries.
1641          */
1642         for (vmid = 1; vmid < 16; vmid++) {
1643                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1644                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1645                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1646                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1647         }
1648 }
1649
1650
1651 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1652 {
1653         int i, j, k;
1654         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1655         u32 tmp, wgp_active_bitmap = 0;
1656         u32 gcrd_targets_disable_tcp = 0;
1657         u32 utcl_invreq_disable = 0;
1658         /*
1659          * GCRD_TARGETS_DISABLE field contains
1660          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
1661          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
1662          */
1663         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1664                 2 * max_wgp_per_sh + /* TCP */
1665                 max_wgp_per_sh + /* SQC */
1666                 4); /* GL1C */
1667         /*
1668          * UTCL1_UTCL0_INVREQ_DISABLE field contains
1669          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
1670          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
1671          */
1672         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1673                 2 * max_wgp_per_sh + /* TCP */
1674                 2 * max_wgp_per_sh + /* SQC */
1675                 4 + /* RMI */
1676                 1); /* SQG */
1677
1678         if (adev->asic_type == CHIP_NAVI10 ||
1679             adev->asic_type == CHIP_NAVI14 ||
1680             adev->asic_type == CHIP_NAVI12) {
1681                 mutex_lock(&adev->grbm_idx_mutex);
1682                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1683                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1684                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1685                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1686                                 /*
1687                                  * Set corresponding TCP bits for the inactive WGPs in
1688                                  * GCRD_SA_TARGETS_DISABLE
1689                                  */
1690                                 gcrd_targets_disable_tcp = 0;
1691                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
1692                                 utcl_invreq_disable = 0;
1693
1694                                 for (k = 0; k < max_wgp_per_sh; k++) {
1695                                         if (!(wgp_active_bitmap & (1 << k))) {
1696                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
1697                                                 utcl_invreq_disable |= (3 << (2 * k)) |
1698                                                         (3 << (2 * (max_wgp_per_sh + k)));
1699                                         }
1700                                 }
1701
1702                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1703                                 /* only override TCP & SQC bits */
1704                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1705                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1706                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1707
1708                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1709                                 /* only override TCP bits */
1710                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1711                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1712                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1713                         }
1714                 }
1715
1716                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1717                 mutex_unlock(&adev->grbm_idx_mutex);
1718         }
1719 }
1720
1721 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
1722 {
1723         /* TCCs are global (not instanced). */
1724         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
1725                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
1726
1727         adev->gfx.config.tcc_disabled_mask =
1728                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1729                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1730 }
1731
1732 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1733 {
1734         u32 tmp;
1735         int i;
1736
1737         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1738
1739         gfx_v10_0_tiling_mode_table_init(adev);
1740
1741         gfx_v10_0_setup_rb(adev);
1742         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1743         gfx_v10_0_get_tcc_info(adev);
1744         adev->gfx.config.pa_sc_tile_steering_override =
1745                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1746
1747         /* XXX SH_MEM regs */
1748         /* where to put LDS, scratch, GPUVM in FSA64 space */
1749         mutex_lock(&adev->srbm_mutex);
1750         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1751                 nv_grbm_select(adev, 0, 0, 0, i);
1752                 /* CP and shaders */
1753                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1754                 if (i != 0) {
1755                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1756                                 (adev->gmc.private_aperture_start >> 48));
1757                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1758                                 (adev->gmc.shared_aperture_start >> 48));
1759                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1760                 }
1761         }
1762         nv_grbm_select(adev, 0, 0, 0, 0);
1763
1764         mutex_unlock(&adev->srbm_mutex);
1765
1766         gfx_v10_0_init_compute_vmid(adev);
1767         gfx_v10_0_init_gds_vmid(adev);
1768
1769 }
1770
1771 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1772                                                bool enable)
1773 {
1774         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1775
1776         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1777                             enable ? 1 : 0);
1778         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1779                             enable ? 1 : 0);
1780         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1781                             enable ? 1 : 0);
1782         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1783                             enable ? 1 : 0);
1784
1785         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1786 }
1787
1788 static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
1789 {
1790         /* csib */
1791         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1792                      adev->gfx.rlc.clear_state_gpu_addr >> 32);
1793         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1794                      adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1795         WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1796 }
1797
1798 static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
1799 {
1800         int i;
1801
1802         gfx_v10_0_init_csb(adev);
1803
1804         for (i = 0; i < adev->num_vmhubs; i++)
1805                 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
1806
1807         /* TODO: init power gating */
1808         return;
1809 }
1810
1811 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1812 {
1813         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1814
1815         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1816         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1817 }
1818
1819 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1820 {
1821         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1822         udelay(50);
1823         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1824         udelay(50);
1825 }
1826
1827 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1828                                              bool enable)
1829 {
1830         uint32_t rlc_pg_cntl;
1831
1832         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1833
1834         if (!enable) {
1835                 /* RLC_PG_CNTL[23] = 0 (default)
1836                  * RLC will wait for handshake acks with SMU
1837                  * GFXOFF will be enabled
1838                  * RLC_PG_CNTL[23] = 1
1839                  * RLC will not issue any message to SMU
1840                  * hence no handshake between SMU & RLC
1841                  * GFXOFF will be disabled
1842                  */
1843                 rlc_pg_cntl |= 0x800000;
1844         } else
1845                 rlc_pg_cntl &= ~0x800000;
1846         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1847 }
1848
1849 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1850 {
1851         /* TODO: enable rlc & smu handshake until smu
1852          * and gfxoff feature works as expected */
1853         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1854                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1855
1856         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1857         udelay(50);
1858 }
1859
1860 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1861 {
1862         uint32_t tmp;
1863
1864         /* enable Save Restore Machine */
1865         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1866         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1867         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1868         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1869 }
1870
1871 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1872 {
1873         const struct rlc_firmware_header_v2_0 *hdr;
1874         const __le32 *fw_data;
1875         unsigned i, fw_size;
1876
1877         if (!adev->gfx.rlc_fw)
1878                 return -EINVAL;
1879
1880         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1881         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1882
1883         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1884                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1885         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1886
1887         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1888                      RLCG_UCODE_LOADING_START_ADDRESS);
1889
1890         for (i = 0; i < fw_size; i++)
1891                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1892                              le32_to_cpup(fw_data++));
1893
1894         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1895
1896         return 0;
1897 }
1898
1899 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1900 {
1901         int r;
1902
1903         if (amdgpu_sriov_vf(adev))
1904                 return 0;
1905
1906         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1907                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1908                 if (r)
1909                         return r;
1910                 gfx_v10_0_init_pg(adev);
1911
1912                 /* enable RLC SRM */
1913                 gfx_v10_0_rlc_enable_srm(adev);
1914
1915         } else {
1916                 adev->gfx.rlc.funcs->stop(adev);
1917
1918                 /* disable CG */
1919                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1920
1921                 /* disable PG */
1922                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1923
1924                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1925                         /* legacy rlc firmware loading */
1926                         r = gfx_v10_0_rlc_load_microcode(adev);
1927                         if (r)
1928                                 return r;
1929                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1930                         /* rlc backdoor autoload firmware */
1931                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1932                         if (r)
1933                                 return r;
1934                 }
1935
1936                 gfx_v10_0_init_pg(adev);
1937                 adev->gfx.rlc.funcs->start(adev);
1938
1939                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1940                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1941                         if (r)
1942                                 return r;
1943                 }
1944         }
1945         return 0;
1946 }
1947
1948 static struct {
1949         FIRMWARE_ID     id;
1950         unsigned int    offset;
1951         unsigned int    size;
1952 } rlc_autoload_info[FIRMWARE_ID_MAX];
1953
1954 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1955 {
1956         int ret;
1957         RLC_TABLE_OF_CONTENT *rlc_toc;
1958
1959         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1960                                         AMDGPU_GEM_DOMAIN_GTT,
1961                                         &adev->gfx.rlc.rlc_toc_bo,
1962                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
1963                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
1964         if (ret) {
1965                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1966                 return ret;
1967         }
1968
1969         /* Copy toc from psp sos fw to rlc toc buffer */
1970         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1971
1972         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1973         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1974                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
1975                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1976                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1977                         /* Offset needs 4KB alignment */
1978                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1979                 }
1980
1981                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1982                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1983                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1984
1985                 rlc_toc++;
1986         };
1987
1988         return 0;
1989 }
1990
1991 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1992 {
1993         uint32_t total_size = 0;
1994         FIRMWARE_ID id;
1995         int ret;
1996
1997         ret = gfx_v10_0_parse_rlc_toc(adev);
1998         if (ret) {
1999                 dev_err(adev->dev, "failed to parse rlc toc\n");
2000                 return 0;
2001         }
2002
2003         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
2004                 total_size += rlc_autoload_info[id].size;
2005
2006         /* In case the offset in rlc toc ucode is aligned */
2007         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
2008                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
2009                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
2010
2011         return total_size;
2012 }
2013
2014 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
2015 {
2016         int r;
2017         uint32_t total_size;
2018
2019         total_size = gfx_v10_0_calc_toc_total_size(adev);
2020
2021         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
2022                                       AMDGPU_GEM_DOMAIN_GTT,
2023                                       &adev->gfx.rlc.rlc_autoload_bo,
2024                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
2025                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2026         if (r) {
2027                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
2028                 return r;
2029         }
2030
2031         return 0;
2032 }
2033
2034 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
2035 {
2036         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
2037                               &adev->gfx.rlc.rlc_toc_gpu_addr,
2038                               (void **)&adev->gfx.rlc.rlc_toc_buf);
2039         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
2040                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
2041                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2042 }
2043
2044 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
2045                                                        FIRMWARE_ID id,
2046                                                        const void *fw_data,
2047                                                        uint32_t fw_size)
2048 {
2049         uint32_t toc_offset;
2050         uint32_t toc_fw_size;
2051         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
2052
2053         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
2054                 return;
2055
2056         toc_offset = rlc_autoload_info[id].offset;
2057         toc_fw_size = rlc_autoload_info[id].size;
2058
2059         if (fw_size == 0)
2060                 fw_size = toc_fw_size;
2061
2062         if (fw_size > toc_fw_size)
2063                 fw_size = toc_fw_size;
2064
2065         memcpy(ptr + toc_offset, fw_data, fw_size);
2066
2067         if (fw_size < toc_fw_size)
2068                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2069 }
2070
2071 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2072 {
2073         void *data;
2074         uint32_t size;
2075
2076         data = adev->gfx.rlc.rlc_toc_buf;
2077         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2078
2079         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2080                                                    FIRMWARE_ID_RLC_TOC,
2081                                                    data, size);
2082 }
2083
2084 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2085 {
2086         const __le32 *fw_data;
2087         uint32_t fw_size;
2088         const struct gfx_firmware_header_v1_0 *cp_hdr;
2089         const struct rlc_firmware_header_v2_0 *rlc_hdr;
2090
2091         /* pfp ucode */
2092         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2093                 adev->gfx.pfp_fw->data;
2094         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2095                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2096         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2097         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2098                                                    FIRMWARE_ID_CP_PFP,
2099                                                    fw_data, fw_size);
2100
2101         /* ce ucode */
2102         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2103                 adev->gfx.ce_fw->data;
2104         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2105                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2106         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2107         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2108                                                    FIRMWARE_ID_CP_CE,
2109                                                    fw_data, fw_size);
2110
2111         /* me ucode */
2112         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2113                 adev->gfx.me_fw->data;
2114         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2115                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2116         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2117         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2118                                                    FIRMWARE_ID_CP_ME,
2119                                                    fw_data, fw_size);
2120
2121         /* rlc ucode */
2122         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2123                 adev->gfx.rlc_fw->data;
2124         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2125                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2126         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2127         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2128                                                    FIRMWARE_ID_RLC_G_UCODE,
2129                                                    fw_data, fw_size);
2130
2131         /* mec1 ucode */
2132         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2133                 adev->gfx.mec_fw->data;
2134         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2135                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2136         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2137                 cp_hdr->jt_size * 4;
2138         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2139                                                    FIRMWARE_ID_CP_MEC,
2140                                                    fw_data, fw_size);
2141         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
2142 }
2143
2144 /* Temporarily put sdma part here */
2145 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2146 {
2147         const __le32 *fw_data;
2148         uint32_t fw_size;
2149         const struct sdma_firmware_header_v1_0 *sdma_hdr;
2150         int i;
2151
2152         for (i = 0; i < adev->sdma.num_instances; i++) {
2153                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2154                         adev->sdma.instance[i].fw->data;
2155                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2156                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2157                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2158
2159                 if (i == 0) {
2160                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2161                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2162                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2163                                 FIRMWARE_ID_SDMA0_JT,
2164                                 (uint32_t *)fw_data +
2165                                 sdma_hdr->jt_offset,
2166                                 sdma_hdr->jt_size * 4);
2167                 } else if (i == 1) {
2168                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2169                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2170                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2171                                 FIRMWARE_ID_SDMA1_JT,
2172                                 (uint32_t *)fw_data +
2173                                 sdma_hdr->jt_offset,
2174                                 sdma_hdr->jt_size * 4);
2175                 }
2176         }
2177 }
2178
2179 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2180 {
2181         uint32_t rlc_g_offset, rlc_g_size, tmp;
2182         uint64_t gpu_addr;
2183
2184         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2185         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2186         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2187
2188         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2189         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2190         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2191
2192         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2193         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2194         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2195
2196         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2197         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2198                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2199                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2200                 return -EINVAL;
2201         }
2202
2203         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2204         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2205                 DRM_ERROR("RLC ROM should halt itself\n");
2206                 return -EINVAL;
2207         }
2208
2209         return 0;
2210 }
2211
2212 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2213 {
2214         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2215         uint32_t tmp;
2216         int i;
2217         uint64_t addr;
2218
2219         /* Trigger an invalidation of the L1 instruction caches */
2220         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2221         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2222         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2223
2224         /* Wait for invalidation complete */
2225         for (i = 0; i < usec_timeout; i++) {
2226                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2227                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2228                         INVALIDATE_CACHE_COMPLETE))
2229                         break;
2230                 udelay(1);
2231         }
2232
2233         if (i >= usec_timeout) {
2234                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2235                 return -EINVAL;
2236         }
2237
2238         /* Program me ucode address into intruction cache address register */
2239         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2240                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2241         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2242                         lower_32_bits(addr) & 0xFFFFF000);
2243         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2244                         upper_32_bits(addr));
2245
2246         return 0;
2247 }
2248
2249 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2250 {
2251         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2252         uint32_t tmp;
2253         int i;
2254         uint64_t addr;
2255
2256         /* Trigger an invalidation of the L1 instruction caches */
2257         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2258         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2259         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2260
2261         /* Wait for invalidation complete */
2262         for (i = 0; i < usec_timeout; i++) {
2263                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2264                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2265                         INVALIDATE_CACHE_COMPLETE))
2266                         break;
2267                 udelay(1);
2268         }
2269
2270         if (i >= usec_timeout) {
2271                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2272                 return -EINVAL;
2273         }
2274
2275         /* Program ce ucode address into intruction cache address register */
2276         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2277                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2278         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2279                         lower_32_bits(addr) & 0xFFFFF000);
2280         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2281                         upper_32_bits(addr));
2282
2283         return 0;
2284 }
2285
2286 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2287 {
2288         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2289         uint32_t tmp;
2290         int i;
2291         uint64_t addr;
2292
2293         /* Trigger an invalidation of the L1 instruction caches */
2294         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2295         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2296         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2297
2298         /* Wait for invalidation complete */
2299         for (i = 0; i < usec_timeout; i++) {
2300                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2301                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2302                         INVALIDATE_CACHE_COMPLETE))
2303                         break;
2304                 udelay(1);
2305         }
2306
2307         if (i >= usec_timeout) {
2308                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2309                 return -EINVAL;
2310         }
2311
2312         /* Program pfp ucode address into intruction cache address register */
2313         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2314                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2315         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2316                         lower_32_bits(addr) & 0xFFFFF000);
2317         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2318                         upper_32_bits(addr));
2319
2320         return 0;
2321 }
2322
2323 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2324 {
2325         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2326         uint32_t tmp;
2327         int i;
2328         uint64_t addr;
2329
2330         /* Trigger an invalidation of the L1 instruction caches */
2331         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2332         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2333         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2334
2335         /* Wait for invalidation complete */
2336         for (i = 0; i < usec_timeout; i++) {
2337                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2338                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2339                         INVALIDATE_CACHE_COMPLETE))
2340                         break;
2341                 udelay(1);
2342         }
2343
2344         if (i >= usec_timeout) {
2345                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2346                 return -EINVAL;
2347         }
2348
2349         /* Program mec1 ucode address into intruction cache address register */
2350         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2351                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2352         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2353                         lower_32_bits(addr) & 0xFFFFF000);
2354         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2355                         upper_32_bits(addr));
2356
2357         return 0;
2358 }
2359
2360 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2361 {
2362         uint32_t cp_status;
2363         uint32_t bootload_status;
2364         int i, r;
2365
2366         for (i = 0; i < adev->usec_timeout; i++) {
2367                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2368                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2369                 if ((cp_status == 0) &&
2370                     (REG_GET_FIELD(bootload_status,
2371                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2372                         break;
2373                 }
2374                 udelay(1);
2375         }
2376
2377         if (i >= adev->usec_timeout) {
2378                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2379                 return -ETIMEDOUT;
2380         }
2381
2382         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2383                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2384                 if (r)
2385                         return r;
2386
2387                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2388                 if (r)
2389                         return r;
2390
2391                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2392                 if (r)
2393                         return r;
2394
2395                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2396                 if (r)
2397                         return r;
2398         }
2399
2400         return 0;
2401 }
2402
2403 static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2404 {
2405         int i;
2406         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2407
2408         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2409         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2410         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2411         if (!enable) {
2412                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2413                         adev->gfx.gfx_ring[i].sched.ready = false;
2414         }
2415         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2416         udelay(50);
2417 }
2418
2419 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2420 {
2421         int r;
2422         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2423         const __le32 *fw_data;
2424         unsigned i, fw_size;
2425         uint32_t tmp;
2426         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2427
2428         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2429                 adev->gfx.pfp_fw->data;
2430
2431         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2432
2433         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2434                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2435         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2436
2437         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2438                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2439                                       &adev->gfx.pfp.pfp_fw_obj,
2440                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2441                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2442         if (r) {
2443                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2444                 gfx_v10_0_pfp_fini(adev);
2445                 return r;
2446         }
2447
2448         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2449
2450         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2451         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2452
2453         /* Trigger an invalidation of the L1 instruction caches */
2454         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2455         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2456         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2457
2458         /* Wait for invalidation complete */
2459         for (i = 0; i < usec_timeout; i++) {
2460                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2461                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2462                         INVALIDATE_CACHE_COMPLETE))
2463                         break;
2464                 udelay(1);
2465         }
2466
2467         if (i >= usec_timeout) {
2468                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2469                 return -EINVAL;
2470         }
2471
2472         if (amdgpu_emu_mode == 1)
2473                 adev->nbio.funcs->hdp_flush(adev, NULL);
2474
2475         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2476         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2477         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2478         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2479         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2480         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2481         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2482                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2483         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2484                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2485
2486         return 0;
2487 }
2488
2489 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2490 {
2491         int r;
2492         const struct gfx_firmware_header_v1_0 *ce_hdr;
2493         const __le32 *fw_data;
2494         unsigned i, fw_size;
2495         uint32_t tmp;
2496         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2497
2498         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2499                 adev->gfx.ce_fw->data;
2500
2501         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2502
2503         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2504                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2505         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2506
2507         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2508                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2509                                       &adev->gfx.ce.ce_fw_obj,
2510                                       &adev->gfx.ce.ce_fw_gpu_addr,
2511                                       (void **)&adev->gfx.ce.ce_fw_ptr);
2512         if (r) {
2513                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2514                 gfx_v10_0_ce_fini(adev);
2515                 return r;
2516         }
2517
2518         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2519
2520         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2521         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2522
2523         /* Trigger an invalidation of the L1 instruction caches */
2524         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2525         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2526         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2527
2528         /* Wait for invalidation complete */
2529         for (i = 0; i < usec_timeout; i++) {
2530                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2531                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2532                         INVALIDATE_CACHE_COMPLETE))
2533                         break;
2534                 udelay(1);
2535         }
2536
2537         if (i >= usec_timeout) {
2538                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2539                 return -EINVAL;
2540         }
2541
2542         if (amdgpu_emu_mode == 1)
2543                 adev->nbio.funcs->hdp_flush(adev, NULL);
2544
2545         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2546         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2547         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2548         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2549         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2550         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2551                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2552         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2553                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2554
2555         return 0;
2556 }
2557
2558 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2559 {
2560         int r;
2561         const struct gfx_firmware_header_v1_0 *me_hdr;
2562         const __le32 *fw_data;
2563         unsigned i, fw_size;
2564         uint32_t tmp;
2565         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2566
2567         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2568                 adev->gfx.me_fw->data;
2569
2570         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2571
2572         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2573                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2574         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2575
2576         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2577                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2578                                       &adev->gfx.me.me_fw_obj,
2579                                       &adev->gfx.me.me_fw_gpu_addr,
2580                                       (void **)&adev->gfx.me.me_fw_ptr);
2581         if (r) {
2582                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2583                 gfx_v10_0_me_fini(adev);
2584                 return r;
2585         }
2586
2587         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2588
2589         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2590         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2591
2592         /* Trigger an invalidation of the L1 instruction caches */
2593         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2594         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2595         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2596
2597         /* Wait for invalidation complete */
2598         for (i = 0; i < usec_timeout; i++) {
2599                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2600                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2601                         INVALIDATE_CACHE_COMPLETE))
2602                         break;
2603                 udelay(1);
2604         }
2605
2606         if (i >= usec_timeout) {
2607                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2608                 return -EINVAL;
2609         }
2610
2611         if (amdgpu_emu_mode == 1)
2612                 adev->nbio.funcs->hdp_flush(adev, NULL);
2613
2614         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2615         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2616         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2617         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2618         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2619         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2620                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2621         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2622                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2623
2624         return 0;
2625 }
2626
2627 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2628 {
2629         int r;
2630
2631         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2632                 return -EINVAL;
2633
2634         gfx_v10_0_cp_gfx_enable(adev, false);
2635
2636         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2637         if (r) {
2638                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2639                 return r;
2640         }
2641
2642         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2643         if (r) {
2644                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2645                 return r;
2646         }
2647
2648         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2649         if (r) {
2650                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2651                 return r;
2652         }
2653
2654         return 0;
2655 }
2656
2657 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2658 {
2659         struct amdgpu_ring *ring;
2660         const struct cs_section_def *sect = NULL;
2661         const struct cs_extent_def *ext = NULL;
2662         int r, i;
2663         int ctx_reg_offset;
2664
2665         /* init the CP */
2666         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2667                      adev->gfx.config.max_hw_contexts - 1);
2668         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2669
2670         gfx_v10_0_cp_gfx_enable(adev, true);
2671
2672         ring = &adev->gfx.gfx_ring[0];
2673         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2674         if (r) {
2675                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2676                 return r;
2677         }
2678
2679         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2680         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2681
2682         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2683         amdgpu_ring_write(ring, 0x80000000);
2684         amdgpu_ring_write(ring, 0x80000000);
2685
2686         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2687                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2688                         if (sect->id == SECT_CONTEXT) {
2689                                 amdgpu_ring_write(ring,
2690                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
2691                                                           ext->reg_count));
2692                                 amdgpu_ring_write(ring, ext->reg_index -
2693                                                   PACKET3_SET_CONTEXT_REG_START);
2694                                 for (i = 0; i < ext->reg_count; i++)
2695                                         amdgpu_ring_write(ring, ext->extent[i]);
2696                         }
2697                 }
2698         }
2699
2700         ctx_reg_offset =
2701                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2702         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2703         amdgpu_ring_write(ring, ctx_reg_offset);
2704         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2705
2706         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2707         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2708
2709         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2710         amdgpu_ring_write(ring, 0);
2711
2712         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2713         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2714         amdgpu_ring_write(ring, 0x8000);
2715         amdgpu_ring_write(ring, 0x8000);
2716
2717         amdgpu_ring_commit(ring);
2718
2719         /* submit cs packet to copy state 0 to next available state */
2720         ring = &adev->gfx.gfx_ring[1];
2721         r = amdgpu_ring_alloc(ring, 2);
2722         if (r) {
2723                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2724                 return r;
2725         }
2726
2727         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2728         amdgpu_ring_write(ring, 0);
2729
2730         amdgpu_ring_commit(ring);
2731
2732         return 0;
2733 }
2734
2735 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2736                                          CP_PIPE_ID pipe)
2737 {
2738         u32 tmp;
2739
2740         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2741         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2742
2743         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2744 }
2745
2746 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2747                                           struct amdgpu_ring *ring)
2748 {
2749         u32 tmp;
2750
2751         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2752         if (ring->use_doorbell) {
2753                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2754                                     DOORBELL_OFFSET, ring->doorbell_index);
2755                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2756                                     DOORBELL_EN, 1);
2757         } else {
2758                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2759                                     DOORBELL_EN, 0);
2760         }
2761         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2762         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2763                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
2764         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2765
2766         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2767                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2768 }
2769
2770 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2771 {
2772         struct amdgpu_ring *ring;
2773         u32 tmp;
2774         u32 rb_bufsz;
2775         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2776         u32 i;
2777
2778         /* Set the write pointer delay */
2779         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2780
2781         /* set the RB to use vmid 0 */
2782         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2783
2784         /* Init gfx ring 0 for pipe 0 */
2785         mutex_lock(&adev->srbm_mutex);
2786         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2787         mutex_unlock(&adev->srbm_mutex);
2788         /* Set ring buffer size */
2789         ring = &adev->gfx.gfx_ring[0];
2790         rb_bufsz = order_base_2(ring->ring_size / 8);
2791         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2792         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2793 #ifdef __BIG_ENDIAN
2794         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2795 #endif
2796         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2797
2798         /* Initialize the ring buffer's write pointers */
2799         ring->wptr = 0;
2800         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2801         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2802
2803         /* set the wb address wether it's enabled or not */
2804         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2805         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2806         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2807                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2808
2809         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2810         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2811                      lower_32_bits(wptr_gpu_addr));
2812         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2813                      upper_32_bits(wptr_gpu_addr));
2814
2815         mdelay(1);
2816         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2817
2818         rb_addr = ring->gpu_addr >> 8;
2819         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2820         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2821
2822         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2823
2824         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2825
2826         /* Init gfx ring 1 for pipe 1 */
2827         mutex_lock(&adev->srbm_mutex);
2828         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2829         mutex_unlock(&adev->srbm_mutex);
2830         ring = &adev->gfx.gfx_ring[1];
2831         rb_bufsz = order_base_2(ring->ring_size / 8);
2832         tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2833         tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2834         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2835         /* Initialize the ring buffer's write pointers */
2836         ring->wptr = 0;
2837         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2838         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2839         /* Set the wb address wether it's enabled or not */
2840         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2841         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2842         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2843                 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2844         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2845         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2846                 lower_32_bits(wptr_gpu_addr));
2847         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2848                 upper_32_bits(wptr_gpu_addr));
2849
2850         mdelay(1);
2851         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2852
2853         rb_addr = ring->gpu_addr >> 8;
2854         WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2855         WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2856         WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2857
2858         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2859
2860         /* Switch to pipe 0 */
2861         mutex_lock(&adev->srbm_mutex);
2862         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2863         mutex_unlock(&adev->srbm_mutex);
2864
2865         /* start the ring */
2866         gfx_v10_0_cp_gfx_start(adev);
2867
2868         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2869                 ring = &adev->gfx.gfx_ring[i];
2870                 ring->sched.ready = true;
2871         }
2872
2873         return 0;
2874 }
2875
2876 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2877 {
2878         int i;
2879
2880         if (enable) {
2881                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2882         } else {
2883                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2884                              (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2885                               CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2886                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2887                         adev->gfx.compute_ring[i].sched.ready = false;
2888                 adev->gfx.kiq.ring.sched.ready = false;
2889         }
2890         udelay(50);
2891 }
2892
2893 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2894 {
2895         const struct gfx_firmware_header_v1_0 *mec_hdr;
2896         const __le32 *fw_data;
2897         unsigned i;
2898         u32 tmp;
2899         u32 usec_timeout = 50000; /* Wait for 50 ms */
2900
2901         if (!adev->gfx.mec_fw)
2902                 return -EINVAL;
2903
2904         gfx_v10_0_cp_compute_enable(adev, false);
2905
2906         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2907         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2908
2909         fw_data = (const __le32 *)
2910                 (adev->gfx.mec_fw->data +
2911                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2912
2913         /* Trigger an invalidation of the L1 instruction caches */
2914         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2915         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2916         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2917
2918         /* Wait for invalidation complete */
2919         for (i = 0; i < usec_timeout; i++) {
2920                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2921                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2922                                        INVALIDATE_CACHE_COMPLETE))
2923                         break;
2924                 udelay(1);
2925         }
2926
2927         if (i >= usec_timeout) {
2928                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2929                 return -EINVAL;
2930         }
2931
2932         if (amdgpu_emu_mode == 1)
2933                 adev->nbio.funcs->hdp_flush(adev, NULL);
2934
2935         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2936         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2937         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2938         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2939         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2940
2941         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2942                      0xFFFFF000);
2943         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2944                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2945
2946         /* MEC1 */
2947         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2948
2949         for (i = 0; i < mec_hdr->jt_size; i++)
2950                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2951                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2952
2953         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2954
2955         /*
2956          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
2957          * different microcode than MEC1.
2958          */
2959
2960         return 0;
2961 }
2962
2963 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2964 {
2965         uint32_t tmp;
2966         struct amdgpu_device *adev = ring->adev;
2967
2968         /* tell RLC which is KIQ queue */
2969         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2970         tmp &= 0xffffff00;
2971         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2972         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2973         tmp |= 0x80;
2974         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2975 }
2976
2977 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2978 {
2979         struct amdgpu_device *adev = ring->adev;
2980         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2981         uint64_t hqd_gpu_addr, wb_gpu_addr;
2982         uint32_t tmp;
2983         uint32_t rb_bufsz;
2984
2985         /* set up gfx hqd wptr */
2986         mqd->cp_gfx_hqd_wptr = 0;
2987         mqd->cp_gfx_hqd_wptr_hi = 0;
2988
2989         /* set the pointer to the MQD */
2990         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2991         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2992
2993         /* set up mqd control */
2994         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2995         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2996         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2997         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2998         mqd->cp_gfx_mqd_control = tmp;
2999
3000         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3001         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
3002         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3003         mqd->cp_gfx_hqd_vmid = 0;
3004
3005         /* set up default queue priority level
3006          * 0x0 = low priority, 0x1 = high priority */
3007         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
3008         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3009         mqd->cp_gfx_hqd_queue_priority = tmp;
3010
3011         /* set up time quantum */
3012         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
3013         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3014         mqd->cp_gfx_hqd_quantum = tmp;
3015
3016         /* set up gfx hqd base. this is similar as CP_RB_BASE */
3017         hqd_gpu_addr = ring->gpu_addr >> 8;
3018         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3019         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3020
3021         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3022         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3023         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3024         mqd->cp_gfx_hqd_rptr_addr_hi =
3025                 upper_32_bits(wb_gpu_addr) & 0xffff;
3026
3027         /* set up rb_wptr_poll addr */
3028         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3029         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3030         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3031
3032         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3033         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
3034         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
3035         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3036         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3037 #ifdef __BIG_ENDIAN
3038         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3039 #endif
3040         mqd->cp_gfx_hqd_cntl = tmp;
3041
3042         /* set up cp_doorbell_control */
3043         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3044         if (ring->use_doorbell) {
3045                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3046                                     DOORBELL_OFFSET, ring->doorbell_index);
3047                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3048                                     DOORBELL_EN, 1);
3049         } else
3050                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3051                                     DOORBELL_EN, 0);
3052         mqd->cp_rb_doorbell_control = tmp;
3053
3054         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3055         ring->wptr = 0;
3056         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
3057
3058         /* active the queue */
3059         mqd->cp_gfx_hqd_active = 1;
3060
3061         return 0;
3062 }
3063
3064 #ifdef BRING_UP_DEBUG
3065 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3066 {
3067         struct amdgpu_device *adev = ring->adev;
3068         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3069
3070         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3071         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3072         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3073
3074         /* set GFX_MQD_BASE */
3075         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3076         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3077
3078         /* set GFX_MQD_CONTROL */
3079         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3080
3081         /* set GFX_HQD_VMID to 0 */
3082         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3083
3084         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3085                         mqd->cp_gfx_hqd_queue_priority);
3086         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3087
3088         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
3089         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3090         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3091
3092         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3093         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3094         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3095
3096         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3097         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3098
3099         /* set RB_WPTR_POLL_ADDR */
3100         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3101         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3102
3103         /* set RB_DOORBELL_CONTROL */
3104         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3105
3106         /* active the queue */
3107         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3108
3109         return 0;
3110 }
3111 #endif
3112
3113 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
3114 {
3115         struct amdgpu_device *adev = ring->adev;
3116         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3117
3118         if (!adev->in_gpu_reset && !adev->in_suspend) {
3119                 memset((void *)mqd, 0, sizeof(*mqd));
3120                 mutex_lock(&adev->srbm_mutex);
3121                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3122                 gfx_v10_0_gfx_mqd_init(ring);
3123 #ifdef BRING_UP_DEBUG
3124                 gfx_v10_0_gfx_queue_init_register(ring);
3125 #endif
3126                 nv_grbm_select(adev, 0, 0, 0, 0);
3127                 mutex_unlock(&adev->srbm_mutex);
3128                 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
3129                         memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd));
3130         } else if (adev->in_gpu_reset) {
3131                 /* reset mqd with the backup copy */
3132                 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
3133                         memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
3134                 /* reset the ring */
3135                 ring->wptr = 0;
3136                 adev->wb.wb[ring->wptr_offs] = 0;
3137                 amdgpu_ring_clear_ring(ring);
3138 #ifdef BRING_UP_DEBUG
3139                 mutex_lock(&adev->srbm_mutex);
3140                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3141                 gfx_v10_0_gfx_queue_init_register(ring);
3142                 nv_grbm_select(adev, 0, 0, 0, 0);
3143                 mutex_unlock(&adev->srbm_mutex);
3144 #endif
3145         } else {
3146                 amdgpu_ring_clear_ring(ring);
3147         }
3148
3149         return 0;
3150 }
3151
3152 #ifndef BRING_UP_DEBUG
3153 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
3154 {
3155         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3156         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3157         int r, i;
3158
3159         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3160                 return -EINVAL;
3161
3162         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3163                                         adev->gfx.num_gfx_rings);
3164         if (r) {
3165                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3166                 return r;
3167         }
3168
3169         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3170                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3171
3172         r = amdgpu_ring_test_ring(kiq_ring);
3173         if (r) {
3174                 DRM_ERROR("kfq enable failed\n");
3175                 kiq_ring->sched.ready = false;
3176         }
3177         return r;
3178 }
3179 #endif
3180
3181 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3182 {
3183         int r, i;
3184         struct amdgpu_ring *ring;
3185
3186         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3187                 ring = &adev->gfx.gfx_ring[i];
3188
3189                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3190                 if (unlikely(r != 0))
3191                         goto done;
3192
3193                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3194                 if (!r) {
3195                         r = gfx_v10_0_gfx_init_queue(ring);
3196                         amdgpu_bo_kunmap(ring->mqd_obj);
3197                         ring->mqd_ptr = NULL;
3198                 }
3199                 amdgpu_bo_unreserve(ring->mqd_obj);
3200                 if (r)
3201                         goto done;
3202         }
3203 #ifndef BRING_UP_DEBUG
3204         r = gfx_v10_0_kiq_enable_kgq(adev);
3205         if (r)
3206                 goto done;
3207 #endif
3208         r = gfx_v10_0_cp_gfx_start(adev);
3209         if (r)
3210                 goto done;
3211
3212         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3213                 ring = &adev->gfx.gfx_ring[i];
3214                 ring->sched.ready = true;
3215         }
3216 done:
3217         return r;
3218 }
3219
3220 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
3221 {
3222         struct amdgpu_device *adev = ring->adev;
3223         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3224         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3225         uint32_t tmp;
3226
3227         mqd->header = 0xC0310800;
3228         mqd->compute_pipelinestat_enable = 0x00000001;
3229         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3230         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3231         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3232         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3233         mqd->compute_misc_reserved = 0x00000003;
3234
3235         eop_base_addr = ring->eop_gpu_addr >> 8;
3236         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3237         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3238
3239         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3240         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3241         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3242                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
3243
3244         mqd->cp_hqd_eop_control = tmp;
3245
3246         /* enable doorbell? */
3247         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3248
3249         if (ring->use_doorbell) {
3250                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3251                                     DOORBELL_OFFSET, ring->doorbell_index);
3252                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3253                                     DOORBELL_EN, 1);
3254                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3255                                     DOORBELL_SOURCE, 0);
3256                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3257                                     DOORBELL_HIT, 0);
3258         } else {
3259                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3260                                     DOORBELL_EN, 0);
3261         }
3262
3263         mqd->cp_hqd_pq_doorbell_control = tmp;
3264
3265         /* disable the queue if it's active */
3266         ring->wptr = 0;
3267         mqd->cp_hqd_dequeue_request = 0;
3268         mqd->cp_hqd_pq_rptr = 0;
3269         mqd->cp_hqd_pq_wptr_lo = 0;
3270         mqd->cp_hqd_pq_wptr_hi = 0;
3271
3272         /* set the pointer to the MQD */
3273         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3274         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3275
3276         /* set MQD vmid to 0 */
3277         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3278         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3279         mqd->cp_mqd_control = tmp;
3280
3281         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3282         hqd_gpu_addr = ring->gpu_addr >> 8;
3283         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3284         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3285
3286         /* set up the HQD, this is similar to CP_RB0_CNTL */
3287         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3288         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3289                             (order_base_2(ring->ring_size / 4) - 1));
3290         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3291                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3292 #ifdef __BIG_ENDIAN
3293         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3294 #endif
3295         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3296         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3297         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3298         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3299         mqd->cp_hqd_pq_control = tmp;
3300
3301         /* set the wb address whether it's enabled or not */
3302         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3303         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3304         mqd->cp_hqd_pq_rptr_report_addr_hi =
3305                 upper_32_bits(wb_gpu_addr) & 0xffff;
3306
3307         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3308         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3309         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3310         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3311
3312         tmp = 0;
3313         /* enable the doorbell if requested */
3314         if (ring->use_doorbell) {
3315                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3316                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3317                                 DOORBELL_OFFSET, ring->doorbell_index);
3318
3319                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3320                                     DOORBELL_EN, 1);
3321                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3322                                     DOORBELL_SOURCE, 0);
3323                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3324                                     DOORBELL_HIT, 0);
3325         }
3326
3327         mqd->cp_hqd_pq_doorbell_control = tmp;
3328
3329         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3330         ring->wptr = 0;
3331         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3332
3333         /* set the vmid for the queue */
3334         mqd->cp_hqd_vmid = 0;
3335
3336         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3337         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3338         mqd->cp_hqd_persistent_state = tmp;
3339
3340         /* set MIN_IB_AVAIL_SIZE */
3341         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3342         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3343         mqd->cp_hqd_ib_control = tmp;
3344
3345         /* activate the queue */
3346         mqd->cp_hqd_active = 1;
3347
3348         return 0;
3349 }
3350
3351 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
3352 {
3353         struct amdgpu_device *adev = ring->adev;
3354         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3355         int j;
3356
3357         /* disable wptr polling */
3358         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3359
3360         /* write the EOP addr */
3361         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3362                mqd->cp_hqd_eop_base_addr_lo);
3363         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3364                mqd->cp_hqd_eop_base_addr_hi);
3365
3366         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3367         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3368                mqd->cp_hqd_eop_control);
3369
3370         /* enable doorbell? */
3371         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3372                mqd->cp_hqd_pq_doorbell_control);
3373
3374         /* disable the queue if it's active */
3375         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3376                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3377                 for (j = 0; j < adev->usec_timeout; j++) {
3378                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3379                                 break;
3380                         udelay(1);
3381                 }
3382                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3383                        mqd->cp_hqd_dequeue_request);
3384                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3385                        mqd->cp_hqd_pq_rptr);
3386                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3387                        mqd->cp_hqd_pq_wptr_lo);
3388                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3389                        mqd->cp_hqd_pq_wptr_hi);
3390         }
3391
3392         /* set the pointer to the MQD */
3393         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3394                mqd->cp_mqd_base_addr_lo);
3395         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3396                mqd->cp_mqd_base_addr_hi);
3397
3398         /* set MQD vmid to 0 */
3399         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3400                mqd->cp_mqd_control);
3401
3402         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3403         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3404                mqd->cp_hqd_pq_base_lo);
3405         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3406                mqd->cp_hqd_pq_base_hi);
3407
3408         /* set up the HQD, this is similar to CP_RB0_CNTL */
3409         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3410                mqd->cp_hqd_pq_control);
3411
3412         /* set the wb address whether it's enabled or not */
3413         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3414                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3415         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3416                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3417
3418         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3419         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3420                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3421         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3422                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3423
3424         /* enable the doorbell if requested */
3425         if (ring->use_doorbell) {
3426                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3427                         (adev->doorbell_index.kiq * 2) << 2);
3428                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3429                         (adev->doorbell_index.userqueue_end * 2) << 2);
3430         }
3431
3432         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3433                mqd->cp_hqd_pq_doorbell_control);
3434
3435         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3436         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3437                mqd->cp_hqd_pq_wptr_lo);
3438         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3439                mqd->cp_hqd_pq_wptr_hi);
3440
3441         /* set the vmid for the queue */
3442         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3443
3444         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3445                mqd->cp_hqd_persistent_state);
3446
3447         /* activate the queue */
3448         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3449                mqd->cp_hqd_active);
3450
3451         if (ring->use_doorbell)
3452                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3453
3454         return 0;
3455 }
3456
3457 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
3458 {
3459         struct amdgpu_device *adev = ring->adev;
3460         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3461         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3462
3463         gfx_v10_0_kiq_setting(ring);
3464
3465         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3466                 /* reset MQD to a clean status */
3467                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3468                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3469
3470                 /* reset ring buffer */
3471                 ring->wptr = 0;
3472                 amdgpu_ring_clear_ring(ring);
3473
3474                 mutex_lock(&adev->srbm_mutex);
3475                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3476                 gfx_v10_0_kiq_init_register(ring);
3477                 nv_grbm_select(adev, 0, 0, 0, 0);
3478                 mutex_unlock(&adev->srbm_mutex);
3479         } else {
3480                 memset((void *)mqd, 0, sizeof(*mqd));
3481                 mutex_lock(&adev->srbm_mutex);
3482                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3483                 gfx_v10_0_compute_mqd_init(ring);
3484                 gfx_v10_0_kiq_init_register(ring);
3485                 nv_grbm_select(adev, 0, 0, 0, 0);
3486                 mutex_unlock(&adev->srbm_mutex);
3487
3488                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3489                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3490         }
3491
3492         return 0;
3493 }
3494
3495 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
3496 {
3497         struct amdgpu_device *adev = ring->adev;
3498         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3499         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3500
3501         if (!adev->in_gpu_reset && !adev->in_suspend) {
3502                 memset((void *)mqd, 0, sizeof(*mqd));
3503                 mutex_lock(&adev->srbm_mutex);
3504                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3505                 gfx_v10_0_compute_mqd_init(ring);
3506                 nv_grbm_select(adev, 0, 0, 0, 0);
3507                 mutex_unlock(&adev->srbm_mutex);
3508
3509                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3510                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3511         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3512                 /* reset MQD to a clean status */
3513                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3514                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3515
3516                 /* reset ring buffer */
3517                 ring->wptr = 0;
3518                 amdgpu_ring_clear_ring(ring);
3519         } else {
3520                 amdgpu_ring_clear_ring(ring);
3521         }
3522
3523         return 0;
3524 }
3525
3526 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
3527 {
3528         struct amdgpu_ring *ring;
3529         int r;
3530
3531         ring = &adev->gfx.kiq.ring;
3532
3533         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3534         if (unlikely(r != 0))
3535                 return r;
3536
3537         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3538         if (unlikely(r != 0))
3539                 return r;
3540
3541         gfx_v10_0_kiq_init_queue(ring);
3542         amdgpu_bo_kunmap(ring->mqd_obj);
3543         ring->mqd_ptr = NULL;
3544         amdgpu_bo_unreserve(ring->mqd_obj);
3545         ring->sched.ready = true;
3546         return 0;
3547 }
3548
3549 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
3550 {
3551         struct amdgpu_ring *ring = NULL;
3552         int r = 0, i;
3553
3554         gfx_v10_0_cp_compute_enable(adev, true);
3555
3556         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3557                 ring = &adev->gfx.compute_ring[i];
3558
3559                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3560                 if (unlikely(r != 0))
3561                         goto done;
3562                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3563                 if (!r) {
3564                         r = gfx_v10_0_kcq_init_queue(ring);
3565                         amdgpu_bo_kunmap(ring->mqd_obj);
3566                         ring->mqd_ptr = NULL;
3567                 }
3568                 amdgpu_bo_unreserve(ring->mqd_obj);
3569                 if (r)
3570                         goto done;
3571         }
3572
3573         r = amdgpu_gfx_enable_kcq(adev);
3574 done:
3575         return r;
3576 }
3577
3578 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
3579 {
3580         int r, i;
3581         struct amdgpu_ring *ring;
3582
3583         if (!(adev->flags & AMD_IS_APU))
3584                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3585
3586         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3587                 /* legacy firmware loading */
3588                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
3589                 if (r)
3590                         return r;
3591
3592                 r = gfx_v10_0_cp_compute_load_microcode(adev);
3593                 if (r)
3594                         return r;
3595         }
3596
3597         r = gfx_v10_0_kiq_resume(adev);
3598         if (r)
3599                 return r;
3600
3601         r = gfx_v10_0_kcq_resume(adev);
3602         if (r)
3603                 return r;
3604
3605         if (!amdgpu_async_gfx_ring) {
3606                 r = gfx_v10_0_cp_gfx_resume(adev);
3607                 if (r)
3608                         return r;
3609         } else {
3610                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
3611                 if (r)
3612                         return r;
3613         }
3614
3615         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3616                 ring = &adev->gfx.gfx_ring[i];
3617                 DRM_INFO("gfx %d ring me %d pipe %d q %d\n",
3618                          i, ring->me, ring->pipe, ring->queue);
3619                 r = amdgpu_ring_test_ring(ring);
3620                 if (r) {
3621                         ring->sched.ready = false;
3622                         return r;
3623                 }
3624         }
3625
3626         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3627                 ring = &adev->gfx.compute_ring[i];
3628                 ring->sched.ready = true;
3629                 DRM_INFO("compute ring %d mec %d pipe %d q %d\n",
3630                          i, ring->me, ring->pipe, ring->queue);
3631                 r = amdgpu_ring_test_ring(ring);
3632                 if (r)
3633                         ring->sched.ready = false;
3634         }
3635
3636         return 0;
3637 }
3638
3639 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
3640 {
3641         gfx_v10_0_cp_gfx_enable(adev, enable);
3642         gfx_v10_0_cp_compute_enable(adev, enable);
3643 }
3644
3645 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
3646 {
3647         uint32_t data, pattern = 0xDEADBEEF;
3648
3649         /* check if mmVGT_ESGS_RING_SIZE_UMD
3650          * has been remapped to mmVGT_ESGS_RING_SIZE */
3651         data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3652
3653         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3654
3655         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3656
3657         if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3658                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3659                 return true;
3660         } else {
3661                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3662                 return false;
3663         }
3664 }
3665
3666 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
3667 {
3668         uint32_t data;
3669
3670         /* initialize cam_index to 0
3671          * index will auto-inc after each data writting */
3672         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3673
3674         /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
3675         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3676                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3677                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3678                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3679         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3680         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3681
3682         /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
3683         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3684                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3685                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3686                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3687         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3688         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3689
3690         /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
3691         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3692                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3693                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3694                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3695         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3696         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3697
3698         /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
3699         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3700                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3701                (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3702                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3703         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3704         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3705
3706         /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
3707         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3708                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3709                (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3710                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3711         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3712         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3713
3714         /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
3715         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3716                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3717                (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3718                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3719         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3720         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3721
3722         /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
3723         data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3724                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3725                (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3726                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3727         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3728         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3729 }
3730
3731 static int gfx_v10_0_hw_init(void *handle)
3732 {
3733         int r;
3734         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3735
3736         r = gfx_v10_0_csb_vram_pin(adev);
3737         if (r)
3738                 return r;
3739
3740         if (!amdgpu_emu_mode)
3741                 gfx_v10_0_init_golden_registers(adev);
3742
3743         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3744                 /**
3745                  * For gfx 10, rlc firmware loading relies on smu firmware is
3746                  * loaded firstly, so in direct type, it has to load smc ucode
3747                  * here before rlc.
3748                  */
3749                 r = smu_load_microcode(&adev->smu);
3750                 if (r)
3751                         return r;
3752
3753                 r = smu_check_fw_status(&adev->smu);
3754                 if (r) {
3755                         pr_err("SMC firmware status is not correct\n");
3756                         return r;
3757                 }
3758         }
3759
3760         /* if GRBM CAM not remapped, set up the remapping */
3761         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
3762                 gfx_v10_0_setup_grbm_cam_remapping(adev);
3763
3764         gfx_v10_0_constants_init(adev);
3765
3766         r = gfx_v10_0_rlc_resume(adev);
3767         if (r)
3768                 return r;
3769
3770         /*
3771          * init golden registers and rlc resume may override some registers,
3772          * reconfig them here
3773          */
3774         gfx_v10_0_tcp_harvest(adev);
3775
3776         r = gfx_v10_0_cp_resume(adev);
3777         if (r)
3778                 return r;
3779
3780         return r;
3781 }
3782
3783 #ifndef BRING_UP_DEBUG
3784 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
3785 {
3786         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3787         struct amdgpu_ring *kiq_ring = &kiq->ring;
3788         int i;
3789
3790         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3791                 return -EINVAL;
3792
3793         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3794                                         adev->gfx.num_gfx_rings))
3795                 return -ENOMEM;
3796
3797         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3798                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3799                                            PREEMPT_QUEUES, 0, 0);
3800
3801         return amdgpu_ring_test_ring(kiq_ring);
3802 }
3803 #endif
3804
3805 static int gfx_v10_0_hw_fini(void *handle)
3806 {
3807         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3808         int r;
3809
3810         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3811         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3812 #ifndef BRING_UP_DEBUG
3813         if (amdgpu_async_gfx_ring) {
3814                 r = gfx_v10_0_kiq_disable_kgq(adev);
3815                 if (r)
3816                         DRM_ERROR("KGQ disable failed\n");
3817         }
3818 #endif
3819         if (amdgpu_gfx_disable_kcq(adev))
3820                 DRM_ERROR("KCQ disable failed\n");
3821         if (amdgpu_sriov_vf(adev)) {
3822                 pr_debug("For SRIOV client, shouldn't do anything.\n");
3823                 return 0;
3824         }
3825         gfx_v10_0_cp_enable(adev, false);
3826         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3827         gfx_v10_0_csb_vram_unpin(adev);
3828
3829         return 0;
3830 }
3831
3832 static int gfx_v10_0_suspend(void *handle)
3833 {
3834         return gfx_v10_0_hw_fini(handle);
3835 }
3836
3837 static int gfx_v10_0_resume(void *handle)
3838 {
3839         return gfx_v10_0_hw_init(handle);
3840 }
3841
3842 static bool gfx_v10_0_is_idle(void *handle)
3843 {
3844         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3845
3846         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3847                                 GRBM_STATUS, GUI_ACTIVE))
3848                 return false;
3849         else
3850                 return true;
3851 }
3852
3853 static int gfx_v10_0_wait_for_idle(void *handle)
3854 {
3855         unsigned i;
3856         u32 tmp;
3857         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3858
3859         for (i = 0; i < adev->usec_timeout; i++) {
3860                 /* read MC_STATUS */
3861                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3862                         GRBM_STATUS__GUI_ACTIVE_MASK;
3863
3864                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3865                         return 0;
3866                 udelay(1);
3867         }
3868         return -ETIMEDOUT;
3869 }
3870
3871 static int gfx_v10_0_soft_reset(void *handle)
3872 {
3873         u32 grbm_soft_reset = 0;
3874         u32 tmp;
3875         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3876
3877         /* GRBM_STATUS */
3878         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3879         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3880                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3881                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
3882                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
3883                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
3884                    | GRBM_STATUS__BCI_BUSY_MASK)) {
3885                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3886                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
3887                                                 1);
3888                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3889                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
3890                                                 1);
3891         }
3892
3893         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3894                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3895                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
3896                                                 1);
3897         }
3898
3899         /* GRBM_STATUS2 */
3900         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3901         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3902                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3903                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC,
3904                                                 1);
3905
3906         if (grbm_soft_reset) {
3907                 /* stop the rlc */
3908                 gfx_v10_0_rlc_stop(adev);
3909
3910                 /* Disable GFX parsing/prefetching */
3911                 gfx_v10_0_cp_gfx_enable(adev, false);
3912
3913                 /* Disable MEC parsing/prefetching */
3914                 gfx_v10_0_cp_compute_enable(adev, false);
3915
3916                 if (grbm_soft_reset) {
3917                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3918                         tmp |= grbm_soft_reset;
3919                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3920                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3921                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3922
3923                         udelay(50);
3924
3925                         tmp &= ~grbm_soft_reset;
3926                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3927                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3928                 }
3929
3930                 /* Wait a little for things to settle down */
3931                 udelay(50);
3932         }
3933         return 0;
3934 }
3935
3936 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3937 {
3938         uint64_t clock;
3939
3940         mutex_lock(&adev->gfx.gpu_clock_mutex);
3941         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3942         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3943                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3944         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3945         return clock;
3946 }
3947
3948 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3949                                            uint32_t vmid,
3950                                            uint32_t gds_base, uint32_t gds_size,
3951                                            uint32_t gws_base, uint32_t gws_size,
3952                                            uint32_t oa_base, uint32_t oa_size)
3953 {
3954         struct amdgpu_device *adev = ring->adev;
3955
3956         /* GDS Base */
3957         gfx_v10_0_write_data_to_reg(ring, 0, false,
3958                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3959                                     gds_base);
3960
3961         /* GDS Size */
3962         gfx_v10_0_write_data_to_reg(ring, 0, false,
3963                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3964                                     gds_size);
3965
3966         /* GWS */
3967         gfx_v10_0_write_data_to_reg(ring, 0, false,
3968                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3969                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3970
3971         /* OA */
3972         gfx_v10_0_write_data_to_reg(ring, 0, false,
3973                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3974                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
3975 }
3976
3977 static int gfx_v10_0_early_init(void *handle)
3978 {
3979         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3980
3981         adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;
3982         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3983
3984         gfx_v10_0_set_kiq_pm4_funcs(adev);
3985         gfx_v10_0_set_ring_funcs(adev);
3986         gfx_v10_0_set_irq_funcs(adev);
3987         gfx_v10_0_set_gds_init(adev);
3988         gfx_v10_0_set_rlc_funcs(adev);
3989
3990         return 0;
3991 }
3992
3993 static int gfx_v10_0_late_init(void *handle)
3994 {
3995         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3996         int r;
3997
3998         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3999         if (r)
4000                 return r;
4001
4002         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4003         if (r)
4004                 return r;
4005
4006         return 0;
4007 }
4008
4009 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
4010 {
4011         uint32_t rlc_cntl;
4012
4013         /* if RLC is not enabled, do nothing */
4014         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4015         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4016 }
4017
4018 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
4019 {
4020         uint32_t data;
4021         unsigned i;
4022
4023         data = RLC_SAFE_MODE__CMD_MASK;
4024         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4025         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4026
4027         /* wait for RLC_SAFE_MODE */
4028         for (i = 0; i < adev->usec_timeout; i++) {
4029                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4030                         break;
4031                 udelay(1);
4032         }
4033 }
4034
4035 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
4036 {
4037         uint32_t data;
4038
4039         data = RLC_SAFE_MODE__CMD_MASK;
4040         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4041 }
4042
4043 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4044                                                       bool enable)
4045 {
4046         uint32_t data, def;
4047
4048         /* It is disabled by HW by default */
4049         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4050                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4051                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4052                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4053                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4054                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4055
4056                 /* only for Vega10 & Raven1 */
4057                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4058
4059                 if (def != data)
4060                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4061
4062                 /* MGLS is a global flag to control all MGLS in GFX */
4063                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4064                         /* 2 - RLC memory Light sleep */
4065                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4066                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4067                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4068                                 if (def != data)
4069                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4070                         }
4071                         /* 3 - CP memory Light sleep */
4072                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4073                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4074                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4075                                 if (def != data)
4076                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4077                         }
4078                 }
4079         } else {
4080                 /* 1 - MGCG_OVERRIDE */
4081                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4082                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4083                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4084                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4085                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4086                 if (def != data)
4087                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4088
4089                 /* 2 - disable MGLS in RLC */
4090                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4091                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4092                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4093                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4094                 }
4095
4096                 /* 3 - disable MGLS in CP */
4097                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4098                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4099                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4100                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4101                 }
4102         }
4103 }
4104
4105 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
4106                                            bool enable)
4107 {
4108         uint32_t data, def;
4109
4110         /* Enable 3D CGCG/CGLS */
4111         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4112                 /* write cmd to clear cgcg/cgls ov */
4113                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4114                 /* unset CGCG override */
4115                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4116                 /* update CGCG and CGLS override bits */
4117                 if (def != data)
4118                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4119                 /* enable 3Dcgcg FSM(0x0000363f) */
4120                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4121                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4122                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4123                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4124                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4125                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4126                 if (def != data)
4127                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4128
4129                 /* set IDLE_POLL_COUNT(0x00900100) */
4130                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4131                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4132                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4133                 if (def != data)
4134                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4135         } else {
4136                 /* Disable CGCG/CGLS */
4137                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4138                 /* disable cgcg, cgls should be disabled */
4139                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4140                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4141                 /* disable cgcg and cgls in FSM */
4142                 if (def != data)
4143                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4144         }
4145 }
4146
4147 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4148                                                       bool enable)
4149 {
4150         uint32_t def, data;
4151
4152         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4153                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4154                 /* unset CGCG override */
4155                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4156                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4157                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4158                 else
4159                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4160                 /* update CGCG and CGLS override bits */
4161                 if (def != data)
4162                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4163
4164                 /* enable cgcg FSM(0x0000363F) */
4165                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4166                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4167                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4168                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4169                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4170                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4171                 if (def != data)
4172                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4173
4174                 /* set IDLE_POLL_COUNT(0x00900100) */
4175                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4176                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4177                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4178                 if (def != data)
4179                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4180         } else {
4181                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4182                 /* reset CGCG/CGLS bits */
4183                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4184                 /* disable cgcg and cgls in FSM */
4185                 if (def != data)
4186                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4187         }
4188 }
4189
4190 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4191                                             bool enable)
4192 {
4193         amdgpu_gfx_rlc_enter_safe_mode(adev);
4194
4195         if (enable) {
4196                 /* CGCG/CGLS should be enabled after MGCG/MGLS
4197                  * ===  MGCG + MGLS ===
4198                  */
4199                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4200                 /* ===  CGCG /CGLS for GFX 3D Only === */
4201                 gfx_v10_0_update_3d_clock_gating(adev, enable);
4202                 /* ===  CGCG + CGLS === */
4203                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4204         } else {
4205                 /* CGCG/CGLS should be disabled before MGCG/MGLS
4206                  * ===  CGCG + CGLS ===
4207                  */
4208                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4209                 /* ===  CGCG /CGLS for GFX 3D Only === */
4210                 gfx_v10_0_update_3d_clock_gating(adev, enable);
4211                 /* ===  MGCG + MGLS === */
4212                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4213         }
4214
4215         if (adev->cg_flags &
4216             (AMD_CG_SUPPORT_GFX_MGCG |
4217              AMD_CG_SUPPORT_GFX_CGLS |
4218              AMD_CG_SUPPORT_GFX_CGCG |
4219              AMD_CG_SUPPORT_GFX_CGLS |
4220              AMD_CG_SUPPORT_GFX_3D_CGCG |
4221              AMD_CG_SUPPORT_GFX_3D_CGLS))
4222                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
4223
4224         amdgpu_gfx_rlc_exit_safe_mode(adev);
4225
4226         return 0;
4227 }
4228
4229 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
4230         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
4231         .set_safe_mode = gfx_v10_0_set_safe_mode,
4232         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
4233         .init = gfx_v10_0_rlc_init,
4234         .get_csb_size = gfx_v10_0_get_csb_size,
4235         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
4236         .resume = gfx_v10_0_rlc_resume,
4237         .stop = gfx_v10_0_rlc_stop,
4238         .reset = gfx_v10_0_rlc_reset,
4239         .start = gfx_v10_0_rlc_start
4240 };
4241
4242 static int gfx_v10_0_set_powergating_state(void *handle,
4243                                           enum amd_powergating_state state)
4244 {
4245         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4246         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
4247         switch (adev->asic_type) {
4248         case CHIP_NAVI10:
4249         case CHIP_NAVI14:
4250                 if (!enable) {
4251                         amdgpu_gfx_off_ctrl(adev, false);
4252                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4253                 } else
4254                         amdgpu_gfx_off_ctrl(adev, true);
4255                 break;
4256         default:
4257                 break;
4258         }
4259         return 0;
4260 }
4261
4262 static int gfx_v10_0_set_clockgating_state(void *handle,
4263                                           enum amd_clockgating_state state)
4264 {
4265         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4266
4267         switch (adev->asic_type) {
4268         case CHIP_NAVI10:
4269         case CHIP_NAVI14:
4270         case CHIP_NAVI12:
4271                 gfx_v10_0_update_gfx_clock_gating(adev,
4272                                                  state == AMD_CG_STATE_GATE ? true : false);
4273                 break;
4274         default:
4275                 break;
4276         }
4277         return 0;
4278 }
4279
4280 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
4281 {
4282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4283         int data;
4284
4285         /* AMD_CG_SUPPORT_GFX_MGCG */
4286         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4287         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4288                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4289
4290         /* AMD_CG_SUPPORT_GFX_CGCG */
4291         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4292         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4293                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4294
4295         /* AMD_CG_SUPPORT_GFX_CGLS */
4296         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4297                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4298
4299         /* AMD_CG_SUPPORT_GFX_RLC_LS */
4300         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4301         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4302                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4303
4304         /* AMD_CG_SUPPORT_GFX_CP_LS */
4305         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4306         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4307                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4308
4309         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4310         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4311         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4312                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4313
4314         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4315         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4316                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4317 }
4318
4319 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4320 {
4321         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
4322 }
4323
4324 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4325 {
4326         struct amdgpu_device *adev = ring->adev;
4327         u64 wptr;
4328
4329         /* XXX check if swapping is necessary on BE */
4330         if (ring->use_doorbell) {
4331                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4332         } else {
4333                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4334                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4335         }
4336
4337         return wptr;
4338 }
4339
4340 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4341 {
4342         struct amdgpu_device *adev = ring->adev;
4343
4344         if (ring->use_doorbell) {
4345                 /* XXX check if swapping is necessary on BE */
4346                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4347                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4348         } else {
4349                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4350                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4351         }
4352 }
4353
4354 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4355 {
4356         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
4357 }
4358
4359 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4360 {
4361         u64 wptr;
4362
4363         /* XXX check if swapping is necessary on BE */
4364         if (ring->use_doorbell)
4365                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4366         else
4367                 BUG();
4368         return wptr;
4369 }
4370
4371 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4372 {
4373         struct amdgpu_device *adev = ring->adev;
4374
4375         /* XXX check if swapping is necessary on BE */
4376         if (ring->use_doorbell) {
4377                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4378                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4379         } else {
4380                 BUG(); /* only DOORBELL method supported on gfx10 now */
4381         }
4382 }
4383
4384 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4385 {
4386         struct amdgpu_device *adev = ring->adev;
4387         u32 ref_and_mask, reg_mem_engine;
4388         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4389
4390         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4391                 switch (ring->me) {
4392                 case 1:
4393                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4394                         break;
4395                 case 2:
4396                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4397                         break;
4398                 default:
4399                         return;
4400                 }
4401                 reg_mem_engine = 0;
4402         } else {
4403                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4404                 reg_mem_engine = 1; /* pfp */
4405         }
4406
4407         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4408                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4409                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4410                                ref_and_mask, ref_and_mask, 0x20);
4411 }
4412
4413 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4414                                        struct amdgpu_job *job,
4415                                        struct amdgpu_ib *ib,
4416                                        uint32_t flags)
4417 {
4418         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4419         u32 header, control = 0;
4420
4421         if (ib->flags & AMDGPU_IB_FLAG_CE)
4422                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4423         else
4424                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4425
4426         control |= ib->length_dw | (vmid << 24);
4427
4428         if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4429                 control |= INDIRECT_BUFFER_PRE_ENB(1);
4430
4431                 if (flags & AMDGPU_IB_PREEMPTED)
4432                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
4433
4434                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4435                         gfx_v10_0_ring_emit_de_meta(ring,
4436                                     flags & AMDGPU_IB_PREEMPTED ? true : false);
4437         }
4438
4439         amdgpu_ring_write(ring, header);
4440         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4441         amdgpu_ring_write(ring,
4442 #ifdef __BIG_ENDIAN
4443                 (2 << 0) |
4444 #endif
4445                 lower_32_bits(ib->gpu_addr));
4446         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4447         amdgpu_ring_write(ring, control);
4448 }
4449
4450 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4451                                            struct amdgpu_job *job,
4452                                            struct amdgpu_ib *ib,
4453                                            uint32_t flags)
4454 {
4455         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4456         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4457
4458         /* Currently, there is a high possibility to get wave ID mismatch
4459          * between ME and GDS, leading to a hw deadlock, because ME generates
4460          * different wave IDs than the GDS expects. This situation happens
4461          * randomly when at least 5 compute pipes use GDS ordered append.
4462          * The wave IDs generated by ME are also wrong after suspend/resume.
4463          * Those are probably bugs somewhere else in the kernel driver.
4464          *
4465          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4466          * GDS to 0 for this ring (me/pipe).
4467          */
4468         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4469                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4470                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4471                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4472         }
4473
4474         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4475         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4476         amdgpu_ring_write(ring,
4477 #ifdef __BIG_ENDIAN
4478                                 (2 << 0) |
4479 #endif
4480                                 lower_32_bits(ib->gpu_addr));
4481         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4482         amdgpu_ring_write(ring, control);
4483 }
4484
4485 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4486                                      u64 seq, unsigned flags)
4487 {
4488         struct amdgpu_device *adev = ring->adev;
4489         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4490         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4491
4492         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
4493         if (adev->pdev->device == 0x50)
4494                 int_sel = false;
4495
4496         /* RELEASE_MEM - flush caches, send int */
4497         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4498         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4499                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
4500                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
4501                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
4502                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4503                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4504                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4505         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4506                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4507
4508         /*
4509          * the address should be Qword aligned if 64bit write, Dword
4510          * aligned if only send 32bit data low (discard data high)
4511          */
4512         if (write64bit)
4513                 BUG_ON(addr & 0x7);
4514         else
4515                 BUG_ON(addr & 0x3);
4516         amdgpu_ring_write(ring, lower_32_bits(addr));
4517         amdgpu_ring_write(ring, upper_32_bits(addr));
4518         amdgpu_ring_write(ring, lower_32_bits(seq));
4519         amdgpu_ring_write(ring, upper_32_bits(seq));
4520         amdgpu_ring_write(ring, 0);
4521 }
4522
4523 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4524 {
4525         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4526         uint32_t seq = ring->fence_drv.sync_seq;
4527         uint64_t addr = ring->fence_drv.gpu_addr;
4528
4529         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4530                                upper_32_bits(addr), seq, 0xffffffff, 4);
4531 }
4532
4533 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4534                                          unsigned vmid, uint64_t pd_addr)
4535 {
4536         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4537
4538         /* compute doesn't have PFP */
4539         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4540                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4541                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4542                 amdgpu_ring_write(ring, 0x0);
4543         }
4544 }
4545
4546 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4547                                           u64 seq, unsigned int flags)
4548 {
4549         struct amdgpu_device *adev = ring->adev;
4550
4551         /* we only allocate 32bit for each seq wb address */
4552         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4553
4554         /* write fence seq to the "addr" */
4555         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4556         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4557                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4558         amdgpu_ring_write(ring, lower_32_bits(addr));
4559         amdgpu_ring_write(ring, upper_32_bits(addr));
4560         amdgpu_ring_write(ring, lower_32_bits(seq));
4561
4562         if (flags & AMDGPU_FENCE_FLAG_INT) {
4563                 /* set register to trigger INT */
4564                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4565                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4566                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4567                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4568                 amdgpu_ring_write(ring, 0);
4569                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4570         }
4571 }
4572
4573 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
4574 {
4575         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4576         amdgpu_ring_write(ring, 0);
4577 }
4578
4579 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4580 {
4581         uint32_t dw2 = 0;
4582
4583         if (amdgpu_mcbp)
4584                 gfx_v10_0_ring_emit_ce_meta(ring,
4585                                     flags & AMDGPU_IB_PREEMPTED ? true : false);
4586
4587         gfx_v10_0_ring_emit_tmz(ring, true);
4588
4589         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4590         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4591                 /* set load_global_config & load_global_uconfig */
4592                 dw2 |= 0x8001;
4593                 /* set load_cs_sh_regs */
4594                 dw2 |= 0x01000000;
4595                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4596                 dw2 |= 0x10002;
4597
4598                 /* set load_ce_ram if preamble presented */
4599                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4600                         dw2 |= 0x10000000;
4601         } else {
4602                 /* still load_ce_ram if this is the first time preamble presented
4603                  * although there is no context switch happens.
4604                  */
4605                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4606                         dw2 |= 0x10000000;
4607         }
4608
4609         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4610         amdgpu_ring_write(ring, dw2);
4611         amdgpu_ring_write(ring, 0);
4612 }
4613
4614 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4615 {
4616         unsigned ret;
4617
4618         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4619         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4620         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4621         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4622         ret = ring->wptr & ring->buf_mask;
4623         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4624
4625         return ret;
4626 }
4627
4628 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4629 {
4630         unsigned cur;
4631         BUG_ON(offset > ring->buf_mask);
4632         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4633
4634         cur = (ring->wptr - 1) & ring->buf_mask;
4635         if (likely(cur > offset))
4636                 ring->ring[offset] = cur - offset;
4637         else
4638                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
4639 }
4640
4641 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
4642 {
4643         int i, r = 0;
4644         struct amdgpu_device *adev = ring->adev;
4645         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4646         struct amdgpu_ring *kiq_ring = &kiq->ring;
4647
4648         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4649                 return -EINVAL;
4650
4651         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
4652                 return -ENOMEM;
4653
4654         /* assert preemption condition */
4655         amdgpu_ring_set_preempt_cond_exec(ring, false);
4656
4657         /* assert IB preemption, emit the trailing fence */
4658         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4659                                    ring->trail_fence_gpu_addr,
4660                                    ++ring->trail_seq);
4661         amdgpu_ring_commit(kiq_ring);
4662
4663         /* poll the trailing fence */
4664         for (i = 0; i < adev->usec_timeout; i++) {
4665                 if (ring->trail_seq ==
4666                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4667                         break;
4668                 udelay(1);
4669         }
4670
4671         if (i >= adev->usec_timeout) {
4672                 r = -EINVAL;
4673                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4674         }
4675
4676         /* deassert preemption condition */
4677         amdgpu_ring_set_preempt_cond_exec(ring, true);
4678         return r;
4679 }
4680
4681 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
4682 {
4683         struct amdgpu_device *adev = ring->adev;
4684         struct v10_ce_ib_state ce_payload = {0};
4685         uint64_t csa_addr;
4686         int cnt;
4687
4688         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4689         csa_addr = amdgpu_csa_vaddr(ring->adev);
4690
4691         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4692         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4693                                  WRITE_DATA_DST_SEL(8) |
4694                                  WR_CONFIRM) |
4695                                  WRITE_DATA_CACHE_POLICY(0));
4696         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4697                               offsetof(struct v10_gfx_meta_data, ce_payload)));
4698         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4699                               offsetof(struct v10_gfx_meta_data, ce_payload)));
4700
4701         if (resume)
4702                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4703                                            offsetof(struct v10_gfx_meta_data,
4704                                                     ce_payload),
4705                                            sizeof(ce_payload) >> 2);
4706         else
4707                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
4708                                            sizeof(ce_payload) >> 2);
4709 }
4710
4711 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
4712 {
4713         struct amdgpu_device *adev = ring->adev;
4714         struct v10_de_ib_state de_payload = {0};
4715         uint64_t csa_addr, gds_addr;
4716         int cnt;
4717
4718         csa_addr = amdgpu_csa_vaddr(ring->adev);
4719         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
4720                          PAGE_SIZE);
4721         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4722         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4723
4724         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4725         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4726         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4727                                  WRITE_DATA_DST_SEL(8) |
4728                                  WR_CONFIRM) |
4729                                  WRITE_DATA_CACHE_POLICY(0));
4730         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4731                               offsetof(struct v10_gfx_meta_data, de_payload)));
4732         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4733                               offsetof(struct v10_gfx_meta_data, de_payload)));
4734
4735         if (resume)
4736                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4737                                            offsetof(struct v10_gfx_meta_data,
4738                                                     de_payload),
4739                                            sizeof(de_payload) >> 2);
4740         else
4741                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
4742                                            sizeof(de_payload) >> 2);
4743 }
4744
4745 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4746 {
4747         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4748         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4749 }
4750
4751 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4752 {
4753         struct amdgpu_device *adev = ring->adev;
4754
4755         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4756         amdgpu_ring_write(ring, 0 |     /* src: register*/
4757                                 (5 << 8) |      /* dst: memory */
4758                                 (1 << 20));     /* write confirm */
4759         amdgpu_ring_write(ring, reg);
4760         amdgpu_ring_write(ring, 0);
4761         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4762                                 adev->virt.reg_val_offs * 4));
4763         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4764                                 adev->virt.reg_val_offs * 4));
4765 }
4766
4767 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4768                                    uint32_t val)
4769 {
4770         uint32_t cmd = 0;
4771
4772         switch (ring->funcs->type) {
4773         case AMDGPU_RING_TYPE_GFX:
4774                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4775                 break;
4776         case AMDGPU_RING_TYPE_KIQ:
4777                 cmd = (1 << 16); /* no inc addr */
4778                 break;
4779         default:
4780                 cmd = WR_CONFIRM;
4781                 break;
4782         }
4783         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4784         amdgpu_ring_write(ring, cmd);
4785         amdgpu_ring_write(ring, reg);
4786         amdgpu_ring_write(ring, 0);
4787         amdgpu_ring_write(ring, val);
4788 }
4789
4790 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4791                                         uint32_t val, uint32_t mask)
4792 {
4793         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4794 }
4795
4796 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4797                                                    uint32_t reg0, uint32_t reg1,
4798                                                    uint32_t ref, uint32_t mask)
4799 {
4800         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4801         struct amdgpu_device *adev = ring->adev;
4802         bool fw_version_ok = false;
4803
4804         fw_version_ok = adev->gfx.cp_fw_write_wait;
4805
4806         if (fw_version_ok)
4807                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4808                                        ref, mask, 0x20);
4809         else
4810                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4811                                                            ref, mask);
4812 }
4813
4814 static void
4815 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4816                                       uint32_t me, uint32_t pipe,
4817                                       enum amdgpu_interrupt_state state)
4818 {
4819         uint32_t cp_int_cntl, cp_int_cntl_reg;
4820
4821         if (!me) {
4822                 switch (pipe) {
4823                 case 0:
4824                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4825                         break;
4826                 case 1:
4827                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4828                         break;
4829                 default:
4830                         DRM_DEBUG("invalid pipe %d\n", pipe);
4831                         return;
4832                 }
4833         } else {
4834                 DRM_DEBUG("invalid me %d\n", me);
4835                 return;
4836         }
4837
4838         switch (state) {
4839         case AMDGPU_IRQ_STATE_DISABLE:
4840                 cp_int_cntl = RREG32(cp_int_cntl_reg);
4841                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4842                                             TIME_STAMP_INT_ENABLE, 0);
4843                 WREG32(cp_int_cntl_reg, cp_int_cntl);
4844                 break;
4845         case AMDGPU_IRQ_STATE_ENABLE:
4846                 cp_int_cntl = RREG32(cp_int_cntl_reg);
4847                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4848                                             TIME_STAMP_INT_ENABLE, 1);
4849                 WREG32(cp_int_cntl_reg, cp_int_cntl);
4850                 break;
4851         default:
4852                 break;
4853         }
4854 }
4855
4856 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4857                                                      int me, int pipe,
4858                                                      enum amdgpu_interrupt_state state)
4859 {
4860         u32 mec_int_cntl, mec_int_cntl_reg;
4861
4862         /*
4863          * amdgpu controls only the first MEC. That's why this function only
4864          * handles the setting of interrupts for this specific MEC. All other
4865          * pipes' interrupts are set by amdkfd.
4866          */
4867
4868         if (me == 1) {
4869                 switch (pipe) {
4870                 case 0:
4871                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4872                         break;
4873                 case 1:
4874                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4875                         break;
4876                 case 2:
4877                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4878                         break;
4879                 case 3:
4880                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4881                         break;
4882                 default:
4883                         DRM_DEBUG("invalid pipe %d\n", pipe);
4884                         return;
4885                 }
4886         } else {
4887                 DRM_DEBUG("invalid me %d\n", me);
4888                 return;
4889         }
4890
4891         switch (state) {
4892         case AMDGPU_IRQ_STATE_DISABLE:
4893                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4894                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4895                                              TIME_STAMP_INT_ENABLE, 0);
4896                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4897                 break;
4898         case AMDGPU_IRQ_STATE_ENABLE:
4899                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4900                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4901                                              TIME_STAMP_INT_ENABLE, 1);
4902                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4903                 break;
4904         default:
4905                 break;
4906         }
4907 }
4908
4909 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4910                                             struct amdgpu_irq_src *src,
4911                                             unsigned type,
4912                                             enum amdgpu_interrupt_state state)
4913 {
4914         switch (type) {
4915         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4916                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4917                 break;
4918         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4919                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4920                 break;
4921         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4922                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4923                 break;
4924         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4925                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4926                 break;
4927         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4928                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4929                 break;
4930         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4931                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4932                 break;
4933         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4934                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4935                 break;
4936         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4937                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4938                 break;
4939         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4940                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4941                 break;
4942         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4943                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4944                 break;
4945         default:
4946                 break;
4947         }
4948         return 0;
4949 }
4950
4951 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
4952                              struct amdgpu_irq_src *source,
4953                              struct amdgpu_iv_entry *entry)
4954 {
4955         int i;
4956         u8 me_id, pipe_id, queue_id;
4957         struct amdgpu_ring *ring;
4958
4959         DRM_DEBUG("IH: CP EOP\n");
4960         me_id = (entry->ring_id & 0x0c) >> 2;
4961         pipe_id = (entry->ring_id & 0x03) >> 0;
4962         queue_id = (entry->ring_id & 0x70) >> 4;
4963
4964         switch (me_id) {
4965         case 0:
4966                 if (pipe_id == 0)
4967                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4968                 else
4969                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4970                 break;
4971         case 1:
4972         case 2:
4973                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4974                         ring = &adev->gfx.compute_ring[i];
4975                         /* Per-queue interrupt is supported for MEC starting from VI.
4976                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4977                           */
4978                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4979                                 amdgpu_fence_process(ring);
4980                 }
4981                 break;
4982         }
4983         return 0;
4984 }
4985
4986 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4987                                               struct amdgpu_irq_src *source,
4988                                               unsigned type,
4989                                               enum amdgpu_interrupt_state state)
4990 {
4991         switch (state) {
4992         case AMDGPU_IRQ_STATE_DISABLE:
4993         case AMDGPU_IRQ_STATE_ENABLE:
4994                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4995                                PRIV_REG_INT_ENABLE,
4996                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4997                 break;
4998         default:
4999                 break;
5000         }
5001
5002         return 0;
5003 }
5004
5005 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5006                                                struct amdgpu_irq_src *source,
5007                                                unsigned type,
5008                                                enum amdgpu_interrupt_state state)
5009 {
5010         switch (state) {
5011         case AMDGPU_IRQ_STATE_DISABLE:
5012         case AMDGPU_IRQ_STATE_ENABLE:
5013                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5014                                PRIV_INSTR_INT_ENABLE,
5015                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5016         default:
5017                 break;
5018         }
5019
5020         return 0;
5021 }
5022
5023 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
5024                                         struct amdgpu_iv_entry *entry)
5025 {
5026         u8 me_id, pipe_id, queue_id;
5027         struct amdgpu_ring *ring;
5028         int i;
5029
5030         me_id = (entry->ring_id & 0x0c) >> 2;
5031         pipe_id = (entry->ring_id & 0x03) >> 0;
5032         queue_id = (entry->ring_id & 0x70) >> 4;
5033
5034         switch (me_id) {
5035         case 0:
5036                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5037                         ring = &adev->gfx.gfx_ring[i];
5038                         /* we only enabled 1 gfx queue per pipe for now */
5039                         if (ring->me == me_id && ring->pipe == pipe_id)
5040                                 drm_sched_fault(&ring->sched);
5041                 }
5042                 break;
5043         case 1:
5044         case 2:
5045                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5046                         ring = &adev->gfx.compute_ring[i];
5047                         if (ring->me == me_id && ring->pipe == pipe_id &&
5048                             ring->queue == queue_id)
5049                                 drm_sched_fault(&ring->sched);
5050                 }
5051                 break;
5052         default:
5053                 BUG();
5054         }
5055 }
5056
5057 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
5058                                   struct amdgpu_irq_src *source,
5059                                   struct amdgpu_iv_entry *entry)
5060 {
5061         DRM_ERROR("Illegal register access in command stream\n");
5062         gfx_v10_0_handle_priv_fault(adev, entry);
5063         return 0;
5064 }
5065
5066 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
5067                                    struct amdgpu_irq_src *source,
5068                                    struct amdgpu_iv_entry *entry)
5069 {
5070         DRM_ERROR("Illegal instruction in command stream\n");
5071         gfx_v10_0_handle_priv_fault(adev, entry);
5072         return 0;
5073 }
5074
5075 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5076                                              struct amdgpu_irq_src *src,
5077                                              unsigned int type,
5078                                              enum amdgpu_interrupt_state state)
5079 {
5080         uint32_t tmp, target;
5081         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5082
5083         if (ring->me == 1)
5084                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5085         else
5086                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5087         target += ring->pipe;
5088
5089         switch (type) {
5090         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5091                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5092                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5093                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5094                                             GENERIC2_INT_ENABLE, 0);
5095                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5096
5097                         tmp = RREG32(target);
5098                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5099                                             GENERIC2_INT_ENABLE, 0);
5100                         WREG32(target, tmp);
5101                 } else {
5102                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5103                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5104                                             GENERIC2_INT_ENABLE, 1);
5105                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5106
5107                         tmp = RREG32(target);
5108                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5109                                             GENERIC2_INT_ENABLE, 1);
5110                         WREG32(target, tmp);
5111                 }
5112                 break;
5113         default:
5114                 BUG(); /* kiq only support GENERIC2_INT now */
5115                 break;
5116         }
5117         return 0;
5118 }
5119
5120 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
5121                              struct amdgpu_irq_src *source,
5122                              struct amdgpu_iv_entry *entry)
5123 {
5124         u8 me_id, pipe_id, queue_id;
5125         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5126
5127         me_id = (entry->ring_id & 0x0c) >> 2;
5128         pipe_id = (entry->ring_id & 0x03) >> 0;
5129         queue_id = (entry->ring_id & 0x70) >> 4;
5130         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
5131                    me_id, pipe_id, queue_id);
5132
5133         amdgpu_fence_process(ring);
5134         return 0;
5135 }
5136
5137 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
5138         .name = "gfx_v10_0",
5139         .early_init = gfx_v10_0_early_init,
5140         .late_init = gfx_v10_0_late_init,
5141         .sw_init = gfx_v10_0_sw_init,
5142         .sw_fini = gfx_v10_0_sw_fini,
5143         .hw_init = gfx_v10_0_hw_init,
5144         .hw_fini = gfx_v10_0_hw_fini,
5145         .suspend = gfx_v10_0_suspend,
5146         .resume = gfx_v10_0_resume,
5147         .is_idle = gfx_v10_0_is_idle,
5148         .wait_for_idle = gfx_v10_0_wait_for_idle,
5149         .soft_reset = gfx_v10_0_soft_reset,
5150         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
5151         .set_powergating_state = gfx_v10_0_set_powergating_state,
5152         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
5153 };
5154
5155 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
5156         .type = AMDGPU_RING_TYPE_GFX,
5157         .align_mask = 0xff,
5158         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5159         .support_64bit_ptrs = true,
5160         .vmhub = AMDGPU_GFXHUB_0,
5161         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
5162         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
5163         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5164         .emit_frame_size = /* totally 242 maximum if 16 IBs */
5165                 5 + /* COND_EXEC */
5166                 7 + /* PIPELINE_SYNC */
5167                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5168                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5169                 2 + /* VM_FLUSH */
5170                 8 + /* FENCE for VM_FLUSH */
5171                 20 + /* GDS switch */
5172                 4 + /* double SWITCH_BUFFER,
5173                      * the first COND_EXEC jump to the place
5174                      * just prior to this double SWITCH_BUFFER
5175                      */
5176                 5 + /* COND_EXEC */
5177                 7 + /* HDP_flush */
5178                 4 + /* VGT_flush */
5179                 14 + /* CE_META */
5180                 31 + /* DE_META */
5181                 3 + /* CNTX_CTRL */
5182                 5 + /* HDP_INVL */
5183                 8 + 8 + /* FENCE x2 */
5184                 2, /* SWITCH_BUFFER */
5185         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
5186         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
5187         .emit_fence = gfx_v10_0_ring_emit_fence,
5188         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5189         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5190         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5191         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5192         .test_ring = gfx_v10_0_ring_test_ring,
5193         .test_ib = gfx_v10_0_ring_test_ib,
5194         .insert_nop = amdgpu_ring_insert_nop,
5195         .pad_ib = amdgpu_ring_generic_pad_ib,
5196         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
5197         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
5198         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
5199         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
5200         .preempt_ib = gfx_v10_0_ring_preempt_ib,
5201         .emit_tmz = gfx_v10_0_ring_emit_tmz,
5202         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5203         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5204         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5205 };
5206
5207 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
5208         .type = AMDGPU_RING_TYPE_COMPUTE,
5209         .align_mask = 0xff,
5210         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5211         .support_64bit_ptrs = true,
5212         .vmhub = AMDGPU_GFXHUB_0,
5213         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5214         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5215         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5216         .emit_frame_size =
5217                 20 + /* gfx_v10_0_ring_emit_gds_switch */
5218                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5219                 5 + /* hdp invalidate */
5220                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5221                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5222                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5223                 2 + /* gfx_v10_0_ring_emit_vm_flush */
5224                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
5225         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5226         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5227         .emit_fence = gfx_v10_0_ring_emit_fence,
5228         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5229         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5230         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5231         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5232         .test_ring = gfx_v10_0_ring_test_ring,
5233         .test_ib = gfx_v10_0_ring_test_ib,
5234         .insert_nop = amdgpu_ring_insert_nop,
5235         .pad_ib = amdgpu_ring_generic_pad_ib,
5236         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5237         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5238         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5239 };
5240
5241 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
5242         .type = AMDGPU_RING_TYPE_KIQ,
5243         .align_mask = 0xff,
5244         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5245         .support_64bit_ptrs = true,
5246         .vmhub = AMDGPU_GFXHUB_0,
5247         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5248         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5249         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5250         .emit_frame_size =
5251                 20 + /* gfx_v10_0_ring_emit_gds_switch */
5252                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5253                 5 + /*hdp invalidate */
5254                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5255                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5256                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5257                 2 + /* gfx_v10_0_ring_emit_vm_flush */
5258                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5259         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5260         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5261         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
5262         .test_ring = gfx_v10_0_ring_test_ring,
5263         .test_ib = gfx_v10_0_ring_test_ib,
5264         .insert_nop = amdgpu_ring_insert_nop,
5265         .pad_ib = amdgpu_ring_generic_pad_ib,
5266         .emit_rreg = gfx_v10_0_ring_emit_rreg,
5267         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5268         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5269         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5270 };
5271
5272 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
5273 {
5274         int i;
5275
5276         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
5277
5278         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5279                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
5280
5281         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5282                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
5283 }
5284
5285 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
5286         .set = gfx_v10_0_set_eop_interrupt_state,
5287         .process = gfx_v10_0_eop_irq,
5288 };
5289
5290 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
5291         .set = gfx_v10_0_set_priv_reg_fault_state,
5292         .process = gfx_v10_0_priv_reg_irq,
5293 };
5294
5295 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
5296         .set = gfx_v10_0_set_priv_inst_fault_state,
5297         .process = gfx_v10_0_priv_inst_irq,
5298 };
5299
5300 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
5301         .set = gfx_v10_0_kiq_set_interrupt_state,
5302         .process = gfx_v10_0_kiq_irq,
5303 };
5304
5305 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
5306 {
5307         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5308         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
5309
5310         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
5311         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
5312
5313         adev->gfx.priv_reg_irq.num_types = 1;
5314         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
5315
5316         adev->gfx.priv_inst_irq.num_types = 1;
5317         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
5318 }
5319
5320 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
5321 {
5322         switch (adev->asic_type) {
5323         case CHIP_NAVI10:
5324         case CHIP_NAVI14:
5325         case CHIP_NAVI12:
5326                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
5327                 break;
5328         default:
5329                 break;
5330         }
5331 }
5332
5333 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
5334 {
5335         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
5336                             adev->gfx.config.max_sh_per_se *
5337                             adev->gfx.config.max_shader_engines;
5338
5339         adev->gds.gds_size = 0x10000;
5340         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
5341         adev->gds.gws_size = 64;
5342         adev->gds.oa_size = 16;
5343 }
5344
5345 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5346                                                           u32 bitmap)
5347 {
5348         u32 data;
5349
5350         if (!bitmap)
5351                 return;
5352
5353         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5354         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5355
5356         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5357 }
5358
5359 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5360 {
5361         u32 data, wgp_bitmask;
5362         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5363         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
5364
5365         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5366         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5367
5368         wgp_bitmask =
5369                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5370
5371         return (~data) & wgp_bitmask;
5372 }
5373
5374 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5375 {
5376         u32 wgp_idx, wgp_active_bitmap;
5377         u32 cu_bitmap_per_wgp, cu_active_bitmap;
5378
5379         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5380         cu_active_bitmap = 0;
5381
5382         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5383                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5384                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5385                 if (wgp_active_bitmap & (1 << wgp_idx))
5386                         cu_active_bitmap |= cu_bitmap_per_wgp;
5387         }
5388
5389         return cu_active_bitmap;
5390 }
5391
5392 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
5393                                  struct amdgpu_cu_info *cu_info)
5394 {
5395         int i, j, k, counter, active_cu_number = 0;
5396         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5397         unsigned disable_masks[4 * 2];
5398
5399         if (!adev || !cu_info)
5400                 return -EINVAL;
5401
5402         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5403
5404         mutex_lock(&adev->grbm_idx_mutex);
5405         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5406                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5407                         mask = 1;
5408                         ao_bitmap = 0;
5409                         counter = 0;
5410                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5411                         if (i < 4 && j < 2)
5412                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
5413                                         adev, disable_masks[i * 2 + j]);
5414                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
5415                         cu_info->bitmap[i][j] = bitmap;
5416
5417                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5418                                 if (bitmap & mask) {
5419                                         if (counter < adev->gfx.config.max_cu_per_sh)
5420                                                 ao_bitmap |= mask;
5421                                         counter++;
5422                                 }
5423                                 mask <<= 1;
5424                         }
5425                         active_cu_number += counter;
5426                         if (i < 2 && j < 2)
5427                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5428                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5429                 }
5430         }
5431         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5432         mutex_unlock(&adev->grbm_idx_mutex);
5433
5434         cu_info->number = active_cu_number;
5435         cu_info->ao_cu_mask = ao_cu_mask;
5436         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5437
5438         return 0;
5439 }
5440
5441 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
5442 {
5443         .type = AMD_IP_BLOCK_TYPE_GFX,
5444         .major = 10,
5445         .minor = 0,
5446         .rev = 0,
5447         .funcs = &gfx_v10_0_ip_funcs,
5448 };