drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43
  44 #include <drm/ttm/ttm_bo_api.h>
  45 #include <drm/ttm/ttm_bo_driver.h>
  46 #include <drm/ttm/ttm_placement.h>
  47 #include <drm/ttm/ttm_module.h>
  48 #include <drm/ttm/ttm_page_alloc.h>
  49
  50 #include <drm/drm_debugfs.h>
  51 #include <drm/amdgpu_drm.h>
  52
  53 #include "amdgpu.h"
  54 #include "amdgpu_object.h"
  55 #include "amdgpu_trace.h"
  56 #include "amdgpu_amdkfd.h"
  57 #include "amdgpu_sdma.h"
  58 #include "amdgpu_ras.h"
  59 #include "bif/bif_4_1_d.h"
  60
  61 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  62                              struct ttm_mem_reg *mem, unsigned num_pages,
  63                              uint64_t offset, unsigned window,
  64                              struct amdgpu_ring *ring,
  65                              uint64_t *addr);
  66
  67 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  68 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  69
  70 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  71 {
  72         return 0;
  73 }
  74
  75 /**
  76  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  77  * memory request.
  78  *
  79  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  80  * @type: The type of memory requested
  81  * @man: The memory type manager for each domain
  82  *
  83  * This is called by ttm_bo_init_mm() when a buffer object is being
  84  * initialized.
  85  */
  86 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  87                                 struct ttm_mem_type_manager *man)
  88 {
  89         struct amdgpu_device *adev;
  90
  91         adev = amdgpu_ttm_adev(bdev);
  92
  93         switch (type) {
  94         case TTM_PL_SYSTEM:
  95                 /* System memory */
  96                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  97                 man->available_caching = TTM_PL_MASK_CACHING;
  98                 man->default_caching = TTM_PL_FLAG_CACHED;
  99                 break;
 100         case TTM_PL_TT:
 101                 /* GTT memory  */
 102                 man->func = &amdgpu_gtt_mgr_func;
 103                 man->gpu_offset = adev->gmc.gart_start;
 104                 man->available_caching = TTM_PL_MASK_CACHING;
 105                 man->default_caching = TTM_PL_FLAG_CACHED;
 106                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 107                 break;
 108         case TTM_PL_VRAM:
 109                 /* "On-card" video ram */
 110                 man->func = &amdgpu_vram_mgr_func;
 111                 man->gpu_offset = adev->gmc.vram_start;
 112                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 113                              TTM_MEMTYPE_FLAG_MAPPABLE;
 114                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 115                 man->default_caching = TTM_PL_FLAG_WC;
 116                 break;
 117         case AMDGPU_PL_GDS:
 118         case AMDGPU_PL_GWS:
 119         case AMDGPU_PL_OA:
 120                 /* On-chip GDS memory*/
 121                 man->func = &ttm_bo_manager_func;
 122                 man->gpu_offset = 0;
 123                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 124                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 125                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 126                 break;
 127         default:
 128                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 129                 return -EINVAL;
 130         }
 131         return 0;
 132 }
 133
 134 /**
 135  * amdgpu_evict_flags - Compute placement flags
 136  *
 137  * @bo: The buffer object to evict
 138  * @placement: Possible destination(s) for evicted BO
 139  *
 140  * Fill in placement data when ttm_bo_evict() is called
 141  */
 142 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 143                                 struct ttm_placement *placement)
 144 {
 145         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 146         struct amdgpu_bo *abo;
 147         static const struct ttm_place placements = {
 148                 .fpfn = 0,
 149                 .lpfn = 0,
 150                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 151         };
 152
 153         /* Don't handle scatter gather BOs */
 154         if (bo->type == ttm_bo_type_sg) {
 155                 placement->num_placement = 0;
 156                 placement->num_busy_placement = 0;
 157                 return;
 158         }
 159
 160         /* Object isn't an AMDGPU object so ignore */
 161         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 162                 placement->placement = &placements;
 163                 placement->busy_placement = &placements;
 164                 placement->num_placement = 1;
 165                 placement->num_busy_placement = 1;
 166                 return;
 167         }
 168
 169         abo = ttm_to_amdgpu_bo(bo);
 170         switch (bo->mem.mem_type) {
 171         case AMDGPU_PL_GDS:
 172         case AMDGPU_PL_GWS:
 173         case AMDGPU_PL_OA:
 174                 placement->num_placement = 0;
 175                 placement->num_busy_placement = 0;
 176                 return;
 177
 178         case TTM_PL_VRAM:
 179                 if (!adev->mman.buffer_funcs_enabled) {
 180                         /* Move to system memory */
 181                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 182                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 183                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 184                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 185
 186                         /* Try evicting to the CPU inaccessible part of VRAM
 187                          * first, but only set GTT as busy placement, so this
 188                          * BO will be evicted to GTT rather than causing other
 189                          * BOs to be evicted from VRAM
 190                          */
 191                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 192                                                          AMDGPU_GEM_DOMAIN_GTT);
 193                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 194                         abo->placements[0].lpfn = 0;
 195                         abo->placement.busy_placement = &abo->placements[1];
 196                         abo->placement.num_busy_placement = 1;
 197                 } else {
 198                         /* Move to GTT memory */
 199                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 200                 }
 201                 break;
 202         case TTM_PL_TT:
 203         default:
 204                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 205                 break;
 206         }
 207         *placement = abo->placement;
 208 }
 209
 210 /**
 211  * amdgpu_verify_access - Verify access for a mmap call
 212  *
 213  * @bo: The buffer object to map
 214  * @filp: The file pointer from the process performing the mmap
 215  *
 216  * This is called by ttm_bo_mmap() to verify whether a process
 217  * has the right to mmap a BO to their process space.
 218  */
 219 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 220 {
 221         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 222
 223         /*
 224          * Don't verify access for KFD BOs. They don't have a GEM
 225          * object associated with them.
 226          */
 227         if (abo->kfd_bo)
 228                 return 0;
 229
 230         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 231                 return -EPERM;
 232         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 233                                           filp->private_data);
 234 }
 235
 236 /**
 237  * amdgpu_move_null - Register memory for a buffer object
 238  *
 239  * @bo: The bo to assign the memory to
 240  * @new_mem: The memory to be assigned.
 241  *
 242  * Assign the memory from new_mem to the memory of the buffer object bo.
 243  */
 244 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 245                              struct ttm_mem_reg *new_mem)
 246 {
 247         struct ttm_mem_reg *old_mem = &bo->mem;
 248
 249         BUG_ON(old_mem->mm_node != NULL);
 250         *old_mem = *new_mem;
 251         new_mem->mm_node = NULL;
 252 }
 253
 254 /**
 255  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 256  *
 257  * @bo: The bo to assign the memory to.
 258  * @mm_node: Memory manager node for drm allocator.
 259  * @mem: The region where the bo resides.
 260  *
 261  */
 262 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 263                                     struct drm_mm_node *mm_node,
 264                                     struct ttm_mem_reg *mem)
 265 {
 266         uint64_t addr = 0;
 267
 268         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 269                 addr = mm_node->start << PAGE_SHIFT;
 270                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 271         }
 272         return addr;
 273 }
 274
 275 /**
 276  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 277  * @offset. It also modifies the offset to be within the drm_mm_node returned
 278  *
 279  * @mem: The region where the bo resides.
 280  * @offset: The offset that drm_mm_node is used for finding.
 281  *
 282  */
 283 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 284                                                unsigned long *offset)
 285 {
 286         struct drm_mm_node *mm_node = mem->mm_node;
 287
 288         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 289                 *offset -= (mm_node->size << PAGE_SHIFT);
 290                 ++mm_node;
 291         }
 292         return mm_node;
 293 }
 294
 295 /**
 296  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 297  *
 298  * The function copies @size bytes from {src->mem + src->offset} to
 299  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 300  * move and different for a BO to BO copy.
 301  *
 302  * @f: Returns the last fence if multiple jobs are submitted.
 303  */
 304 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 305                                struct amdgpu_copy_mem *src,
 306                                struct amdgpu_copy_mem *dst,
 307                                uint64_t size,
 308                                struct dma_resv *resv,
 309                                struct dma_fence **f)
 310 {
 311         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 312         struct drm_mm_node *src_mm, *dst_mm;
 313         uint64_t src_node_start, dst_node_start, src_node_size,
 314                  dst_node_size, src_page_offset, dst_page_offset;
 315         struct dma_fence *fence = NULL;
 316         int r = 0;
 317         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 318                                         AMDGPU_GPU_PAGE_SIZE);
 319
 320         if (!adev->mman.buffer_funcs_enabled) {
 321                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 322                 return -EINVAL;
 323         }
 324
 325         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 326         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 327                                              src->offset;
 328         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 329         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 330
 331         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 332         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 333                                              dst->offset;
 334         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 335         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 336
 337         mutex_lock(&adev->mman.gtt_window_lock);
 338
 339         while (size) {
 340                 unsigned long cur_size;
 341                 uint64_t from = src_node_start, to = dst_node_start;
 342                 struct dma_fence *next;
 343
 344                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 345                  * begins at an offset, then adjust the size accordingly
 346                  */
 347                 cur_size = min3(min(src_node_size, dst_node_size), size,
 348                                 GTT_MAX_BYTES);
 349                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 350                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 351                         cur_size -= max(src_page_offset, dst_page_offset);
 352
 353                 /* Map only what needs to be accessed. Map src to window 0 and
 354                  * dst to window 1
 355                  */
 356                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 357                         r = amdgpu_map_buffer(src->bo, src->mem,
 358                                         PFN_UP(cur_size + src_page_offset),
 359                                         src_node_start, 0, ring,
 360                                         &from);
 361                         if (r)
 362                                 goto error;
 363                         /* Adjust the offset because amdgpu_map_buffer returns
 364                          * start of mapped page
 365                          */
 366                         from += src_page_offset;
 367                 }
 368
 369                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 370                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 371                                         PFN_UP(cur_size + dst_page_offset),
 372                                         dst_node_start, 1, ring,
 373                                         &to);
 374                         if (r)
 375                                 goto error;
 376                         to += dst_page_offset;
 377                 }
 378
 379                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 380                                        resv, &next, false, true);
 381                 if (r)
 382                         goto error;
 383
 384                 dma_fence_put(fence);
 385                 fence = next;
 386
 387                 size -= cur_size;
 388                 if (!size)
 389                         break;
 390
 391                 src_node_size -= cur_size;
 392                 if (!src_node_size) {
 393                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 394                                                              src->mem);
 395                         src_node_size = (src_mm->size << PAGE_SHIFT);
 396                         src_page_offset = 0;
 397                 } else {
 398                         src_node_start += cur_size;
 399                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 400                 }
 401                 dst_node_size -= cur_size;
 402                 if (!dst_node_size) {
 403                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 404                                                              dst->mem);
 405                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 406                         dst_page_offset = 0;
 407                 } else {
 408                         dst_node_start += cur_size;
 409                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 410                 }
 411         }
 412 error:
 413         mutex_unlock(&adev->mman.gtt_window_lock);
 414         if (f)
 415                 *f = dma_fence_get(fence);
 416         dma_fence_put(fence);
 417         return r;
 418 }
 419
 420 /**
 421  * amdgpu_move_blit - Copy an entire buffer to another buffer
 422  *
 423  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 424  * help move buffers to and from VRAM.
 425  */
 426 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 427                             bool evict, bool no_wait_gpu,
 428                             struct ttm_mem_reg *new_mem,
 429                             struct ttm_mem_reg *old_mem)
 430 {
 431         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 432         struct amdgpu_copy_mem src, dst;
 433         struct dma_fence *fence = NULL;
 434         int r;
 435
 436         src.bo = bo;
 437         dst.bo = bo;
 438         src.mem = old_mem;
 439         dst.mem = new_mem;
 440         src.offset = 0;
 441         dst.offset = 0;
 442
 443         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 444                                        new_mem->num_pages << PAGE_SHIFT,
 445                                        bo->base.resv, &fence);
 446         if (r)
 447                 goto error;
 448
 449         /* clear the space being freed */
 450         if (old_mem->mem_type == TTM_PL_VRAM &&
 451             (ttm_to_amdgpu_bo(bo)->flags &
 452              AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 453                 struct dma_fence *wipe_fence = NULL;
 454
 455                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 456                                        NULL, &wipe_fence);
 457                 if (r) {
 458                         goto error;
 459                 } else if (wipe_fence) {
 460                         dma_fence_put(fence);
 461                         fence = wipe_fence;
 462                 }
 463         }
 464
 465         /* Always block for VM page tables before committing the new location */
 466         if (bo->type == ttm_bo_type_kernel)
 467                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 468         else
 469                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 470         dma_fence_put(fence);
 471         return r;
 472
 473 error:
 474         if (fence)
 475                 dma_fence_wait(fence, false);
 476         dma_fence_put(fence);
 477         return r;
 478 }
 479
 480 /**
 481  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 482  *
 483  * Called by amdgpu_bo_move().
 484  */
 485 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 486                                 struct ttm_operation_ctx *ctx,
 487                                 struct ttm_mem_reg *new_mem)
 488 {
 489         struct ttm_mem_reg *old_mem = &bo->mem;
 490         struct ttm_mem_reg tmp_mem;
 491         struct ttm_place placements;
 492         struct ttm_placement placement;
 493         int r;
 494
 495         /* create space/pages for new_mem in GTT space */
 496         tmp_mem = *new_mem;
 497         tmp_mem.mm_node = NULL;
 498         placement.num_placement = 1;
 499         placement.placement = &placements;
 500         placement.num_busy_placement = 1;
 501         placement.busy_placement = &placements;
 502         placements.fpfn = 0;
 503         placements.lpfn = 0;
 504         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 505         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 506         if (unlikely(r)) {
 507                 pr_err("Failed to find GTT space for blit from VRAM\n");
 508                 return r;
 509         }
 510
 511         /* set caching flags */
 512         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 513         if (unlikely(r)) {
 514                 goto out_cleanup;
 515         }
 516
 517         /* Bind the memory to the GTT space */
 518         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 519         if (unlikely(r)) {
 520                 goto out_cleanup;
 521         }
 522
 523         /* blit VRAM to GTT */
 524         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 525         if (unlikely(r)) {
 526                 goto out_cleanup;
 527         }
 528
 529         /* move BO (in tmp_mem) to new_mem */
 530         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 531 out_cleanup:
 532         ttm_bo_mem_put(bo, &tmp_mem);
 533         return r;
 534 }
 535
 536 /**
 537  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 538  *
 539  * Called by amdgpu_bo_move().
 540  */
 541 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 542                                 struct ttm_operation_ctx *ctx,
 543                                 struct ttm_mem_reg *new_mem)
 544 {
 545         struct ttm_mem_reg *old_mem = &bo->mem;
 546         struct ttm_mem_reg tmp_mem;
 547         struct ttm_placement placement;
 548         struct ttm_place placements;
 549         int r;
 550
 551         /* make space in GTT for old_mem buffer */
 552         tmp_mem = *new_mem;
 553         tmp_mem.mm_node = NULL;
 554         placement.num_placement = 1;
 555         placement.placement = &placements;
 556         placement.num_busy_placement = 1;
 557         placement.busy_placement = &placements;
 558         placements.fpfn = 0;
 559         placements.lpfn = 0;
 560         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 561         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 562         if (unlikely(r)) {
 563                 pr_err("Failed to find GTT space for blit to VRAM\n");
 564                 return r;
 565         }
 566
 567         /* move/bind old memory to GTT space */
 568         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 569         if (unlikely(r)) {
 570                 goto out_cleanup;
 571         }
 572
 573         /* copy to VRAM */
 574         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 575         if (unlikely(r)) {
 576                 goto out_cleanup;
 577         }
 578 out_cleanup:
 579         ttm_bo_mem_put(bo, &tmp_mem);
 580         return r;
 581 }
 582
 583 /**
 584  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 585  *
 586  * Called by amdgpu_bo_move()
 587  */
 588 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 589                                struct ttm_mem_reg *mem)
 590 {
 591         struct drm_mm_node *nodes = mem->mm_node;
 592
 593         if (mem->mem_type == TTM_PL_SYSTEM ||
 594             mem->mem_type == TTM_PL_TT)
 595                 return true;
 596         if (mem->mem_type != TTM_PL_VRAM)
 597                 return false;
 598
 599         /* ttm_mem_reg_ioremap only supports contiguous memory */
 600         if (nodes->size != mem->num_pages)
 601                 return false;
 602
 603         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 604                 <= adev->gmc.visible_vram_size;
 605 }
 606
 607 /**
 608  * amdgpu_bo_move - Move a buffer object to a new memory location
 609  *
 610  * Called by ttm_bo_handle_move_mem()
 611  */
 612 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 613                           struct ttm_operation_ctx *ctx,
 614                           struct ttm_mem_reg *new_mem)
 615 {
 616         struct amdgpu_device *adev;
 617         struct amdgpu_bo *abo;
 618         struct ttm_mem_reg *old_mem = &bo->mem;
 619         int r;
 620
 621         /* Can't move a pinned BO */
 622         abo = ttm_to_amdgpu_bo(bo);
 623         if (WARN_ON_ONCE(abo->pin_count > 0))
 624                 return -EINVAL;
 625
 626         adev = amdgpu_ttm_adev(bo->bdev);
 627
 628         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 629                 amdgpu_move_null(bo, new_mem);
 630                 return 0;
 631         }
 632         if ((old_mem->mem_type == TTM_PL_TT &&
 633              new_mem->mem_type == TTM_PL_SYSTEM) ||
 634             (old_mem->mem_type == TTM_PL_SYSTEM &&
 635              new_mem->mem_type == TTM_PL_TT)) {
 636                 /* bind is enough */
 637                 amdgpu_move_null(bo, new_mem);
 638                 return 0;
 639         }
 640         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 641             old_mem->mem_type == AMDGPU_PL_GWS ||
 642             old_mem->mem_type == AMDGPU_PL_OA ||
 643             new_mem->mem_type == AMDGPU_PL_GDS ||
 644             new_mem->mem_type == AMDGPU_PL_GWS ||
 645             new_mem->mem_type == AMDGPU_PL_OA) {
 646                 /* Nothing to save here */
 647                 amdgpu_move_null(bo, new_mem);
 648                 return 0;
 649         }
 650
 651         if (!adev->mman.buffer_funcs_enabled) {
 652                 r = -ENODEV;
 653                 goto memcpy;
 654         }
 655
 656         if (old_mem->mem_type == TTM_PL_VRAM &&
 657             new_mem->mem_type == TTM_PL_SYSTEM) {
 658                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 659         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 660                    new_mem->mem_type == TTM_PL_VRAM) {
 661                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 662         } else {
 663                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 664                                      new_mem, old_mem);
 665         }
 666
 667         if (r) {
 668 memcpy:
 669                 /* Check that all memory is CPU accessible */
 670                 if (!amdgpu_mem_visible(adev, old_mem) ||
 671                     !amdgpu_mem_visible(adev, new_mem)) {
 672                         pr_err("Move buffer fallback to memcpy unavailable\n");
 673                         return r;
 674                 }
 675
 676                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 677                 if (r)
 678                         return r;
 679         }
 680
 681         if (bo->type == ttm_bo_type_device &&
 682             new_mem->mem_type == TTM_PL_VRAM &&
 683             old_mem->mem_type != TTM_PL_VRAM) {
 684                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 685                  * accesses the BO after it's moved.
 686                  */
 687                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 688         }
 689
 690         /* update statistics */
 691         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 692         return 0;
 693 }
 694
 695 /**
 696  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 697  *
 698  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 699  */
 700 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 701 {
 702         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 703         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 704         struct drm_mm_node *mm_node = mem->mm_node;
 705
 706         mem->bus.addr = NULL;
 707         mem->bus.offset = 0;
 708         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 709         mem->bus.base = 0;
 710         mem->bus.is_iomem = false;
 711         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 712                 return -EINVAL;
 713         switch (mem->mem_type) {
 714         case TTM_PL_SYSTEM:
 715                 /* system memory */
 716                 return 0;
 717         case TTM_PL_TT:
 718                 break;
 719         case TTM_PL_VRAM:
 720                 mem->bus.offset = mem->start << PAGE_SHIFT;
 721                 /* check if it's visible */
 722                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 723                         return -EINVAL;
 724                 /* Only physically contiguous buffers apply. In a contiguous
 725                  * buffer, size of the first mm_node would match the number of
 726                  * pages in ttm_mem_reg.
 727                  */
 728                 if (adev->mman.aper_base_kaddr &&
 729                     (mm_node->size == mem->num_pages))
 730                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 731                                         mem->bus.offset;
 732
 733                 mem->bus.base = adev->gmc.aper_base;
 734                 mem->bus.is_iomem = true;
 735                 break;
 736         default:
 737                 return -EINVAL;
 738         }
 739         return 0;
 740 }
 741
 742 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 743 {
 744 }
 745
 746 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 747                                            unsigned long page_offset)
 748 {
 749         struct drm_mm_node *mm;
 750         unsigned long offset = (page_offset << PAGE_SHIFT);
 751
 752         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 753         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 754                 (offset >> PAGE_SHIFT);
 755 }
 756
 757 /*
 758  * TTM backend functions.
 759  */
 760 struct amdgpu_ttm_tt {
 761         struct ttm_dma_tt       ttm;
 762         struct drm_gem_object   *gobj;
 763         u64                     offset;
 764         uint64_t                userptr;
 765         struct task_struct      *usertask;
 766         uint32_t                userflags;
 767 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 768         struct hmm_range        *range;
 769 #endif
 770 };
 771
 772 /**
 773  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 774  * memory and start HMM tracking CPU page table update
 775  *
 776  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 777  * once afterwards to stop HMM tracking
 778  */
 779 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 780
 781 #define MAX_RETRY_HMM_RANGE_FAULT       16
 782
 783 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 784 {
 785         struct hmm_mirror *mirror = bo->mn ? &bo->mn->mirror : NULL;
 786         struct ttm_tt *ttm = bo->tbo.ttm;
 787         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 788         struct mm_struct *mm = gtt->usertask->mm;
 789         unsigned long start = gtt->userptr;
 790         struct vm_area_struct *vma;
 791         struct hmm_range *range;
 792         unsigned long i;
 793         uint64_t *pfns;
 794         int r = 0;
 795
 796         if (!mm) /* Happens during process shutdown */
 797                 return -ESRCH;
 798
 799         if (unlikely(!mirror)) {
 800                 DRM_DEBUG_DRIVER("Failed to get hmm_mirror\n");
 801                 r = -EFAULT;
 802                 goto out;
 803         }
 804
 805         vma = find_vma(mm, start);
 806         if (unlikely(!vma || start < vma->vm_start)) {
 807                 r = -EFAULT;
 808                 goto out;
 809         }
 810         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 811                 vma->vm_file)) {
 812                 r = -EPERM;
 813                 goto out;
 814         }
 815
 816         range = kzalloc(sizeof(*range), GFP_KERNEL);
 817         if (unlikely(!range)) {
 818                 r = -ENOMEM;
 819                 goto out;
 820         }
 821
 822         pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
 823         if (unlikely(!pfns)) {
 824                 r = -ENOMEM;
 825                 goto out_free_ranges;
 826         }
 827
 828         amdgpu_hmm_init_range(range);
 829         range->default_flags = range->flags[HMM_PFN_VALID];
 830         range->default_flags |= amdgpu_ttm_tt_is_readonly(ttm) ?
 831                                 0 : range->flags[HMM_PFN_WRITE];
 832         range->pfn_flags_mask = 0;
 833         range->pfns = pfns;
 834         range->start = start;
 835         range->end = start + ttm->num_pages * PAGE_SIZE;
 836
 837         hmm_range_register(range, mirror);
 838
 839         /*
 840          * Just wait for range to be valid, safe to ignore return value as we
 841          * will use the return value of hmm_range_fault() below under the
 842          * mmap_sem to ascertain the validity of the range.
 843          */
 844         hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
 845
 846         down_read(&mm->mmap_sem);
 847         r = hmm_range_fault(range, 0);
 848         up_read(&mm->mmap_sem);
 849
 850         if (unlikely(r < 0))
 851                 goto out_free_pfns;
 852
 853         for (i = 0; i < ttm->num_pages; i++) {
 854                 pages[i] = hmm_device_entry_to_page(range, pfns[i]);
 855                 if (unlikely(!pages[i])) {
 856                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 857                                i, pfns[i]);
 858                         r = -ENOMEM;
 859
 860                         goto out_free_pfns;
 861                 }
 862         }
 863
 864         gtt->range = range;
 865
 866         return 0;
 867
 868 out_free_pfns:
 869         hmm_range_unregister(range);
 870         kvfree(pfns);
 871 out_free_ranges:
 872         kfree(range);
 873 out:
 874         return r;
 875 }
 876
 877 /**
 878  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 879  * Check if the pages backing this ttm range have been invalidated
 880  *
 881  * Returns: true if pages are still valid
 882  */
 883 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 884 {
 885         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 886         bool r = false;
 887
 888         if (!gtt || !gtt->userptr)
 889                 return false;
 890
 891         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 892                 gtt->userptr, ttm->num_pages);
 893
 894         WARN_ONCE(!gtt->range || !gtt->range->pfns,
 895                 "No user pages to check\n");
 896
 897         if (gtt->range) {
 898                 r = hmm_range_valid(gtt->range);
 899                 hmm_range_unregister(gtt->range);
 900
 901                 kvfree(gtt->range->pfns);
 902                 kfree(gtt->range);
 903                 gtt->range = NULL;
 904         }
 905
 906         return r;
 907 }
 908 #endif
 909
 910 /**
 911  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 912  *
 913  * Called by amdgpu_cs_list_validate(). This creates the page list
 914  * that backs user memory and will ultimately be mapped into the device
 915  * address space.
 916  */
 917 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 918 {
 919         unsigned long i;
 920
 921         for (i = 0; i < ttm->num_pages; ++i)
 922                 ttm->pages[i] = pages ? pages[i] : NULL;
 923 }
 924
 925 /**
 926  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 927  *
 928  * Called by amdgpu_ttm_backend_bind()
 929  **/
 930 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 931 {
 932         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 933         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 934         unsigned nents;
 935         int r;
 936
 937         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 938         enum dma_data_direction direction = write ?
 939                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 940
 941         /* Allocate an SG array and squash pages into it */
 942         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 943                                       ttm->num_pages << PAGE_SHIFT,
 944                                       GFP_KERNEL);
 945         if (r)
 946                 goto release_sg;
 947
 948         /* Map SG to device */
 949         r = -ENOMEM;
 950         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 951         if (nents != ttm->sg->nents)
 952                 goto release_sg;
 953
 954         /* convert SG to linear array of pages and dma addresses */
 955         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 956                                          gtt->ttm.dma_address, ttm->num_pages);
 957
 958         return 0;
 959
 960 release_sg:
 961         kfree(ttm->sg);
 962         return r;
 963 }
 964
 965 /**
 966  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 967  */
 968 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 969 {
 970         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 971         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 972
 973         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 974         enum dma_data_direction direction = write ?
 975                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 976
 977         /* double check that we don't free the table twice */
 978         if (!ttm->sg->sgl)
 979                 return;
 980
 981         /* unmap the pages mapped to the device */
 982         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 983
 984         sg_free_table(ttm->sg);
 985
 986 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 987         if (gtt->range &&
 988             ttm->pages[0] == hmm_device_entry_to_page(gtt->range,
 989                                                       gtt->range->pfns[0]))
 990                 WARN_ONCE(1, "Missing get_user_page_done\n");
 991 #endif
 992 }
 993
 994 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 995                                 struct ttm_buffer_object *tbo,
 996                                 uint64_t flags)
 997 {
 998         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 999         struct ttm_tt *ttm = tbo->ttm;
1000         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1001         int r;
1002
1003         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
1004                 uint64_t page_idx = 1;
1005
1006                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1007                                 ttm->pages, gtt->ttm.dma_address, flags);
1008                 if (r)
1009                         goto gart_bind_fail;
1010
1011                 /* Patch mtype of the second part BO */
1012                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1013                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1014
1015                 r = amdgpu_gart_bind(adev,
1016                                 gtt->offset + (page_idx << PAGE_SHIFT),
1017                                 ttm->num_pages - page_idx,
1018                                 &ttm->pages[page_idx],
1019                                 &(gtt->ttm.dma_address[page_idx]), flags);
1020         } else {
1021                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1022                                      ttm->pages, gtt->ttm.dma_address, flags);
1023         }
1024
1025 gart_bind_fail:
1026         if (r)
1027                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1028                           ttm->num_pages, gtt->offset);
1029
1030         return r;
1031 }
1032
1033 /**
1034  * amdgpu_ttm_backend_bind - Bind GTT memory
1035  *
1036  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1037  * This handles binding GTT memory to the device address space.
1038  */
1039 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1040                                    struct ttm_mem_reg *bo_mem)
1041 {
1042         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1043         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1044         uint64_t flags;
1045         int r = 0;
1046
1047         if (gtt->userptr) {
1048                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1049                 if (r) {
1050                         DRM_ERROR("failed to pin userptr\n");
1051                         return r;
1052                 }
1053         }
1054         if (!ttm->num_pages) {
1055                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1056                      ttm->num_pages, bo_mem, ttm);
1057         }
1058
1059         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1060             bo_mem->mem_type == AMDGPU_PL_GWS ||
1061             bo_mem->mem_type == AMDGPU_PL_OA)
1062                 return -EINVAL;
1063
1064         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1065                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1066                 return 0;
1067         }
1068
1069         /* compute PTE flags relevant to this BO memory */
1070         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1071
1072         /* bind pages into GART page tables */
1073         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1074         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1075                 ttm->pages, gtt->ttm.dma_address, flags);
1076
1077         if (r)
1078                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1079                           ttm->num_pages, gtt->offset);
1080         return r;
1081 }
1082
1083 /**
1084  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1085  */
1086 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1087 {
1088         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1089         struct ttm_operation_ctx ctx = { false, false };
1090         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1091         struct ttm_mem_reg tmp;
1092         struct ttm_placement placement;
1093         struct ttm_place placements;
1094         uint64_t addr, flags;
1095         int r;
1096
1097         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1098                 return 0;
1099
1100         addr = amdgpu_gmc_agp_addr(bo);
1101         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1102                 bo->mem.start = addr >> PAGE_SHIFT;
1103         } else {
1104
1105                 /* allocate GART space */
1106                 tmp = bo->mem;
1107                 tmp.mm_node = NULL;
1108                 placement.num_placement = 1;
1109                 placement.placement = &placements;
1110                 placement.num_busy_placement = 1;
1111                 placement.busy_placement = &placements;
1112                 placements.fpfn = 0;
1113                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1114                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1115                         TTM_PL_FLAG_TT;
1116
1117                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1118                 if (unlikely(r))
1119                         return r;
1120
1121                 /* compute PTE flags for this buffer object */
1122                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1123
1124                 /* Bind pages */
1125                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1126                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1127                 if (unlikely(r)) {
1128                         ttm_bo_mem_put(bo, &tmp);
1129                         return r;
1130                 }
1131
1132                 ttm_bo_mem_put(bo, &bo->mem);
1133                 bo->mem = tmp;
1134         }
1135
1136         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1137                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1138
1139         return 0;
1140 }
1141
1142 /**
1143  * amdgpu_ttm_recover_gart - Rebind GTT pages
1144  *
1145  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1146  * rebind GTT pages during a GPU reset.
1147  */
1148 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1149 {
1150         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1151         uint64_t flags;
1152         int r;
1153
1154         if (!tbo->ttm)
1155                 return 0;
1156
1157         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1158         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1159
1160         return r;
1161 }
1162
1163 /**
1164  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1165  *
1166  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1167  * ttm_tt_destroy().
1168  */
1169 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1170 {
1171         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1172         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1173         int r;
1174
1175         /* if the pages have userptr pinning then clear that first */
1176         if (gtt->userptr)
1177                 amdgpu_ttm_tt_unpin_userptr(ttm);
1178
1179         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1180                 return 0;
1181
1182         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1183         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1184         if (r)
1185                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1186                           gtt->ttm.ttm.num_pages, gtt->offset);
1187         return r;
1188 }
1189
1190 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1191 {
1192         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1193
1194         if (gtt->usertask)
1195                 put_task_struct(gtt->usertask);
1196
1197         ttm_dma_tt_fini(&gtt->ttm);
1198         kfree(gtt);
1199 }
1200
1201 static struct ttm_backend_func amdgpu_backend_func = {
1202         .bind = &amdgpu_ttm_backend_bind,
1203         .unbind = &amdgpu_ttm_backend_unbind,
1204         .destroy = &amdgpu_ttm_backend_destroy,
1205 };
1206
1207 /**
1208  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1209  *
1210  * @bo: The buffer object to create a GTT ttm_tt object around
1211  *
1212  * Called by ttm_tt_create().
1213  */
1214 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1215                                            uint32_t page_flags)
1216 {
1217         struct amdgpu_ttm_tt *gtt;
1218
1219         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1220         if (gtt == NULL) {
1221                 return NULL;
1222         }
1223         gtt->ttm.ttm.func = &amdgpu_backend_func;
1224         gtt->gobj = &bo->base;
1225
1226         /* allocate space for the uninitialized page entries */
1227         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1228                 kfree(gtt);
1229                 return NULL;
1230         }
1231         return &gtt->ttm.ttm;
1232 }
1233
1234 /**
1235  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1236  *
1237  * Map the pages of a ttm_tt object to an address space visible
1238  * to the underlying device.
1239  */
1240 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1241                         struct ttm_operation_ctx *ctx)
1242 {
1243         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1244         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1245
1246         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1247         if (gtt && gtt->userptr) {
1248                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1249                 if (!ttm->sg)
1250                         return -ENOMEM;
1251
1252                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1253                 ttm->state = tt_unbound;
1254                 return 0;
1255         }
1256
1257         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1258                 if (!ttm->sg) {
1259                         struct dma_buf_attachment *attach;
1260                         struct sg_table *sgt;
1261
1262                         attach = gtt->gobj->import_attach;
1263                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1264                         if (IS_ERR(sgt))
1265                                 return PTR_ERR(sgt);
1266
1267                         ttm->sg = sgt;
1268                 }
1269
1270                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1271                                                  gtt->ttm.dma_address,
1272                                                  ttm->num_pages);
1273                 ttm->state = tt_unbound;
1274                 return 0;
1275         }
1276
1277 #ifdef CONFIG_SWIOTLB
1278         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1279                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1280         }
1281 #endif
1282
1283         /* fall back to generic helper to populate the page array
1284          * and map them to the device */
1285         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1286 }
1287
1288 /**
1289  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1290  *
1291  * Unmaps pages of a ttm_tt object from the device address space and
1292  * unpopulates the page array backing it.
1293  */
1294 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1295 {
1296         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1297         struct amdgpu_device *adev;
1298
1299         if (gtt && gtt->userptr) {
1300                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1301                 kfree(ttm->sg);
1302                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1303                 return;
1304         }
1305
1306         if (ttm->sg && gtt->gobj->import_attach) {
1307                 struct dma_buf_attachment *attach;
1308
1309                 attach = gtt->gobj->import_attach;
1310                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1311                 ttm->sg = NULL;
1312                 return;
1313         }
1314
1315         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1316                 return;
1317
1318         adev = amdgpu_ttm_adev(ttm->bdev);
1319
1320 #ifdef CONFIG_SWIOTLB
1321         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1322                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1323                 return;
1324         }
1325 #endif
1326
1327         /* fall back to generic helper to unmap and unpopulate array */
1328         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1329 }
1330
1331 /**
1332  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1333  * task
1334  *
1335  * @ttm: The ttm_tt object to bind this userptr object to
1336  * @addr:  The address in the current tasks VM space to use
1337  * @flags: Requirements of userptr object.
1338  *
1339  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1340  * to current task
1341  */
1342 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1343                               uint32_t flags)
1344 {
1345         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1346
1347         if (gtt == NULL)
1348                 return -EINVAL;
1349
1350         gtt->userptr = addr;
1351         gtt->userflags = flags;
1352
1353         if (gtt->usertask)
1354                 put_task_struct(gtt->usertask);
1355         gtt->usertask = current->group_leader;
1356         get_task_struct(gtt->usertask);
1357
1358         return 0;
1359 }
1360
1361 /**
1362  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1363  */
1364 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1365 {
1366         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1367
1368         if (gtt == NULL)
1369                 return NULL;
1370
1371         if (gtt->usertask == NULL)
1372                 return NULL;
1373
1374         return gtt->usertask->mm;
1375 }
1376
1377 /**
1378  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1379  * address range for the current task.
1380  *
1381  */
1382 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1383                                   unsigned long end)
1384 {
1385         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1386         unsigned long size;
1387
1388         if (gtt == NULL || !gtt->userptr)
1389                 return false;
1390
1391         /* Return false if no part of the ttm_tt object lies within
1392          * the range
1393          */
1394         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1395         if (gtt->userptr > end || gtt->userptr + size <= start)
1396                 return false;
1397
1398         return true;
1399 }
1400
1401 /**
1402  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1403  */
1404 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1405 {
1406         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1407
1408         if (gtt == NULL || !gtt->userptr)
1409                 return false;
1410
1411         return true;
1412 }
1413
1414 /**
1415  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1416  */
1417 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1418 {
1419         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1420
1421         if (gtt == NULL)
1422                 return false;
1423
1424         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1425 }
1426
1427 /**
1428  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1429  *
1430  * @ttm: The ttm_tt object to compute the flags for
1431  * @mem: The memory registry backing this ttm_tt object
1432  *
1433  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1434  */
1435 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1436 {
1437         uint64_t flags = 0;
1438
1439         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1440                 flags |= AMDGPU_PTE_VALID;
1441
1442         if (mem && mem->mem_type == TTM_PL_TT) {
1443                 flags |= AMDGPU_PTE_SYSTEM;
1444
1445                 if (ttm->caching_state == tt_cached)
1446                         flags |= AMDGPU_PTE_SNOOPED;
1447         }
1448
1449         return flags;
1450 }
1451
1452 /**
1453  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1454  *
1455  * @ttm: The ttm_tt object to compute the flags for
1456  * @mem: The memory registry backing this ttm_tt object
1457
1458  * Figure out the flags to use for a VM PTE (Page Table Entry).
1459  */
1460 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1461                                  struct ttm_mem_reg *mem)
1462 {
1463         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1464
1465         flags |= adev->gart.gart_pte_flags;
1466         flags |= AMDGPU_PTE_READABLE;
1467
1468         if (!amdgpu_ttm_tt_is_readonly(ttm))
1469                 flags |= AMDGPU_PTE_WRITEABLE;
1470
1471         return flags;
1472 }
1473
1474 /**
1475  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1476  * object.
1477  *
1478  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1479  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1480  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1481  * used to clean out a memory space.
1482  */
1483 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1484                                             const struct ttm_place *place)
1485 {
1486         unsigned long num_pages = bo->mem.num_pages;
1487         struct drm_mm_node *node = bo->mem.mm_node;
1488         struct dma_resv_list *flist;
1489         struct dma_fence *f;
1490         int i;
1491
1492         /* Don't evict VM page tables while they are busy, otherwise we can't
1493          * cleanly handle page faults.
1494          */
1495         if (bo->type == ttm_bo_type_kernel &&
1496             !dma_resv_test_signaled_rcu(bo->base.resv, true))
1497                 return false;
1498
1499         /* If bo is a KFD BO, check if the bo belongs to the current process.
1500          * If true, then return false as any KFD process needs all its BOs to
1501          * be resident to run successfully
1502          */
1503         flist = dma_resv_get_list(bo->base.resv);
1504         if (flist) {
1505                 for (i = 0; i < flist->shared_count; ++i) {
1506                         f = rcu_dereference_protected(flist->shared[i],
1507                                 dma_resv_held(bo->base.resv));
1508                         if (amdkfd_fence_check_mm(f, current->mm))
1509                                 return false;
1510                 }
1511         }
1512
1513         switch (bo->mem.mem_type) {
1514         case TTM_PL_TT:
1515                 return true;
1516
1517         case TTM_PL_VRAM:
1518                 /* Check each drm MM node individually */
1519                 while (num_pages) {
1520                         if (place->fpfn < (node->start + node->size) &&
1521                             !(place->lpfn && place->lpfn <= node->start))
1522                                 return true;
1523
1524                         num_pages -= node->size;
1525                         ++node;
1526                 }
1527                 return false;
1528
1529         default:
1530                 break;
1531         }
1532
1533         return ttm_bo_eviction_valuable(bo, place);
1534 }
1535
1536 /**
1537  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1538  *
1539  * @bo:  The buffer object to read/write
1540  * @offset:  Offset into buffer object
1541  * @buf:  Secondary buffer to write/read from
1542  * @len: Length in bytes of access
1543  * @write:  true if writing
1544  *
1545  * This is used to access VRAM that backs a buffer object via MMIO
1546  * access for debugging purposes.
1547  */
1548 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1549                                     unsigned long offset,
1550                                     void *buf, int len, int write)
1551 {
1552         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1553         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1554         struct drm_mm_node *nodes;
1555         uint32_t value = 0;
1556         int ret = 0;
1557         uint64_t pos;
1558         unsigned long flags;
1559
1560         if (bo->mem.mem_type != TTM_PL_VRAM)
1561                 return -EIO;
1562
1563         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1564         pos = (nodes->start << PAGE_SHIFT) + offset;
1565
1566         while (len && pos < adev->gmc.mc_vram_size) {
1567                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1568                 uint32_t bytes = 4 - (pos & 3);
1569                 uint32_t shift = (pos & 3) * 8;
1570                 uint32_t mask = 0xffffffff << shift;
1571
1572                 if (len < bytes) {
1573                         mask &= 0xffffffff >> (bytes - len) * 8;
1574                         bytes = len;
1575                 }
1576
1577                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1578                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1579                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1580                 if (!write || mask != 0xffffffff)
1581                         value = RREG32_NO_KIQ(mmMM_DATA);
1582                 if (write) {
1583                         value &= ~mask;
1584                         value |= (*(uint32_t *)buf << shift) & mask;
1585                         WREG32_NO_KIQ(mmMM_DATA, value);
1586                 }
1587                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1588                 if (!write) {
1589                         value = (value & mask) >> shift;
1590                         memcpy(buf, &value, bytes);
1591                 }
1592
1593                 ret += bytes;
1594                 buf = (uint8_t *)buf + bytes;
1595                 pos += bytes;
1596                 len -= bytes;
1597                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1598                         ++nodes;
1599                         pos = (nodes->start << PAGE_SHIFT);
1600                 }
1601         }
1602
1603         return ret;
1604 }
1605
1606 static struct ttm_bo_driver amdgpu_bo_driver = {
1607         .ttm_tt_create = &amdgpu_ttm_tt_create,
1608         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1609         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1610         .invalidate_caches = &amdgpu_invalidate_caches,
1611         .init_mem_type = &amdgpu_init_mem_type,
1612         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1613         .evict_flags = &amdgpu_evict_flags,
1614         .move = &amdgpu_bo_move,
1615         .verify_access = &amdgpu_verify_access,
1616         .move_notify = &amdgpu_bo_move_notify,
1617         .release_notify = &amdgpu_bo_release_notify,
1618         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1619         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1620         .io_mem_free = &amdgpu_ttm_io_mem_free,
1621         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1622         .access_memory = &amdgpu_ttm_access_memory,
1623         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1624 };
1625
1626 /*
1627  * Firmware Reservation functions
1628  */
1629 /**
1630  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1631  *
1632  * @adev: amdgpu_device pointer
1633  *
1634  * free fw reserved vram if it has been reserved.
1635  */
1636 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1637 {
1638         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1639                 NULL, &adev->fw_vram_usage.va);
1640 }
1641
1642 /**
1643  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1644  *
1645  * @adev: amdgpu_device pointer
1646  *
1647  * create bo vram reservation from fw.
1648  */
1649 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1650 {
1651         uint64_t vram_size = adev->gmc.visible_vram_size;
1652
1653         adev->fw_vram_usage.va = NULL;
1654         adev->fw_vram_usage.reserved_bo = NULL;
1655
1656         if (adev->fw_vram_usage.size == 0 ||
1657             adev->fw_vram_usage.size > vram_size)
1658                 return 0;
1659
1660         return amdgpu_bo_create_kernel_at(adev,
1661                                           adev->fw_vram_usage.start_offset,
1662                                           adev->fw_vram_usage.size,
1663                                           AMDGPU_GEM_DOMAIN_VRAM,
1664                                           &adev->fw_vram_usage.reserved_bo,
1665                                           &adev->fw_vram_usage.va);
1666 }
1667
1668 /*
1669  * Memoy training reservation functions
1670  */
1671
1672 /**
1673  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1674  *
1675  * @adev: amdgpu_device pointer
1676  *
1677  * free memory training reserved vram if it has been reserved.
1678  */
1679 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1680 {
1681         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1682
1683         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1684         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1685         ctx->c2p_bo = NULL;
1686
1687         amdgpu_bo_free_kernel(&ctx->p2c_bo, NULL, NULL);
1688         ctx->p2c_bo = NULL;
1689
1690         return 0;
1691 }
1692
1693 /**
1694  * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1695  *
1696  * @adev: amdgpu_device pointer
1697  *
1698  * create bo vram reservation from memory training.
1699  */
1700 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1701 {
1702         int ret;
1703         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1704
1705         memset(ctx, 0, sizeof(*ctx));
1706         if (!adev->fw_vram_usage.mem_train_support) {
1707                 DRM_DEBUG("memory training does not support!\n");
1708                 return 0;
1709         }
1710
1711         ctx->c2p_train_data_offset = adev->fw_vram_usage.mem_train_fb_loc;
1712         ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1713         ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1714
1715         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1716                   ctx->train_data_size,
1717                   ctx->p2c_train_data_offset,
1718                   ctx->c2p_train_data_offset);
1719
1720         ret = amdgpu_bo_create_kernel_at(adev,
1721                                          ctx->p2c_train_data_offset,
1722                                          ctx->train_data_size,
1723                                          AMDGPU_GEM_DOMAIN_VRAM,
1724                                          &ctx->p2c_bo,
1725                                          NULL);
1726         if (ret) {
1727                 DRM_ERROR("alloc p2c_bo failed(%d)!\n", ret);
1728                 goto Err_out;
1729         }
1730
1731         ret = amdgpu_bo_create_kernel_at(adev,
1732                                          ctx->c2p_train_data_offset,
1733                                          ctx->train_data_size,
1734                                          AMDGPU_GEM_DOMAIN_VRAM,
1735                                          &ctx->c2p_bo,
1736                                          NULL);
1737         if (ret) {
1738                 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1739                 goto Err_out;
1740         }
1741
1742         ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1743         return 0;
1744
1745 Err_out:
1746         amdgpu_ttm_training_reserve_vram_fini(adev);
1747         return ret;
1748 }
1749
1750 /**
1751  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1752  * gtt/vram related fields.
1753  *
1754  * This initializes all of the memory space pools that the TTM layer
1755  * will need such as the GTT space (system memory mapped to the device),
1756  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1757  * can be mapped per VMID.
1758  */
1759 int amdgpu_ttm_init(struct amdgpu_device *adev)
1760 {
1761         uint64_t gtt_size;
1762         int r;
1763         u64 vis_vram_limit;
1764         void *stolen_vga_buf;
1765
1766         mutex_init(&adev->mman.gtt_window_lock);
1767
1768         /* No others user of address space so set it to 0 */
1769         r = ttm_bo_device_init(&adev->mman.bdev,
1770                                &amdgpu_bo_driver,
1771                                adev->ddev->anon_inode->i_mapping,
1772                                adev->ddev->vma_offset_manager,
1773                                dma_addressing_limited(adev->dev));
1774         if (r) {
1775                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1776                 return r;
1777         }
1778         adev->mman.initialized = true;
1779
1780         /* We opt to avoid OOM on system pages allocations */
1781         adev->mman.bdev.no_retry = true;
1782
1783         /* Initialize VRAM pool with all of VRAM divided into pages */
1784         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1785                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1786         if (r) {
1787                 DRM_ERROR("Failed initializing VRAM heap.\n");
1788                 return r;
1789         }
1790
1791         /* Reduce size of CPU-visible VRAM if requested */
1792         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1793         if (amdgpu_vis_vram_limit > 0 &&
1794             vis_vram_limit <= adev->gmc.visible_vram_size)
1795                 adev->gmc.visible_vram_size = vis_vram_limit;
1796
1797         /* Change the size here instead of the init above so only lpfn is affected */
1798         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1799 #ifdef CONFIG_64BIT
1800         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1801                                                 adev->gmc.visible_vram_size);
1802 #endif
1803
1804         /*
1805          *The reserved vram for firmware must be pinned to the specified
1806          *place on the VRAM, so reserve it early.
1807          */
1808         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1809         if (r) {
1810                 return r;
1811         }
1812
1813         /*
1814          *The reserved vram for memory training must be pinned to the specified
1815          *place on the VRAM, so reserve it early.
1816          */
1817         r = amdgpu_ttm_training_reserve_vram_init(adev);
1818         if (r)
1819                 return r;
1820
1821         /* allocate memory as required for VGA
1822          * This is used for VGA emulation and pre-OS scanout buffers to
1823          * avoid display artifacts while transitioning between pre-OS
1824          * and driver.  */
1825         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1826                                     AMDGPU_GEM_DOMAIN_VRAM,
1827                                     &adev->stolen_vga_memory,
1828                                     NULL, &stolen_vga_buf);
1829         if (r)
1830                 return r;
1831
1832         /*
1833          * reserve one TMR (64K) memory at the top of VRAM which holds
1834          * IP Discovery data and is protected by PSP.
1835          */
1836         r = amdgpu_bo_create_kernel_at(adev,
1837                                        adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1838                                        DISCOVERY_TMR_SIZE,
1839                                        AMDGPU_GEM_DOMAIN_VRAM,
1840                                        &adev->discovery_memory,
1841                                        NULL);
1842         if (r)
1843                 return r;
1844
1845         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1846                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1847
1848         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1849          * or whatever the user passed on module init */
1850         if (amdgpu_gtt_size == -1) {
1851                 struct sysinfo si;
1852
1853                 si_meminfo(&si);
1854                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1855                                adev->gmc.mc_vram_size),
1856                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1857         }
1858         else
1859                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1860
1861         /* Initialize GTT memory pool */
1862         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1863         if (r) {
1864                 DRM_ERROR("Failed initializing GTT heap.\n");
1865                 return r;
1866         }
1867         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1868                  (unsigned)(gtt_size / (1024 * 1024)));
1869
1870         /* Initialize various on-chip memory pools */
1871         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1872                            adev->gds.gds_size);
1873         if (r) {
1874                 DRM_ERROR("Failed initializing GDS heap.\n");
1875                 return r;
1876         }
1877
1878         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1879                            adev->gds.gws_size);
1880         if (r) {
1881                 DRM_ERROR("Failed initializing gws heap.\n");
1882                 return r;
1883         }
1884
1885         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1886                            adev->gds.oa_size);
1887         if (r) {
1888                 DRM_ERROR("Failed initializing oa heap.\n");
1889                 return r;
1890         }
1891
1892         /* Register debugfs entries for amdgpu_ttm */
1893         r = amdgpu_ttm_debugfs_init(adev);
1894         if (r) {
1895                 DRM_ERROR("Failed to init debugfs\n");
1896                 return r;
1897         }
1898         return 0;
1899 }
1900
1901 /**
1902  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1903  */
1904 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1905 {
1906         void *stolen_vga_buf;
1907         /* return the VGA stolen memory (if any) back to VRAM */
1908         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1909
1910         /* return the IP Discovery TMR memory back to VRAM */
1911         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
1912 }
1913
1914 /**
1915  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1916  */
1917 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1918 {
1919         if (!adev->mman.initialized)
1920                 return;
1921
1922         amdgpu_ttm_debugfs_fini(adev);
1923         amdgpu_ttm_training_reserve_vram_fini(adev);
1924         amdgpu_ttm_fw_reserve_vram_fini(adev);
1925         if (adev->mman.aper_base_kaddr)
1926                 iounmap(adev->mman.aper_base_kaddr);
1927         adev->mman.aper_base_kaddr = NULL;
1928
1929         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1930         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1931         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1932         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1933         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1934         ttm_bo_device_release(&adev->mman.bdev);
1935         adev->mman.initialized = false;
1936         DRM_INFO("amdgpu: ttm finalized\n");
1937 }
1938
1939 /**
1940  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1941  *
1942  * @adev: amdgpu_device pointer
1943  * @enable: true when we can use buffer functions.
1944  *
1945  * Enable/disable use of buffer functions during suspend/resume. This should
1946  * only be called at bootup or when userspace isn't running.
1947  */
1948 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1949 {
1950         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1951         uint64_t size;
1952         int r;
1953
1954         if (!adev->mman.initialized || adev->in_gpu_reset ||
1955             adev->mman.buffer_funcs_enabled == enable)
1956                 return;
1957
1958         if (enable) {
1959                 struct amdgpu_ring *ring;
1960                 struct drm_sched_rq *rq;
1961
1962                 ring = adev->mman.buffer_funcs_ring;
1963                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1964                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1965                 if (r) {
1966                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1967                                   r);
1968                         return;
1969                 }
1970         } else {
1971                 drm_sched_entity_destroy(&adev->mman.entity);
1972                 dma_fence_put(man->move);
1973                 man->move = NULL;
1974         }
1975
1976         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1977         if (enable)
1978                 size = adev->gmc.real_vram_size;
1979         else
1980                 size = adev->gmc.visible_vram_size;
1981         man->size = size >> PAGE_SHIFT;
1982         adev->mman.buffer_funcs_enabled = enable;
1983 }
1984
1985 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1986 {
1987         struct drm_file *file_priv = filp->private_data;
1988         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
1989
1990         if (adev == NULL)
1991                 return -EINVAL;
1992
1993         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1994 }
1995
1996 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1997                              struct ttm_mem_reg *mem, unsigned num_pages,
1998                              uint64_t offset, unsigned window,
1999                              struct amdgpu_ring *ring,
2000                              uint64_t *addr)
2001 {
2002         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
2003         struct amdgpu_device *adev = ring->adev;
2004         struct ttm_tt *ttm = bo->ttm;
2005         struct amdgpu_job *job;
2006         unsigned num_dw, num_bytes;
2007         dma_addr_t *dma_address;
2008         struct dma_fence *fence;
2009         uint64_t src_addr, dst_addr;
2010         uint64_t flags;
2011         int r;
2012
2013         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
2014                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
2015
2016         *addr = adev->gmc.gart_start;
2017         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
2018                 AMDGPU_GPU_PAGE_SIZE;
2019
2020         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
2021         num_bytes = num_pages * 8;
2022
2023         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
2024         if (r)
2025                 return r;
2026
2027         src_addr = num_dw * 4;
2028         src_addr += job->ibs[0].gpu_addr;
2029
2030         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
2031         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
2032         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
2033                                 dst_addr, num_bytes);
2034
2035         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2036         WARN_ON(job->ibs[0].length_dw > num_dw);
2037
2038         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
2039         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2040         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
2041                             &job->ibs[0].ptr[num_dw]);
2042         if (r)
2043                 goto error_free;
2044
2045         r = amdgpu_job_submit(job, &adev->mman.entity,
2046                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
2047         if (r)
2048                 goto error_free;
2049
2050         dma_fence_put(fence);
2051
2052         return r;
2053
2054 error_free:
2055         amdgpu_job_free(job);
2056         return r;
2057 }
2058
2059 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2060                        uint64_t dst_offset, uint32_t byte_count,
2061                        struct dma_resv *resv,
2062                        struct dma_fence **fence, bool direct_submit,
2063                        bool vm_needs_flush)
2064 {
2065         struct amdgpu_device *adev = ring->adev;
2066         struct amdgpu_job *job;
2067
2068         uint32_t max_bytes;
2069         unsigned num_loops, num_dw;
2070         unsigned i;
2071         int r;
2072
2073         if (direct_submit && !ring->sched.ready) {
2074                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2075                 return -EINVAL;
2076         }
2077
2078         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2079         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2080         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2081
2082         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2083         if (r)
2084                 return r;
2085
2086         if (vm_needs_flush) {
2087                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2088                 job->vm_needs_flush = true;
2089         }
2090         if (resv) {
2091                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2092                                      AMDGPU_FENCE_OWNER_UNDEFINED,
2093                                      false);
2094                 if (r) {
2095                         DRM_ERROR("sync failed (%d).\n", r);
2096                         goto error_free;
2097                 }
2098         }
2099
2100         for (i = 0; i < num_loops; i++) {
2101                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2102
2103                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2104                                         dst_offset, cur_size_in_bytes);
2105
2106                 src_offset += cur_size_in_bytes;
2107                 dst_offset += cur_size_in_bytes;
2108                 byte_count -= cur_size_in_bytes;
2109         }
2110
2111         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2112         WARN_ON(job->ibs[0].length_dw > num_dw);
2113         if (direct_submit)
2114                 r = amdgpu_job_submit_direct(job, ring, fence);
2115         else
2116                 r = amdgpu_job_submit(job, &adev->mman.entity,
2117                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2118         if (r)
2119                 goto error_free;
2120
2121         return r;
2122
2123 error_free:
2124         amdgpu_job_free(job);
2125         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2126         return r;
2127 }
2128
2129 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2130                        uint32_t src_data,
2131                        struct dma_resv *resv,
2132                        struct dma_fence **fence)
2133 {
2134         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2135         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2136         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2137
2138         struct drm_mm_node *mm_node;
2139         unsigned long num_pages;
2140         unsigned int num_loops, num_dw;
2141
2142         struct amdgpu_job *job;
2143         int r;
2144
2145         if (!adev->mman.buffer_funcs_enabled) {
2146                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2147                 return -EINVAL;
2148         }
2149
2150         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2151                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2152                 if (r)
2153                         return r;
2154         }
2155
2156         num_pages = bo->tbo.num_pages;
2157         mm_node = bo->tbo.mem.mm_node;
2158         num_loops = 0;
2159         while (num_pages) {
2160                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2161
2162                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2163                 num_pages -= mm_node->size;
2164                 ++mm_node;
2165         }
2166         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2167
2168         /* for IB padding */
2169         num_dw += 64;
2170
2171         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2172         if (r)
2173                 return r;
2174
2175         if (resv) {
2176                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2177                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2178                 if (r) {
2179                         DRM_ERROR("sync failed (%d).\n", r);
2180                         goto error_free;
2181                 }
2182         }
2183
2184         num_pages = bo->tbo.num_pages;
2185         mm_node = bo->tbo.mem.mm_node;
2186
2187         while (num_pages) {
2188                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2189                 uint64_t dst_addr;
2190
2191                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2192                 while (byte_count) {
2193                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2194                                                            max_bytes);
2195
2196                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2197                                                 dst_addr, cur_size_in_bytes);
2198
2199                         dst_addr += cur_size_in_bytes;
2200                         byte_count -= cur_size_in_bytes;
2201                 }
2202
2203                 num_pages -= mm_node->size;
2204                 ++mm_node;
2205         }
2206
2207         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2208         WARN_ON(job->ibs[0].length_dw > num_dw);
2209         r = amdgpu_job_submit(job, &adev->mman.entity,
2210                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2211         if (r)
2212                 goto error_free;
2213
2214         return 0;
2215
2216 error_free:
2217         amdgpu_job_free(job);
2218         return r;
2219 }
2220
2221 #if defined(CONFIG_DEBUG_FS)
2222
2223 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2224 {
2225         struct drm_info_node *node = (struct drm_info_node *)m->private;
2226         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2227         struct drm_device *dev = node->minor->dev;
2228         struct amdgpu_device *adev = dev->dev_private;
2229         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2230         struct drm_printer p = drm_seq_file_printer(m);
2231
2232         man->func->debug(man, &p);
2233         return 0;
2234 }
2235
2236 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2237         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2238         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2239         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2240         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2241         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2242         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2243 #ifdef CONFIG_SWIOTLB
2244         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2245 #endif
2246 };
2247
2248 /**
2249  * amdgpu_ttm_vram_read - Linear read access to VRAM
2250  *
2251  * Accesses VRAM via MMIO for debugging purposes.
2252  */
2253 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2254                                     size_t size, loff_t *pos)
2255 {
2256         struct amdgpu_device *adev = file_inode(f)->i_private;
2257         ssize_t result = 0;
2258         int r;
2259
2260         if (size & 0x3 || *pos & 0x3)
2261                 return -EINVAL;
2262
2263         if (*pos >= adev->gmc.mc_vram_size)
2264                 return -ENXIO;
2265
2266         while (size) {
2267                 unsigned long flags;
2268                 uint32_t value;
2269
2270                 if (*pos >= adev->gmc.mc_vram_size)
2271                         return result;
2272
2273                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2274                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2275                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2276                 value = RREG32_NO_KIQ(mmMM_DATA);
2277                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2278
2279                 r = put_user(value, (uint32_t *)buf);
2280                 if (r)
2281                         return r;
2282
2283                 result += 4;
2284                 buf += 4;
2285                 *pos += 4;
2286                 size -= 4;
2287         }
2288
2289         return result;
2290 }
2291
2292 /**
2293  * amdgpu_ttm_vram_write - Linear write access to VRAM
2294  *
2295  * Accesses VRAM via MMIO for debugging purposes.
2296  */
2297 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2298                                     size_t size, loff_t *pos)
2299 {
2300         struct amdgpu_device *adev = file_inode(f)->i_private;
2301         ssize_t result = 0;
2302         int r;
2303
2304         if (size & 0x3 || *pos & 0x3)
2305                 return -EINVAL;
2306
2307         if (*pos >= adev->gmc.mc_vram_size)
2308                 return -ENXIO;
2309
2310         while (size) {
2311                 unsigned long flags;
2312                 uint32_t value;
2313
2314                 if (*pos >= adev->gmc.mc_vram_size)
2315                         return result;
2316
2317                 r = get_user(value, (uint32_t *)buf);
2318                 if (r)
2319                         return r;
2320
2321                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2322                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2323                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2324                 WREG32_NO_KIQ(mmMM_DATA, value);
2325                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2326
2327                 result += 4;
2328                 buf += 4;
2329                 *pos += 4;
2330                 size -= 4;
2331         }
2332
2333         return result;
2334 }
2335
2336 static const struct file_operations amdgpu_ttm_vram_fops = {
2337         .owner = THIS_MODULE,
2338         .read = amdgpu_ttm_vram_read,
2339         .write = amdgpu_ttm_vram_write,
2340         .llseek = default_llseek,
2341 };
2342
2343 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2344
2345 /**
2346  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2347  */
2348 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2349                                    size_t size, loff_t *pos)
2350 {
2351         struct amdgpu_device *adev = file_inode(f)->i_private;
2352         ssize_t result = 0;
2353         int r;
2354
2355         while (size) {
2356                 loff_t p = *pos / PAGE_SIZE;
2357                 unsigned off = *pos & ~PAGE_MASK;
2358                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2359                 struct page *page;
2360                 void *ptr;
2361
2362                 if (p >= adev->gart.num_cpu_pages)
2363                         return result;
2364
2365                 page = adev->gart.pages[p];
2366                 if (page) {
2367                         ptr = kmap(page);
2368                         ptr += off;
2369
2370                         r = copy_to_user(buf, ptr, cur_size);
2371                         kunmap(adev->gart.pages[p]);
2372                 } else
2373                         r = clear_user(buf, cur_size);
2374
2375                 if (r)
2376                         return -EFAULT;
2377
2378                 result += cur_size;
2379                 buf += cur_size;
2380                 *pos += cur_size;
2381                 size -= cur_size;
2382         }
2383
2384         return result;
2385 }
2386
2387 static const struct file_operations amdgpu_ttm_gtt_fops = {
2388         .owner = THIS_MODULE,
2389         .read = amdgpu_ttm_gtt_read,
2390         .llseek = default_llseek
2391 };
2392
2393 #endif
2394
2395 /**
2396  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2397  *
2398  * This function is used to read memory that has been mapped to the
2399  * GPU and the known addresses are not physical addresses but instead
2400  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2401  */
2402 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2403                                  size_t size, loff_t *pos)
2404 {
2405         struct amdgpu_device *adev = file_inode(f)->i_private;
2406         struct iommu_domain *dom;
2407         ssize_t result = 0;
2408         int r;
2409
2410         /* retrieve the IOMMU domain if any for this device */
2411         dom = iommu_get_domain_for_dev(adev->dev);
2412
2413         while (size) {
2414                 phys_addr_t addr = *pos & PAGE_MASK;
2415                 loff_t off = *pos & ~PAGE_MASK;
2416                 size_t bytes = PAGE_SIZE - off;
2417                 unsigned long pfn;
2418                 struct page *p;
2419                 void *ptr;
2420
2421                 bytes = bytes < size ? bytes : size;
2422
2423                 /* Translate the bus address to a physical address.  If
2424                  * the domain is NULL it means there is no IOMMU active
2425                  * and the address translation is the identity
2426                  */
2427                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2428
2429                 pfn = addr >> PAGE_SHIFT;
2430                 if (!pfn_valid(pfn))
2431                         return -EPERM;
2432
2433                 p = pfn_to_page(pfn);
2434                 if (p->mapping != adev->mman.bdev.dev_mapping)
2435                         return -EPERM;
2436
2437                 ptr = kmap(p);
2438                 r = copy_to_user(buf, ptr + off, bytes);
2439                 kunmap(p);
2440                 if (r)
2441                         return -EFAULT;
2442
2443                 size -= bytes;
2444                 *pos += bytes;
2445                 result += bytes;
2446         }
2447
2448         return result;
2449 }
2450
2451 /**
2452  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2453  *
2454  * This function is used to write memory that has been mapped to the
2455  * GPU and the known addresses are not physical addresses but instead
2456  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2457  */
2458 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2459                                  size_t size, loff_t *pos)
2460 {
2461         struct amdgpu_device *adev = file_inode(f)->i_private;
2462         struct iommu_domain *dom;
2463         ssize_t result = 0;
2464         int r;
2465
2466         dom = iommu_get_domain_for_dev(adev->dev);
2467
2468         while (size) {
2469                 phys_addr_t addr = *pos & PAGE_MASK;
2470                 loff_t off = *pos & ~PAGE_MASK;
2471                 size_t bytes = PAGE_SIZE - off;
2472                 unsigned long pfn;
2473                 struct page *p;
2474                 void *ptr;
2475
2476                 bytes = bytes < size ? bytes : size;
2477
2478                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2479
2480                 pfn = addr >> PAGE_SHIFT;
2481                 if (!pfn_valid(pfn))
2482                         return -EPERM;
2483
2484                 p = pfn_to_page(pfn);
2485                 if (p->mapping != adev->mman.bdev.dev_mapping)
2486                         return -EPERM;
2487
2488                 ptr = kmap(p);
2489                 r = copy_from_user(ptr + off, buf, bytes);
2490                 kunmap(p);
2491                 if (r)
2492                         return -EFAULT;
2493
2494                 size -= bytes;
2495                 *pos += bytes;
2496                 result += bytes;
2497         }
2498
2499         return result;
2500 }
2501
2502 static const struct file_operations amdgpu_ttm_iomem_fops = {
2503         .owner = THIS_MODULE,
2504         .read = amdgpu_iomem_read,
2505         .write = amdgpu_iomem_write,
2506         .llseek = default_llseek
2507 };
2508
2509 static const struct {
2510         char *name;
2511         const struct file_operations *fops;
2512         int domain;
2513 } ttm_debugfs_entries[] = {
2514         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2515 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2516         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2517 #endif
2518         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2519 };
2520
2521 #endif
2522
2523 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2524 {
2525 #if defined(CONFIG_DEBUG_FS)
2526         unsigned count;
2527
2528         struct drm_minor *minor = adev->ddev->primary;
2529         struct dentry *ent, *root = minor->debugfs_root;
2530
2531         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2532                 ent = debugfs_create_file(
2533                                 ttm_debugfs_entries[count].name,
2534                                 S_IFREG | S_IRUGO, root,
2535                                 adev,
2536                                 ttm_debugfs_entries[count].fops);
2537                 if (IS_ERR(ent))
2538                         return PTR_ERR(ent);
2539                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2540                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2541                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2542                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2543                 adev->mman.debugfs_entries[count] = ent;
2544         }
2545
2546         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2547
2548 #ifdef CONFIG_SWIOTLB
2549         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2550                 --count;
2551 #endif
2552
2553         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2554 #else
2555         return 0;
2556 #endif
2557 }
2558
2559 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2560 {
2561 #if defined(CONFIG_DEBUG_FS)
2562         unsigned i;
2563
2564         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2565                 debugfs_remove(adev->mman.debugfs_entries[i]);
2566 #endif
2567 }