drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
  51
  52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
  54
  55 #define SDMA1_REG_OFFSET 0x600
  56 #define SDMA3_REG_OFFSET 0x400
  57 #define SDMA0_HYP_DEC_REG_START 0x5880
  58 #define SDMA0_HYP_DEC_REG_END 0x5893
  59 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  60
  61 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  64 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  65
  66 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  67 {
  68         u32 base;
  69
  70         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  71             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  72                 base = adev->reg_offset[GC_HWIP][0][1];
  73                 if (instance != 0)
  74                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  75         } else {
  76                 if (instance < 2) {
  77                         base = adev->reg_offset[GC_HWIP][0][0];
  78                         if (instance == 1)
  79                                 internal_offset += SDMA1_REG_OFFSET;
  80                 } else {
  81                         base = adev->reg_offset[GC_HWIP][0][2];
  82                         if (instance == 3)
  83                                 internal_offset += SDMA3_REG_OFFSET;
  84                 }
  85         }
  86
  87         return base + internal_offset;
  88 }
  89
  90 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
  91 {
  92         int err = 0;
  93         const struct sdma_firmware_header_v1_0 *hdr;
  94
  95         err = amdgpu_ucode_validate(sdma_inst->fw);
  96         if (err)
  97                 return err;
  98
  99         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 100         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 101         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 102
 103         if (sdma_inst->feature_version >= 20)
 104                 sdma_inst->burst_nop = true;
 105
 106         return 0;
 107 }
 108
 109 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 110 {
 111         release_firmware(adev->sdma.instance[0].fw);
 112
 113         memset((void *)adev->sdma.instance, 0,
 114                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 115 }
 116
 117 /**
 118  * sdma_v5_2_init_microcode - load ucode images from disk
 119  *
 120  * @adev: amdgpu_device pointer
 121  *
 122  * Use the firmware interface to load the ucode images into
 123  * the driver (not loaded into hw).
 124  * Returns 0 on success, error on failure.
 125  */
 126
 127 // emulation only, won't work on real chip
 128 // navi10 real chip need to use PSP to load firmware
 129 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 130 {
 131         const char *chip_name;
 132         char fw_name[40];
 133         int err = 0, i;
 134         struct amdgpu_firmware_info *info = NULL;
 135         const struct common_firmware_header *header = NULL;
 136
 137         DRM_DEBUG("\n");
 138
 139         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 140         case IP_VERSION(5, 2, 0):
 141                 chip_name = "sienna_cichlid";
 142                 break;
 143         case IP_VERSION(5, 2, 2):
 144                 chip_name = "navy_flounder";
 145                 break;
 146         case IP_VERSION(5, 2, 1):
 147                 chip_name = "vangogh";
 148                 break;
 149         case IP_VERSION(5, 2, 4):
 150                 chip_name = "dimgrey_cavefish";
 151                 break;
 152         case IP_VERSION(5, 2, 5):
 153                 chip_name = "beige_goby";
 154                 break;
 155         case IP_VERSION(5, 2, 3):
 156                 chip_name = "yellow_carp";
 157                 break;
 158         default:
 159                 BUG();
 160         }
 161
 162         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 163
 164         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 165         if (err)
 166                 goto out;
 167
 168         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 169         if (err)
 170                 goto out;
 171
 172         for (i = 1; i < adev->sdma.num_instances; i++)
 173                 memcpy((void *)&adev->sdma.instance[i],
 174                        (void *)&adev->sdma.instance[0],
 175                        sizeof(struct amdgpu_sdma_instance));
 176
 177         if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
 178                 return 0;
 179
 180         DRM_DEBUG("psp_load == '%s'\n",
 181                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 182
 183         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 184                 for (i = 0; i < adev->sdma.num_instances; i++) {
 185                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 186                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 187                         info->fw = adev->sdma.instance[i].fw;
 188                         header = (const struct common_firmware_header *)info->fw->data;
 189                         adev->firmware.fw_size +=
 190                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 191                 }
 192         }
 193
 194 out:
 195         if (err) {
 196                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 197                 sdma_v5_2_destroy_inst_ctx(adev);
 198         }
 199         return err;
 200 }
 201
 202 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 203 {
 204         unsigned ret;
 205
 206         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 207         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 208         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 209         amdgpu_ring_write(ring, 1);
 210         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 211         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 212
 213         return ret;
 214 }
 215
 216 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 217                                            unsigned offset)
 218 {
 219         unsigned cur;
 220
 221         BUG_ON(offset > ring->buf_mask);
 222         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 223
 224         cur = (ring->wptr - 1) & ring->buf_mask;
 225         if (cur > offset)
 226                 ring->ring[offset] = cur - offset;
 227         else
 228                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 229 }
 230
 231 /**
 232  * sdma_v5_2_ring_get_rptr - get the current read pointer
 233  *
 234  * @ring: amdgpu ring pointer
 235  *
 236  * Get the current rptr from the hardware (NAVI10+).
 237  */
 238 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 239 {
 240         u64 *rptr;
 241
 242         /* XXX check if swapping is necessary on BE */
 243         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 244
 245         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 246         return ((*rptr) >> 2);
 247 }
 248
 249 /**
 250  * sdma_v5_2_ring_get_wptr - get the current write pointer
 251  *
 252  * @ring: amdgpu ring pointer
 253  *
 254  * Get the current wptr from the hardware (NAVI10+).
 255  */
 256 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 257 {
 258         struct amdgpu_device *adev = ring->adev;
 259         u64 wptr;
 260
 261         if (ring->use_doorbell) {
 262                 /* XXX check if swapping is necessary on BE */
 263                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 264                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 265         } else {
 266                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 267                 wptr = wptr << 32;
 268                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 269                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 270         }
 271
 272         return wptr >> 2;
 273 }
 274
 275 /**
 276  * sdma_v5_2_ring_set_wptr - commit the write pointer
 277  *
 278  * @ring: amdgpu ring pointer
 279  *
 280  * Write the wptr back to the hardware (NAVI10+).
 281  */
 282 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 283 {
 284         struct amdgpu_device *adev = ring->adev;
 285
 286         DRM_DEBUG("Setting write pointer\n");
 287         if (ring->use_doorbell) {
 288                 DRM_DEBUG("Using doorbell -- "
 289                                 "wptr_offs == 0x%08x "
 290                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 291                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 292                                 ring->wptr_offs,
 293                                 lower_32_bits(ring->wptr << 2),
 294                                 upper_32_bits(ring->wptr << 2));
 295                 /* XXX check if swapping is necessary on BE */
 296                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 297                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 298                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 299                                 ring->doorbell_index, ring->wptr << 2);
 300                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 301         } else {
 302                 DRM_DEBUG("Not using doorbell -- "
 303                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 304                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 305                                 ring->me,
 306                                 lower_32_bits(ring->wptr << 2),
 307                                 ring->me,
 308                                 upper_32_bits(ring->wptr << 2));
 309                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 310                         lower_32_bits(ring->wptr << 2));
 311                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 312                         upper_32_bits(ring->wptr << 2));
 313         }
 314 }
 315
 316 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 317 {
 318         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 319         int i;
 320
 321         for (i = 0; i < count; i++)
 322                 if (sdma && sdma->burst_nop && (i == 0))
 323                         amdgpu_ring_write(ring, ring->funcs->nop |
 324                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 325                 else
 326                         amdgpu_ring_write(ring, ring->funcs->nop);
 327 }
 328
 329 /**
 330  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 331  *
 332  * @ring: amdgpu ring pointer
 333  * @job: job to retrieve vmid from
 334  * @ib: IB object to schedule
 335  * @flags: unused
 336  *
 337  * Schedule an IB in the DMA ring.
 338  */
 339 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 340                                    struct amdgpu_job *job,
 341                                    struct amdgpu_ib *ib,
 342                                    uint32_t flags)
 343 {
 344         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 345         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 346
 347         /* An IB packet must end on a 8 DW boundary--the next dword
 348          * must be on a 8-dword boundary. Our IB packet below is 6
 349          * dwords long, thus add x number of NOPs, such that, in
 350          * modular arithmetic,
 351          * wptr + 6 + x = 8k, k >= 0, which in C is,
 352          * (wptr + 6 + x) % 8 = 0.
 353          * The expression below, is a solution of x.
 354          */
 355         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 356
 357         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 358                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 359         /* base must be 32 byte aligned */
 360         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 361         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 362         amdgpu_ring_write(ring, ib->length_dw);
 363         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 364         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 365 }
 366
 367 /**
 368  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
 369  *
 370  * @ring: amdgpu ring pointer
 371  *
 372  * flush the IB by graphics cache rinse.
 373  */
 374 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
 375 {
 376         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
 377                             SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
 378                             SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 379                             SDMA_GCR_GLI_INV(1);
 380
 381         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 382         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 383         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 384         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 385                         SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 386         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 387                         SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 388         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 389                         SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 390 }
 391
 392 /**
 393  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 394  *
 395  * @ring: amdgpu ring pointer
 396  *
 397  * Emit an hdp flush packet on the requested DMA ring.
 398  */
 399 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 400 {
 401         struct amdgpu_device *adev = ring->adev;
 402         u32 ref_and_mask = 0;
 403         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 404
 405         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 406
 407         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 408                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 409                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 410         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 411         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 412         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 413         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 414         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 415                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 416 }
 417
 418 /**
 419  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 420  *
 421  * @ring: amdgpu ring pointer
 422  * @addr: address
 423  * @seq: sequence number
 424  * @flags: fence related flags
 425  *
 426  * Add a DMA fence packet to the ring to write
 427  * the fence seq number and DMA trap packet to generate
 428  * an interrupt if needed.
 429  */
 430 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 431                                       unsigned flags)
 432 {
 433         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 434         /* write the fence */
 435         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 436                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 437         /* zero in first two bits */
 438         BUG_ON(addr & 0x3);
 439         amdgpu_ring_write(ring, lower_32_bits(addr));
 440         amdgpu_ring_write(ring, upper_32_bits(addr));
 441         amdgpu_ring_write(ring, lower_32_bits(seq));
 442
 443         /* optionally write high bits as well */
 444         if (write64bit) {
 445                 addr += 4;
 446                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 447                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 448                 /* zero in first two bits */
 449                 BUG_ON(addr & 0x3);
 450                 amdgpu_ring_write(ring, lower_32_bits(addr));
 451                 amdgpu_ring_write(ring, upper_32_bits(addr));
 452                 amdgpu_ring_write(ring, upper_32_bits(seq));
 453         }
 454
 455         if (flags & AMDGPU_FENCE_FLAG_INT) {
 456                 /* generate an interrupt */
 457                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 458                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 459         }
 460 }
 461
 462
 463 /**
 464  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 465  *
 466  * @adev: amdgpu_device pointer
 467  *
 468  * Stop the gfx async dma ring buffers.
 469  */
 470 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 471 {
 472         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 473         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 474         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 475         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 476         u32 rb_cntl, ib_cntl;
 477         int i;
 478
 479         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 480             (adev->mman.buffer_funcs_ring == sdma1) ||
 481             (adev->mman.buffer_funcs_ring == sdma2) ||
 482             (adev->mman.buffer_funcs_ring == sdma3))
 483                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 484
 485         for (i = 0; i < adev->sdma.num_instances; i++) {
 486                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 487                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 488                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 489                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 490                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 491                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 492         }
 493 }
 494
 495 /**
 496  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 497  *
 498  * @adev: amdgpu_device pointer
 499  *
 500  * Stop the compute async dma queues.
 501  */
 502 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 503 {
 504         /* XXX todo */
 505 }
 506
 507 /**
 508  * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
 509  *
 510  * @adev: amdgpu_device pointer
 511  * @enable: enable/disable the DMA MEs context switch.
 512  *
 513  * Halt or unhalt the async dma engines context switch.
 514  */
 515 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 516 {
 517         u32 f32_cntl, phase_quantum = 0;
 518         int i;
 519
 520         if (amdgpu_sdma_phase_quantum) {
 521                 unsigned value = amdgpu_sdma_phase_quantum;
 522                 unsigned unit = 0;
 523
 524                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 525                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 526                         value = (value + 1) >> 1;
 527                         unit++;
 528                 }
 529                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 530                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 531                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 532                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 533                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 534                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 535                         WARN_ONCE(1,
 536                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 537                                   value << unit);
 538                 }
 539                 phase_quantum =
 540                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 541                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 542         }
 543
 544         for (i = 0; i < adev->sdma.num_instances; i++) {
 545                 if (enable && amdgpu_sdma_phase_quantum) {
 546                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 547                                phase_quantum);
 548                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 549                                phase_quantum);
 550                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 551                                phase_quantum);
 552                 }
 553
 554                 if (!amdgpu_sriov_vf(adev)) {
 555                         f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 556                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 557                                         AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 558                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 559                 }
 560         }
 561
 562 }
 563
 564 /**
 565  * sdma_v5_2_enable - stop the async dma engines
 566  *
 567  * @adev: amdgpu_device pointer
 568  * @enable: enable/disable the DMA MEs.
 569  *
 570  * Halt or unhalt the async dma engines.
 571  */
 572 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 573 {
 574         u32 f32_cntl;
 575         int i;
 576
 577         if (!enable) {
 578                 sdma_v5_2_gfx_stop(adev);
 579                 sdma_v5_2_rlc_stop(adev);
 580         }
 581
 582         if (!amdgpu_sriov_vf(adev)) {
 583                 for (i = 0; i < adev->sdma.num_instances; i++) {
 584                         f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 585                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 586                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 587                 }
 588         }
 589 }
 590
 591 /**
 592  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 593  *
 594  * @adev: amdgpu_device pointer
 595  *
 596  * Set up the gfx DMA ring buffers and enable them.
 597  * Returns 0 for success, error for failure.
 598  */
 599 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 600 {
 601         struct amdgpu_ring *ring;
 602         u32 rb_cntl, ib_cntl;
 603         u32 rb_bufsz;
 604         u32 wb_offset;
 605         u32 doorbell;
 606         u32 doorbell_offset;
 607         u32 temp;
 608         u32 wptr_poll_cntl;
 609         u64 wptr_gpu_addr;
 610         int i, r;
 611
 612         for (i = 0; i < adev->sdma.num_instances; i++) {
 613                 ring = &adev->sdma.instance[i].ring;
 614                 wb_offset = (ring->rptr_offs * 4);
 615
 616                 if (!amdgpu_sriov_vf(adev))
 617                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 618
 619                 /* Set ring buffer size in dwords */
 620                 rb_bufsz = order_base_2(ring->ring_size / 4);
 621                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 622                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 623 #ifdef __BIG_ENDIAN
 624                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 625                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 626                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 627 #endif
 628                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 629
 630                 /* Initialize the ring buffer's read and write pointers */
 631                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 632                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 633                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 634                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 635
 636                 /* setup the wptr shadow polling */
 637                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 638                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 639                        lower_32_bits(wptr_gpu_addr));
 640                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 641                        upper_32_bits(wptr_gpu_addr));
 642                 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
 643                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 644                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 645                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 646                                                F32_POLL_ENABLE, 1);
 647                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 648                        wptr_poll_cntl);
 649
 650                 /* set the wb address whether it's enabled or not */
 651                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 652                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 653                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 654                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 655
 656                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 657
 658                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 659                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 660
 661                 ring->wptr = 0;
 662
 663                 /* before programing wptr to a less value, need set minor_ptr_update first */
 664                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 665
 666                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 667                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 668                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 669                 }
 670
 671                 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 672                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 673
 674                 if (ring->use_doorbell) {
 675                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 676                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 677                                         OFFSET, ring->doorbell_index);
 678                 } else {
 679                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 680                 }
 681                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 682                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 683
 684                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 685                                                       ring->doorbell_index,
 686                                                       adev->doorbell_index.sdma_doorbell_range);
 687
 688                 if (amdgpu_sriov_vf(adev))
 689                         sdma_v5_2_ring_set_wptr(ring);
 690
 691                 /* set minor_ptr_update to 0 after wptr programed */
 692
 693                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 694
 695                 /* SRIOV VF has no control of any of registers below */
 696                 if (!amdgpu_sriov_vf(adev)) {
 697                         /* set utc l1 enable flag always to 1 */
 698                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 699                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 700
 701                         /* enable MCBP */
 702                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 703                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 704
 705                         /* Set up RESP_MODE to non-copy addresses */
 706                         temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 707                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 708                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 709                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 710
 711                         /* program default cache read and write policy */
 712                         temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 713                         /* clean read policy and write policy bits */
 714                         temp &= 0xFF0FFF;
 715                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 716                                  (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 717                                  SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 718                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 719
 720                         /* unhalt engine */
 721                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 722                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 723                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 724                 }
 725
 726                 /* enable DMA RB */
 727                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 728                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 729
 730                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 731                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 732 #ifdef __BIG_ENDIAN
 733                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 734 #endif
 735                 /* enable DMA IBs */
 736                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 737
 738                 ring->sched.ready = true;
 739
 740                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 741                         sdma_v5_2_ctx_switch_enable(adev, true);
 742                         sdma_v5_2_enable(adev, true);
 743                 }
 744
 745                 r = amdgpu_ring_test_ring(ring);
 746                 if (r) {
 747                         ring->sched.ready = false;
 748                         return r;
 749                 }
 750
 751                 if (adev->mman.buffer_funcs_ring == ring)
 752                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 753         }
 754
 755         return 0;
 756 }
 757
 758 /**
 759  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 760  *
 761  * @adev: amdgpu_device pointer
 762  *
 763  * Set up the compute DMA queues and enable them.
 764  * Returns 0 for success, error for failure.
 765  */
 766 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 767 {
 768         return 0;
 769 }
 770
 771 /**
 772  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 773  *
 774  * @adev: amdgpu_device pointer
 775  *
 776  * Loads the sDMA0/1/2/3 ucode.
 777  * Returns 0 for success, -EINVAL if the ucode is not available.
 778  */
 779 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 780 {
 781         const struct sdma_firmware_header_v1_0 *hdr;
 782         const __le32 *fw_data;
 783         u32 fw_size;
 784         int i, j;
 785
 786         /* halt the MEs */
 787         sdma_v5_2_enable(adev, false);
 788
 789         for (i = 0; i < adev->sdma.num_instances; i++) {
 790                 if (!adev->sdma.instance[i].fw)
 791                         return -EINVAL;
 792
 793                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 794                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 795                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 796
 797                 fw_data = (const __le32 *)
 798                         (adev->sdma.instance[i].fw->data +
 799                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 800
 801                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 802
 803                 for (j = 0; j < fw_size; j++) {
 804                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 805                                 msleep(1);
 806                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 807                 }
 808
 809                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 810         }
 811
 812         return 0;
 813 }
 814
 815 static int sdma_v5_2_soft_reset(void *handle)
 816 {
 817         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 818         u32 grbm_soft_reset;
 819         u32 tmp;
 820         int i;
 821
 822         for (i = 0; i < adev->sdma.num_instances; i++) {
 823                 grbm_soft_reset = REG_SET_FIELD(0,
 824                                                 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
 825                                                 1);
 826                 grbm_soft_reset <<= i;
 827
 828                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 829                 tmp |= grbm_soft_reset;
 830                 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
 831                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 832                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 833
 834                 udelay(50);
 835
 836                 tmp &= ~grbm_soft_reset;
 837                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 838                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 839
 840                 udelay(50);
 841         }
 842
 843         return 0;
 844 }
 845
 846 /**
 847  * sdma_v5_2_start - setup and start the async dma engines
 848  *
 849  * @adev: amdgpu_device pointer
 850  *
 851  * Set up the DMA engines and enable them.
 852  * Returns 0 for success, error for failure.
 853  */
 854 static int sdma_v5_2_start(struct amdgpu_device *adev)
 855 {
 856         int r = 0;
 857
 858         if (amdgpu_sriov_vf(adev)) {
 859                 sdma_v5_2_ctx_switch_enable(adev, false);
 860                 sdma_v5_2_enable(adev, false);
 861
 862                 /* set RB registers */
 863                 r = sdma_v5_2_gfx_resume(adev);
 864                 return r;
 865         }
 866
 867         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 868                 r = sdma_v5_2_load_microcode(adev);
 869                 if (r)
 870                         return r;
 871
 872                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 873                 if (amdgpu_emu_mode == 1)
 874                         msleep(1000);
 875         }
 876
 877         /* TODO: check whether can submit a doorbell request to raise
 878          * a doorbell fence to exit gfxoff.
 879          */
 880         if (adev->in_s0ix)
 881                 amdgpu_gfx_off_ctrl(adev, false);
 882
 883         sdma_v5_2_soft_reset(adev);
 884         /* unhalt the MEs */
 885         sdma_v5_2_enable(adev, true);
 886         /* enable sdma ring preemption */
 887         sdma_v5_2_ctx_switch_enable(adev, true);
 888
 889         /* start the gfx rings and rlc compute queues */
 890         r = sdma_v5_2_gfx_resume(adev);
 891         if (adev->in_s0ix)
 892                 amdgpu_gfx_off_ctrl(adev, true);
 893         if (r)
 894                 return r;
 895         r = sdma_v5_2_rlc_resume(adev);
 896
 897         return r;
 898 }
 899
 900 /**
 901  * sdma_v5_2_ring_test_ring - simple async dma engine test
 902  *
 903  * @ring: amdgpu_ring structure holding ring information
 904  *
 905  * Test the DMA engine by writing using it to write an
 906  * value to memory.
 907  * Returns 0 for success, error for failure.
 908  */
 909 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 910 {
 911         struct amdgpu_device *adev = ring->adev;
 912         unsigned i;
 913         unsigned index;
 914         int r;
 915         u32 tmp;
 916         u64 gpu_addr;
 917
 918         r = amdgpu_device_wb_get(adev, &index);
 919         if (r) {
 920                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 921                 return r;
 922         }
 923
 924         gpu_addr = adev->wb.gpu_addr + (index * 4);
 925         tmp = 0xCAFEDEAD;
 926         adev->wb.wb[index] = cpu_to_le32(tmp);
 927
 928         r = amdgpu_ring_alloc(ring, 5);
 929         if (r) {
 930                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 931                 amdgpu_device_wb_free(adev, index);
 932                 return r;
 933         }
 934
 935         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 936                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 937         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 938         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 939         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 940         amdgpu_ring_write(ring, 0xDEADBEEF);
 941         amdgpu_ring_commit(ring);
 942
 943         for (i = 0; i < adev->usec_timeout; i++) {
 944                 tmp = le32_to_cpu(adev->wb.wb[index]);
 945                 if (tmp == 0xDEADBEEF)
 946                         break;
 947                 if (amdgpu_emu_mode == 1)
 948                         msleep(1);
 949                 else
 950                         udelay(1);
 951         }
 952
 953         if (i >= adev->usec_timeout)
 954                 r = -ETIMEDOUT;
 955
 956         amdgpu_device_wb_free(adev, index);
 957
 958         return r;
 959 }
 960
 961 /**
 962  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 963  *
 964  * @ring: amdgpu_ring structure holding ring information
 965  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 966  *
 967  * Test a simple IB in the DMA ring.
 968  * Returns 0 on success, error on failure.
 969  */
 970 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 971 {
 972         struct amdgpu_device *adev = ring->adev;
 973         struct amdgpu_ib ib;
 974         struct dma_fence *f = NULL;
 975         unsigned index;
 976         long r;
 977         u32 tmp = 0;
 978         u64 gpu_addr;
 979
 980         r = amdgpu_device_wb_get(adev, &index);
 981         if (r) {
 982                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 983                 return r;
 984         }
 985
 986         gpu_addr = adev->wb.gpu_addr + (index * 4);
 987         tmp = 0xCAFEDEAD;
 988         adev->wb.wb[index] = cpu_to_le32(tmp);
 989         memset(&ib, 0, sizeof(ib));
 990         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 991         if (r) {
 992                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 993                 goto err0;
 994         }
 995
 996         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 997                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 998         ib.ptr[1] = lower_32_bits(gpu_addr);
 999         ib.ptr[2] = upper_32_bits(gpu_addr);
1000         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1001         ib.ptr[4] = 0xDEADBEEF;
1002         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1003         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1004         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1005         ib.length_dw = 8;
1006
1007         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1008         if (r)
1009                 goto err1;
1010
1011         r = dma_fence_wait_timeout(f, false, timeout);
1012         if (r == 0) {
1013                 DRM_ERROR("amdgpu: IB test timed out\n");
1014                 r = -ETIMEDOUT;
1015                 goto err1;
1016         } else if (r < 0) {
1017                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1018                 goto err1;
1019         }
1020         tmp = le32_to_cpu(adev->wb.wb[index]);
1021         if (tmp == 0xDEADBEEF)
1022                 r = 0;
1023         else
1024                 r = -EINVAL;
1025
1026 err1:
1027         amdgpu_ib_free(adev, &ib, NULL);
1028         dma_fence_put(f);
1029 err0:
1030         amdgpu_device_wb_free(adev, index);
1031         return r;
1032 }
1033
1034
1035 /**
1036  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1037  *
1038  * @ib: indirect buffer to fill with commands
1039  * @pe: addr of the page entry
1040  * @src: src addr to copy from
1041  * @count: number of page entries to update
1042  *
1043  * Update PTEs by copying them from the GART using sDMA.
1044  */
1045 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1046                                   uint64_t pe, uint64_t src,
1047                                   unsigned count)
1048 {
1049         unsigned bytes = count * 8;
1050
1051         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1052                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1053         ib->ptr[ib->length_dw++] = bytes - 1;
1054         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1055         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1056         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1057         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1058         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1059
1060 }
1061
1062 /**
1063  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1064  *
1065  * @ib: indirect buffer to fill with commands
1066  * @pe: addr of the page entry
1067  * @value: dst addr to write into pe
1068  * @count: number of page entries to update
1069  * @incr: increase next addr by incr bytes
1070  *
1071  * Update PTEs by writing them manually using sDMA.
1072  */
1073 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1074                                    uint64_t value, unsigned count,
1075                                    uint32_t incr)
1076 {
1077         unsigned ndw = count * 2;
1078
1079         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1080                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1081         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1082         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1083         ib->ptr[ib->length_dw++] = ndw - 1;
1084         for (; ndw > 0; ndw -= 2) {
1085                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1086                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1087                 value += incr;
1088         }
1089 }
1090
1091 /**
1092  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1093  *
1094  * @ib: indirect buffer to fill with commands
1095  * @pe: addr of the page entry
1096  * @addr: dst addr to write into pe
1097  * @count: number of page entries to update
1098  * @incr: increase next addr by incr bytes
1099  * @flags: access flags
1100  *
1101  * Update the page tables using sDMA.
1102  */
1103 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1104                                      uint64_t pe,
1105                                      uint64_t addr, unsigned count,
1106                                      uint32_t incr, uint64_t flags)
1107 {
1108         /* for physically contiguous pages (vram) */
1109         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1110         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1111         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1112         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1113         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1114         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1115         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1116         ib->ptr[ib->length_dw++] = incr; /* increment size */
1117         ib->ptr[ib->length_dw++] = 0;
1118         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1119 }
1120
1121 /**
1122  * sdma_v5_2_ring_pad_ib - pad the IB
1123  *
1124  * @ib: indirect buffer to fill with padding
1125  * @ring: amdgpu_ring structure holding ring information
1126  *
1127  * Pad the IB with NOPs to a boundary multiple of 8.
1128  */
1129 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1130 {
1131         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1132         u32 pad_count;
1133         int i;
1134
1135         pad_count = (-ib->length_dw) & 0x7;
1136         for (i = 0; i < pad_count; i++)
1137                 if (sdma && sdma->burst_nop && (i == 0))
1138                         ib->ptr[ib->length_dw++] =
1139                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1140                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1141                 else
1142                         ib->ptr[ib->length_dw++] =
1143                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1144 }
1145
1146
1147 /**
1148  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1149  *
1150  * @ring: amdgpu_ring pointer
1151  *
1152  * Make sure all previous operations are completed (CIK).
1153  */
1154 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1155 {
1156         uint32_t seq = ring->fence_drv.sync_seq;
1157         uint64_t addr = ring->fence_drv.gpu_addr;
1158
1159         /* wait for idle */
1160         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1161                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1162                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1163                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1164         amdgpu_ring_write(ring, addr & 0xfffffffc);
1165         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1166         amdgpu_ring_write(ring, seq); /* reference */
1167         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1168         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1169                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1170 }
1171
1172
1173 /**
1174  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1175  *
1176  * @ring: amdgpu_ring pointer
1177  * @vmid: vmid number to use
1178  * @pd_addr: address
1179  *
1180  * Update the page table base and flush the VM TLB
1181  * using sDMA.
1182  */
1183 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1184                                          unsigned vmid, uint64_t pd_addr)
1185 {
1186         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1187 }
1188
1189 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1190                                      uint32_t reg, uint32_t val)
1191 {
1192         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1193                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1194         amdgpu_ring_write(ring, reg);
1195         amdgpu_ring_write(ring, val);
1196 }
1197
1198 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1199                                          uint32_t val, uint32_t mask)
1200 {
1201         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1202                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1203                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1204         amdgpu_ring_write(ring, reg << 2);
1205         amdgpu_ring_write(ring, 0);
1206         amdgpu_ring_write(ring, val); /* reference */
1207         amdgpu_ring_write(ring, mask); /* mask */
1208         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1209                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1210 }
1211
1212 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1213                                                    uint32_t reg0, uint32_t reg1,
1214                                                    uint32_t ref, uint32_t mask)
1215 {
1216         amdgpu_ring_emit_wreg(ring, reg0, ref);
1217         /* wait for a cycle to reset vm_inv_eng*_ack */
1218         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1219         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1220 }
1221
1222 static int sdma_v5_2_early_init(void *handle)
1223 {
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225
1226         sdma_v5_2_set_ring_funcs(adev);
1227         sdma_v5_2_set_buffer_funcs(adev);
1228         sdma_v5_2_set_vm_pte_funcs(adev);
1229         sdma_v5_2_set_irq_funcs(adev);
1230
1231         return 0;
1232 }
1233
1234 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1235 {
1236         switch (seq_num) {
1237         case 0:
1238                 return SOC15_IH_CLIENTID_SDMA0;
1239         case 1:
1240                 return SOC15_IH_CLIENTID_SDMA1;
1241         case 2:
1242                 return SOC15_IH_CLIENTID_SDMA2;
1243         case 3:
1244                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1245         default:
1246                 break;
1247         }
1248         return -EINVAL;
1249 }
1250
1251 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1252 {
1253         switch (seq_num) {
1254         case 0:
1255                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1256         case 1:
1257                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1258         case 2:
1259                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1260         case 3:
1261                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1262         default:
1263                 break;
1264         }
1265         return -EINVAL;
1266 }
1267
1268 static int sdma_v5_2_sw_init(void *handle)
1269 {
1270         struct amdgpu_ring *ring;
1271         int r, i;
1272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1273
1274         /* SDMA trap event */
1275         for (i = 0; i < adev->sdma.num_instances; i++) {
1276                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1277                                       sdma_v5_2_seq_to_trap_id(i),
1278                                       &adev->sdma.trap_irq);
1279                 if (r)
1280                         return r;
1281         }
1282
1283         r = sdma_v5_2_init_microcode(adev);
1284         if (r) {
1285                 DRM_ERROR("Failed to load sdma firmware!\n");
1286                 return r;
1287         }
1288
1289         for (i = 0; i < adev->sdma.num_instances; i++) {
1290                 ring = &adev->sdma.instance[i].ring;
1291                 ring->ring_obj = NULL;
1292                 ring->use_doorbell = true;
1293                 ring->me = i;
1294
1295                 DRM_INFO("use_doorbell being set to: [%s]\n",
1296                                 ring->use_doorbell?"true":"false");
1297
1298                 ring->doorbell_index =
1299                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1300
1301                 sprintf(ring->name, "sdma%d", i);
1302                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1303                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1304                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1305                 if (r)
1306                         return r;
1307         }
1308
1309         return r;
1310 }
1311
1312 static int sdma_v5_2_sw_fini(void *handle)
1313 {
1314         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1315         int i;
1316
1317         for (i = 0; i < adev->sdma.num_instances; i++)
1318                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1319
1320         sdma_v5_2_destroy_inst_ctx(adev);
1321
1322         return 0;
1323 }
1324
1325 static int sdma_v5_2_hw_init(void *handle)
1326 {
1327         int r;
1328         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1329
1330         r = sdma_v5_2_start(adev);
1331
1332         return r;
1333 }
1334
1335 static int sdma_v5_2_hw_fini(void *handle)
1336 {
1337         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338
1339         if (amdgpu_sriov_vf(adev))
1340                 return 0;
1341
1342         sdma_v5_2_ctx_switch_enable(adev, false);
1343         sdma_v5_2_enable(adev, false);
1344
1345         return 0;
1346 }
1347
1348 static int sdma_v5_2_suspend(void *handle)
1349 {
1350         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351
1352         return sdma_v5_2_hw_fini(adev);
1353 }
1354
1355 static int sdma_v5_2_resume(void *handle)
1356 {
1357         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1358
1359         return sdma_v5_2_hw_init(adev);
1360 }
1361
1362 static bool sdma_v5_2_is_idle(void *handle)
1363 {
1364         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1365         u32 i;
1366
1367         for (i = 0; i < adev->sdma.num_instances; i++) {
1368                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1369
1370                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1371                         return false;
1372         }
1373
1374         return true;
1375 }
1376
1377 static int sdma_v5_2_wait_for_idle(void *handle)
1378 {
1379         unsigned i;
1380         u32 sdma0, sdma1, sdma2, sdma3;
1381         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1382
1383         for (i = 0; i < adev->usec_timeout; i++) {
1384                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1385                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1386                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1387                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1388
1389                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1390                         return 0;
1391                 udelay(1);
1392         }
1393         return -ETIMEDOUT;
1394 }
1395
1396 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1397 {
1398         int i, r = 0;
1399         struct amdgpu_device *adev = ring->adev;
1400         u32 index = 0;
1401         u64 sdma_gfx_preempt;
1402
1403         amdgpu_sdma_get_index_from_ring(ring, &index);
1404         sdma_gfx_preempt =
1405                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1406
1407         /* assert preemption condition */
1408         amdgpu_ring_set_preempt_cond_exec(ring, false);
1409
1410         /* emit the trailing fence */
1411         ring->trail_seq += 1;
1412         amdgpu_ring_alloc(ring, 10);
1413         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1414                                   ring->trail_seq, 0);
1415         amdgpu_ring_commit(ring);
1416
1417         /* assert IB preemption */
1418         WREG32(sdma_gfx_preempt, 1);
1419
1420         /* poll the trailing fence */
1421         for (i = 0; i < adev->usec_timeout; i++) {
1422                 if (ring->trail_seq ==
1423                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1424                         break;
1425                 udelay(1);
1426         }
1427
1428         if (i >= adev->usec_timeout) {
1429                 r = -EINVAL;
1430                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1431         }
1432
1433         /* deassert IB preemption */
1434         WREG32(sdma_gfx_preempt, 0);
1435
1436         /* deassert the preemption condition */
1437         amdgpu_ring_set_preempt_cond_exec(ring, true);
1438         return r;
1439 }
1440
1441 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1442                                         struct amdgpu_irq_src *source,
1443                                         unsigned type,
1444                                         enum amdgpu_interrupt_state state)
1445 {
1446         u32 sdma_cntl;
1447         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1448
1449         if (!amdgpu_sriov_vf(adev)) {
1450                 sdma_cntl = RREG32(reg_offset);
1451                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1452                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1453                 WREG32(reg_offset, sdma_cntl);
1454         }
1455
1456         return 0;
1457 }
1458
1459 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1460                                       struct amdgpu_irq_src *source,
1461                                       struct amdgpu_iv_entry *entry)
1462 {
1463         DRM_DEBUG("IH: SDMA trap\n");
1464         switch (entry->client_id) {
1465         case SOC15_IH_CLIENTID_SDMA0:
1466                 switch (entry->ring_id) {
1467                 case 0:
1468                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1469                         break;
1470                 case 1:
1471                         /* XXX compute */
1472                         break;
1473                 case 2:
1474                         /* XXX compute */
1475                         break;
1476                 case 3:
1477                         /* XXX page queue*/
1478                         break;
1479                 }
1480                 break;
1481         case SOC15_IH_CLIENTID_SDMA1:
1482                 switch (entry->ring_id) {
1483                 case 0:
1484                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1485                         break;
1486                 case 1:
1487                         /* XXX compute */
1488                         break;
1489                 case 2:
1490                         /* XXX compute */
1491                         break;
1492                 case 3:
1493                         /* XXX page queue*/
1494                         break;
1495                 }
1496                 break;
1497         case SOC15_IH_CLIENTID_SDMA2:
1498                 switch (entry->ring_id) {
1499                 case 0:
1500                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1501                         break;
1502                 case 1:
1503                         /* XXX compute */
1504                         break;
1505                 case 2:
1506                         /* XXX compute */
1507                         break;
1508                 case 3:
1509                         /* XXX page queue*/
1510                         break;
1511                 }
1512                 break;
1513         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1514                 switch (entry->ring_id) {
1515                 case 0:
1516                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1517                         break;
1518                 case 1:
1519                         /* XXX compute */
1520                         break;
1521                 case 2:
1522                         /* XXX compute */
1523                         break;
1524                 case 3:
1525                         /* XXX page queue*/
1526                         break;
1527                 }
1528                 break;
1529         }
1530         return 0;
1531 }
1532
1533 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1534                                               struct amdgpu_irq_src *source,
1535                                               struct amdgpu_iv_entry *entry)
1536 {
1537         return 0;
1538 }
1539
1540 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1541                                                        bool enable)
1542 {
1543         uint32_t data, def;
1544         int i;
1545
1546         for (i = 0; i < adev->sdma.num_instances; i++) {
1547
1548                 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1549                         adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1550
1551                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1552                         /* Enable sdma clock gating */
1553                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1554                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1555                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1556                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1557                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1558                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1559                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1560                         if (def != data)
1561                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1562                 } else {
1563                         /* Disable sdma clock gating */
1564                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1565                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1566                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1567                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1568                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1569                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1570                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1571                         if (def != data)
1572                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1573                 }
1574         }
1575 }
1576
1577 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1578                                                       bool enable)
1579 {
1580         uint32_t data, def;
1581         int i;
1582
1583         for (i = 0; i < adev->sdma.num_instances; i++) {
1584
1585                 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1586                         adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1587
1588                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1589                         /* Enable sdma mem light sleep */
1590                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1591                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1592                         if (def != data)
1593                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1594
1595                 } else {
1596                         /* Disable sdma mem light sleep */
1597                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1598                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1599                         if (def != data)
1600                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1601
1602                 }
1603         }
1604 }
1605
1606 static int sdma_v5_2_set_clockgating_state(void *handle,
1607                                            enum amd_clockgating_state state)
1608 {
1609         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1610
1611         if (amdgpu_sriov_vf(adev))
1612                 return 0;
1613
1614         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1615         case IP_VERSION(5, 2, 0):
1616         case IP_VERSION(5, 2, 2):
1617         case IP_VERSION(5, 2, 1):
1618         case IP_VERSION(5, 2, 4):
1619         case IP_VERSION(5, 2, 5):
1620         case IP_VERSION(5, 2, 3):
1621                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1622                                 state == AMD_CG_STATE_GATE);
1623                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1624                                 state == AMD_CG_STATE_GATE);
1625                 break;
1626         default:
1627                 break;
1628         }
1629
1630         return 0;
1631 }
1632
1633 static int sdma_v5_2_set_powergating_state(void *handle,
1634                                           enum amd_powergating_state state)
1635 {
1636         return 0;
1637 }
1638
1639 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1640 {
1641         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1642         int data;
1643
1644         if (amdgpu_sriov_vf(adev))
1645                 *flags = 0;
1646
1647         /* AMD_CG_SUPPORT_SDMA_LS */
1648         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1649         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1650                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1651 }
1652
1653 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1654         .name = "sdma_v5_2",
1655         .early_init = sdma_v5_2_early_init,
1656         .late_init = NULL,
1657         .sw_init = sdma_v5_2_sw_init,
1658         .sw_fini = sdma_v5_2_sw_fini,
1659         .hw_init = sdma_v5_2_hw_init,
1660         .hw_fini = sdma_v5_2_hw_fini,
1661         .suspend = sdma_v5_2_suspend,
1662         .resume = sdma_v5_2_resume,
1663         .is_idle = sdma_v5_2_is_idle,
1664         .wait_for_idle = sdma_v5_2_wait_for_idle,
1665         .soft_reset = sdma_v5_2_soft_reset,
1666         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1667         .set_powergating_state = sdma_v5_2_set_powergating_state,
1668         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1669 };
1670
1671 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1672         .type = AMDGPU_RING_TYPE_SDMA,
1673         .align_mask = 0xf,
1674         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1675         .support_64bit_ptrs = true,
1676         .vmhub = AMDGPU_GFXHUB_0,
1677         .get_rptr = sdma_v5_2_ring_get_rptr,
1678         .get_wptr = sdma_v5_2_ring_get_wptr,
1679         .set_wptr = sdma_v5_2_ring_set_wptr,
1680         .emit_frame_size =
1681                 5 + /* sdma_v5_2_ring_init_cond_exec */
1682                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1683                 3 + /* hdp_invalidate */
1684                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1685                 /* sdma_v5_2_ring_emit_vm_flush */
1686                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1687                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1688                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1689         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1690         .emit_ib = sdma_v5_2_ring_emit_ib,
1691         .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1692         .emit_fence = sdma_v5_2_ring_emit_fence,
1693         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1694         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1695         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1696         .test_ring = sdma_v5_2_ring_test_ring,
1697         .test_ib = sdma_v5_2_ring_test_ib,
1698         .insert_nop = sdma_v5_2_ring_insert_nop,
1699         .pad_ib = sdma_v5_2_ring_pad_ib,
1700         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1701         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1702         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1703         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1704         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1705         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1706 };
1707
1708 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1709 {
1710         int i;
1711
1712         for (i = 0; i < adev->sdma.num_instances; i++) {
1713                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1714                 adev->sdma.instance[i].ring.me = i;
1715         }
1716 }
1717
1718 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1719         .set = sdma_v5_2_set_trap_irq_state,
1720         .process = sdma_v5_2_process_trap_irq,
1721 };
1722
1723 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1724         .process = sdma_v5_2_process_illegal_inst_irq,
1725 };
1726
1727 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1728 {
1729         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1730                                         adev->sdma.num_instances;
1731         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1732         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1733 }
1734
1735 /**
1736  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1737  *
1738  * @ib: indirect buffer to copy to
1739  * @src_offset: src GPU address
1740  * @dst_offset: dst GPU address
1741  * @byte_count: number of bytes to xfer
1742  * @tmz: if a secure copy should be used
1743  *
1744  * Copy GPU buffers using the DMA engine.
1745  * Used by the amdgpu ttm implementation to move pages if
1746  * registered as the asic copy callback.
1747  */
1748 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1749                                        uint64_t src_offset,
1750                                        uint64_t dst_offset,
1751                                        uint32_t byte_count,
1752                                        bool tmz)
1753 {
1754         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1755                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1756                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1757         ib->ptr[ib->length_dw++] = byte_count - 1;
1758         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1759         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1760         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1761         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1762         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1763 }
1764
1765 /**
1766  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1767  *
1768  * @ib: indirect buffer to fill
1769  * @src_data: value to write to buffer
1770  * @dst_offset: dst GPU address
1771  * @byte_count: number of bytes to xfer
1772  *
1773  * Fill GPU buffers using the DMA engine.
1774  */
1775 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1776                                        uint32_t src_data,
1777                                        uint64_t dst_offset,
1778                                        uint32_t byte_count)
1779 {
1780         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1781         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1782         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1783         ib->ptr[ib->length_dw++] = src_data;
1784         ib->ptr[ib->length_dw++] = byte_count - 1;
1785 }
1786
1787 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1788         .copy_max_bytes = 0x400000,
1789         .copy_num_dw = 7,
1790         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1791
1792         .fill_max_bytes = 0x400000,
1793         .fill_num_dw = 5,
1794         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1795 };
1796
1797 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1798 {
1799         if (adev->mman.buffer_funcs == NULL) {
1800                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1801                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1802         }
1803 }
1804
1805 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1806         .copy_pte_num_dw = 7,
1807         .copy_pte = sdma_v5_2_vm_copy_pte,
1808         .write_pte = sdma_v5_2_vm_write_pte,
1809         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1810 };
1811
1812 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1813 {
1814         unsigned i;
1815
1816         if (adev->vm_manager.vm_pte_funcs == NULL) {
1817                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1818                 for (i = 0; i < adev->sdma.num_instances; i++) {
1819                         adev->vm_manager.vm_pte_scheds[i] =
1820                                 &adev->sdma.instance[i].ring.sched;
1821                 }
1822                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1823         }
1824 }
1825
1826 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1827         .type = AMD_IP_BLOCK_TYPE_SDMA,
1828         .major = 5,
1829         .minor = 2,
1830         .rev = 0,
1831         .funcs = &sdma_v5_2_ip_funcs,
1832 };