drivers/usb/chipidea/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - ChipIdea USB IP core family device controller
   4  *
   5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   6  *
   7  * Author: David Lopo
   8  */
   9
  10 /*
  11  * Description: ChipIdea USB IP core family device controller
  12  *
  13  * This driver is composed of several blocks:
  14  * - HW:     hardware interface
  15  * - DBG:    debug facilities (optional)
  16  * - UTIL:   utilities
  17  * - ISR:    interrupts handling
  18  * - ENDPT:  endpoint operations (Gadget API)
  19  * - GADGET: gadget operations (Gadget API)
  20  * - BUS:    bus glue code, bus abstraction layer
  21  *
  22  * Compile Options
  23  * - STALL_IN:  non-empty bulk-in pipes cannot be halted
  24  *              if defined mass storage compliance succeeds but with warnings
  25  *              => case 4: Hi >  Dn
  26  *              => case 5: Hi >  Di
  27  *              => case 8: Hi <> Do
  28  *              if undefined usbtest 13 fails
  29  * - TRACE:     enable function tracing (depends on DEBUG)
  30  *
  31  * Main Features
  32  * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  33  * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  34  * - Normal & LPM support
  35  *
  36  * USBTEST Report
  37  * - OK: 0-12, 13 (STALL_IN defined) & 14
  38  * - Not Supported: 15 & 16 (ISO)
  39  *
  40  * TODO List
  41  * - Suspend & Remote Wakeup
  42  */
  43 #include <linux/delay.h>
  44 #include <linux/device.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/extcon.h>
  47 #include <linux/phy/phy.h>
  48 #include <linux/platform_device.h>
  49 #include <linux/module.h>
  50 #include <linux/idr.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/io.h>
  53 #include <linux/kernel.h>
  54 #include <linux/slab.h>
  55 #include <linux/pm_runtime.h>
  56 #include <linux/usb/ch9.h>
  57 #include <linux/usb/gadget.h>
  58 #include <linux/usb/otg.h>
  59 #include <linux/usb/chipidea.h>
  60 #include <linux/usb/of.h>
  61 #include <linux/of.h>
  62 #include <linux/regulator/consumer.h>
  63 #include <linux/usb/ehci_def.h>
  64
  65 #include "ci.h"
  66 #include "udc.h"
  67 #include "bits.h"
  68 #include "host.h"
  69 #include "otg.h"
  70 #include "otg_fsm.h"
  71
  72 /* Controller register map */
  73 static const u8 ci_regs_nolpm[] = {
  74         [CAP_CAPLENGTH]         = 0x00U,
  75         [CAP_HCCPARAMS]         = 0x08U,
  76         [CAP_DCCPARAMS]         = 0x24U,
  77         [CAP_TESTMODE]          = 0x38U,
  78         [OP_USBCMD]             = 0x00U,
  79         [OP_USBSTS]             = 0x04U,
  80         [OP_USBINTR]            = 0x08U,
  81         [OP_DEVICEADDR]         = 0x14U,
  82         [OP_ENDPTLISTADDR]      = 0x18U,
  83         [OP_TTCTRL]             = 0x1CU,
  84         [OP_BURSTSIZE]          = 0x20U,
  85         [OP_ULPI_VIEWPORT]      = 0x30U,
  86         [OP_PORTSC]             = 0x44U,
  87         [OP_DEVLC]              = 0x84U,
  88         [OP_OTGSC]              = 0x64U,
  89         [OP_USBMODE]            = 0x68U,
  90         [OP_ENDPTSETUPSTAT]     = 0x6CU,
  91         [OP_ENDPTPRIME]         = 0x70U,
  92         [OP_ENDPTFLUSH]         = 0x74U,
  93         [OP_ENDPTSTAT]          = 0x78U,
  94         [OP_ENDPTCOMPLETE]      = 0x7CU,
  95         [OP_ENDPTCTRL]          = 0x80U,
  96 };
  97
  98 static const u8 ci_regs_lpm[] = {
  99         [CAP_CAPLENGTH]         = 0x00U,
 100         [CAP_HCCPARAMS]         = 0x08U,
 101         [CAP_DCCPARAMS]         = 0x24U,
 102         [CAP_TESTMODE]          = 0xFCU,
 103         [OP_USBCMD]             = 0x00U,
 104         [OP_USBSTS]             = 0x04U,
 105         [OP_USBINTR]            = 0x08U,
 106         [OP_DEVICEADDR]         = 0x14U,
 107         [OP_ENDPTLISTADDR]      = 0x18U,
 108         [OP_TTCTRL]             = 0x1CU,
 109         [OP_BURSTSIZE]          = 0x20U,
 110         [OP_ULPI_VIEWPORT]      = 0x30U,
 111         [OP_PORTSC]             = 0x44U,
 112         [OP_DEVLC]              = 0x84U,
 113         [OP_OTGSC]              = 0xC4U,
 114         [OP_USBMODE]            = 0xC8U,
 115         [OP_ENDPTSETUPSTAT]     = 0xD8U,
 116         [OP_ENDPTPRIME]         = 0xDCU,
 117         [OP_ENDPTFLUSH]         = 0xE0U,
 118         [OP_ENDPTSTAT]          = 0xE4U,
 119         [OP_ENDPTCOMPLETE]      = 0xE8U,
 120         [OP_ENDPTCTRL]          = 0xECU,
 121 };
 122
 123 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
 124 {
 125         int i;
 126
 127         for (i = 0; i < OP_ENDPTCTRL; i++)
 128                 ci->hw_bank.regmap[i] =
 129                         (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
 130                         (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
 131
 132         for (; i <= OP_LAST; i++)
 133                 ci->hw_bank.regmap[i] = ci->hw_bank.op +
 134                         4 * (i - OP_ENDPTCTRL) +
 135                         (is_lpm
 136                          ? ci_regs_lpm[OP_ENDPTCTRL]
 137                          : ci_regs_nolpm[OP_ENDPTCTRL]);
 138
 139 }
 140
 141 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
 142 {
 143         int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
 144         enum ci_revision rev = CI_REVISION_UNKNOWN;
 145
 146         if (ver == 0x2) {
 147                 rev = hw_read_id_reg(ci, ID_ID, REVISION)
 148                         >> __ffs(REVISION);
 149                 rev += CI_REVISION_20;
 150         } else if (ver == 0x0) {
 151                 rev = CI_REVISION_1X;
 152         }
 153
 154         return rev;
 155 }
 156
 157 /**
 158  * hw_read_intr_enable: returns interrupt enable register
 159  *
 160  * @ci: the controller
 161  *
 162  * This function returns register data
 163  */
 164 u32 hw_read_intr_enable(struct ci_hdrc *ci)
 165 {
 166         return hw_read(ci, OP_USBINTR, ~0);
 167 }
 168
 169 /**
 170  * hw_read_intr_status: returns interrupt status register
 171  *
 172  * @ci: the controller
 173  *
 174  * This function returns register data
 175  */
 176 u32 hw_read_intr_status(struct ci_hdrc *ci)
 177 {
 178         return hw_read(ci, OP_USBSTS, ~0);
 179 }
 180
 181 /**
 182  * hw_port_test_set: writes port test mode (execute without interruption)
 183  * @mode: new value
 184  *
 185  * This function returns an error code
 186  */
 187 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
 188 {
 189         const u8 TEST_MODE_MAX = 7;
 190
 191         if (mode > TEST_MODE_MAX)
 192                 return -EINVAL;
 193
 194         hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
 195         return 0;
 196 }
 197
 198 /**
 199  * hw_port_test_get: reads port test mode value
 200  *
 201  * @ci: the controller
 202  *
 203  * This function returns port test mode value
 204  */
 205 u8 hw_port_test_get(struct ci_hdrc *ci)
 206 {
 207         return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
 208 }
 209
 210 static void hw_wait_phy_stable(void)
 211 {
 212         /*
 213          * The phy needs some delay to output the stable status from low
 214          * power mode. And for OTGSC, the status inputs are debounced
 215          * using a 1 ms time constant, so, delay 2ms for controller to get
 216          * the stable status, like vbus and id when the phy leaves low power.
 217          */
 218         usleep_range(2000, 2500);
 219 }
 220
 221 /* The PHY enters/leaves low power mode */
 222 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
 223 {
 224         enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
 225         bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
 226
 227         if (enable && !lpm)
 228                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 229                                 PORTSC_PHCD(ci->hw_bank.lpm));
 230         else if (!enable && lpm)
 231                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 232                                 0);
 233 }
 234
 235 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
 236 {
 237         u32 reg;
 238
 239         /* bank is a module variable */
 240         ci->hw_bank.abs = base;
 241
 242         ci->hw_bank.cap = ci->hw_bank.abs;
 243         ci->hw_bank.cap += ci->platdata->capoffset;
 244         ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
 245
 246         hw_alloc_regmap(ci, false);
 247         reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
 248                 __ffs(HCCPARAMS_LEN);
 249         ci->hw_bank.lpm  = reg;
 250         if (reg)
 251                 hw_alloc_regmap(ci, !!reg);
 252         ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
 253         ci->hw_bank.size += OP_LAST;
 254         ci->hw_bank.size /= sizeof(u32);
 255
 256         reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
 257                 __ffs(DCCPARAMS_DEN);
 258         ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
 259
 260         if (ci->hw_ep_max > ENDPT_MAX)
 261                 return -ENODEV;
 262
 263         ci_hdrc_enter_lpm(ci, false);
 264
 265         /* Disable all interrupts bits */
 266         hw_write(ci, OP_USBINTR, 0xffffffff, 0);
 267
 268         /* Clear all interrupts status bits*/
 269         hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
 270
 271         ci->rev = ci_get_revision(ci);
 272
 273         dev_dbg(ci->dev,
 274                 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
 275                 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
 276
 277         /* setup lock mode ? */
 278
 279         /* ENDPTSETUPSTAT is '0' by default */
 280
 281         /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
 282
 283         return 0;
 284 }
 285
 286 void hw_phymode_configure(struct ci_hdrc *ci)
 287 {
 288         u32 portsc, lpm, sts = 0;
 289
 290         switch (ci->platdata->phy_mode) {
 291         case USBPHY_INTERFACE_MODE_UTMI:
 292                 portsc = PORTSC_PTS(PTS_UTMI);
 293                 lpm = DEVLC_PTS(PTS_UTMI);
 294                 break;
 295         case USBPHY_INTERFACE_MODE_UTMIW:
 296                 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
 297                 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
 298                 break;
 299         case USBPHY_INTERFACE_MODE_ULPI:
 300                 portsc = PORTSC_PTS(PTS_ULPI);
 301                 lpm = DEVLC_PTS(PTS_ULPI);
 302                 break;
 303         case USBPHY_INTERFACE_MODE_SERIAL:
 304                 portsc = PORTSC_PTS(PTS_SERIAL);
 305                 lpm = DEVLC_PTS(PTS_SERIAL);
 306                 sts = 1;
 307                 break;
 308         case USBPHY_INTERFACE_MODE_HSIC:
 309                 portsc = PORTSC_PTS(PTS_HSIC);
 310                 lpm = DEVLC_PTS(PTS_HSIC);
 311                 break;
 312         default:
 313                 return;
 314         }
 315
 316         if (ci->hw_bank.lpm) {
 317                 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
 318                 if (sts)
 319                         hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
 320         } else {
 321                 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
 322                 if (sts)
 323                         hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
 324         }
 325 }
 326 EXPORT_SYMBOL_GPL(hw_phymode_configure);
 327
 328 /**
 329  * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
 330  * interfaces
 331  * @ci: the controller
 332  *
 333  * This function returns an error code if the phy failed to init
 334  */
 335 static int _ci_usb_phy_init(struct ci_hdrc *ci)
 336 {
 337         int ret;
 338
 339         if (ci->phy) {
 340                 ret = phy_init(ci->phy);
 341                 if (ret)
 342                         return ret;
 343
 344                 ret = phy_power_on(ci->phy);
 345                 if (ret) {
 346                         phy_exit(ci->phy);
 347                         return ret;
 348                 }
 349         } else {
 350                 ret = usb_phy_init(ci->usb_phy);
 351         }
 352
 353         return ret;
 354 }
 355
 356 /**
 357  * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
 358  * interfaces
 359  * @ci: the controller
 360  */
 361 static void ci_usb_phy_exit(struct ci_hdrc *ci)
 362 {
 363         if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
 364                 return;
 365
 366         if (ci->phy) {
 367                 phy_power_off(ci->phy);
 368                 phy_exit(ci->phy);
 369         } else {
 370                 usb_phy_shutdown(ci->usb_phy);
 371         }
 372 }
 373
 374 /**
 375  * ci_usb_phy_init: initialize phy according to different phy type
 376  * @ci: the controller
 377  *
 378  * This function returns an error code if usb_phy_init has failed
 379  */
 380 static int ci_usb_phy_init(struct ci_hdrc *ci)
 381 {
 382         int ret;
 383
 384         if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
 385                 return 0;
 386
 387         switch (ci->platdata->phy_mode) {
 388         case USBPHY_INTERFACE_MODE_UTMI:
 389         case USBPHY_INTERFACE_MODE_UTMIW:
 390         case USBPHY_INTERFACE_MODE_HSIC:
 391                 ret = _ci_usb_phy_init(ci);
 392                 if (!ret)
 393                         hw_wait_phy_stable();
 394                 else
 395                         return ret;
 396                 hw_phymode_configure(ci);
 397                 break;
 398         case USBPHY_INTERFACE_MODE_ULPI:
 399         case USBPHY_INTERFACE_MODE_SERIAL:
 400                 hw_phymode_configure(ci);
 401                 ret = _ci_usb_phy_init(ci);
 402                 if (ret)
 403                         return ret;
 404                 break;
 405         default:
 406                 ret = _ci_usb_phy_init(ci);
 407                 if (!ret)
 408                         hw_wait_phy_stable();
 409         }
 410
 411         return ret;
 412 }
 413
 414
 415 /**
 416  * ci_platform_configure: do controller configure
 417  * @ci: the controller
 418  *
 419  */
 420 void ci_platform_configure(struct ci_hdrc *ci)
 421 {
 422         bool is_device_mode, is_host_mode;
 423
 424         is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
 425         is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
 426
 427         if (is_device_mode) {
 428                 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
 429
 430                 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
 431                         hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
 432                                  USBMODE_CI_SDIS);
 433         }
 434
 435         if (is_host_mode) {
 436                 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
 437
 438                 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
 439                         hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
 440                                  USBMODE_CI_SDIS);
 441         }
 442
 443         if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
 444                 if (ci->hw_bank.lpm)
 445                         hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
 446                 else
 447                         hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
 448         }
 449
 450         if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
 451                 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
 452
 453         hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
 454
 455         if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
 456                 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
 457                         ci->platdata->ahb_burst_config);
 458
 459         /* override burst size, take effect only when ahb_burst_config is 0 */
 460         if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
 461                 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
 462                         hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
 463                         ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
 464
 465                 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
 466                         hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
 467                                 ci->platdata->rx_burst_size);
 468         }
 469 }
 470
 471 /**
 472  * hw_controller_reset: do controller reset
 473  * @ci: the controller
 474   *
 475  * This function returns an error code
 476  */
 477 static int hw_controller_reset(struct ci_hdrc *ci)
 478 {
 479         int count = 0;
 480
 481         hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
 482         while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
 483                 udelay(10);
 484                 if (count++ > 1000)
 485                         return -ETIMEDOUT;
 486         }
 487
 488         return 0;
 489 }
 490
 491 /**
 492  * hw_device_reset: resets chip (execute without interruption)
 493  * @ci: the controller
 494  *
 495  * This function returns an error code
 496  */
 497 int hw_device_reset(struct ci_hdrc *ci)
 498 {
 499         int ret;
 500
 501         /* should flush & stop before reset */
 502         hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
 503         hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
 504
 505         ret = hw_controller_reset(ci);
 506         if (ret) {
 507                 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
 508                 return ret;
 509         }
 510
 511         if (ci->platdata->notify_event) {
 512                 ret = ci->platdata->notify_event(ci,
 513                         CI_HDRC_CONTROLLER_RESET_EVENT);
 514                 if (ret)
 515                         return ret;
 516         }
 517
 518         /* USBMODE should be configured step by step */
 519         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
 520         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
 521         /* HW >= 2.3 */
 522         hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
 523
 524         if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
 525                 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
 526                 pr_err("lpm = %i", ci->hw_bank.lpm);
 527                 return -ENODEV;
 528         }
 529
 530         ci_platform_configure(ci);
 531
 532         return 0;
 533 }
 534
 535 static irqreturn_t ci_irq(int irq, void *data)
 536 {
 537         struct ci_hdrc *ci = data;
 538         irqreturn_t ret = IRQ_NONE;
 539         u32 otgsc = 0;
 540
 541         if (ci->in_lpm) {
 542                 disable_irq_nosync(irq);
 543                 ci->wakeup_int = true;
 544                 pm_runtime_get(ci->dev);
 545                 return IRQ_HANDLED;
 546         }
 547
 548         if (ci->is_otg) {
 549                 otgsc = hw_read_otgsc(ci, ~0);
 550                 if (ci_otg_is_fsm_mode(ci)) {
 551                         ret = ci_otg_fsm_irq(ci);
 552                         if (ret == IRQ_HANDLED)
 553                                 return ret;
 554                 }
 555         }
 556
 557         /*
 558          * Handle id change interrupt, it indicates device/host function
 559          * switch.
 560          */
 561         if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
 562                 ci->id_event = true;
 563                 /* Clear ID change irq status */
 564                 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
 565                 ci_otg_queue_work(ci);
 566                 return IRQ_HANDLED;
 567         }
 568
 569         /*
 570          * Handle vbus change interrupt, it indicates device connection
 571          * and disconnection events.
 572          */
 573         if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
 574                 ci->b_sess_valid_event = true;
 575                 /* Clear BSV irq */
 576                 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
 577                 ci_otg_queue_work(ci);
 578                 return IRQ_HANDLED;
 579         }
 580
 581         /* Handle device/host interrupt */
 582         if (ci->role != CI_ROLE_END)
 583                 ret = ci_role(ci)->irq(ci);
 584
 585         return ret;
 586 }
 587
 588 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
 589                              void *ptr)
 590 {
 591         struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
 592         struct ci_hdrc *ci = cbl->ci;
 593
 594         cbl->connected = event;
 595         cbl->changed = true;
 596
 597         ci_irq(ci->irq, ci);
 598         return NOTIFY_DONE;
 599 }
 600
 601 static int ci_get_platdata(struct device *dev,
 602                 struct ci_hdrc_platform_data *platdata)
 603 {
 604         struct extcon_dev *ext_vbus, *ext_id;
 605         struct ci_hdrc_cable *cable;
 606         int ret;
 607
 608         if (!platdata->phy_mode)
 609                 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
 610
 611         if (!platdata->dr_mode)
 612                 platdata->dr_mode = usb_get_dr_mode(dev);
 613
 614         if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
 615                 platdata->dr_mode = USB_DR_MODE_OTG;
 616
 617         if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
 618                 /* Get the vbus regulator */
 619                 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
 620                 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
 621                         return -EPROBE_DEFER;
 622                 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
 623                         /* no vbus regulator is needed */
 624                         platdata->reg_vbus = NULL;
 625                 } else if (IS_ERR(platdata->reg_vbus)) {
 626                         dev_err(dev, "Getting regulator error: %ld\n",
 627                                 PTR_ERR(platdata->reg_vbus));
 628                         return PTR_ERR(platdata->reg_vbus);
 629                 }
 630                 /* Get TPL support */
 631                 if (!platdata->tpl_support)
 632                         platdata->tpl_support =
 633                                 of_usb_host_tpl_support(dev->of_node);
 634         }
 635
 636         if (platdata->dr_mode == USB_DR_MODE_OTG) {
 637                 /* We can support HNP and SRP of OTG 2.0 */
 638                 platdata->ci_otg_caps.otg_rev = 0x0200;
 639                 platdata->ci_otg_caps.hnp_support = true;
 640                 platdata->ci_otg_caps.srp_support = true;
 641
 642                 /* Update otg capabilities by DT properties */
 643                 ret = of_usb_update_otg_caps(dev->of_node,
 644                                         &platdata->ci_otg_caps);
 645                 if (ret)
 646                         return ret;
 647         }
 648
 649         if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
 650                 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
 651
 652         of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
 653                                      &platdata->phy_clkgate_delay_us);
 654
 655         platdata->itc_setting = 1;
 656
 657         of_property_read_u32(dev->of_node, "itc-setting",
 658                                         &platdata->itc_setting);
 659
 660         ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
 661                                 &platdata->ahb_burst_config);
 662         if (!ret) {
 663                 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
 664         } else if (ret != -EINVAL) {
 665                 dev_err(dev, "failed to get ahb-burst-config\n");
 666                 return ret;
 667         }
 668
 669         ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
 670                                 &platdata->tx_burst_size);
 671         if (!ret) {
 672                 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
 673         } else if (ret != -EINVAL) {
 674                 dev_err(dev, "failed to get tx-burst-size-dword\n");
 675                 return ret;
 676         }
 677
 678         ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
 679                                 &platdata->rx_burst_size);
 680         if (!ret) {
 681                 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
 682         } else if (ret != -EINVAL) {
 683                 dev_err(dev, "failed to get rx-burst-size-dword\n");
 684                 return ret;
 685         }
 686
 687         if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
 688                 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
 689
 690         ext_id = ERR_PTR(-ENODEV);
 691         ext_vbus = ERR_PTR(-ENODEV);
 692         if (of_property_read_bool(dev->of_node, "extcon")) {
 693                 /* Each one of them is not mandatory */
 694                 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
 695                 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
 696                         return PTR_ERR(ext_vbus);
 697
 698                 ext_id = extcon_get_edev_by_phandle(dev, 1);
 699                 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
 700                         return PTR_ERR(ext_id);
 701         }
 702
 703         cable = &platdata->vbus_extcon;
 704         cable->nb.notifier_call = ci_cable_notifier;
 705         cable->edev = ext_vbus;
 706
 707         if (!IS_ERR(ext_vbus)) {
 708                 ret = extcon_get_state(cable->edev, EXTCON_USB);
 709                 if (ret)
 710                         cable->connected = true;
 711                 else
 712                         cable->connected = false;
 713         }
 714
 715         cable = &platdata->id_extcon;
 716         cable->nb.notifier_call = ci_cable_notifier;
 717         cable->edev = ext_id;
 718
 719         if (!IS_ERR(ext_id)) {
 720                 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
 721                 if (ret)
 722                         cable->connected = true;
 723                 else
 724                         cable->connected = false;
 725         }
 726         return 0;
 727 }
 728
 729 static int ci_extcon_register(struct ci_hdrc *ci)
 730 {
 731         struct ci_hdrc_cable *id, *vbus;
 732         int ret;
 733
 734         id = &ci->platdata->id_extcon;
 735         id->ci = ci;
 736         if (!IS_ERR_OR_NULL(id->edev)) {
 737                 ret = devm_extcon_register_notifier(ci->dev, id->edev,
 738                                                 EXTCON_USB_HOST, &id->nb);
 739                 if (ret < 0) {
 740                         dev_err(ci->dev, "register ID failed\n");
 741                         return ret;
 742                 }
 743         }
 744
 745         vbus = &ci->platdata->vbus_extcon;
 746         vbus->ci = ci;
 747         if (!IS_ERR_OR_NULL(vbus->edev)) {
 748                 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
 749                                                 EXTCON_USB, &vbus->nb);
 750                 if (ret < 0) {
 751                         dev_err(ci->dev, "register VBUS failed\n");
 752                         return ret;
 753                 }
 754         }
 755
 756         return 0;
 757 }
 758
 759 static DEFINE_IDA(ci_ida);
 760
 761 struct platform_device *ci_hdrc_add_device(struct device *dev,
 762                         struct resource *res, int nres,
 763                         struct ci_hdrc_platform_data *platdata)
 764 {
 765         struct platform_device *pdev;
 766         int id, ret;
 767
 768         ret = ci_get_platdata(dev, platdata);
 769         if (ret)
 770                 return ERR_PTR(ret);
 771
 772         id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
 773         if (id < 0)
 774                 return ERR_PTR(id);
 775
 776         pdev = platform_device_alloc("ci_hdrc", id);
 777         if (!pdev) {
 778                 ret = -ENOMEM;
 779                 goto put_id;
 780         }
 781
 782         pdev->dev.parent = dev;
 783
 784         ret = platform_device_add_resources(pdev, res, nres);
 785         if (ret)
 786                 goto err;
 787
 788         ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
 789         if (ret)
 790                 goto err;
 791
 792         ret = platform_device_add(pdev);
 793         if (ret)
 794                 goto err;
 795
 796         return pdev;
 797
 798 err:
 799         platform_device_put(pdev);
 800 put_id:
 801         ida_simple_remove(&ci_ida, id);
 802         return ERR_PTR(ret);
 803 }
 804 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
 805
 806 void ci_hdrc_remove_device(struct platform_device *pdev)
 807 {
 808         int id = pdev->id;
 809         platform_device_unregister(pdev);
 810         ida_simple_remove(&ci_ida, id);
 811 }
 812 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
 813
 814 static inline void ci_role_destroy(struct ci_hdrc *ci)
 815 {
 816         ci_hdrc_gadget_destroy(ci);
 817         ci_hdrc_host_destroy(ci);
 818         if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
 819                 ci_hdrc_otg_destroy(ci);
 820 }
 821
 822 static void ci_get_otg_capable(struct ci_hdrc *ci)
 823 {
 824         if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
 825                 ci->is_otg = false;
 826         else
 827                 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
 828                                 DCCPARAMS_DC | DCCPARAMS_HC)
 829                                         == (DCCPARAMS_DC | DCCPARAMS_HC));
 830         if (ci->is_otg) {
 831                 dev_dbg(ci->dev, "It is OTG capable controller\n");
 832                 /* Disable and clear all OTG irq */
 833                 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
 834                                                         OTGSC_INT_STATUS_BITS);
 835         }
 836 }
 837
 838 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
 839                           char *buf)
 840 {
 841         struct ci_hdrc *ci = dev_get_drvdata(dev);
 842
 843         if (ci->role != CI_ROLE_END)
 844                 return sprintf(buf, "%s\n", ci_role(ci)->name);
 845
 846         return 0;
 847 }
 848
 849 static ssize_t role_store(struct device *dev,
 850                 struct device_attribute *attr, const char *buf, size_t n)
 851 {
 852         struct ci_hdrc *ci = dev_get_drvdata(dev);
 853         enum ci_role role;
 854         int ret;
 855
 856         if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
 857                 dev_warn(dev, "Current configuration is not dual-role, quit\n");
 858                 return -EPERM;
 859         }
 860
 861         for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
 862                 if (!strncmp(buf, ci->roles[role]->name,
 863                              strlen(ci->roles[role]->name)))
 864                         break;
 865
 866         if (role == CI_ROLE_END || role == ci->role)
 867                 return -EINVAL;
 868
 869         pm_runtime_get_sync(dev);
 870         disable_irq(ci->irq);
 871         ci_role_stop(ci);
 872         ret = ci_role_start(ci, role);
 873         if (!ret && ci->role == CI_ROLE_GADGET)
 874                 ci_handle_vbus_change(ci);
 875         enable_irq(ci->irq);
 876         pm_runtime_put_sync(dev);
 877
 878         return (ret == 0) ? n : ret;
 879 }
 880 static DEVICE_ATTR_RW(role);
 881
 882 static struct attribute *ci_attrs[] = {
 883         &dev_attr_role.attr,
 884         NULL,
 885 };
 886
 887 static const struct attribute_group ci_attr_group = {
 888         .attrs = ci_attrs,
 889 };
 890
 891 static int ci_hdrc_probe(struct platform_device *pdev)
 892 {
 893         struct device   *dev = &pdev->dev;
 894         struct ci_hdrc  *ci;
 895         struct resource *res;
 896         void __iomem    *base;
 897         int             ret;
 898         enum usb_dr_mode dr_mode;
 899
 900         if (!dev_get_platdata(dev)) {
 901                 dev_err(dev, "platform data missing\n");
 902                 return -ENODEV;
 903         }
 904
 905         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 906         base = devm_ioremap_resource(dev, res);
 907         if (IS_ERR(base))
 908                 return PTR_ERR(base);
 909
 910         ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
 911         if (!ci)
 912                 return -ENOMEM;
 913
 914         spin_lock_init(&ci->lock);
 915         ci->dev = dev;
 916         ci->platdata = dev_get_platdata(dev);
 917         ci->imx28_write_fix = !!(ci->platdata->flags &
 918                 CI_HDRC_IMX28_WRITE_FIX);
 919         ci->supports_runtime_pm = !!(ci->platdata->flags &
 920                 CI_HDRC_SUPPORTS_RUNTIME_PM);
 921         platform_set_drvdata(pdev, ci);
 922
 923         ret = hw_device_init(ci, base);
 924         if (ret < 0) {
 925                 dev_err(dev, "can't initialize hardware\n");
 926                 return -ENODEV;
 927         }
 928
 929         ret = ci_ulpi_init(ci);
 930         if (ret)
 931                 return ret;
 932
 933         if (ci->platdata->phy) {
 934                 ci->phy = ci->platdata->phy;
 935         } else if (ci->platdata->usb_phy) {
 936                 ci->usb_phy = ci->platdata->usb_phy;
 937         } else {
 938                 ci->phy = devm_phy_get(dev->parent, "usb-phy");
 939                 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
 940
 941                 /* if both generic PHY and USB PHY layers aren't enabled */
 942                 if (PTR_ERR(ci->phy) == -ENOSYS &&
 943                                 PTR_ERR(ci->usb_phy) == -ENXIO) {
 944                         ret = -ENXIO;
 945                         goto ulpi_exit;
 946                 }
 947
 948                 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) {
 949                         ret = -EPROBE_DEFER;
 950                         goto ulpi_exit;
 951                 }
 952
 953                 if (IS_ERR(ci->phy))
 954                         ci->phy = NULL;
 955                 else if (IS_ERR(ci->usb_phy))
 956                         ci->usb_phy = NULL;
 957         }
 958
 959         ret = ci_usb_phy_init(ci);
 960         if (ret) {
 961                 dev_err(dev, "unable to init phy: %d\n", ret);
 962                 return ret;
 963         }
 964
 965         ci->hw_bank.phys = res->start;
 966
 967         ci->irq = platform_get_irq(pdev, 0);
 968         if (ci->irq < 0) {
 969                 dev_err(dev, "missing IRQ\n");
 970                 ret = ci->irq;
 971                 goto deinit_phy;
 972         }
 973
 974         ci_get_otg_capable(ci);
 975
 976         dr_mode = ci->platdata->dr_mode;
 977         /* initialize role(s) before the interrupt is requested */
 978         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
 979                 ret = ci_hdrc_host_init(ci);
 980                 if (ret) {
 981                         if (ret == -ENXIO)
 982                                 dev_info(dev, "doesn't support host\n");
 983                         else
 984                                 goto deinit_phy;
 985                 }
 986         }
 987
 988         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
 989                 ret = ci_hdrc_gadget_init(ci);
 990                 if (ret) {
 991                         if (ret == -ENXIO)
 992                                 dev_info(dev, "doesn't support gadget\n");
 993                         else
 994                                 goto deinit_host;
 995                 }
 996         }
 997
 998         if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
 999                 dev_err(dev, "no supported roles\n");
1000                 ret = -ENODEV;
1001                 goto deinit_gadget;
1002         }
1003
1004         if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1005                 ret = ci_hdrc_otg_init(ci);
1006                 if (ret) {
1007                         dev_err(dev, "init otg fails, ret = %d\n", ret);
1008                         goto deinit_gadget;
1009                 }
1010         }
1011
1012         if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1013                 if (ci->is_otg) {
1014                         ci->role = ci_otg_role(ci);
1015                         /* Enable ID change irq */
1016                         hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1017                 } else {
1018                         /*
1019                          * If the controller is not OTG capable, but support
1020                          * role switch, the defalt role is gadget, and the
1021                          * user can switch it through debugfs.
1022                          */
1023                         ci->role = CI_ROLE_GADGET;
1024                 }
1025         } else {
1026                 ci->role = ci->roles[CI_ROLE_HOST]
1027                         ? CI_ROLE_HOST
1028                         : CI_ROLE_GADGET;
1029         }
1030
1031         if (!ci_otg_is_fsm_mode(ci)) {
1032                 /* only update vbus status for peripheral */
1033                 if (ci->role == CI_ROLE_GADGET)
1034                         ci_handle_vbus_change(ci);
1035
1036                 ret = ci_role_start(ci, ci->role);
1037                 if (ret) {
1038                         dev_err(dev, "can't start %s role\n",
1039                                                 ci_role(ci)->name);
1040                         goto stop;
1041                 }
1042         }
1043
1044         ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1045                         ci->platdata->name, ci);
1046         if (ret)
1047                 goto stop;
1048
1049         ret = ci_extcon_register(ci);
1050         if (ret)
1051                 goto stop;
1052
1053         if (ci->supports_runtime_pm) {
1054                 pm_runtime_set_active(&pdev->dev);
1055                 pm_runtime_enable(&pdev->dev);
1056                 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1057                 pm_runtime_mark_last_busy(ci->dev);
1058                 pm_runtime_use_autosuspend(&pdev->dev);
1059         }
1060
1061         if (ci_otg_is_fsm_mode(ci))
1062                 ci_hdrc_otg_fsm_start(ci);
1063
1064         device_set_wakeup_capable(&pdev->dev, true);
1065         dbg_create_files(ci);
1066
1067         ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
1068         if (ret)
1069                 goto remove_debug;
1070
1071         return 0;
1072
1073 remove_debug:
1074         dbg_remove_files(ci);
1075 stop:
1076         if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1077                 ci_hdrc_otg_destroy(ci);
1078 deinit_gadget:
1079         ci_hdrc_gadget_destroy(ci);
1080 deinit_host:
1081         ci_hdrc_host_destroy(ci);
1082 deinit_phy:
1083         ci_usb_phy_exit(ci);
1084 ulpi_exit:
1085         ci_ulpi_exit(ci);
1086
1087         return ret;
1088 }
1089
1090 static int ci_hdrc_remove(struct platform_device *pdev)
1091 {
1092         struct ci_hdrc *ci = platform_get_drvdata(pdev);
1093
1094         if (ci->supports_runtime_pm) {
1095                 pm_runtime_get_sync(&pdev->dev);
1096                 pm_runtime_disable(&pdev->dev);
1097                 pm_runtime_put_noidle(&pdev->dev);
1098         }
1099
1100         dbg_remove_files(ci);
1101         sysfs_remove_group(&ci->dev->kobj, &ci_attr_group);
1102         ci_role_destroy(ci);
1103         ci_hdrc_enter_lpm(ci, true);
1104         ci_usb_phy_exit(ci);
1105         ci_ulpi_exit(ci);
1106
1107         return 0;
1108 }
1109
1110 #ifdef CONFIG_PM
1111 /* Prepare wakeup by SRP before suspend */
1112 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1113 {
1114         if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1115                                 !hw_read_otgsc(ci, OTGSC_ID)) {
1116                 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1117                                                                 PORTSC_PP);
1118                 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1119                                                                 PORTSC_WKCN);
1120         }
1121 }
1122
1123 /* Handle SRP when wakeup by data pulse */
1124 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1125 {
1126         if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1127                 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1128                 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1129                         ci->fsm.a_srp_det = 1;
1130                         ci->fsm.a_bus_drop = 0;
1131                 } else {
1132                         ci->fsm.id = 1;
1133                 }
1134                 ci_otg_queue_work(ci);
1135         }
1136 }
1137
1138 static void ci_controller_suspend(struct ci_hdrc *ci)
1139 {
1140         disable_irq(ci->irq);
1141         ci_hdrc_enter_lpm(ci, true);
1142         if (ci->platdata->phy_clkgate_delay_us)
1143                 usleep_range(ci->platdata->phy_clkgate_delay_us,
1144                              ci->platdata->phy_clkgate_delay_us + 50);
1145         usb_phy_set_suspend(ci->usb_phy, 1);
1146         ci->in_lpm = true;
1147         enable_irq(ci->irq);
1148 }
1149
1150 static int ci_controller_resume(struct device *dev)
1151 {
1152         struct ci_hdrc *ci = dev_get_drvdata(dev);
1153         int ret;
1154
1155         dev_dbg(dev, "at %s\n", __func__);
1156
1157         if (!ci->in_lpm) {
1158                 WARN_ON(1);
1159                 return 0;
1160         }
1161
1162         ci_hdrc_enter_lpm(ci, false);
1163
1164         ret = ci_ulpi_resume(ci);
1165         if (ret)
1166                 return ret;
1167
1168         if (ci->usb_phy) {
1169                 usb_phy_set_suspend(ci->usb_phy, 0);
1170                 usb_phy_set_wakeup(ci->usb_phy, false);
1171                 hw_wait_phy_stable();
1172         }
1173
1174         ci->in_lpm = false;
1175         if (ci->wakeup_int) {
1176                 ci->wakeup_int = false;
1177                 pm_runtime_mark_last_busy(ci->dev);
1178                 pm_runtime_put_autosuspend(ci->dev);
1179                 enable_irq(ci->irq);
1180                 if (ci_otg_is_fsm_mode(ci))
1181                         ci_otg_fsm_wakeup_by_srp(ci);
1182         }
1183
1184         return 0;
1185 }
1186
1187 #ifdef CONFIG_PM_SLEEP
1188 static int ci_suspend(struct device *dev)
1189 {
1190         struct ci_hdrc *ci = dev_get_drvdata(dev);
1191
1192         if (ci->wq)
1193                 flush_workqueue(ci->wq);
1194         /*
1195          * Controller needs to be active during suspend, otherwise the core
1196          * may run resume when the parent is at suspend if other driver's
1197          * suspend fails, it occurs before parent's suspend has not started,
1198          * but the core suspend has finished.
1199          */
1200         if (ci->in_lpm)
1201                 pm_runtime_resume(dev);
1202
1203         if (ci->in_lpm) {
1204                 WARN_ON(1);
1205                 return 0;
1206         }
1207
1208         if (device_may_wakeup(dev)) {
1209                 if (ci_otg_is_fsm_mode(ci))
1210                         ci_otg_fsm_suspend_for_srp(ci);
1211
1212                 usb_phy_set_wakeup(ci->usb_phy, true);
1213                 enable_irq_wake(ci->irq);
1214         }
1215
1216         ci_controller_suspend(ci);
1217
1218         return 0;
1219 }
1220
1221 static int ci_resume(struct device *dev)
1222 {
1223         struct ci_hdrc *ci = dev_get_drvdata(dev);
1224         int ret;
1225
1226         if (device_may_wakeup(dev))
1227                 disable_irq_wake(ci->irq);
1228
1229         ret = ci_controller_resume(dev);
1230         if (ret)
1231                 return ret;
1232
1233         if (ci->supports_runtime_pm) {
1234                 pm_runtime_disable(dev);
1235                 pm_runtime_set_active(dev);
1236                 pm_runtime_enable(dev);
1237         }
1238
1239         return ret;
1240 }
1241 #endif /* CONFIG_PM_SLEEP */
1242
1243 static int ci_runtime_suspend(struct device *dev)
1244 {
1245         struct ci_hdrc *ci = dev_get_drvdata(dev);
1246
1247         dev_dbg(dev, "at %s\n", __func__);
1248
1249         if (ci->in_lpm) {
1250                 WARN_ON(1);
1251                 return 0;
1252         }
1253
1254         if (ci_otg_is_fsm_mode(ci))
1255                 ci_otg_fsm_suspend_for_srp(ci);
1256
1257         usb_phy_set_wakeup(ci->usb_phy, true);
1258         ci_controller_suspend(ci);
1259
1260         return 0;
1261 }
1262
1263 static int ci_runtime_resume(struct device *dev)
1264 {
1265         return ci_controller_resume(dev);
1266 }
1267
1268 #endif /* CONFIG_PM */
1269 static const struct dev_pm_ops ci_pm_ops = {
1270         SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1271         SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1272 };
1273
1274 static struct platform_driver ci_hdrc_driver = {
1275         .probe  = ci_hdrc_probe,
1276         .remove = ci_hdrc_remove,
1277         .driver = {
1278                 .name   = "ci_hdrc",
1279                 .pm     = &ci_pm_ops,
1280         },
1281 };
1282
1283 static int __init ci_hdrc_platform_register(void)
1284 {
1285         ci_hdrc_host_driver_init();
1286         return platform_driver_register(&ci_hdrc_driver);
1287 }
1288 module_init(ci_hdrc_platform_register);
1289
1290 static void __exit ci_hdrc_platform_unregister(void)
1291 {
1292         platform_driver_unregister(&ci_hdrc_driver);
1293 }
1294 module_exit(ci_hdrc_platform_unregister);
1295
1296 MODULE_ALIAS("platform:ci_hdrc");
1297 MODULE_LICENSE("GPL v2");
1298 MODULE_AUTHOR("David Lopo <[email protected]>");
1299 MODULE_DESCRIPTION("ChipIdea HDRC Driver");